A connector-based port management method and related device

Abstract

A connector-based port management method comprises the following steps: identifying component access, obtaining component requirements through a transmission interface provided by a connector, the component requirements being used to indicate attributes of ports required by the component, and adapting a port mode of ports connected by the connector to the component according to the component requirements. Thus, the port signal definition of the same connector cannot be self-adaptively and flexibly configured, and can only be applied to one type of high-speed signal, which has the disadvantage of supporting the same type of component. The flexibility of the port is effectively improved, more components are supported by the same port, and the configuration flexibility of the whole machine is improved.

Description

[0001] This application is a divisional application, the original application number is 202210188357.1, the original application date is February 28, 2022, and the entire contents of the original application are incorporated herein by reference. TECHNICAL FIELD

[0002] The present application relates to the technical field of computers, and in particular to a port management method based on a connector, a baseboard, a mainboard and a computing device. BACKGROUND

[0003] Since the 1980s, Microsoft and Intel have formed the Wintel alliance to promote the development of the personal computer (PC) industry. The two companies have closely cooperated in the PC industry to drive faster development of the computing industry and gradually influence other computing devices such as servers. The application scenarios of servers and other computing devices are various, the configuration types are various, and the reliability requirements are relatively high. At the same time, servers and other computing devices have a huge commercial volume and are the focus of open industry ecosystem construction.

[0004] The technical threshold for developing a traditional server mainboard is high. In addition to a central processing unit (CPU), it also includes bus fanout, power fanout, maintenance management and other functions. The CPU-related circuits on these mainboards all come from the reference design provided by the CPU manufacturer, and the reference designs provided by different CPU manufacturers are completely different, which makes the development and design of the mainboard require a large amount of resources and time. In order to meet the demand for rapid updating and upgrading of servers and other computing products, system manufacturers need to invest more effort in differentiation innovation, but often can only focus on low-level hardware specification comparison. This not only cannot meet the needs of customers for various scenarios and computing power, but also forces system manufacturers to fall into inefficient homogenization competition. With the trend of computing power diversity, more processor manufacturers have emerged and launched more processor products with different architectures, and the functions of various processors have become increasingly enhanced. For example, the ports of some processors can be flexibly configured with multiple protocols. Specifically, the ports of the processors can support peripheral component interconnect express (PCIe), Serial Attached Small Computer System Interface (SAS), Serial Advanced Technology Attachment (SATA) or Ethernet (ETH) and other protocol types.

[0005] To meet the requirements of application scenarios, configuration types or reliability of a computing device such as a server, a motherboard of the computing device such as the server can also access components. The motherboard and the components can be interconnected through connectors and cables. For example, when the components are high-speed components, the motherboard and the high-speed components can be interconnected at high speed through high-speed connectors and high-speed cables.

[0006] However, the port definition on the connector in the motherboard is usually fixed, so the motherboard is usually used to connect components of the same type, for example, components supporting PCIe, thereby limiting the application scenarios of the motherboard and being not conducive to flexible and differentiated configuration of the whole machine. SUMMARY

[0007] The present application provides a port management method based on a connector. The method uses a transmission interface provided by the connector to obtain requirements, and adapts a port mode of a port connected by the connector to a component according to a component requirement, so as to solve the problem that the interface signal definition of the same connector cannot be flexibly configured and can only be applied to one type of high-speed signal, and the disadvantage that the same type of components is supported, effectively improve the flexibility of the port, realize that the same port supports more components, and improve the configuration flexibility of the whole machine. The present application also provides a baseboard, a component, a motherboard and a computing device, a computer readable storage medium and a computer program product corresponding to the above method.

[0008] In a first aspect, an embodiment of the present application provides a port management method based on a connector. The method is proposed on the basis of a new server architecture. The new server architecture refers to a peer-to-peer interconnection architecture, in which a traditional motherboard is split into a baseboard and an expansion board, and the baseboard is used in combination with the expansion board to support the specifications and forms of the motherboard required for different scenarios. In the new server architecture, the baseboard is connected in communication with components through PCIe, memory interconnection or a unified bus, and is connected to the expansion board through a management interface. The components are a general term for a class of devices or equipment. For example, the components can include storage components, input / output components, acceleration components, memory expansion components, cooling components, computing components, management components and components with different functions.

[0009] The method can be executed by the baseboard. Specifically, the baseboard identifies component access, obtains component requirements through a transmission interface provided by the connector, the component requirements are used to indicate the attributes of the ports required by the components, and then the baseboard can adapt a port mode of a port connected by the connector to the components according to the component requirements.

[0010] In the method, the baseboard acquires component requirements through a transmission interface provided by the connector, and adapts the port mode of the port connected by the connector to the component according to the component requirements, so as to solve the problem that the port signal definition of the same connector cannot be adaptively and flexibly configured and can only be applied to one type of high-speed signal, and the disadvantage of supporting the same type of component, effectively improve the flexibility of the port, realize that the same port supports more components, and improve the competitiveness of the baseboard and the configuration flexibility of the whole machine.

[0011] In some possible implementation manners, before acquiring the component requirements through the transmission interface provided by the connector, the baseboard can further acquire a component type of the component, and then configure a corresponding sideband signal of the component according to the component type. The sideband signal includes the transmission interface.

[0012] In the method, the baseboard identifies the component type, adaptively configures a sideband signal according to the component type, and then transmits component requirements through a transmission interface in the sideband signal, to realize port adaptation based on the component requirements. In this way, the baseboard can support different components based on the same connector.

[0013] In some possible implementation manners, the component requirements include one or more of a port type, a link bit width, a port maximum rate, a lane order reversal capability, a signal polarity reversal capability, and a hot plug capability. The method realizes adaptive configuration of the port type, the lane order reversal, the polarity reversal, and the hot plug through the component requirements transmitted by the component.

[0014] In some possible implementation manners, the connector is provided with a first pin for transmitting the component type. The first pin can be a plurality of pins for transmitting the sideband signal, for example, three fixed pins for transmitting the sideband signal. Correspondingly, the baseboard can sample the first pin of the connector to obtain the component type of the component. The baseboard includes a controller, and the controller has a component type identification circuit. The baseboard can sample the first pin of the connector through the controller, and then identify the signal of the first pin by using the component type identification circuit in the controller, to obtain the component type of the component.

[0015] In some possible implementation manners, the component type is identified by high and low levels of the first pin. Specifically, the component type can be represented by a component type identification code, and the component type identification code can be identified by high and low levels of the first pin. In this way, the baseboard can quickly identify the component type of the component based on the first pin, and then configure the sideband signal based on the component type, and quickly configure the port mode of the port based on the component requirements transmitted through the transmission interface in the sideband signal, to improve the adaptation efficiency.

[0016] In some possible implementation manners, the connector is provided with a second pin for transmitting component requirements. The second pin can be a plurality of pins for transmitting sideband signals, for example, can be a plurality of fixed pins for transmitting sideband signals in addition to the first pin. Accordingly, the baseboard can sample the second pin of the connector to obtain component requirements transmitted by the component through the transmission interface.

[0017] In some possible implementation manners, the component has a reporting function. The component can actively report component requirements, and the baseboard can receive the component requirements reported by the component through the transmission interface provided by the connector, thereby realizing port mode adaptation and further realizing expansion of different types of components. In this way, a baseboard can flexibly support more overall machine configurations, improve the multiplexing degree of the baseboard, and reduce development costs.

[0018] In some possible implementation manners, the baseboard can also first send a request to the component, and then the baseboard can receive component requirements returned by the component in response to the request through the transmission interface provided by the connector, thereby realizing port adaptation.

[0019] In some possible implementation manners, the transmission interface is a single-wire transmission interface. The single-wire transmission interface uses a single-wire transmission communication protocol. The protocol is a private communication protocol, and the protocol layer can use a Hisport interface protocol. This method can save pins and reserve more pins for other sideband signals by transmitting component requirements through the single-wire transmission communication protocol.

[0020] In some possible implementation manners, the component type is generated by a component type identification code implementation circuit in the component. The component type identification code implementation circuit can generate a corresponding component type identification code by controlling a pull-up resistor and a pull-down resistor, and then transmit the component type identification code to the baseboard, so that the baseboard can adaptively configure sideband signals according to the component type identification code.

[0021] In some possible implementation manners, the method is performed by the baseboard. In this way, the baseboard can expand different types of components through one connector, meet business requirements, and avoid limited application scenarios.

[0022] In some possible implementation manners, the component includes one or more of a storage component, an input / output (IO) component, an acceleration component, and a memory expansion component. In this way, the baseboard can expand components with corresponding functions according to business requirements.

[0023] In a second aspect, an embodiment of the present application provides a port management method based on a connector. The method is performed by a component. The method includes:

[0024] accessing a baseboard;

[0025] providing, by the connector, a component requirement to the baseboard, so that the baseboard adapts a port mode of a port to a component according to the component requirement.

[0026] In some possible implementation manners, before the providing, by the connector, a component requirement to the baseboard, the method further includes:

[0027] providing, by the connector, a component type to the baseboard, so that the baseboard configures a corresponding sideband signal of the component according to the component type, the sideband signal including the transmission interface.

[0028] In some possible implementation manners, the providing, by the connector, a component requirement to the baseboard includes:

[0029] reporting, by the connector, a component requirement to the baseboard through a transmission interface.

[0030] In some possible implementation manners, the providing, by the connector, a component requirement to the baseboard includes:

[0031] returning, by the connector, a component requirement to the baseboard through a transmission interface in response to a request of the baseboard.

[0032] In some possible implementation manners, the component requirement includes one or more of a port type, a link bit width, a port maximum rate, a lane order reversal capability, a signal polarity reversal capability, and a hot plug capability.

[0033] In a third aspect, the present application provides a baseboard. The baseboard includes a processor and a connector, the processor having a port, and the baseboard is configured to perform the method in any one of the implementation manners of the first aspect of the present application, so as to manage the port of the processor based on the connector.

[0034] In some possible implementation manners, the processor is a central processing unit, and the central processing unit is packaged with a main processor and a coprocessor, the coprocessor is configured to acquire a component requirement through a transmission interface provided by the connector, the component requirement is used to indicate an attribute of a port required by the component, and the coprocessor is configured to deliver the component requirement to the main processor, and the main processor is configured to adapt a port mode of the port connected by the connector to the component according to the component requirement.

[0035] In some possible implementation manners, the baseboard further includes a controller configured to acquire component requirements through a transmission interface provided by the connector, the component requirements being used to indicate properties of ports required by the component, and transmit the component requirements to the processor, the processor being configured to adapt the port mode of the ports connected by the connector.

[0036] In some possible implementation manners, the controller includes one or more of a micro control unit (MCU), a complex programmable logic device (CPLD), and a field programmable gate array (FPGA).

[0037] In a fourth aspect, the present application provides a component. The component includes a memory and a connector, and is configured to perform the method in any of the implementation manners of the second aspect of the present application, so as to manage the ports of the processor based on the connector.

[0038] In a fifth aspect, the present application provides a mainboard. The mainboard includes a baseboard and a component, and when the component is connected to the baseboard, the baseboard is configured to perform the method in any of the implementation manners of the first aspect of the present application, so as to manage the ports of the processor in the baseboard based on the connector.

[0039] In a sixth aspect, the present application provides a computing device. The computing device includes a baseboard, and the baseboard is configured to perform the method in any of the implementation manners of the first aspect of the present application, so as to manage the ports of the processor in the baseboard based on the connector.

[0040] In a seventh aspect, the present application provides a computer readable storage medium, which stores instructions. The instructions instruct a computing device to perform the method in any of the implementation manners of the first aspect or the second aspect.

[0041] In an eighth aspect, the present application provides a computer program product including instructions, which, when executed on a computing device, cause the computing device to perform the method in any of the implementation manners of the first aspect or the second aspect.

[0042] On the basis of the implementation manners of the aspects of the present application, further combinations can be made to provide more implementation manners. BRIEF DESCRIPTION OF DRAWINGS

[0043] In order to more clearly illustrate the technical methods of the embodiments of the present application, the drawings required to be used in the embodiments will be briefly introduced as follows.

[0044] Figure 1 FIG. 1 is a structural schematic diagram of a mainboard provided by an embodiment of the present application;

[0045] Figure 2 A structural diagram of a mainboard provided for an embodiment of the present application is shown in FIG. 1.

[0046] Figure 3 A flowchart of a port management method based on a connector provided for an embodiment of the present application is shown in FIG. 4.

[0047] Figure 4 A principle diagram of stable access detection provided for an embodiment of the present application is shown in FIG. 5.

[0048] Figure 5 A structural diagram of a computing device provided for an embodiment of the present application is shown in FIG. 6. DETAILED DESCRIPTION

[0049] For the convenience of understanding, first, technical terms involved in the present application are introduced.

[0050] The server new architecture, which can also be referred to as a new architecture, refers to a peer-to-peer interconnection architecture. In this architecture, the traditional mainboard is first split into a basic computing unit (BCU) and an extension unit (EXU), and the basic computing unit is used in combination with the extension unit to support the specifications and forms of the mainboard required for different scenarios.

[0051] The basic computing unit includes a CPU, a double data rate (DDR), and related power supplies, and provides general computing capabilities and peripheral storage, input / output (IO), acceleration, and other expansion interfaces. The basic computing unit supports CPUs of different series. Optionally, the basic computing unit supports heterogeneous processors, i.e., the basic computing unit can support different types of processors, for example, the basic computing unit supports a CPU, and any one of an application-specific integrated circuit (ASIC), a programmable logic device (PLD), a complex programmable logical device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), a system on chip (SoC), a software-defined infrastructure (SDI) chip, an artificial intelligence (AI) chip, or any combination thereof.

[0052] The expansion board includes a baseboard management controller (BMC) chip and a management system, a bridge (for example, a platform controller hub (PCH) of an Intel system), is a management expansion of the baseboard, serves as a management center of the entire system, and provides device, security, energy efficiency, reliability, and the like management functions. The BMC can also be referred to as a baseboard management controller.

[0053] In the new architecture, the baseboard is connected to the components through PCIe, Compute Express Link (CXL), or a unified bus (UB or Ubus), and is connected to the expansion board through a management interface. The management interface can transmit management signals, power timing control signals, and IO expansion interface signals. In specific implementations, the specific connection modes of the baseboard and the components, and the baseboard and the expansion board include a soft connection mode in which a cable is used to implement the connection, or a hard connection mode in which a connector is used to implement the connection.

[0054] Further, the components are a collective term for a class of devices or equipment. The components include, according to different functions, a storage unit (STU), an input output unit (IOU), an acceleration unit (ACU), a memory expansion unit (MEU), a heat dissipation component, a computing component, a management component, and the like.

[0055] The storage components include a hard disk backplane and the like, provide system storage expansion, and support multiple media and forms such as a hard disk drive (HDD), a solid-state drive (SSD), a non-volatile memory express (NVMe), and a storage class memory (SCM).

[0056] The IO components include a riser and the like, implement expansion of system IO, and support PCIe cards and Open Compute Project (OCP) cards.

[0057] The acceleration components include card-type acceleration cards and in-module acceleration modules, and provide system acceleration component expansion and interconnection functions.

[0058] The memory expansion component includes a carrier board, a memory expansion chip, a dual in-line memory module (DIMM), an SCM medium, and the like, and provides functions of expanding memory bandwidth and content capacity of a system.

[0059] The heat dissipation component is used for dissipating heat of a computing device or hardware in the computing device, and includes a combination of several heat dissipation modes such as air cooling, liquid cooling, or the combination of the two. It should be understood that the structure, type, and number of the heat dissipation component do not constitute a limitation on the technical solutions to be protected by the present application.

[0060] The computing component includes a central processing unit (CPU), a memory, and the like, and provides general computing capability.

[0061] The management component includes a baseboard management controller, and the like, and provides device management.

[0062] The present application proposes a port management scheme based on connector adaptation on the basis of a new server architecture, uses a transmission interface provided by a connector to obtain component requirements, the component requirements are used to indicate attributes of ports required by a component (for the convenience of description, high-speed components are used as examples in the following description), and port modes of the ports connected by the connector are adapted to high-speed components (such as the storage component, the IO component, the acceleration component, the memory expansion component, and the like) according to the component requirements, so as to solve the drawbacks that interface signal definitions of the same connector cannot be flexibly configured adaptively, can only be applied to one type of high-speed signal, and support the same type of high-speed component, effectively improve the flexibility of the ports, realize that one port supports more high-speed components, and improve the competitiveness of the baseboard and the configuration flexibility of the whole machine.

[0063] In order to make the technical solutions of the present application clearer and easier to understand, the technical solutions provided by the present application are described in detail below in combination with the drawings.

[0064] First, referring to the structural schematic diagram of the mainboard shown in Figure 1 The mainboard 10 includes a baseboard 100 and peripheral high-speed components 200. The high-speed components 200 are connected to the baseboard 100, for example, the high-speed components 200 can be connected to the baseboard 100 in a plug-in manner. The mainboard 10 further includes an expansion board (not shown in the figure), which provides management functions and power supply for the baseboard 100 and the expanded high-speed components 200. Figure 1

[0065] ​The baseboard 100 includes a processor 102, a controller 104 and a connector 106. The processor 102 can be a CPU. The controller 104 can be one or more of a micro controller unit (MCU), a complex Programming logic device (CPLD), a Field Programmable Gate Array (FPGA). The connector 106 is used to connect a peripheral high-speed component 200. In some embodiments, the connector 106 can be a high-speed connector, for example, a Unified Bus Connector (UBC) or a Unified Bus Connector-Double Density (UBC-DD). The baseboard 100 can include one or more connectors 106, and the multiple connectors 106 can be used to connect different types of high-speed components 200 (for example, a PCIe-supported high-speed component 200, an ETH-supported high-speed component 200).

[0066] The high-speed component 200 includes a memory 202 and a connector 204. The memory 202 is used to store component requirements of the high-speed component. The component requirements include attributes of ports required by the component. In some embodiments, the attributes of the ports include one or more of a port type, a link bit width, a port maximum rate, a lane flipping capability, a signal polarity flipping capability, a hot plug capability. The connector 204 is used to interface with the baseboard 100, specifically, the connector 204 and the connector 106 in the baseboard 100 are connected, so as to realize the interface with the baseboard 100.

[0067] The component requirements stored in the memory 202 can be transmitted to the baseboard 100 through the connector 204, so that the baseboard 100 adapts the port mode of the ports connected by the connector 106 to the high-speed component 200 according to the component requirements. The port mode refers to a mode divided based on the attributes of the ports. When the ports are in different port modes, the attributes of the ports are usually different.

[0068] It should be noted that the high-speed component 200 can actively report the component requirements, or respond to a request (for example, a read request) from the baseboard 100 to return the component requirements to the baseboard 100. In some embodiments, the high-speed component 200 can further include a component requirement reporting module 206, which is respectively connected with the memory 202 and the connector 204. The component requirement reporting module 206 reads the component requirements stored in the memory 202, and transmits the component requirements to the baseboard 100 through a transmission interface provided by the connector 204.

[0069] The component requirement reporting module 206 can be implemented by an MCU, a CPLD, or an FPGA, etc. The MCU, the CPLD, or the FPGA can include a built-in memory, such as an on-chip read-only memory (ROM). The component requirements can also be stored in the built-in memory, and the component requirement reporting module 206 can read the component requirements from the built-in memory and then report the component requirements to the baseboard 100. In some embodiments, the component requirements can also be stored in a separate memory, such as the memory 202 described above, and the component requirement reporting module 206 can read the component requirements from the separate memory and then report the component requirements to the baseboard 100. In other embodiments, when the baseboard 100 actively reads the component requirements, the baseboard 100 can directly read the component requirements from the separate memory, such as the memory 204.

[0070] Further, the high-speed component 200 can also include a component type identification code implementation circuit 208. The component type identification code implementation circuit 208 is configured to generate a component type, which can be represented by a component type identification code. In some embodiments, the component type identification code can be 101, 110, 011, 010, etc. Based on this, the component type can be identified by the high and low levels of a plurality of pins (for the sake of description, which can be referred to as first pins) of the connector 204. The component type identification code implementation circuit 208 can transmit the component type (e.g., the component type identification code) to the baseboard 100 through the connector 204, so that the baseboard 100 can configure a side band signal corresponding to the high-speed component 200 according to the component type. The side band signal includes a transmission interface for transmitting component requirements.

[0071] The embodiments of the present application achieve adaptive configuration of high-speed signal types and side band signal definitions for the same connector 106 according to different types of connected high-speed components 200 by designing port definitions on the connector 106, which greatly improves the flexibility and applicability of the connector 106.

[0072] For the sake of understanding, the pin map of the connector 106 is described below by taking a widely used 74-pin high-speed connector (e.g., a 74-pin slimline high-speed connector) as an example.

[0073] The 74-pin high-speed connector has 74 pins, including 8 pairs (i.e., 16) pins for transmitting high-speed signals (such as high-speed port data receiving signals and high-speed port data transmitting signals), 20 pins for transmitting side band signals (usually low-speed side band signals, which can also be referred to as low-speed signals), and some pins for transmitting ground signals, as shown below:

[0074] Table 1 pin map example of 74-pin high-speed connector

[0075]

[0076]

[0077] When the connector is applied to different ports (different IO ports of CPU) and different types of high-speed components 200 are connected, different port definitions are required, and for this purpose, multiplexing relationship definitions are made for the sideband signals in the connector. When the high-speed signals are respectively used as PCIe or SAS / SATA or ETH network ports, the sideband signals can be assigned different signal definitions to meet the needs of different high-speed components 200. The specific definitions are as follows:

[0078] Table 2 sideband signal multiplexing relationship

[0079]

[0080]

[0081]

[0082] In order to realize the transmission of different types of high-speed signals, such as PCIe type high-speed signals and ETH type high-speed signals, the embodiments of the present application select different types of pins in the pins of the connector 106 used to transmit sideband signals for defining the transmission interface. Among them, different types of pins can also be selected in the pins of the connector 106 used to transmit sideband signals for transmitting component types. In order to facilitate distinction, the embodiments of the present application refer to the pins used to transmit component types as first pins, and the pins used to transmit component requirements as second pins.

[0083] In some embodiments, the first pins can be A8, A26 and B10, as shown below:

[0084] Table 3 definition of first pins

[0085]

[0086] The three (low-speed) sideband signals P0_SB_7A, P0_SB_7B and P0_SB_2A can be used as component type (BP_type) detection signals. The BP_type detection signal is an indication signal of the component to the BCU, which is pulled up on the BCU and enters the CPLD. It is suspended or pulled down on the high-speed component 200, and different BP_type combinations can be used to distinguish the types of high-speed components 200 connected by the connector (such as UBC or UBC-DD), so as to distinguish the use of other sideband signals inside the CPLD logic.

[0087] Specifically, the high-speed component 200 can indicate the component type of the high-speed component 200 through BP_TYPE[2:0], as shown in the following table:

[0088] Table 4 Component type identification code

[0089]

[0090] It should be noted that BP_type[0] can be used as a plug-stable detection signal of the high-speed component 200. The detection principle thereof will be described in detail below.

[0091] The baseboard 100 can sample BP_TYPE[2:0] using a CPLD (or other controllers such as FPGA, MCU), and according to the component type obtained by sampling, adaptively configure the remaining sideband signals (specifically, the transmission interface in the sideband signal), as follows:

[0092] Table 5 Definition of transmission interface

[0093]

[0094]

[0095] Among them, P0_SB_3A is defined as GND, as the reference GND of the high-speed homologous clock. P0_SB_2B is defined as Vstby_3v3, as the 3.3V standby power supply provided by the baseboard 100 side to the high-speed component 200 side. In order to protect the cable and the connector 106, the baseboard 100 side can provide an overcurrent protection function for the P0_SB_2B power supply. P0_SB_3B is defined as not connected (NC). Since the P0_SB_2B pin of the connector 106 at the opposite end has been defined as a power supply, in order to prevent the case of power supply short circuit caused by the connector 106 interconnection of the baseboard 100 side, P0_SB_3B is directly suspended. P0_SB_A+ / P0_SB_A- and P0_SB_B+ / P0_SB_B-, these two groups of signals are defined as high-speed signal homologous clock, used for high-speed port synchronization.

[0096] P0_SB_6B is defined as a transmission interface, also known as a cable detection signal TOPOLOGY_DET. Among them, the transmission interface can be a single-wire transmission interface, which is used for the high-speed component 200 to report the component requirements of the peripheral high-speed component 200 to the side of the baseboard 100. The component requirements can include one or more of port type, link bit width, port maximum rate, lane order reversal capability, signal polarity reversal capability, and hot plug capability. Among them, the lane order reversal capability is used to identify whether the connector 106 supports the capability of lane order reversal, the signal polarity reversal capability is used to identify whether the connector 106 supports signal polarity reversal, and the hot plug capability is used to identify whether the connector 106 supports hot plug.

[0097] For the above-mentioned sideband signals of multiplexing, the signal transmission and analysis process will be described below according to different access high-speed components 200.

[0098] When the accessed high-speed component 200 is a SAS / SATA hard disk backboard, the high-speed component 200 transmits BP_type[2:0] = 000 to the BCU, and according to the BP_type, two groups of SGPIO signals can be provided on the high-speed interface of the BCU for hard disk lighting, and a cable detection signal is added for high-speed cable use. The signal definition is compatible with the signal definition in the Universal Backplane Management (UBM) protocol standard.

[0099] When the accessed high-speed component 200 is a Nvme hard disk backboard, the high-speed component 200 transmits BP_type[2:0] = 011 to the BCU module, and according to the BP_type, two groups of HP_I2C signals can be provided on the high-speed interface of the BCU for hard disk hot plug operation, and two I2C reset signals are matched, two PCIe reset signals are provided, and a CHANGE_DET# interrupt signal is provided. The signal definition is compatible with the signal definition in the UBM protocol standard.

[0100] When the accessed high-speed component 200 is an OCP network card / Raid card / BBU module, the high-speed component 200 transmits BP_type[2:0] = 100 to the BCU, and according to the BP_type, a group of BMC_I2C signals can be provided on the high-speed interface of the BCU for out-of-band management system component management, a group of CPU_I2C for in-band CPU component management, and two PCIe platform reset signals, a PCIe_PWRBRK# signal, a PCIe_WAKE# signal, and a device in-place indication signal are matched. The signal definition is compatible with the signal definition in the OCP standard protocol.

[0101] When the accessed high-speed component 200 is a CPU direct NIC network card, the high-speed component 200 delivers BP_type[2:0] = 101 to the BCU, and according to the BP_type, the BCU can provide a set of BMC_I2C signals on the external high-speed interface for out-of-band management system component management, a set of CPU_I2C for in-band CPU management of the component, a set of MDIO for in-band CPU management of the component, and a supporting I2C reset signal, a device in place indication signal and a reserved signal.

[0102] When the accessed high-speed component 200 is a Riser module, the high-speed component 200 delivers BP_type[2:0] = 110 to the BCU module, and according to the BP_type, the BCU can provide a set of BMC_I2C signals on the external high-speed interface for out-of-band management system component management, and a supporting PCIe platform reset signal, a PCIe_PWRBRK# signal, a PCIe_WAKE# signal, a JTAG_TRST / AC_LOSS signal, a PCIe_CLKREQ# signal, and two reserved signals. The signal definitions are compatible with the signal definitions in the PCI Express Card Electromechanical Specification standard protocol.

[0103] Among them, the SPGIO signal is used for hard disk lighting control on the high-speed component 200, and the signal definition conforms to the SFF-8485 protocol standard. The HP_I2C signal is used for hot plug device control on the high-speed component 200, and the signal definition conforms to the I2C standard definition. The BMC_I2C signal is used for out-of-band management control on the high-speed component 200, and the signal definition conforms to the I2C standard definition. The CPU_I2C signal is used for in-band CPU management of the high-speed component 200, and the signal definition conforms to the I2C standard definition. The MDIO signal is used for in-band CPU management of the NIC card type high-speed component 200, and the signal definition conforms to the standard definition of MDIO in 802.3 clause 22. The CHANGE_DET signal is used for the high-speed component 200 to report an interrupt to the BCU, and the signal definition conforms to the definition of CHANGE_DET in SFF-TA-1005 Specification for UBM. The PCIe_PWRBRK / PCIe_WAKE / PCIe_RST / PCIe_CLKREQ / JTAG_TRST signals are used for PCIe standard device control on the high-speed component 200, and the signal definition conforms to the signal definition in the PCI Express Card Electromechanical Specification standard protocol.

[0104] In some possible implementations, the component requirement is stored in the memory 202 of the high-speed component 200. The memory 202 can be a separate memory, and when the high-speed component 200 includes the component requirement reporting module 208, the memory 202 can also be the built-in memory of the component requirement reporting module 208. The memory 202 can be an electrically erasable programmable read-only memory (EEPROM) or a Mask-programmed read-only memory (MROM), etc. The component requirement reporting module 208 (including but not limited to implemented by using CPLD logic) in the peripheral high-speed component 200 can read the component requirement in the memory 202, and transmit the component requirement to the controller 104 (including but not limited to implemented by using CPLD logic) through the transmission interface provided by the connector 106. The controller 104 parses the component requirement, and transmits the parsed component requirement to the processor 102. The processor 102 adapts the port mode of the port to the high-speed component 200 in the start-up stage, so as to realize the self-adaptive configuration of the port.

[0105] The transmission interface can use a single-wire transmission communication protocol. The protocol is a private communication protocol, and the protocol layer can use the Hisport interface protocol. The single-wire transmission communication protocol defines the bus signal frequency, the verification mode, and the maximum data amount of single transmission. In this example, the bus signal frequency can be 250 kilohertz (Khz), the verification mode is a standard cyclic redundancy check (CRC), and the maximum data amount of single transmission can be 32 bytes (B).

[0106] The 32-byte data and 1-byte CRC content transmitted by the transmission interface are defined as follows:

[0107] Table 6: Transmission interface transmission content

[0108]

[0109]

[0110] In the above content, the content related to the port mode configuration includes the component type, the port information, and the parameter (the attribute of the port). The port information is used to identify the type of the port, and the parameter is used to define the attribute of the port. For details, refer to the following table:

[0111] Table 7: Definition of port information and parameters

[0112]

[0113]

[0114] where parameter BYTE 1 (also referred to as parameter 1) defines the link width as shown in the following table:

[0115] Table 8 Definition of parameter BYTE 1

[0116] byte index bit stream information content Parameter 1 0000_0000 default value Parameter 1 0000_0001 x16 Parameter 1 0000_0010 x8 Parameter 1 0000_0011 x4 x4 Parameter 1 0000_0100 x2 x2 x2 x2 Parameter 1 0000_0101 x4 x2 x2 Parameter 1 0000_0110 x2 x2 x4

[0117] Bits [7:4] of parameter BYTE 2 (also referred to as parameter 2) define the port maximum rate as shown in the following table:

[0118] Table 9 Definition of bits [7:4] of parameter BYTE 2

[0119] byte index bit stream information content Parameter 2 0000 none Parameter 2 0001 GEN1 Parameter 2 0010 GEN2 Parameter 2 0011 GEN3 Parameter 2 0100 GEN4 Parameter 2 0101 GEN5 Parameter 2 0110 ……

[0120] Bits [3] and [2] of parameter BYTE 2 (also referred to as parameter 2) define the hot plug capability and lane flip capability of the port, respectively, as shown in the following tables:

[0121] Table 10 Definition of bit [3] of parameter BYTE 2

[0122]

[0123] Table 11 Definition of bit [2] of parameter BYTE 2

[0124] byte index bit stream information content Parameter 2 0 no flip Parameter 2 1 flip

[0125] Bits [1:0] of parameter BYTE 2 are reserved bits and can be used to define other attributes of the port.

[0126] Parameters BYTE 3 (also referred to as parameter 3) and BYTE 4 (also referred to as parameter 4) are used to define polarity flips, where parameter 3 is used to define polarity flip RX and parameter 4 is used to define polarity flip TX. The following tables show the definitions:

[0127] Table 12 Definition of parameter BYTE 3

[0128] byte index bit stream information content Parameter 3 0000_0000 none / default no flip Parameter 3 0000_0001 represents lane0 polarity flip Parameter 3 0000_0010 represents lane1 polarity flip ... and so on represents lane n polarity flip

[0129] Table 13 Definition of parameter BYTE 4

[0130] byte index bit stream information content Parameter 4 0000_0000 none / default no flip Parameter 4 0000_0001 represents lane 0 polarity flip Parameter 4 0000_0010 represents lane 1 polarity flip ... and so on represents lane n polarity flip

[0131] As Figure 1As shown, after the connector 106 transmits the component requirement including the port type, the port maximum rate, the lane order flip capability, the polarity flip capability, and the hot plug capability to the controller 104 through the above-mentioned pins, and the controller 104 transmits the component requirement to the processor 102, the processor 102 can realize the port mode self-adaptation. Accordingly, the processor 102 can receive the corresponding type of high-speed signal transmitted by the high-speed component 200 through the connector 106, instead of being limited to a fixed type of high-speed signal.

[0132] In some possible implementation manners, as shown in Figure 2 As shown, the processor 102 of the baseboard 100 can be packaged with a main processor 1024 and a coprocessor 1022, and the coprocessor 1022 is configured to assist the main processor 1024 in the processor 102 to complete the processing work that cannot be executed or is executed inefficiently or with low effect. When the processor 102 is packaged with the coprocessor 1022, the coprocessor 1022 can sample the first pins of the connector 106 to obtain the component type, and configure the corresponding sideband signal of the high-speed component 200 according to the component type. Then the coprocessor 1022 obtains the component requirement of the high-speed component 200 through the transmission interface in the sideband signal. The coprocessor 1022 can transmit the component requirement to the main processor 1024, and the main processor 1024 adapts the port mode of the port of the processor 102 to the high-speed component 200 based on the component requirement. In other words, in the example of Figure 2 The function of the controller 104 can be implemented by the coprocessor 1022, and the baseboard 100 can not include the above-mentioned controller 104.

[0133] Next, the flow of the connector-based port management method according to the embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0134] Referring to the flowchart of the connector-based port management method shown in Figure 3 The method includes the following steps.

[0135] S302: The baseboard 100 identifies the access of the high-speed component 200.

[0136] The high-speed component 200 is specifically a component for expanding the function of the baseboard 100. The high-speed component 200 usually has a high IO rate. Based on different expansion functions, the component 200 can include one or more of a storage component, an IO component, an acceleration component, and a memory expansion component.

[0137] In this embodiment, the high-speed component 200 can be divided into different types according to the supported protocol type. For example, the high-speed component 200 can include different types of PCIe components, ETH components, SAS components, SATA components, and the like.

[0138] The high-speed component 200 can be connected to the base board 100 to expand the function of the base board 100. There are various connection modes. In some embodiments, the high-speed component 200 can be connected to the base board 100 by plugging. In other embodiments, the high-speed component 200 can be connected to the base board 100 by snapping.

[0139] The base board 100 identifies whether the high-speed component 200 is connected. For example, when the high-speed component 200 is connected to the base board 100 by plugging, the base board 100 can identify whether the high-speed component 200 is connected by detecting the in-place signal and the like. When it is identified that the high-speed component 200 is connected, the base board 100 can perform the subsequent process.

[0140] S304: The base board 100 identifies whether the high-speed component 200 is stably connected. If yes, S306 is performed, and if no, S314 is performed.

[0141] Considering that the high-speed component 200 can be connected unstably, for example, when the high-speed component 200 is plugged into the base board 100, the high-speed component 200 can be plugged unstably, resulting in intermittent connection of the high-speed component 200 and the base board 100. Therefore, the base board 100 can also identify whether the high-speed component 200 is stably connected.

[0142] For example, the base board 100 can identify whether the high-speed component 200 is stably connected by detecting the in-place signal of the connector 204 in the high-speed component 200. When the high-speed component 200 is not stably connected, the base board 100 can perform S314 to perform an alarm prompt to remind the user to re-connect the high-speed component. When the high-speed component 200 is stably connected, S306 can be performed to start the port management based on the connector 106.

[0143] Referring to Figure 4 The stable connection detection principle diagram shown in the figure, the controller 104 such as CPLD in the base board 100 can design an output pin A and an input pin B. When the CPLD logic starts to detect BP_type tri-state, first output high resistance state to A pin, if B pin detects high level, it indicates that the high-speed component 200 is in place, and BP_type[0]=1; if B pin detects low level, output a high level to A pin, and detect B pin level again, if B pin is still low level, it indicates that the high-speed component 200 is in place, and BP_type[0]=0; if B pin detects high level, it indicates that the high-speed component 200 is not in place. The base board 100 continuously detects whether the high-speed component 200 is in place by CPLD, for example, whether the high-speed component 100 is in place is detected in continuous N cycles, which can realize whether the high-speed component 200 is stably connected.

[0144] It should be noted that the method of the embodiment of the present application can also not perform S304 described above. For example, the baseboard 100 can directly perform S306 to perform the port management method based on the connector 106.

[0145] S306: The baseboard 100 samples the first pin of the connector 106 to obtain the component type of the high-speed component 200.

[0146] Specifically, the connector 106 is provided with a first pin for transmitting the component type of the high-speed component. For example, the connector 106 with 74 pins is provided with pins with pin numbers A8, A26, and B10 for transmitting the component type of the high-speed component. The baseboard 100 can sample the above-mentioned first pin of the connector 106 to obtain the component type identification code of the high-speed component 200, which is used to identify the component type of the high-speed component 200.

[0147] In some possible implementation manners, the baseboard 100 includes the controller 104, and the baseboard 100 can sample the first pin through the controller 104 to obtain the component type of the high-speed component 200. The controller 104 has a component type identification circuit, and the controller 104 can sample the first pin and identify the signal of the first pin based on the component type identification circuit, thereby obtaining the component type. In another possible implementation manner, when the processor 102 of the baseboard 100 is packaged with the coprocessor 1022, the baseboard 100 can sample the first pin through the coprocessor 1022 to obtain the component type of the high-speed component.

[0148] S308: The baseboard 100 configures the sideband signal corresponding to the high-speed component 200 according to the component type.

[0149] In some possible implementation manners, the baseboard 100 includes the controller 104, and the controller 104 has a sideband signal configuration implementation circuit. The baseboard 100 can configure the sideband signal corresponding to the high-speed component 200 through the sideband signal configuration implementation circuit.

[0150] In another possible implementation manner, the processor 102 of the baseboard 100 is packaged with the coprocessor 1022, and the coprocessor 1022 can configure the sideband signal corresponding to the high-speed component according to the component type, thereby realizing adaptive configuration of the sideband signal.

[0151] It should be noted that the method of the embodiment of the present application can also not perform S306 to S308 described above. For example, the baseboard 100 can directly perform S310.

[0152] S310: The high-speed component 200 reports the component demand of the high-speed component 200 through a transmission interface provided by a second pin of the connector 106.

[0153] The second pin of the connector 106 is used to transmit the component requirement of the high-speed component 200. Specifically, the second pin defines a transmission interface through which the high-speed component 200 can actively report the component requirement.

[0154] The component requirement includes one or more of a port type, a link bit width, a port maximum rate, a lane order reversal capability, a signal polarity reversal capability, and a hot plug capability. Referring to Table 6, the component requirement can be characterized by a 32-byte content.

[0155] It should be noted that S310 is only one implementation manner in which the baseboard 100 acquires the component requirement transmitted by the high-speed component 200, and in other possible implementation manners of the present embodiment, the baseboard 100 can also acquire the component requirement through other manners. For example, the baseboard 100 can send a read request to the high-speed component 200, and the high-speed component 200 responds to the read request and receives the component requirement returned by the high-speed component 200 through the transmission interface provided by the connector 106.

[0156] S312: The baseboard 100 adapts the port mode of the port connected by the connector 106 to the high-speed component 200 according to the component requirement.

[0157] Specifically, the processor 102 of the baseboard 100 has a port, and the port has multiple port modes. Different port modes correspond to different attributes of the port. For example, in one port mode, the port type can be a PCIe type; for another example, in another port mode, the port type can be a SAS. The baseboard 100 can adapt the port mode of the port to the high-speed component 200 according to the component requirement, so as to configure the port of the processor 102 as a high-speed port required by the high-speed component 200, thereby realizing port mode adaptation.

[0158] S314: The baseboard 100 reports an unstable access alarm.

[0159] The unstable access alarm is used to alert the user that the high-speed component 200 is not stably accessed to the baseboard 100. The unstable access alarm can have multiple implementation forms. In some embodiments, the baseboard 100 can play an alarm sound for alarm, or present an alarm message through an alarm interface.

[0160] It should be noted that the above S314 is an optional step of the present embodiment, and the method of the present embodiment can also be executed without executing the above S314.

[0161] Based on the above content description, the embodiment of the present application provides a port management method based on the connector 106. In the method, the baseboard 100 can define the transmission interface based on the connector 106, define the transmission component requirement, and adapt the port mode of the port to the high-speed component 200 according to the component requirement, so as to realize the port mode adaptation and further realize the high-speed signal adaptation. The high-speed signal definition in the port definition on the connector 106 can be adapted according to the component type. When the port supports multiple port modes, one connector 106 can be used to transmit different types of high-speed signals, so that the flexible and configurable characteristics of the port can be fully utilized, and the flexible and differentiated configuration of the whole machine is facilitated.

[0162] The above embodiment describes the management of the port based on the 74-pin high-speed connector such as UBC. In some possible implementation manners, the baseboard 100 can also manage the port based on the 184-pin high-speed connector such as UBC-DD. The UBC-DD includes X16 high-speed signals, part of out-of-band low-speed signals, and power supply signals, supports 150W power supply capability, and can support a maximum of 2 75W PCIe standard cards. The specific implementation is as follows:

[0163] Table 14 Interface pin map example of 184-pin high-speed connector

[0164]

[0165]

[0166]

[0167]

[0168]

[0169] The multiplexing relationship of the low-speed management control signal (sideband signal) can refer to the definition of the multiplexing relationship in the 74-pin high-speed connector, and will not be described here.

[0170] Based on the above method and the baseboard 100 provided in the embodiment of the present application, the embodiment of the present application further provides a mainboard 10. Referring to the structural schematic diagram of the mainboard 10 shown in Figure 1 or Figure 2 The mainboard 10 includes the baseboard 100 and the high-speed component 200. The mainboard 10 further includes an expansion board (not shown in the figure).

[0171] The high-speed component 200 accesses the baseboard 100, and the baseboard 100 and the high-speed component 200 cooperatively execute Figure 3 The method shown in the embodiment, so as to adapt the port mode of the port of the processor 102 in the baseboard 100 to the high-speed component 200.

[0172] Further, the embodiments of the present application also provide a computing device. In some embodiments, the computing device can be a server, for example, a rack-mounted server. In other embodiments, the computing device can also be a terminal.

[0173] Figure 5 A structural diagram of a computing device is provided, as shown in Figure 5 The computing device 50 includes a base board 100 and a high-speed component 200. In some embodiments, the base board 100 includes a processor 102, a controller 104 and a connector 106. In other embodiments, the processor 102 can be packaged with a main processor and a coprocessor, in which case the functions of the controller 104 can be implemented by the coprocessor, and the base board 100 can not include the controller 104. The high-speed component 200 includes a memory 202 and a connector 204. The high-speed component 200 accesses the base board 100.

[0174] The processor 102 can be any one or more of a central processing unit (CPU), a graphics processing unit (GPU), a microprocessor (MP), or a digital signal processor (DSP). In some embodiments, the processor 102 can also include a coprocessor.

[0175] The controller 104 can be one or more of a micro control unit (MCU), a field programmable logic gate array (FPGA), or a complex programmable logic device (CPLD).

[0176] The connector 106 can be a high-speed connector, such as a UBC or a UBC-DD. In some embodiments, the connector 106 can also be a normal connector (e.g., a low-speed connector). Similarly, the connector 204 of the high-speed component 200 can be a high-speed connector, or a normal connector (e.g., a low-speed connector). The connector 204 of the high-speed component 200 is connected to the connector 106 of the base board 100, thereby enabling the high-speed component 200 to access the base board 100.

[0177] The base board 100 identifies the access of the high-speed component 200, obtains the component requirements transmitted by the high-speed component 200 through the transmission interface provided by the connector 106, and adapts the port mode of the port connected to the connector 106 to the high-speed component 200 according to the component requirements.

[0178] The embodiments of the present application also provide a computer readable storage medium. The computer readable storage medium can be any available medium or data storage that can be used to store data and that can be accessed by a computing device. The computer readable storage medium can be a magnetic-based, (e.g., a floppy disk, a hard disk, a magnetic tape), an optical-based, (e.g., a compact disk, a DVD), or a semiconductor-based, (e.g., a solid state disk), or any other medium that can be used to store and / or transport data. The computer readable storage medium includes instructions that instruct a computing device to perform the connector-based port management method described above.

[0179] The embodiments of the present application also provide a computer program product. The computer program product includes one or more computer instructions. When loaded and executed by a computing device, the computer instructions generate, in whole or in part, the processes or functions described in the embodiments of the present application. The computer instructions can be stored in a computer readable storage medium or transferred from one computer readable storage medium to another computer readable storage medium. For example, the computer instructions can be transferred from one website, computing device or data center to another website, computing device or data center through a wired (e.g., a coaxial cable, an optical fiber, a digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) manner. The computer program product can be a software package that can be downloaded and executed on a computing device when any of the methods described above needs to be used.

[0180] The descriptions of the processes or structures corresponding to the above-mentioned various figures are each focused on a certain aspect. For the parts not described in detail in a certain process or structure, please refer to the relevant descriptions of other processes or structures.

Claims

1. A connector-based port management method, characterized in that, The method is executed by a component, which includes any one of the following high-speed components: Serial Connected Small Computer System Interface (SAS) / Serial Advanced Technology Accessory (SATA) hard drive backplane, Non-Volatile High-Speed ​​Bus (NVMe) hard drive backplane, Open Compute Project (OCP) network card, Independent Hard Drive Redundant Array (RAID) card, Baseband Unit (BBU) module, CPU Direct Output Network Card, and Riser module. The component is used to transmit any one of the following high-speed signal types: PCIe, SAS, SATA, and ETH. The component includes a component type identification code implementation circuit and a component requirement reporting module. The method includes: After the component is connected to the base board, the component type identification code implementation circuit generates a component type identification code for the component and transmits the component type identification code to the base board. This allows the controller of the base board to configure the corresponding sideband signal for the component based on the component type. The sideband signal includes a transmission interface. The component requirement reporting module provides the component requirement to the controller through the transmission interface provided by the second pin of the connector on the base board. The component requirement indicates the attributes of the port required by the component. This allows the controller to adapt the port mode of the port connected to the connector to the component based on the component requirement. Then, the processor of the base board receives the corresponding type of high-speed signal transmitted by the component through the connector.

2. The method according to claim 1, characterized in that, The port attributes required by the component include one or more of the following: port type, link width, maximum port speed, channel order reversal capability, signal polarity reversal capability, and hot-plug capability.

3. The method according to claim 2, characterized in that, The component type of the component is provided to the controller through the first pin of the connector.

4. The method according to claim 3, characterized in that, The component type is identified by the high or low level of the first pin.

5. The method according to any one of claims 1 to 4, characterized in that, The component requirement reporting module provides component requirements to the controller through the transmission interface provided by the second pin of the connector on the base board, including: The component requirements of the component are reported through the transmission interface provided by the second pin of the connector on the base board.

6. The method according to any one of claims 1 to 4, characterized in that, The component requirement reporting module provides component requirements to the controller through the transmission interface provided by the second pin of the connector on the base board, including: Receive a request sent by the controller, the request instructing the component to return the component's component requirements; Based on the request, the component requirements are returned through the transmission interface provided by the second pin of the connector on the base board.

7. The method according to any one of claims 1 to 4, characterized in that, The transmission interface is a single-line transmission interface.

8. A motherboard, characterized in that, The motherboard includes a base board and components. When the components are connected to the base board, they perform the method as described in any one of claims 1 to 7.

9. A computing device, characterized in that, The computing device includes the motherboard as described in claim 8.

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