Parameter Determination Hardware System, Method, Storage Medium and Electronic Device for Storing Application Chips

Abstract

An embodiment of the present application provides a parameter determination hardware system, method, storage medium and electronic device for a storage application chip, belonging to the field of server design. The system includes: a server host for sending video data to the storage application chip; a storage application chip for determining the parameters of the storage application chip, adjusting the parameters of the storage application chip according to the determined parameters, and processing the video data into compressed video data after the parameter adjustment; a storage hard disk for receiving the compressed video data; the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; the video compression module includes a storage array depth determination module; through the above system, parameters such as the processor frequency of the storage application chip, the system bus frequency, and the storage array depth of the video compression module can be determined.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of servers, and more specifically, to a parameter determination hardware system, method, storage medium, and electronic device for a storage application chip. Background Technique

[0002] Storage application chips are becoming increasingly important in modern electronic devices. They are not only responsible for data storage but also generally integrate video processing functions. This integrated video processing function is usually implemented by an SoC (System on a Chip) chip. In terms of video processing functions, storage application chips can perform a series of complex operations. These operations include color space conversion of original RGB format video data to generate YUV format video data, generating data blocks, performing compression processing, and storing and transmitting the compressed data. These operations all involve a large amount of data processing and resource consumption.

[0003] During the video processing of storage application chips, video data is usually compressed in frames. Before the video data of the current frame is completely compressed, the video data of subsequent frames is not allowed to enter the video compression module. However, the data in the video processing channel is continuously generated. To avoid data loss during the video data processing, in the traditional solution, the data block generation module, which is the pre-stage module of the video compression module, caches the continuously input video data. Since it is impossible to accurately predict the storage capacity required for the data block generation module to cache data, a storage array with a relatively large depth is usually set inside the data block generation module of the storage application chip. Setting a storage array with a relatively large depth for a general storage application chip will result in a large consumption of on-chip storage resources, not only increasing the area of the chip but also increasing the production and manufacturing cost of the chip. At the same time, setting a storage array with a relatively large depth will also bring great difficulties to the subsequent synthesis, packaging, etc. of the storage application chip, thus reducing the yield rate of the chip.

[0004] Secondly, in the traditional chip design process, the settings of the CPU (Central Processing Unit) frequency and the system bus frequency of the storage application chip often rely on the experience of engineers, lacking an accurate guiding scheme. Therefore, the optimal combination of the CPU frequency and the system bus frequency of the storage application chip cannot be accurately determined. If the CPU frequency and the system bus frequency of the storage application chip are set too high, higher production process requirements are needed to meet the design requirements, which not only increases the chip production cost but also greatly increases the chip power consumption. If the CPU frequency and the system bus frequency of the storage application chip are set too low, the chip application requirements may not be met, resulting in chip design failure. In addition, under an unreasonable frequency combination of the CPU frequency and the system bus frequency of the storage application chip, it may also lead to waste of the performance of the CPU and the system bus of the storage application chip. Therefore, in the related art, there is a problem of how to accurately determine the parameters of the storage application chip.

[0005] In the related art, no effective solution has been proposed for the problem of how to accurately determine the parameters of the storage application chip. Summary of the Invention

[0006] The embodiments of the present application provide a parameter determination hardware system, method, storage medium, and electronic device for a storage application chip, so as to at least solve the problem of how to accurately determine the parameters of the storage application chip in the related art.

[0007] According to an embodiment of the present application, a parameter determination hardware system for a storage application chip, the system comprising: a server host for sending video data to the storage application chip; the storage application chip for determining parameters of the storage application chip, adjusting the parameters of the storage application chip according to the determined parameters, and processing the video data into compressed video data after the parameter adjustment; a storage hard disk for receiving the compressed video data; wherein, the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; the video graphics array module is used for receiving the video data sent by the server host and transmitting the video data to the video compression module of the storage application chip; the video compression module is used for processing the video data into the compressed video data and transmitting the compressed video data to the storage controller through the system bus; the storage controller is used for sending the compressed video data to the storage hard disk; wherein, the video compression module includes a storage array depth determination module; the parameters of the storage application chip include: processor frequency, system bus frequency, and the storage array depth of the video compression module; the frequency determination module is used for determining the processor frequency and the system bus frequency according to the response time and the latency time, wherein, the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of the peripheral module connected to the processor through the system bus; the storage array depth determination module is used for determining the storage array depth according to the time for the video compression module to compress an image frame.

[0008] In an exemplary embodiment, the video compression module further includes: a color space conversion module for performing color space conversion on the video data, wherein the color space conversion includes converting the color channel data in the video data into luminance-chrominance data; a data block generation module for converting the video data after the color space conversion into video data in a data block format; a video core compression module for compressing the video data in the data block format into the compressed video data.

[0009] In an exemplary embodiment, the video compression module further includes: a storage array for storing the video data in the data block format; wherein, the size of the storage array is determined by the storage array depth, and when the video core compression module compresses the video data of the current image frame, it only obtains the video data in the data block format corresponding to the current image frame from the storage array.

[0010] In an exemplary embodiment, the storage array depth determination module includes: a hardware compression time acquisition module, configured to acquire the time taken by the video core compression module to compress a first image frame multiple times in a real environment, where the resolution of the first image frame is less than a preset resolution; a simulation compression time acquisition module, configured to acquire the time taken by the video core compression module to compress the first image frame multiple times in a simulation environment, and to acquire the time taken by the video core compression module to compress a second image frame multiple times in the simulation environment, where the resolution of the second image frame is greater than the preset resolution, and the simulation compression time acquisition module is configured with the compression times of multiple first image frames and the compression times of multiple second image frames.

[0011] In an exemplary embodiment, the storage array depth determination module further includes: a hardware compression time calculation module, configured to calculate a target time according to the time taken by the video core compression module to compress the first image frame multiple times in the real environment, the time taken by the video core compression module to compress the first image frame multiple times in the simulation environment, and the time taken by the video core compression module to compress the second image frame multiple times in the simulation environment, where the target time represents the calculated time taken by the video core compression module to compress the second image frame in the real environment; a storage array write speed calculation module, configured to calculate the target data write speed of the storage array within a preset time period when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, where the target data volume represents the data write volume of the storage array within the preset time period when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; a storage array depth calculation module, configured to calculate the storage array depth according to the target time and the target data write speed.

[0012] In an exemplary embodiment, the frequency determination module includes: a system response time test module, configured to test the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, where a frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are both lower than a preset frequency; a peripheral delay time test module, configured to test the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times.

[0013] In an exemplary embodiment, the frequency determination module further includes: a simulation frequency combination determination module, configured to test the minimum latency time of the peripheral module under multiple second frequency combinations in a simulation environment, and determine the frequency combination corresponding to the minimum latency time, where the value ranges of the processor frequency and the system bus frequency in the multiple second frequency combinations are all frequency ranges; a frequency combination determination module, configured to calculate a minimum response time and a target frequency combination corresponding to the minimum response time according to the multiple response times, the multiple latency times, the minimum latency time, and the frequency combination corresponding to the minimum latency time, where the target frequency combination includes a target processor frequency and a target system bus frequency.

[0014] According to another embodiment of the present application, a method for determining parameters of a storage application chip is provided, which is applied to the above-mentioned hardware system for determining parameters of a storage application chip. The system includes a storage application chip, and the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, and a storage controller. The parameters of the storage application chip include: a processor frequency, a system bus frequency, and a storage array depth of the video compression module. The method includes: determining the processor frequency and the system bus frequency according to a response time and a latency time, where the response time represents the response time of an operating system running on the processor, and the latency time represents the latency time of a peripheral module connected to the processor through the system bus; determining the storage array depth according to the time for the video compression module to compress an image frame; adjusting the parameters of the storage application chip according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes video data into compressed video data after parameter adjustment.

[0015] In an exemplary embodiment, the video compression module includes a video core compression module and a storage array. Determining the depth of the storage array according to the time for the video compression module to compress an image frame includes: obtaining the time for the video core compression module to compress a first image frame multiple times in a real environment, where the resolution of the first image frame is less than a preset resolution; obtaining the time for the video core compression module to compress the first image frame multiple times in a simulation environment, and obtaining the time for the video core compression module to compress a second image frame multiple times in the simulation environment, where the resolution of the second image frame is greater than the preset resolution, and the compression times of multiple first image frames and multiple second image frames have been configured in the simulation compression time acquisition module; calculating a target time according to the time for the video core compression module to compress the first image frame multiple times in the real environment, the time for the video core compression module to compress the first image frame multiple times in the simulation environment, and the time for the video core compression module to compress the second image frame multiple times in the simulation environment, where the target time represents the calculated time for the video core compression module to compress the second image frame in the real environment; calculating the target data writing speed of the storage array within a preset duration when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, where the target data volume represents the data writing volume of the storage array within the preset duration when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; calculating the depth of the storage array according to the target time and the target data writing speed.

[0016] In an exemplary embodiment, the target time is calculated by the following formula: ; where represents the target time, represents the time for the video core compression module to compress the first image frame for the first time in the real environment, represents the time for the video core compression module to compress the first image frame for the Nth time in the real environment, represents the time for the video core compression module to compress the first image frame for the first time in the simulation environment, represents the time for the video core compression module to compress the first image frame for the Nth time in the simulation environment, represents the time for the video core compression module to compress the second image frame for the first time in the simulation environment, represents the time for the video core compression module to compress the second image frame for the Nth time in the simulation environment, and N is a positive integer.

[0017] In an exemplary embodiment, determining the processor frequency and the system bus frequency according to the response time and the latency time includes: testing the response time of the operating system at a plurality of first frequency combinations in a real environment to obtain a plurality of response times, where a frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the plurality of first frequency combinations are both lower than a preset frequency; testing the latency time of the peripheral module at the plurality of first frequency combinations in a simulation environment to obtain a plurality of latency times; testing the minimum latency time of the peripheral module at a plurality of second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum latency time, where the value ranges of the processor frequency and the system bus frequency in the plurality of second frequency combinations are all frequency ranges; calculating a minimum response time and a target frequency combination corresponding to the minimum response time according to the plurality of response times, the plurality of latency times, the minimum latency time, and the frequency combination corresponding to the minimum latency time, where the target frequency combination includes a target processor frequency and a target system bus frequency.

[0018] In an exemplary embodiment, the minimum response time is calculated by the following formula: ; where represents the minimum response time, represents the minimum latency time, represents the response time of the operating system at the first first frequency combination in a real environment, represents the response time of the operating system at the Mth first frequency combination in a real environment, represents the latency time of the peripheral module at the first first frequency combination in a simulation environment, represents the latency time of the peripheral module at the Mth first frequency combination in a simulation environment, and M is a positive integer.

[0019] According to another embodiment of the present application, there is also provided a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any one of the above method embodiments when running.

[0020] According to another embodiment of the present application, there is also provided an electronic device including a memory and a processor, where the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any one of the above method embodiments.

[0021] According to another embodiment of the present application, a computer program product is further provided, including a computer program, and when the computer program is executed by a processor, the steps in the above method embodiment are implemented.

[0022] Through the present application, the processor frequency and the system bus frequency can be determined according to the response time and the latency time, where the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of the peripheral module connected to the processor through the system bus; the storage array depth is determined according to the time for the video compression module to compress the image frame; the storage application chip is parameter-adjusted according to the processor frequency, the system bus frequency, and the storage array depth, so that after the parameter adjustment, the storage application chip processes the video data into compressed video data. Therefore, the problem of how to accurately determine the parameters of the storage application chip in the related art can be solved, and then the design parameters of the chip can be optimized, and the storage resources of the chip can be fully utilized. Specifically, by determining the most suitable combination of the CPU frequency and the system bus frequency of the chip, the occupation of the RAM (Random Access Memory) resources by the video function of the chip is reduced, while accurately meeting the user requirements, reducing the overall power consumption of the storage application chip, and greatly reducing the cost of the chip project. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a structural block diagram of a hardware system for determining parameters of a storage application chip according to an embodiment of the present application;

[0024] Figure 2 is a structural block diagram of a storage application chip according to an embodiment of the present application;

[0025] Figure 3 is a schematic diagram of a data block conversion process according to an embodiment of the present application;

[0026] Figure 4 is a structural block diagram of a video compression module according to an embodiment of the present application;

[0027] Figure 5 is a structural block diagram of a storage array depth determination module according to an embodiment of the present application;

[0028] Figure 6 is a structural block diagram of a frequency determination module according to an embodiment of the present application;

[0029] Figure 7 is a flowchart of a method for determining parameters of a storage application chip according to an embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0030] Embodiments of the present application will be described in detail below with reference to the accompanying drawings and in conjunction with the embodiments.

[0031] It should be noted that the terms "first", "second", etc. in the specification, claims and the above-mentioned drawings of the present application are used to distinguish similar objects and do not necessarily have to be used to describe a specific order or sequence.

[0032] According to an embodiment of the present application, a hardware system for determining parameters of a storage application chip, the system includes: a server host for sending video data to the storage application chip; the storage application chip for determining parameters of the storage application chip, adjusting the parameters of the storage application chip according to the determined parameters, and processing the video data into compressed video data after parameter adjustment; a storage hard disk for receiving the compressed video data; wherein, the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; the video graphics array module is used to receive the video data sent by the server host and transmit the video data to the video compression module of the storage application chip; the video compression module is used to process the video data into the compressed video data and transmit the compressed video data to the storage controller through the system bus; the storage controller is used to send the compressed video data to the storage hard disk; wherein, the video compression module includes a storage array depth determination module; the parameters of the storage application chip include: processor frequency, system bus frequency, and storage array depth of the video compression module; the frequency determination module is used to determine the processor frequency and the system bus frequency according to the response time and the delay time, wherein the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of the peripheral module connected to the processor through the system bus; the storage array depth determination module is used to determine the storage array depth according to the time for the video compression module to compress an image frame.

[0033] In an alternative embodiment, as Figure 1As shown in the figure, the parameter determination hardware system of the above storage application chip includes a HOST host (equivalent to a server host), a storage application chip integrated with video functions (equivalent to a storage application chip), and a DDR storage hard disk (equivalent to a storage hard disk). Among them, the storage application chip integrated with video functions specifically includes a VGA (Video Graphics Array) module, a video compression module, a frequency determination module, a system bus, a CPU (equivalent to a processor), a DDR (Double Data Rate) storage controller (equivalent to a storage controller), and a DDR storage hard disk (equivalent to a storage hard disk); peripheral modules such as a UART (Universal Asynchronous Receiver / Transmitter) interface module, an IIC (Inter-Integrated Circuit) interface module, a USB (Universal Serial Bus) module, and a network module are connected to the processor through the system bus, and a software program for server management and control runs on the processor CPU.

[0034] During the video transmission process, the video data on the operating system of the server host is input into the storage application chip integrated with video functions through a PCIe (Peripheral Component Interconnect Express) interface. After being processed by the VGA module of the server host, the video data in RGB format is output to the video compression module, and the video compression module processes the video data into compressed video data, and then writes the compressed video data into the external DDR storage hard disk through the storage controller.

[0035] Optionally, in the above embodiment, for example, the server management control chip is a typical storage application chip integrated with video functions. In the server field, the server management control chip is used to monitor the status of the server (temperature, fan, CPU operation, etc.), and at the same time, it has an important function, that is, to transmit the local video information to the remote end through the network for video display and monitoring at the remote end. It should be noted that the solution of this application is not limited to being applied to the server management control chip, but can also be applied to any storage application chip integrated with video processing functions.

[0036] In an exemplary embodiment, the video compression module further includes: a color space conversion module for performing color space conversion on the video data, wherein the color space conversion includes converting the color channel data in the video data into luminance-chrominance data; a data block generation module for converting the video data after color space conversion into video data in a data block format; and a video core compression module for compressing the video data in the data block format into the compressed video data.

[0037] Optionally, in the above embodiment, as Figure 2 shown, the video compression module specifically includes a color space conversion module, a data block generation module, a video core compression module, and a storage array depth determination module. After the video data of the server host is processed by the VGA module, the output is RGB-format video data (equivalent to color channel data). The RGB-format data is input to the color space conversion module to convert the RGB-format video data into YUV-format video data (equivalent to luminance-chrominance data). The specific conversion formula is as follows:

[0038] Y = 0.257R + 0.504G + 0.098B + 16;

[0039] U = 0.148R – 0.291G + 0.439B + 128;

[0040] V = 0.439R - 0.368G - 0.071B + 128;

[0041] wherein, R represents the value of the red channel in the color channel data, G represents the value of the green channel in the color channel data, B represents the value of the blue channel in the color channel data, Y represents the value of the luminance in the luminance-chrominance data, U represents the value of the blue chrominance in the luminance-chrominance data, and V represents the value of the red chrominance in the luminance-chrominance data.

[0042] After the color space conversion module converts the RGB-format video data into YUV-format video data, the database generation module performs a BLOCK (data block) conversion on the YUV-format video data. During the conversion process, by Figure 2The write control module in writes data to the data block generation module, and the read control module reads data from the data block generation module. The size of the BLOCK can be 16*16, 16*8, or 8*8 according to the three different formats of YUV444 / YUV422 / YUV420. Therefore, 16 Y_FIFOs, 16 U_FIFOs, and 16 V_FIFOs are required for data caching. FIFO is a special data structure, short for "First-In, First-Out", that is, "first in, first out", and is used to store and manage data in a program to ensure that data is read out in the order it was written. In this embodiment, multiple FIFOs are used to store the data of the Y, U, and V components respectively.

[0043] In an alternative embodiment, the process of BLOCK conversion is as Figure 3 shown. The grid on the left is equivalent to multiple data blocks in YUV format ( Figure 3 the BLOCK in ), and the size of each data block is 8*8 or 16*16 pixels. Through the above method, the video data can be divided into multiple data blocks. According to the brightness, red chrominance, and blue chrominance of the pixels, it can be divided into 3 components: Y, U, and V.

[0044] Among them, for multiple rows of pixels in the left video data, in the YUV420 format, all Y data is written, and the U and V data of even rows and even columns are written. Therefore, in the processed data block format, the height and width of the data block representing the Y component remain unchanged, while the height and width of the data blocks representing the U and V components are reduced to 1 / 2 of the original.

[0045] In the YUV422 format, all Y data is written, but for the U and V data, only one of every two pixels needs to be written. Specifically, the U and V components are stored alternately, and each U (or V) value corresponds to two Y values, which means that the sampling rate of the U and V data is half of the sampling rate of the Y component. This format samples all Y components horizontally, but maintains the same sampling rate as the Y component vertically. Therefore, the height and width of the data block of the Y component remain unchanged because the Y component contains information for each row and column of the image. The width of the data blocks representing the U and V components is reduced to half of the original because each U and V value corresponds to two pixels horizontally. However, the height remains unchanged because the U and V components match the number of rows of the Y component vertically.

[0046] In the YUV444 format, all rows and columns of Y / U / V data need to be written when writing data. Therefore, in the processed data block format, the height and width of the data blocks representing the Y, U, and V components remain unchanged.

[0047] In an exemplary embodiment, the video compression module further includes: a storage array for storing video data in the data block format; wherein, the size of the storage array is determined by the depth of the storage array, and when compressing the video data of the current image frame, the video core compression module only obtains the video data in the data block format corresponding to the current image frame from the storage array.

[0048] Optionally, in the above embodiment, as Figure 2 shown, after obtaining the video data in the data block format, the video data is input into the video core compression module for compression processing. During the compression process of the current image frame, the video core compression module does not receive the writing of the next frame of data, and the video data after the current image frame is stored in the storage array. Therefore, in the design, to avoid the loss of the data of the subsequent frame, the depth of the storage array is generally set very deep, and in the present application, the depth of the storage array can be determined by the storage array depth determination module according to the time for the video compression module to compress the image frame.

[0049] In an exemplary embodiment, the storage array depth determination module includes: a hardware compression time acquisition module for acquiring the time for the video core compression module to compress the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; a simulation compression time acquisition module for acquiring the time for the video core compression module to compress the first image frame multiple times in a simulation environment, and for acquiring the time for the video core compression module to compress the second image frame multiple times in the simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the compression times of multiple first image frames and multiple second image frames are configured in the simulation compression time acquisition module.

[0050] In an exemplary embodiment, the storage array depth determination module further includes: a hardware compression time calculation module, configured to calculate a target time according to the time for the video core compression module to compress the first image frame multiple times in a real environment, the time for the video core compression module to compress the first image frame multiple times in a simulation environment, and the time for the video core compression module to compress the second image frame multiple times in the simulation environment, where the target time represents the calculated time for the video core compression module to compress the second image frame in the real environment; a storage array write speed calculation module, configured to calculate the target data write speed of the storage array within a preset duration when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, where the target data volume represents the data write volume of the storage array within the preset duration when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; a storage array depth calculation module, configured to calculate the storage array depth according to the target time and the target data write speed.

[0051] Optionally, in the above embodiment, as Figure 4 shown, the storage array depth determination module includes:

[0052] Hardware Compression Time Acquisition Module: Obtain the time taken by the video core compression module to compress low-resolution image frames in a low-resolution scenario that can be tested on the actual hardware environment of the storage application chip (such as resolutions 640*480, 800*600, 1024*768, etc., where the resolution does not exceed the maximum resolution that can be tested on the actual hardware environment (equivalent to the preset resolution)). Denote these times as T_L_H_0, T_L_H_1... T_L_H_N-1 respectively. Here, L (Low) represents low resolution, H (Hard) represents hardware, T_L_H represents the low-resolution hardware environment, and N represents the number of statistical times. T_L_H_0, T_L_H_1... T_L_H_N-1 are equivalent to the times taken by the video core compression module to compress the first image frame multiple times in the simulation environment. The resolution of the first image frame is, for example, an image frame with a resolution of 640*480, 800*600, or 1024*768. In this module, use the resolution information and the YUV format (YUV444 / YUV420 / YUV422) to calculate the total number of data blocks of the current image frame, and simultaneously detect the compression frame tail flag at the output end of the video core compression module (such as FFD9 for the number of JPEGs, etc.) to determine when it is the last data block of the previous frame and when the compression of the current frame is completed. Count the number of clock cycles T_num within the time period from the last data block of the previous frame to the completion of the compression of the current frame, and multiply it by the duration T_length of each clock cycle (such as when the frequency is 50M, the duration of the corresponding clock cycle is 1000 / 50 = 20ns). T_num * T_length is the statistical time.

[0053] Simulation Compression Time Acquisition Module: In this module, configure the times taken by the video core compression module to compress low-resolution image frames and high-resolution image frames respectively in the simulation software, where high resolution means exceeding the maximum resolution that can be tested on the actual hardware environment of the storage application chip. It should be noted that the specific simulation process is completed by the user in advance, and what is configured in this module is only the compression time obtained from the simulation results. Among them, the time taken to compress low-resolution image frames (equivalent to the first image frame) is denoted as T_L_S_0, T_L_S_1... T_L_S_N-1, and the time taken to compress high-resolution image frames (equivalent to the second image frame) is denoted as T_H_S_0, T_H_S_1... T_H_S_N-1. Here, L (Low) represents low resolution, H (High) represents high resolution, S (Simulation) represents software simulation, T_L_S represents the low-resolution simulation environment, and T_H_S represents the high-resolution simulation environment.

[0054] Hardware Compression Time Calculation Module: Receive the time for the storage application chip to compress low-resolution image frames in a real hardware environment, as well as the time for compressing low-resolution image frames in a simulation environment and the time for compressing high-resolution image frames in a simulation environment. Calculate the estimated time for compressing high-resolution image frames in a real hardware environment (equivalent to the target time) based on the above times. The specific calculation formula is as follows:

[0055] , where represents the target time, represents the time for the video core compression module to compress the first image frame for the first time in a real environment, represents the time for the video core compression module to compress the first image frame for the Nth time in a real environment, represents the time for the video core compression module to compress the first image frame for the first time in a simulation environment, represents the time for the video core compression module to compress the first image frame for the Nth time in a simulation environment, represents the time for the video core compression module to compress the second image frame for the first time in a simulation environment, represents the time for the video core compression module to compress the second image frame for the Nth time in a simulation environment, where N is a positive integer.

[0056] Storage Array Write Speed Calculation Module: Estimate the write speed of video data in a high-resolution scenario. Statistically calculate the amount of data written to the storage array within the T time period in a low-resolution scenario, which is data_num_0, data_num_1... data_num_N-1 (in bytes). Among them, the pixel clock corresponding to low resolution is pixel_clk_L (equivalent to the first pixel clock), and the pixel clock corresponding to high resolution is pixel_clk_H (equivalent to the second pixel clock). Both of the above pixel clocks are standard known quantities. Then, the calculation formula for the data write speed Wr_Speed_H_estimate of the storage array within the T time period is as follows:

[0057] .

[0058] Storage Array Depth Calculation Module: Calculate the depth of the storage array in a high-resolution scenario based on the time T_H_H_estimate for compressing high-resolution image frames in a real hardware environment and the calculated data write speed Wr_Speed_H_estimate of the storage array in a high-resolution scenario. The calculation formula is as follows:

[0059] ,

[0060] Among them, Array_Width is the width of the storage array, and the widths set for different specifications of SoC chips can be different, such as 8 or 16, etc. Array_Depth_estimate is the calculated depth of the storage array. It should be noted that for different chip projects, the highest resolution to be supported is different. For example, the high-resolution value that a storage application chip needs to support is 1920*1200, while an imaging dedicated display chip may support a 4K resolution, that is, a resolution of 4096×2160. Therefore, this application can calculate the most suitable storage array depth for different SoC chip projects and different application scenarios of different customers. Therefore, the technical solution of this patent has extremely strong application flexibility.

[0061] In an exemplary embodiment, the frequency determination module includes: a system response time test module, configured to test the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, where the frequency combination represents the combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are both lower than a preset frequency; a peripheral delay time test module, configured to test the delay time of the peripheral module under the multiple first frequency combinations in a simulation environment to obtain multiple delay times.

[0062] In an exemplary embodiment, the frequency determination module further includes: a simulation frequency combination determination module, configured to test the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determine the frequency combination corresponding to the minimum delay time, where the value ranges of the processor frequency and the system bus frequency in the multiple second frequency combinations are all frequency ranges; a frequency combination determination module, configured to calculate a minimum response time and the target frequency combination corresponding to the minimum response time according to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, where the target frequency combination includes a target processor frequency and a target system bus frequency.

[0063] Optionally, in the above embodiment, as Figure 5 shown, the frequency determination module includes:

[0064] System response time test module, which tests the response time of the operating system corresponding to different CPU main frequencies (equivalent to the processor frequency) and system bus frequency combinations of the storage application chip in a real hardware environment. The operating system runs on the CPU. It should be noted that only frequency combinations in the low-frequency range (equivalent to multiple first frequency combinations below the preset frequency) can be tested in the real hardware environment. The response time of the operating system refers to the system response time when the operating system and the application program are running simultaneously. This response time reflects the impact of the CPU main frequency and the system bus frequency on the system performance of the chip in a real hardware environment. Different application programs are used in different chips. Therefore, this application can be applied to the determination of the optimal CPU main frequency and system bus frequency combinations for different chips, with strong application flexibility. After testing, a system response time mapping table corresponding to different low-frequency range CPU main frequencies and system bus frequency combination modes can be created inside the module according to the test results, as shown in Table 1 specifically.

[0065] Table 1

[0066]

[0067] Peripheral delay time test module, which tests the delay time of the peripheral module corresponding to different CPU main frequencies and system bus frequency combinations in a simulation environment. The tested frequency combinations are the same as those tested by the above system response time test module, both being low-frequency combinations. For example, if the peripheral module is a network module, the delay time refers to the delay value (equivalent to the delay time) of the process of the network module and others sending data from software to the DDR storage hard disk, then the network module reading the DDR storage hard disk to obtain the sent data, and then through the internal processing of the network module to form a network frame format. After testing, a mapping table of the CPU main frequency and system bus frequency combination and the delay value in the simulation environment can be created inside the module according to the test results, as shown in Table 2 specifically.

[0068] Table 2

[0069]

[0070] The simulation frequency combination determination module tests the delay values of the peripheral module under different combinations of CPU main frequencies and system bus frequencies in the simulation environment. The tested frequency combinations include high-frequency combinations that the FPGA cannot test in the real hardware environment (equivalent to multiple second frequency combinations within all frequency ranges). When both the CPU main frequency and the system bus frequency are relatively low, as the CPU main frequency and the system bus frequency increase, the delay value of the peripheral module decreases accordingly. When the CPU main frequency increases to near a certain high-frequency value, further increasing the CPU main frequency has almost no effect on improving the delay value of the peripheral module. Then, fix this CPU main frequency value to obtain the optimal CPU main frequency CPU_FREQ_BEST. Next, increase the system bus frequency value. When increasing the system bus frequency value also has almost no effect on improving the delay value of the peripheral module, fix this system bus frequency value to obtain the optimal system bus frequency SYS_BUS_FREQ_BEST. The frequency combination of the optimal CPU main frequency CPU_FREQ_BEST and the optimal system bus frequency SYS_BUS_FREQ_BEST is the optimal frequency combination (equivalent to the frequency combination corresponding to the minimum delay time), and the delay value DELAY_BEST corresponding to this frequency combination is the minimum delay time.

[0071] The frequency combination determination module, based on the test results of the system response time test module and the peripheral delay time test module, establishes the correspondence between the system response time in the real hardware environment under the low-frequency combination and the delay value of the peripheral module in the simulation environment. Then, based on the optimal frequency combination in the simulation environment obtained by the simulation frequency combination determination module, that is, the optimal CPU main frequency CPU_FREQ_BEST and the optimal system bus frequency SYS_BUS_FREQ_BEST, further infer the minimum system response time corresponding to the optimal frequency combination in the real hardware environment. The calculation formula is as follows:

[0072] ;

[0073] Wherein, represents the minimum response time, represents the minimum delay time, represents the response time of the operating system in the real environment under the first first frequency combination, represents the response time of the operating system in the real environment under the Mth first frequency combination, represents the delay time of the peripheral module in the simulation environment under the first first frequency combination, represents the delay time of the peripheral module in the simulation environment under the Mth first frequency combination, and M is a positive integer.

[0074] Optionally, in the above embodiments, after calculating the system response time corresponding to the optimal frequency combination, if the system response time meets the project requirements, the CPU main frequency and system bus frequency of the storage application chip are set according to the optimal CPU main frequency CPU_FREQ_BEST and the optimal system bus frequency SYS_BUS_FREQ_BEST. If the requirements are not met, a set of efficient combinations of CPU main frequency and system bus frequency are continuously tested in the simulation environment, and the system response time corresponding to this combination is continuously calculated using the above formula.

[0075] In an alternative embodiment, after obtaining the optimal CPU main frequency, system bus frequency, and the optimal storage array depth in the above text, the designer modifies the design parameters of the storage application chip according to the above parameters. Specifically, as Figure 6 shown, it includes the following steps:

[0076] 1. RTL code development:

[0077] RTL (Register Transfer Level) is a description method of hardware description language (such as Verilog or VHDL) at a higher abstraction level. In this stage, the designer writes code using a hardware description language to define the behavior of digital circuits.

[0078] 2. RTL code simulation:

[0079] Use simulation software (such as ModelSim, VCS, or Vivado simulation tools) to simulate the behavior of RTL code under various conditions. Through simulation, the designer can test and verify whether the function of the circuit meets the expectations without actual hardware. This stage can detect circuit logic errors, timing issues, and performance bottlenecks. For example, in this embodiment, the optimal CPU main frequency and system bus frequency of the chip are obtained by determining the performance bottleneck.

[0080] 3. FPGA prototype verification:

[0081] An FPGA is a reprogrammable programmable logic circuit chip that can implement different functions by loading different logic circuit configurations. In the field of chip design, FPGA prototype verification is an essential process. After synthesizing the code of the chip design, an FPGA configuration file corresponding to the function is generated. In this way, the logical function of the chip code runs on the FPGA to verify the functional correctness of the design code and the performance of the system, etc. At this stage, the above-mentioned determined optimal CPU main frequency, system bus frequency, storage array depth and other parameters can be verified. If the verification passes, the backend design chip tape-out enters the next stage. If the verification does not meet the requirements, parameter adjustment is required, and steps 1-3 are repeated to determine the parameters that meet the requirements.

[0082] 4. Backend Design Chip Tape-out:

[0083] After determining the various parameters of the chip, backend design is carried out, specifically including layout, wiring, timing analysis, power consumption analysis, etc. After the design is completed, chip tape-out is performed. Tape-out means sending the designed circuit diagram to the manufacturing factory to fabricate the actual silicon chip. After successful tape-out, the actual chips are obtained, and these chips will be put into products for use.

[0084] Through the above embodiments, it is more convenient for chip designers to determine the chip parameters that meet the requirements, thereby reducing the situation of chip performance waste or chip performance not meeting the standards caused by inappropriate chip parameters.

[0085] In this embodiment, a method for determining the parameters of a storage application chip is also provided, which is applied to the hardware system for determining the parameters of the above storage application chip. Figure 7 It is a flowchart of the method for determining the parameters of the storage application chip according to the embodiment of the present application, as Figure 7 shown, and this process includes the following steps:

[0086] Step S702, determining the processor frequency and the system bus frequency according to the response time and the latency time, where the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of the peripheral module connected to the processor through the system bus;

[0087] Step S704, determining the storage array depth according to the time for the video compression module to compress the image frame;

[0088] Step S706, adjusting the parameters of the storage application chip according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after parameter adjustment.

[0089] Through the above steps, the processor frequency and the system bus frequency can be determined according to the response time of the operating system running on the processor and the latency of the peripheral modules connected to the processor through the system bus. Then, the storage array depth can be determined according to the time taken by the video compression module to compress the image frames. Finally, the parameters of the storage application chip are adjusted according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment. Therefore, the problem of how to accurately determine the parameters of the storage application chip in the related art can be solved.

[0090] In an exemplary embodiment, the video compression module includes a video core compression module and a storage array. Determining the storage array depth according to the time taken by the video compression module to compress the image frames includes: obtaining the time taken by the video core compression module to compress a first image frame multiple times in a real environment, where the resolution of the first image frame is less than a preset resolution; obtaining the time taken by the video core compression module to compress the first image frame multiple times in a simulation environment, and obtaining the time taken by the video core compression module to compress a second image frame multiple times in the simulation environment, where the resolution of the second image frame is greater than the preset resolution, and the compression time acquisition module in the simulation environment has configured the compression times of multiple first image frames and multiple second image frames; calculating a target time according to the time taken by the video core compression module to compress the first image frame multiple times in the real environment, the time taken by the video core compression module to compress the first image frame multiple times in the simulation environment, and the time taken by the video core compression module to compress the second image frame multiple times in the simulation environment, where the target time represents the calculated time taken by the video core compression module to compress the second image frame in the real environment; calculating the target data writing speed of the storage array within a preset duration when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, where the target data volume represents the data writing volume of the storage array within the preset duration when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; calculating the storage array depth according to the target time and the target data writing speed.

[0091] In an exemplary embodiment, the target time is calculated by the following formula: ; where represents the target time, represents the time taken by the video core compression module to compress the first image frame for the first time in the real environment, Indicates the time when the video core compression module compresses the first image frame for the Nth time in the real environment. Indicates the time when the video core compression module compresses the first image frame for the first time in the simulation environment. Indicates the time when the video core compression module compresses the first image frame for the Nth time in the simulation environment. Indicates the time when the video core compression module compresses the second image frame for the first time in the simulation environment. Indicates the time when the video core compression module compresses the second image frame for the Nth time in the simulation environment, where N is a positive integer.

[0092] In an exemplary embodiment, determining the processor frequency and the system bus frequency according to the response time and the delay time includes: testing the response time of the operating system under multiple first frequency combinations in the real environment to obtain multiple response times, where the frequency combination represents the combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are both lower than the preset frequency; testing the delay time of the peripheral module under the multiple first frequency combinations in the simulation environment to obtain multiple delay times; testing the minimum delay time of the peripheral module under multiple second frequency combinations in the simulation environment, and determining the frequency combination corresponding to the minimum delay time, where the value ranges of the processor frequency and the system bus frequency in the multiple second frequency combinations are all frequency ranges; calculating the minimum response time and the target frequency combination corresponding to the minimum response time according to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, where the target frequency combination includes the target processor frequency and the target system bus frequency.

[0093] In an exemplary embodiment, the minimum response time is calculated by the following formula: ; where represents the minimum response time, represents the minimum delay time, represents the response time of the operating system under the first first frequency combination in the real environment, represents the response time of the operating system under the Mth first frequency combination in the real environment, represents the delay time of the peripheral module under the first first frequency combination in the simulation environment, represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

[0094] Embodiments of the present application further provide a computer-readable storage medium storing a computer program, where the computer program is configured to execute the steps in any of the above method embodiments when running.

[0095] Optionally, in this embodiment, the above storage medium may be configured to store program code for executing the following steps:

[0096] S1. Determine the processor frequency and the system bus frequency according to the response time and the latency time, where the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of a peripheral module connected to the processor through the system bus;

[0097] S2. Determine the storage array depth according to the time taken by the video compression module to compress an image frame;

[0098] S3. Adjust the parameters of the storage application chip according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes video data into compressed video data after the parameter adjustment.

[0099] In an exemplary embodiment, the above computer-readable storage medium may include, but is not limited to, various media capable of storing a computer program, such as a USB flash drive, a read-only memory (ROM for short), a random access memory (RAM for short), a mobile hard disk, a magnetic disk, or an optical disc.

[0100] Embodiments of the present application further provide an electronic device, including a memory and a processor, where the memory stores a computer program, and the processor is configured to run the computer program to execute the steps in any of the above method embodiments.

[0101] Optionally, in this embodiment, the above processor may be configured to execute the following steps through a computer program:

[0102] S1. Determine the processor frequency and the system bus frequency according to the response time and the latency time, where the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of a peripheral module connected to the processor through the system bus;

[0103] S2. Determine the storage array depth according to the time taken by the video compression module to compress an image frame;

[0104] S3. Adjust the parameters of the storage application chip according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes video data into compressed video data after the parameter adjustment.

[0105] An embodiment of the present application also provides a computer program product. The computer program product includes a computer program, and when the computer program is executed by a processor, the steps in any of the above method embodiments are implemented.

[0106] Optionally, in this embodiment, the above computer program may be set to execute the following steps through the computer program:

[0107] S1. Determine the processor frequency and the system bus frequency according to the response time and the latency time, where the response time represents the response time of the operating system running on the processor, and the latency time represents the latency time of a peripheral module connected to the processor through the system bus;

[0108] S2. Determine the storage array depth according to the time for the video compression module to compress an image frame;

[0109] S3. Adjust the parameters of the storage application chip according to the processor frequency, the system bus frequency, and the storage array depth, so that the storage application chip processes video data into compressed video data after the parameter adjustment.

[0110] Specific examples in this embodiment may refer to the examples described in the above embodiments and exemplary embodiments, and will not be repeated here.

[0111] Obviously, those skilled in the art should understand that the above modules or steps of the present application can be implemented by a general-purpose computing device. They can be concentrated on a single computing device or distributed on a network composed of multiple computing devices. They can be implemented by program codes executable by the computing device, so that they can be stored in a storage device and executed by the computing device. And in some cases, the steps shown or described can be executed in a different order than here, or they can be separately fabricated into individual integrated circuit modules, or multiple modules or steps among them can be fabricated into a single integrated circuit module to implement. In this way, the present application is not limited to any specific combination of hardware and software.

[0112] The above are only the preferred embodiments of the present application and are not used to limit the present application. For those skilled in the art, the present application can have various changes and modifications. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application shall be included in the protection scope of the present application.

Claims

1. A hardware system for determining parameters of a storage application chip, characterized in that: The system comprises: A server host, used for sending video data to a storage application chip; The storage application chip is used to determine parameters of the storage application chip, adjust the parameters of the storage application chip according to the determined parameters, and process the video data into compressed video data after the parameter adjustment; A storage hard disk, used for receiving the compressed video data; Wherein, the storage application chip includes a video graphics array module, a video compression module, a system bus, a processor, a storage controller, and a frequency determination module; The video graphics array module is used to receive the video data sent by the server host, and transmit the video data to the video compression module of the storage application chip; The video compression module is used to process the video data into the compressed video data, and transmit the compressed video data to the storage controller through the system bus; The storage controller is used to send the compressed video data to the storage hard disk; Wherein, the video compression module includes a storage array depth determination module; The parameters of the storage application chip include: processor frequency, system bus frequency, and storage array depth of the video compression module; The frequency determination module is used to determine the processor frequency and the system bus frequency according to the response time of multiple frequency combinations in a real environment and the delay time of multiple frequency combinations in a simulation environment, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, the response time represents the response time of the operating system running on the processor, and the delay time represents the delay time of a peripheral module connected to the processor through the system bus; The storage array depth determination module is used to determine the storage array depth according to the time taken by the video compression module to compress the first image frame in a real environment, the time taken to compress the first image frame in a simulation environment, the time taken to compress the second image frame in a simulation environment, and the storage array write speed of the video compression module, wherein the resolution of the first image frame is less than a preset resolution, and the resolution of the second image frame is greater than the preset resolution.

2. The system according to claim 1, characterized in that The video compression module also includes: A color space conversion module, used for performing color space conversion on the video data, wherein the color space conversion includes converting color channel data in the video data into brightness and chrominance data; A data block generation module, used for converting the video data after the color space conversion into video data in a data block format; The video core compression module is used to compress the video data in the data block format into the compressed video data.

3. The system according to claim 2, characterized in that The video compression module also includes: A storage array, used for storing the video data in the data block format; The size of the storage array is determined by the depth of the storage array, and when compressing the video data of the current image frame, the video core compression module only obtains the video data in the data block format corresponding to the current image frame from the storage array.

4. The system according to claim 3, characterized in that The storage array depth determination module comprises: A hardware compression time acquisition module, used for acquiring the time when the video core compression module compresses the first image frame multiple times in a real environment; A simulation compression time acquisition module is used to obtain the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and to obtain the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the simulation compression time acquisition module has been configured with the compression time of multiple first image frames and the compression time of multiple second image frames.

5. The system according to claim 4, characterized in that The storage array depth determination module further includes: a hardware compression time calculation module, used to calculate a target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; a storage array write speed calculation module, configured to calculate a target data write speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, wherein the target data volume represents the data write volume of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; A storage array depth calculation module is used to calculate the storage array depth according to the target time and the target data writing speed.

6. The system according to claim 1, characterized in that The frequency determination module comprises: A system response time testing module, used for testing the response time of the operating system under a plurality of first frequency combinations in a real environment to obtain a plurality of response times, wherein the value ranges of the processor frequency and the system bus frequency in the plurality of first frequency combinations are all lower than a preset frequency; The peripheral delay time testing module is used to test the delay time of the peripheral module under the plurality of first frequency combinations in a simulation environment to obtain a plurality of delay times.

7. The system according to claim 6, characterized in that The frequency determination module further includes: A simulation frequency combination determination module, used for testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; A frequency combination determination module is used to calculate the minimum response time and the target frequency combination corresponding to the minimum response time based on the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

8. A method for determining parameters of a storage application chip, characterized in that: Applied to the system described in any one of claims 1 to 7, the system comprises a storage application chip, the storage application chip comprises a video graphics array module, a video compression module, a system bus, a processor, and a storage controller, the parameters of the storage application chip comprise: processor frequency, system bus frequency, and storage array depth of the video compression module, the method comprises: Determining the processor frequency and the system bus frequency according to a response time and a delay time, wherein the response time represents a response time of an operating system running on the processor, and the delay time represents a delay time of a peripheral module connected to the processor through the system bus; Determining the storage array depth according to the time taken by the video compression module to compress the image frame; The storage application chip is parameter-adjusted according to the processor frequency, the system bus frequency and the storage array depth, so that the storage application chip processes the video data into compressed video data after the parameter adjustment.

9. The method according to claim 8, characterized in that The video compression module includes a video core compression module and a storage array, and the depth of the storage array is determined according to the time for compressing the image frame by the video compression module, including: Acquire the time for the video core compression module to compress the first image frame multiple times in a real environment, wherein the resolution of the first image frame is less than a preset resolution; Acquire the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and acquire the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the resolution of the second image frame is greater than the preset resolution, and the compression time of multiple first image frames and the compression time of multiple second image frames are configured in the simulation compression time acquisition module; Calculate the target time according to the time when the video core compression module compresses the first image frame multiple times in a real environment, the time when the video core compression module compresses the first image frame multiple times in a simulation environment, and the time when the video core compression module compresses the second image frame multiple times in a simulation environment, wherein the target time represents the calculated time when the video core compression module compresses the second image frame in a real environment; Calculating a target data writing speed of the storage array within a preset time length when the video core compression module compresses the second image frame according to a target data volume, a first pixel clock, and a second pixel clock, wherein the target data volume represents the data writing volume of the storage array within the preset time length when the video core compression module compresses the first image frame, the first pixel clock represents the pixel clock corresponding to the first image frame, and the second pixel clock represents the pixel clock corresponding to the second image frame; The storage array depth is calculated according to the target time and the target data writing speed.

10. The method according to claim 9, characterized in that The target time is calculated by the following formula: , in, Indicates the target time, represents the time when the video core compression module first compresses the first image frame in a real environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a real environment, represents the time when the video core compression module first compresses the first image frame in the simulation environment, represents the time when the video core compression module compresses the first image frame for the Nth time in a simulation environment, represents the time when the video core compression module first compresses the second image frame in the simulation environment, It represents the time when the video core compression module compresses the second image frame for the Nth time in a simulation environment, where N is a positive integer.

11. The method according to claim 8, characterized in that Determining the processor frequency and the system bus frequency according to the response time and the delay time includes: Testing the response time of the operating system under multiple first frequency combinations in a real environment to obtain multiple response times, wherein the frequency combination represents a combination of the processor frequency and the system bus frequency, and the value ranges of the processor frequency and the system bus frequency in the multiple first frequency combinations are all lower than a preset frequency; Testing the delay time of the peripheral module under the plurality of first frequency combinations in a simulation environment to obtain a plurality of delay times; Testing the minimum delay time of the peripheral module under multiple second frequency combinations in a simulation environment, and determining the frequency combination corresponding to the minimum delay time, wherein the value range of the processor frequency and the system bus frequency in the multiple second frequency combinations is all frequency ranges; According to the multiple response times, the multiple delay times, the minimum delay time, and the frequency combination corresponding to the minimum delay time, the minimum response time and the target frequency combination corresponding to the minimum response time are calculated, wherein the target frequency combination includes a target processor frequency and a target system bus frequency.

12. The method according to claim 11, characterized in that The minimum response time is calculated by the following formula: ； in, Indicates the minimum response time, Indicates the minimum delay time, represents the response time of the operating system under the first frequency combination in a real environment, represents the response time of the operating system under the Mth first frequency combination in a real environment, represents the delay time of the peripheral module under the first frequency combination in the simulation environment, It represents the delay time of the peripheral module under the Mth first frequency combination in the simulation environment, where M is a positive integer.

13. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, wherein the computer program implements the steps of the method described in any one of claims 8 to 12 when executed by a processor.

14. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that: When the processor executes the computer program, the steps of the method described in any one of claims 8 to 12 are implemented.

15. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method described in any one of claims 8 to 12 are implemented.

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