Memory allocation method and related equipment

Abstract

The invention discloses a memory allocation method and related equipment, which are applied to electronic equipment, and the method comprises the following steps: receiving a first memory request of an application program, the first memory request comprising a target memory space value; determining a virtual address matched with the target memory space value from a virtual memory space, and determining a target virtual address to be mapped from the virtual address; a to-be-mapped target physical address is determined from a physical memory space, whether the target virtual address and the size and byte boundary of the target physical address meet a first condition is judged, and the first condition comprises the alignment type of the byte boundary; if the first condition is met, determining an attribute parameter matched with the first condition; and creating a page table matched with the attribute parameter, and establishing a mapping relationship between the target virtual address and the target physical address. By adopting the embodiment of the invention, the memory access efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the computer field, and in particular to a memory allocation method and related equipment. Background Art

[0002] With the development of computer technology, operating systems have also developed rapidly and have been applied to a variety of electronic products. With the help of operating systems, a large number of applications can be used. When applications run on operating systems, they need to use memory, so the efficiency of memory allocation will directly affect the user experience of using electronic products.

[0003] For example, various devices such as smartphones and tablets support memory page settings of multiple different granularities, such as 4KB, 16KB, and 64KB. L1, L2, and L3 page table entries refer to entries in the page table used for virtual address translation in the computer operating system, and they are closely related to the page granularity. When the page granularity is set to 4KB, the L1 page table entry can support page table entries for continuous physical memory of 1GB, the L2 page table entry can support page table entries for continuous physical memory of 2MB, and the L3 page table entry can support 16 consecutive pages represented by a single page table entry. The memory allocation performance can be improved by the above L1, L2, and L3 page table entries. However, in the prior art, memory pools of multiple different units are generally provided in memory resources. When performing address mapping, address mapping is usually performed according to a fixed page table entry size, which will lead to low memory access efficiency in some memory usage scenarios. For example, there are problems such as low addressing performance of the central processing unit (CPU) and high miss rate of the translation lookaside buffer (TLB). Summary of the invention

[0004] The embodiments of the present application provide a memory allocation method and related devices, which can improve memory access efficiency.

[0005] In order to achieve the above technical objectives, the embodiments of the present application provide the following technical solutions:

[0006] In a first aspect, an embodiment of the present application provides a memory allocation method, which is applied to an electronic device, and the method may include: receiving a first memory request from an application, the first memory request including a target memory space value; searching a virtual address matching the target memory space value from a virtual memory space, and determining a target virtual address to be mapped from the virtual address; searching a target physical address to be mapped from a physical memory space, and determining whether the size and byte boundary of the target virtual address and the target physical address meet a first condition, the first condition including an alignment type of a byte boundary; if the first condition is met, determining an attribute parameter matching the first condition; creating a page table matching the attribute parameter, and establishing a mapping relationship between the target virtual address and the target physical address.

[0007] In the embodiment of the present application, when the system receives a memory request initiated by an application, a matching virtual address is allocated to the application from the virtual memory space based on the target memory space value in the memory request, and the corresponding target physical address is determined for the target virtual address currently to be mapped in the virtual address. In the specific address mapping process, firstly, by judging whether the size and byte boundary of the target virtual address and the target physical address meet the first condition, if the first condition is met, the attribute parameter matching the first condition is determined, and further, based on the attribute parameter, a page table with an attribute matching the first condition can be created, thereby establishing a mapping relationship between the target virtual address and the target physical address. Since the physical address size that can be mapped by a single page table entry of the page table matches the first condition, and the first condition includes the alignment type of the byte boundary (byte boundaries of different sizes can be set according to different application scenarios), therefore, in the process of mapping the virtual address to the physical address, a single page table entry can map physical pages of different attributes under different requirements in the embodiment of the present application, and the memory access efficiency can be effectively improved by improving the page table query efficiency when the CPU accesses the memory and / or reducing the TLB Miss rate. For example, a single page table entry can map a large page or a continuous page, so that a mapping relationship between a virtual address and a physical address can be established using fewer page table entries, so that the page table level or the number of page tables queried when the CPU accesses the memory is reduced. Exemplarily, when the embodiment of the present application is applied in an application scenario of a direct memory access buffer (DMA-BUF), and the alignment type of the byte boundary corresponds to a larger value, the number of page table entries can be reduced, the number of valid TLB page tables can be increased, and the TLB miss rate can be reduced, so that the physical address can be accessed faster when using the fast buffer TLB for direct memory access, thereby improving the addressing performance of the CPU.

[0008] In one possible implementation, the alignment type of the byte boundary includes a first space value alignment and a second space value alignment, and the target virtual address includes a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment, wherein the first space value or the second space value is determined based on the size of the page granularity, and the first space value is greater than the second space value.

[0009] In an embodiment of the present application, the alignment type of the byte boundary may be a plurality of alignment types of different space value sizes, for example, may include a first space value alignment and a second space value alignment. Correspondingly, the target virtual address may include a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment. The first space value or the second space value is determined based on the size of the page granularity, and the size of the first space value is greater than the second space value.

[0010] In a possible implementation, the first space value is aligned so that the lower M bits of the address are all 0, and the second space value is aligned so that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N.

[0011] In an embodiment of the present application, the alignment type of the byte boundary can be determined by the address. Specifically, the first space value alignment is that the lower M bits of the address are all 0, and the second space value alignment is that the lower N bits of the address are all 0, wherein M and N are both positive integers, and M is greater than N. Therefore, the address that satisfies the first space value alignment also satisfies the second space value alignment. That is, when the byte boundary alignment type in the first condition includes multiple alignment space values, then in the process of determining the target virtual address in the early stage, the target virtual address that meets the corresponding condition can be determined according to the alignment space value in the first condition.

[0012] In one possible implementation, the page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB.

[0013] In an embodiment of the present application, the page granularity includes granularities of multiple different sizes, and the larger the page granularity, the larger the size of the first space value and the second space value. Specifically, the page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB. Since the first space value or the second space value is used to align the target physical address and the virtual address, when the first space value is aligned, it means that the page table matching the first condition has the attribute of a relatively large page, and when the second space value is aligned, it means that the page table matching the first condition has the attribute of a relatively small page.

[0014] In one possible implementation, determining a virtual address that matches the target memory space value from the virtual memory space includes: applying for a virtual address in the virtual memory space whose size is the target memory space value and whose byte boundaries are aligned with the first space value; and determining whether the application is successful. If the application is successful, obtaining a first virtual address that matches the target memory space value.

[0015] In the embodiment of the present application, when determining a virtual address from a virtual memory space, by first making the byte boundary of the virtual address satisfy the first condition, the byte boundary of the target virtual address to be mapped also satisfies the first condition. That is, a virtual address matching the target memory space value is determined from the virtual memory space. In order to make the byte boundary of the virtual address matching the target memory space value satisfy the first condition, a virtual address matching the target memory space value whose byte boundary satisfies the first condition can be searched in the virtual memory space. Specifically, a virtual address whose size is the target memory space value and whose byte boundary satisfies the alignment of the first space value is applied in the virtual memory space, and then it is determined whether the application is successful. If the application is successful, the first virtual address matching the target memory space value is obtained, so as to increase the probability that the size and byte boundary of the target virtual address and the target physical address both meet the first condition.

[0016] In one possible implementation, determining a virtual address that matches the target memory space value from the virtual memory space includes: if the application fails, reapplying for a virtual address whose size is the target memory space value and whose byte boundaries satisfy the alignment of the second space value; and judging whether the application is successful. If the application is successful, obtaining a second virtual address that matches the target memory space value.

[0017] In an embodiment of the present application, when a virtual address whose size is the target memory space value and whose byte boundary satisfies the alignment of the first space value fails to be applied in the virtual memory space, another virtual address that satisfies the first condition and matches the target memory space value is re-applied, and the byte boundary type of the virtual address is an alignment type smaller than the first space value. Specifically, a virtual address whose size is the target memory space value and whose byte boundary satisfies the alignment of the second space value is re-applied, and then it is determined whether the application is successful. If the application is successful, a second virtual address that matches the target memory space value is obtained. That is, the alignment of the byte boundary of the larger value is performed first. If the alignment is successful, a single page table entry can map a larger page, thereby reducing the page table entries, so that the number of times the page table is created for addressing when memory allocation is performed is reduced. If the byte boundary of the larger value cannot be aligned, the byte boundary of the second largest value is further aligned to establish the page table with a larger page attribute as much as possible, thereby reducing the number of times the page table entries are established and addressed, and improving memory access efficiency.

[0018] In one possible implementation, determining the target virtual address to be mapped includes: searching for a virtual address to be mapped that matches the size of the first space value; if found, determining the virtual address to be mapped that matches the size of the first space value as the target virtual address; if not found, searching for a virtual address to be mapped that matches the size of the second space value; if found, determining the virtual address to be mapped that matches the size of the second space value as the target virtual address.

[0019] In the embodiment of the present application, when determining the target virtual address to be mapped, since the byte boundary of the target virtual address has satisfied the first condition, in order to make the size of the space value of the target virtual address also satisfy the first condition and increase the probability of successful matching between the target virtual address and the target physical address, the target virtual address to be mapped whose space value size can satisfy the first condition can be searched in the above virtual address. Specifically, the virtual address to be mapped that matches the size of the first space value can be searched first, and if found, the found virtual address is determined as the target virtual address; if not found, another target virtual address to be mapped whose space value size can satisfy the first condition is searched, wherein the size of the target virtual address is smaller than the first space value, and then the virtual address to be mapped that matches the size of the second space value is searched, and if found, the virtual address to be mapped that matches the size of the second space value is determined as the target virtual address. Since the first space value or the second space value is used to align the target physical address and the virtual address, when the target virtual address has satisfied the first space value or the second space value alignment, the probability that the target physical address subsequently determined based on the target virtual address satisfies the first space value or the second space value alignment will also increase, that is, the probability of establishing a large page attribute will also increase accordingly.

[0020] In one possible implementation, determining the target physical address to be mapped includes: searching for a physical address that matches the size of the first space value or the second space value; creating a physical address page table, and passing the physical addresses that match the size of the first space value and the second space value into the physical address page table from top to bottom according to the size of the space value; and determining the physical address in the physical address page table pointed to by the pointer as the target physical address.

[0021] In the embodiment of the present application, since the physical address is randomly allocated from the memory pool, and the size of the physical address has many different types, therefore, in order to make the size of the target physical address meet the first condition as much as possible and increase the probability of successful matching between the target virtual address and the target physical address, the target physical address whose space value size can meet the first condition can be found. Specifically, the physical address matching the first space value or the second space value size is first found, and then a physical address page table is created, and the found physical address is passed to the physical address page table from top to bottom according to the space value size, and the physical address pointed to by the pointer is determined as the target physical address. That is, based on the current physical memory allocation in the memory pool, continuous physical addresses are allocated as much as possible for the target virtual address to be mapped, thereby increasing the probability of alignment between the virtual address and the physical address.

[0022] In one possible implementation, the determining whether the size and byte boundaries of the target virtual address and the target physical address satisfy a first condition includes: determining whether the size and byte boundaries of the target virtual address and the target physical address satisfy a first alignment condition, the first alignment condition including that the size of the target virtual address and the target physical address is the first space value, and the byte boundaries satisfy the first space value alignment; if the first condition is satisfied, determining the attribute parameters that match the first condition includes: if the first alignment condition is satisfied, determining the first attribute parameters that match the first alignment condition, wherein the first attribute parameters are used to indicate that the page corresponding to the physical address stored in a single page table entry is a large page whose size is the first space value.

[0023] In an embodiment of the present application, it is determined whether the size and byte boundary of the target virtual address and the target physical address meet the first condition. If the first condition is met, the attribute parameter matching the first condition is set. Specifically, based on the fact that the size of the target virtual address and the target physical address are both the first space value, and the byte boundary meets the first space value alignment as the first alignment condition, it is determined whether the size and byte boundary of the target virtual address and the target physical address meet the first alignment condition. When the first alignment condition is met, the first attribute parameter matching the first alignment condition is determined, which is used to indicate that the physical address stored in a single page table entry corresponds to a large page whose size is the first space value. Accordingly, when mapping the target virtual address to the target physical address, a single page table entry in the established page table can map a large page whose size is the first space value. Among them, when performing the first condition judgment, it is necessary to judge whether the space value size and byte boundary of the target physical address and the target virtual address meet the conditions, so as to ensure that when the CPU performs memory access, it can access the corresponding target physical address according to the target virtual address. For example, when only the byte boundary is aligned and the space value size does not meet the conditions, such as the virtual address is 2MB and the physical address is 1.5MB, then when the CPU accesses according to the 2MB value, there will be a problem of accessing non-existent space. Therefore, the judgment of the above first condition enables the CPU to access the address space of the size of the first space value when performing memory access, avoiding the problem of accessing non-existent space.

[0024] In one possible implementation, the determining whether the size and byte boundaries of the target virtual address and the target physical address satisfy a first condition includes: if the first alignment condition is not satisfied, determining whether the size and byte boundaries of the target virtual address and the target physical address satisfy a second alignment condition, the second alignment condition including that the size of the target virtual address and the target physical address is the second space value, and that the byte boundaries satisfy the second space value alignment; if the first condition is satisfied, determining the attribute parameters that match the first condition also includes: if the second alignment condition is satisfied, determining the second attribute parameters that match the second alignment condition, wherein the second attribute parameters are used to indicate that the page corresponding to the physical address stored in a single page table entry is a continuous page of a size of the second space value.

[0025] In an embodiment of the present application, when the size and byte boundary of the target virtual address and the target physical address do not satisfy the first alignment condition, it is determined whether the size and byte boundary of the target virtual address and the target physical address satisfy another situation of the first condition. Specifically, according to the second alignment condition that the size of the address space is the second space value and the byte boundary satisfies the alignment of the second space value, it is determined whether the size and byte boundary of the target virtual address and the target physical address satisfy the second alignment condition. When the second alignment condition is satisfied, a second attribute parameter matching the second alignment condition is determined, and the parameter is used to indicate that the physical address stored in a single page table entry corresponds to a continuous page of a size of the second space value. Accordingly, when mapping the target virtual address to the target physical address, a single page table entry in the established page table can map a continuous page of a size of the second space value, so that the CPU can access the address space of a size of the second space value when performing memory access, avoiding the problem of accessing a non-existent space.

[0026] In a possible implementation, the creating a page table matching the attribute parameter includes: sequentially creating L-level page tables, transferring the attribute parameter matching the first condition to a current page table in the L-level page table level by level, and searching for a corresponding next-level page table based on the target virtual address and a corresponding page table entry in the current page table; when creating an L-th level page table in the L-level page table, transferring the attribute parameter matching the first condition to the L-th level page table, and determining whether the transferred attribute parameter is the first attribute parameter; if so, searching for a corresponding next-level page table based on the target virtual address and the corresponding page table entry in the current page table; The corresponding page table entry in the table is searched for the corresponding physical page and the target physical address is passed into the physical page, so as to establish a mapping relationship between the target physical address and the L-th level page table; if not, based on the target virtual address and the corresponding page table entry in the L-th level page table, the corresponding L+1 page table is searched; the L+1-th level page table is created, based on the target virtual address and the corresponding page table entry in the L+1-th page table, the corresponding physical page is searched and the target physical address is passed into the physical page, so as to establish a mapping relationship between the target physical address and the L+1-th level page table.

[0027] In the embodiment of the present application, when creating a page table matching the above-mentioned attribute parameters, a multi-level page table is created according to the characteristic that a multi-level page table can effectively map a large space of physical memory. By judging the attribute parameters passed into the page table, a page table matching the attribute parameters is created, and the mapping relationship between the target virtual address and the target physical address is determined, so that in the process of mapping the virtual address to the physical address, a single page table entry of the above-mentioned page table can map physical pages of different attributes under different requirements, thereby effectively improving the efficiency of page table query when the CPU accesses the memory and reducing the TLB Miss rate. Specifically, L-level page tables are created in sequence, and the attribute parameters are passed into the current page table in the L-level page table step by step, and based on the target virtual address and the corresponding page table entry in the page table, the corresponding next-level page table is searched; when creating the L-level page table, the attribute parameters are passed into the L-level page table, and it is judged whether the passed-in attribute parameters are the first attribute parameters. If so, based on the target virtual address and the corresponding page table entry in the L-level page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the page table is established, thereby determining the target virtual address and the target physical address. The mapping relationship between the physical addresses; if not, the attribute parameter passed in is the second attribute parameter, then the L+1th level page table is the page table that matches the attribute parameter, based on the target virtual address and the corresponding page table entry in the L-level page table, find the corresponding L+1th page table; create the L+1th level page table, based on the target virtual address and the corresponding page table entry in the L+1th page table, find the corresponding physical page and pass the target physical address to the physical page, establish the mapping relationship between the target physical address and the L+1th level page table, so as to determine the mapping relationship between the target virtual address and the target physical address. Creating a multi-level page table can improve the efficiency of memory management. When only part of the virtual address space needs to be mapped, only the required page table level can be mapped without allocating a page table for the entire address space, thereby saving memory space. At the same time, when performing address conversion, only a relatively small page table level needs to be accessed without traversing the entire page table structure, thereby reducing the number of memory accesses and increasing the memory conversion speed to improve memory access efficiency.

[0028] In a possible implementation, the physical address range mapped by the Lth level page table is larger than the physical address range mapped by the L+1th level page table, where L is a positive integer.

[0029] In a second aspect, an embodiment of the present application provides a memory allocation device, which may include:

[0030] The receiving unit is used to receive a first memory request from an application, where the first memory request includes a target memory space value.

[0031] The first determining unit 502 is used to determine a virtual address matching the target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the virtual address.

[0032] The second determination unit 503 is used to determine the target physical address to be mapped from the physical address, and determine whether the size and byte boundary of the target virtual address and the target physical address meet a first condition, wherein the first condition includes the alignment type of the byte boundary. If the first condition is met, determine the attribute parameter matching the first condition.

[0033] The mapping unit 504 is used to create a page table matching the attribute parameters and establish a mapping relationship between the target virtual address and the target physical address.

[0034] In one possible implementation, the alignment type of the byte boundary includes a first space value alignment and a second space value alignment; the target virtual address includes a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment; wherein the first space value or the second space value is determined based on the size of the page granularity, and the first space value is greater than the second space value.

[0035] In a possible implementation, the first space value is aligned so that the lower M bits of the address are all 0, and the second space value is aligned so that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N.

[0036] In one possible implementation, the page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB.

[0037] In a possible implementation manner, the first determining unit is specifically configured to:

[0038] Apply for a virtual address from the virtual memory space whose size is the target memory space value and whose byte boundaries meet the alignment of the first space value; determine whether the application is successful, and if so, obtain a first virtual address that matches the target memory space value.

[0039] In a possible implementation manner, the first determining unit is specifically configured to:

[0040] If the application fails, then reapply for a virtual address whose size is the target memory space value and whose byte boundaries meet the alignment of the second space value; determine whether the application is successful. If the application is successful, obtain a second virtual address that matches the target memory space value.

[0041] In a possible implementation manner, the first determining unit is specifically configured to:

[0042] Search for a virtual address to be mapped that matches the size of the first space value; if found, determine the virtual address to be mapped that matches the size of the first space value as the target virtual address; if not found, search for a virtual address to be mapped that matches the size of the second space value; if found, determine the virtual address to be mapped that matches the size of the second space value as the target virtual address.

[0043] In a possible implementation manner, the second determining unit is specifically configured to:

[0044] Search for a physical address that matches the size of the first space value or the second space value; create a physical address page table, and pass the physical addresses that match the size of the first space value and the second space value into the physical address page table from top to bottom according to the size of the space value; determine the physical address in the physical address page table pointed to by the pointer as the target physical address.

[0045] In a possible implementation manner, the second determining unit is specifically configured to:

[0046] Determine whether the size and byte boundary of the target virtual address and the target physical address meet a first alignment condition, wherein the first alignment condition includes that the size of the target virtual address and the target physical address is the first space value, and the byte boundary meets the first space value alignment;

[0047] If the first condition is met, determining the attribute parameter matching the first condition, the second determining unit is specifically configured to:

[0048] If the first alignment condition is met, a first attribute parameter matching the first alignment condition is determined, wherein the first attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a large page having a size of the first space value.

[0049] In a possible implementation manner, the second determining unit is specifically configured to:

[0050] If the first alignment condition is not met, determining whether the size and byte boundary of the target virtual address and the target physical address meet a second alignment condition, wherein the second alignment condition includes that the size of the target virtual address and the target physical address is the second space value, and the byte boundary meets the second space value alignment;

[0051] If the first condition is met, determining the attribute parameter matching the first condition, the second determining unit is specifically configured to:

[0052] If the second alignment condition is met, a second attribute parameter matching the second alignment condition is determined, wherein the second attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a continuous page having a size of the second space value.

[0053] In a possible implementation manner, the mapping unit is specifically configured to:

[0054] Create L-level page tables in sequence, pass the attribute parameters matching the first condition to the current page table in the L-level page tables step by step, and search for the corresponding next-level page table based on the target virtual address and the corresponding page table entry in the current page table; when creating the L-th level page table in the L-level page table, pass the attribute parameters matching the first condition to the L-th level page table, and determine whether the passed-in attribute parameters are the first attribute parameters; if so, search for the corresponding physical page based on the target virtual address and the corresponding page table entry in the L-th level page table and pass the target physical address to the physical page, and establish a mapping relationship between the target physical address and the L-th level page table; if not, search for the corresponding L+1th page table based on the target virtual address and the corresponding page table entry in the L-th level page table; create the L+1th level page table, search for the corresponding physical page based on the target virtual address and the corresponding page table entry in the L+1th page table and pass the target physical address to the physical page, and establish a mapping relationship between the target physical address and the L+1th level page table.

[0055] In a possible implementation, it is characterized in that the physical address range mapped by the L-th level page table is larger than the physical address range mapped by the L+1-th level page table, where L is a positive integer.

[0056] In a third aspect, an embodiment of the present application provides an electronic device, comprising a processor and a memory, wherein the memory is used to store programs and various data, and the processor is used to call the program code stored in the memory so that the electronic device executes any one of the methods described in the first aspect above.

[0057] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, which stores a computer program. When the computer program runs on the electronic device, the electronic device can execute any one of the methods described in the first aspect above.

[0058] In a fifth aspect, an embodiment of the present application provides a computer program, which includes instructions. When the computer program is executed by an electronic device, the electronic device executes any one of the methods described in the first aspect above. BRIEF DESCRIPTION OF THE DRAWINGS

[0059] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the background technology, the drawings required for use in the embodiments of the present application or the background technology will be described below.

[0060] Figure 1A The present invention is a memory mapping flow chart for executing dynamic memory allocation based on a DMA-BUF mechanism of 4KB page granularity in the prior art.

[0061] Figure 1B The present invention is a flow chart of applying for a virtual address in the prior art.

[0062] Figure 2 A schematic diagram of a system architecture provided for an embodiment of the present application.

[0063] Figure 3A A schematic flowchart of a memory allocation method is provided for an embodiment of the present application.

[0064] Figure 3B A schematic diagram of a process for determining a virtual address that matches a target memory space value is provided in an embodiment of the present application.

[0065] Figure 3C A simplified schematic diagram of a three-level page table mapping provided in an embodiment of the present application.

[0066] Figure 3D A simplified schematic diagram of a four-level page table mapping provided in an embodiment of the present application.

[0067] Figure 4 An example flowchart of performing dynamic memory allocation based on a DMA-BUF mechanism with a 4KB page granularity is provided in an embodiment of the present application.

[0068] Figure 5 A schematic diagram of the logical structure of the device provided in an embodiment of the present application.

[0069] Figure 6 It is a schematic diagram of the hardware structure of a possible device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0070] The technical solutions in the embodiments of the present application will be described clearly and in detail below in conjunction with the accompanying drawings. In the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" means two or more than two.

[0071] In the following, the terms "first", "second", "third" and "fourth" etc. are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0072] Reference to "embodiments" herein means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present application. The appearance of the phrase in various locations in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0073] The terms "component", "module", "system", etc. used in this specification are used to represent computer-related entities, hardware, firmware, a combination of hardware and software, software, or software in execution. For example, a component can be, but is not limited to, a process running on a processor, a processor, an object, an executable file, an execution thread, a program and / or a computer. By way of illustration, both applications running on a computing device and a computing device can be components. One or more components may reside in a process and / or an execution thread, and a component may be located on a computer and / or distributed between two or more computers. In addition, these components may be executed from various computer-readable media having various data structures stored thereon. Components may, for example, communicate through local and / or remote processes according to signals having one or more data packets (e.g., data from two components interacting with another component between a local system, a distributed system and / or a network, such as the Internet interacting with other systems through signals).

[0074] The electronic device is a smart terminal device, which can be of various types, and the embodiments of the present application do not limit its specific type. For example, the electronic device can be a mobile phone, and can also include a tablet computer, a desktop computer, a desktop computer with a touch-sensitive surface or a touch panel, a laptop computer (laptop), a handheld computer, a notebook computer, a smart screen, a wearable device (such as a smart watch, a smart bracelet, etc.), an augmented reality (AR) device, a virtual reality (VR) device, an artificial intelligence (AI) device, a car machine, a smart headset, a game console, and can also be an Internet of Things (IOT) device or a smart home device such as a smart water heater, a smart lamp, a smart air conditioner, etc.

[0075] First, some terms in the present application are explained to facilitate those skilled in the art to understand the embodiments of the present application.

[0076] (1) Direct memory access buffer (DMA-BUF) is a mechanism for sharing memory buffers in Linux systems. It provides a standardized, lock-free, low-latency data sharing method by introducing a shared memory descriptor, which is used to implement memory sharing between different devices or processes. This memory descriptor can be referenced by multiple devices or processes to obtain access rights to the shared memory buffer. This memory descriptor contains information related to the shared memory buffer, such as physical address, size, offset, etc.

[0077] (2) Direct memory access (DMA) is a data transfer technology in computer systems. DMA allows external devices (such as hard disks, network cards, graphics cards, etc.) to directly access system memory without the intervention of the CPU, which can greatly improve the speed and efficiency of data transfer. DMA technology can reduce the burden on the CPU, improve the overall performance of the system, and enable peripherals to transfer data more quickly. This is particularly useful when there is a large amount of data to be transferred, such as audio, video, network communication and other application scenarios.

[0078] (3) The memory management unit (MMU) is mainly used by the central processing unit (CPU) to convert virtual addresses into physical addresses. When an application requests a continuous range of virtual memory, the MMU can map the virtual address range to configurable discrete physical memory addresses.

[0079] (4) Translation lookaside buffer (TLB) is a high-speed cache in computer architecture, usually located inside the CPU, used to improve the efficiency of fast conversion of virtual memory addresses to physical memory addresses. The TLB page table can store mapping entries between virtual addresses and physical addresses, so that each time the processor (CPU) accesses memory, it first checks whether there is a corresponding mapping relationship in the TLB. If it exists, the TLB can directly provide the physical address, avoiding the overhead of querying the page table and improving the access speed.

[0080] (5) A TLB miss occurs when the translation lookaside buffer cannot find the required mapping relationship from a virtual address to a physical address. TLBs generally have a small capacity and can only store a limited number of mapping entries. When the CPU accesses a virtual address and cannot find the corresponding mapping entry in the TLB, a TLB miss occurs, and an additional address translation process is required to query the page table and load the mapping relationship into the TLB. TLB misses can cause a certain amount of delay because additional steps are required to handle the missing mapping relationship. However, compared to querying the entire page table or segment table every time, a TLB miss can still significantly increase the speed of address translation.

[0081] (6) A TLB hit is a successful search of the required virtual address to physical address mapping in the translation lookaside buffer. A TLB hit is an efficient situation because the TLB is a high-speed cache that can provide fast address translation. When a TLB hit occurs, the CPU can directly obtain the physical address from the TLB without querying the entire page table or segment table.

[0082] (7) Page granularity (PG) refers to the smallest unit size of memory management in an operating system or virtual memory system. It determines the granularity of memory allocation and access. In a virtual memory system, memory is divided into pages (or page frames) of equal size to facilitate management and mapping of virtual addresses to physical addresses. The size of page granularity has an important impact on system performance and the efficiency of memory management. Common page granularities are:

[0083] Small page granularity: Small page granularity refers to a smaller page size, usually ranging from a few KB to tens of KB. Small page granularity can make memory utilization more efficient, especially in scenarios with a large number of small memory allocations. However, since the overhead of each page is also relatively large, small page granularity may cause memory fragmentation problems and increase the size of the paging table and query time.

[0084] Large page granularity: Large page granularity refers to a larger page size, usually in the range of tens of KB to several MB. Large page granularity can reduce the number of entries in the paging table, reduce query time, and reduce the memory overhead of the page table. However, for small memory allocations or scenarios with large memory fragmentation problems, large page granularity may waste memory space.

[0085] The choice of page granularity needs to be weighed according to the specific application scenario and system requirements. Generally speaking, small page granularity is suitable for scenarios where small blocks of memory need to be frequently allocated and released, while large page granularity is suitable for scenarios where memory access is relatively continuous or memory management overhead is large. In actual applications, the size of page granularity is generally fixed and determined by the operating system or virtual memory system during initialization. Therefore, once the page granularity is determined, it cannot usually be changed at will.

[0086] (8) Memory pool (MP) refers to a continuous memory space that is allocated and managed in advance in a computer system for efficient allocation and recovery of memory resources. It is a memory management technology that is often used to improve memory allocation performance and reduce memory fragmentation. Normally, the memory pool will first apply for a continuous memory space when the program starts. This memory space will be divided into multiple smaller blocks, and the size of each block is fixed. Each block can be allocated to the program as an independent memory unit. The memory pool is suitable for scenarios where small blocks of memory need to be frequently allocated and released, such as network servers, database systems, embedded systems, etc. It can improve the performance and efficiency of the program and reduce the overhead of memory management.

[0087] (9) Dynamic memory allocation (DMA) refers to the dynamic allocation and release of memory space as needed while the program is running. In contrast to static memory allocation, which determines the memory usage when the program is compiled, dynamic memory allocation allows for flexible application and release of memory based on actual needs during program execution.

[0088] (10) Address alignment is a concept in computer architecture. Address alignment means that the starting address of data stored in memory must be a multiple of a specific value. When expressed in hexadecimal, the low bit must be guaranteed to be 0.

[0089] First, the technical problems to be solved by this application are analyzed and proposed. In the field of computer technology, the memory allocation technology under the DMA-BUF mechanism related to this application includes the following two solutions:

[0090] Solution 1: Please refer to Figure 1A , Figure 1A The memory mapping flow chart of the DMA-BUF mechanism based on 4KB page granularity in the prior art for dynamic memory allocation is shown below:

[0091] Step S101: receiving a memory request from an application and making a system call.

[0092] Step S102: Execute a system call to start a memory mapping operation.

[0093] Step S103: randomly allocating a segment of physical addresses to be mapped from the physical memory space.

[0094] Step S104: Create a first-level page table and search for a corresponding second-level page table based on the virtual address and the corresponding page table entry in the first-level page table.

[0095] Step S105: Create a second-level page table and search for a corresponding third-level page table based on the virtual address and the corresponding page table entry in the second-level page table.

[0096] Step S106: Create a third-level page table and search for a corresponding fourth-level page table based on the virtual address and the corresponding page table entry in the third-level page table.

[0097] Step S107: Create a fourth-level page table and search for a corresponding fifth-level page table based on the virtual address and the corresponding page table entry in the fourth-level page table.

[0098] Step S108: Create a fifth-level page table and search for a corresponding physical page based on the virtual address and the corresponding page table entry in the fifth-level page table.

[0099] Step S109: the target physical address is transferred into the physical page, and a mapping relationship between the target physical address and the fifth-level page table is established.

[0100] This solution is usually used for dynamic memory allocation based on the DMA-BUF mechanism with a 4KB page granularity. It is currently mainly applicable to application scenarios where memory allocation is performed during the cold start of an application. However, it has the following disadvantages:

[0101] Essentially, only a memory pool of 4KB is used in the mapping from virtual memory to physical memory, and the other two memory pools provided by DMA-BUF are not used. That is, a single TLB page table entry is not used to map 2MB large pages and 64KB continuous pages, so the benefit of this feature cannot be reflected. When allocating memory, only more page table entries can be established, which increases the number of CPU addressing times and reduces the addressing performance, resulting in low memory access efficiency and slow cold start of applications.

[0102] Solution 2: Based on the DMA-BUF mechanism of Solution 1 above, please refer to Figure 1B , Figure 1B Flow chart of applying for virtual address in prior art:

[0103] Step S201: Search in the memory for a virtual address whose size is equal to the target memory space value.

[0104] Step S202: Determine whether direct access (DAX) is possible, if so, proceed to step S203, if not, proceed to step S205.

[0105] Step S203: Apply for a virtual address whose size is equal to the target memory space value.

[0106] Step S204: Determine whether the application is successful, if so, the process ends, if not, proceed to step S205.

[0107] Step S205: Search for a suitable unmapped area in the virtual address space.

[0108] This solution is usually used for applying for virtual memory based on the DMA-BUF mechanism with a 4KB page granularity. It is currently mainly applicable to application scenarios where unmapped virtual memory is applied. However, it has the following disadvantages:

[0109] Essentially, the byte boundaries of the applied virtual addresses all meet 4KB alignment. That is, when the applied virtual memory is mapped to physical memory, the page table entries of the last-level page table created can only map 4KB pages. It is impossible to create a single TLB page table entry that can map 2MB large pages and 64KB continuous pages. As a result, the other two memory pools provided by DMA-BUF are not used and memory access efficiency is low.

[0110] Based on the technical problems raised above, the embodiments of the present application disclose a memory allocation method, which can specifically solve one or more of the following technical problems:

[0111] (1) Solve the technical problem of insufficient utilization of memory pool resources so as to use a larger memory pool for memory allocation as much as possible, thereby making full use of the memory pools of different sizes provided by DMA-BUF.

[0112] (2) Solve the technical problem of wasting memory resources due to the need to create a large number of page table entries in the mapping process from virtual addresses to physical addresses. That is, a single page table entry can be used to map a larger number of physical pages with different attributes, thereby reducing the number of page table entries to be created, and fewer page table entries can be used to represent the mapping relationship between virtual addresses and physical addresses.

[0113] (3) Solve the technical problem that a large number of page table entries need to be established in the mapping process from virtual addresses to physical addresses, resulting in a large number of CPU addressing times and low addressing efficiency. That is, reduce the number of CPU addressing times, thereby improving the CPU addressing performance and improving the efficiency of memory access.

[0114] (4) To solve the technical problem that when fast memory access is performed through the page table cached by TLB, the physical page mapped by a single page table entry is small, the number of valid page table entries in the page table cached by TLB is small, and the TLB miss rate is high, resulting in low address conversion efficiency. That is, by mapping larger physical pages with different attributes through a single page table entry, the number of valid page table entries in the page table cached by TLB is increased, and the TLB miss rate is reduced, thereby improving the address conversion efficiency.

[0115] The embodiments of the present application can be implemented as follows: Figure 2 See the system architecture shown in Figure 2 , Figure 2A system architecture diagram provided for an embodiment of the present application can be implemented by a computing device running a computer program, mainly including a software layer and a hardware layer. Wherein the software layer 210 is an operating system (operating system, OS), and the operating system is a software system that manages and controls computer hardware resources and provides an operating environment and services for applications. The operating system can be Windows OS, Mac OS, Linux OS or other operating systems. The electronic device can be a computing device, which can be of various types, and the embodiment of the present application does not limit its specific type. For example, it can be a desktop computer, a laptop computer (laptop), a handheld computer, a notebook computer, a tablet computer, and can also be a mobile phone, a smart screen, a wearable device (such as a smart watch, a smart bracelet, etc.), an augmented reality (augmented reality, AR) device, a virtual reality (virtualreality, VR) device, an artificial intelligence (artificial intelligence, AI) device, a car machine, a smart headset, a game console, and can also be an Internet of Things (internet of things, IOT) device or a smart home device such as a smart water heater, a smart lamp, a smart air conditioner, etc.

[0116] The software layer 210 is divided into user state and kernel state. It should be noted that the embodiment of the present application only takes this as an example for illustration. In other embodiments, the software layer of other operating systems may also present a similar distinction between user state and kernel state or other forms, which is not limited in the present application.

[0117] Exemplarily, the user state of the software layer 210 may include an application 211 and an interface module 212: the application 211 is a process that executes services in the user state; the interface module 212 is used to provide an interface for the application, and the application 211 needs to rely on the interface provided by the interface module 212 to access the kernel state. The kernel state of the software layer 210 may include a system call module 213, a memory management module 214, a device driver module 215, a file system module 216, a scheduling module 217, and a kernel communication module 218. The system call module 213, when the process of the application 211 needs to apply for memory through the interface module 212, it needs to be completed through the system call module 213. The memory management module 214 is used to manage physical memory and virtual memory, which may include operations such as memory allocation, management and release, address mapping, page replacement and memory protection; the device driver module 215 is used to manage the hardware devices of the computer and provide drive and control for the devices; the file system module 216 is responsible for the management and operation of files, including operations such as file creation, writing, reading and deletion; the scheduling module 217 is used to manage the state transition and context switching of the process to realize the scheduling of the process; the kernel communication module 218 is used for communication and data sharing between different kernel modules. Taking the Linux system as an example, the user state can also be called the user space, which provides a space for the application program to run, and allows the application program to access the resources managed by the kernel, such as the processor, memory, etc. The kernel state can also be called the kernel space, which controls the hardware resources of the computing device, such as coordinating processor resources, allocating memory resources, etc., and can provide a stable environment for the application program to run. It should be understood that the software layer may include more or less modules described above, as well as other modules not described in this article.

[0118] Exemplarily, the hardware layer 220 may include a processor 221, a memory 222, and a storage device 223. The processor 221 is used to execute the code or instructions of the computer program loaded from the memory 222; the memory 222 stores the resources required for the computer to run, including, for example, the assembly code, variables, heap, stack and other data obtained after the computer program is compiled; the storage device 223 may be used to store data persistently. It is understandable that the hardware layer 220 may include more or less hardware devices described above, as well as other hardware devices not described herein. Specifically,

[0119] Processor 221: can run an operating system, a file system or an application program, etc., to control multiple hardware or software elements connected to the processor 221, and can process various data and perform operations. Exemplarily, the processor 221 can load instructions or data stored in the storage device 223 into the memory 222, and call the instructions or data that need to be calculated to the processor 221 for calculation. After the calculation is completed, the processor 221 temporarily stores the result in the memory 222, and stores the instructions or data that need to be stored for a long time in the storage device 223. Optionally, the processor 221 may include one or more processing units (also called processing cores), for example: the processor 221 may include one or more of a central processing unit (CPU), an application processing unit (application processor, AP), a modem processing unit, a graphics processing unit (graphics processing unit, GPU), an image signal processing unit (image signal processor, ISP), a video codec unit, a digital signal processing unit (digital signal processor, DSP), a baseband processing unit and a neural network processing unit (neural-network processing unit, NPU). Among them, different processing units can be independent devices or integrated in one or more devices. For a multi-core processor, each physical core corresponds to a memory management unit (MMU) 2211 .

[0120] Optionally, there is a TLB (Translation Lookaside Buffer) 2212 cache inside the processor 221, also known as a fast table cache, which is used to store the most recent address conversion results and cache the mapping relationship between the virtual address and the physical address. When the processor 221 accesses the memory, it will first search for the mapping of the virtual address and the physical address in the TLB cache 2212. If a matching mapping is found, the physical address can be directly accessed without accessing the main memory or external memory, so as to complete the address conversion operation faster. However, if the required mapping cannot be found in the TLB 2212, a TLB miss will occur, and the processor 221 will map the virtual address to the physical address through the memory management unit MMU 2211. Once the correct mapping information is obtained, the processor 221 will store it in the TLB 2212 cache so that it can be directly used in future accesses. Among them, the memory management unit (MMU) 2211 performs address conversion to map the page virtual address addressed by the process to the physical address of the corresponding frame in the memory 222. MMU 2211 can also implement virtual memory management functions for the memory management module 214 of the operating system. For example, the memory management module 214 is responsible for maintaining and managing data structures such as page tables and segment tables, as well as communicating with MMU 2211 to provide interfaces for allocating and reclaiming memory. MMU 2211 is responsible for converting logical addresses and performing access rights checks based on the page table and segment table information provided by the memory management module. When pages are moved between different physical memory locations, MMU 2211 manages the entries of the corresponding page tables, thereby updating the page tables as needed.

[0121] Memory 222: Usually a volatile memory that loses power when the power is off. The content stored on it will be lost when the power is off. It can also be called main memory. The memory 222 in this application includes a readable and writable operating memory, which is used to temporarily store the calculation data in the processor 221, and to exchange data with the storage device 223 or other external memory. It can be used as a storage medium for temporary data of the operating system or other running programs. For example, the operating system running on the processor 221 transfers the data to be calculated from the internal memory 222 to the processor 221 for calculation, and when the calculation is completed, the processor 221 transmits the result.

[0122] The memory 222 may include one or more of a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), etc. Among them, DRAM includes double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), referred to as DDR, second-generation double data rate synchronous dynamic random access memory (DDR2), third-generation double data rate synchronous dynamic random access memory (DDR3), fourth-generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 4, LPDDR4) and fifth-generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 5, LPDDR5), etc. Further, the memory 222 may include a plurality of memory cells. Each memory cell has an address for identifying the location of the memory cell in the memory 222. Generally, system software such as BIOS and operating system in the startup state can directly access the physical memory 222, while for other processes (such as process access to memory, etc.), a virtual address space is usually used. The virtual address space is similar to the physical address space, but the address does not correspond to a location in the physical memory 222. For example, the virtual address space provides a continuous virtual address for the process, while the corresponding physical address is usually discontinuous. The mapping of virtual addresses to physical addresses is stored in a data structure called a page table. Each entry in the page table can be called a page table entry. A page, memory page, or virtual page is a fixed-length continuous block of virtual memory, represented by a single page table entry. Among them, a frame is a fixed-length continuous block of a page mapped to physical memory.

[0123] The storage device 223 is a non-volatile memory, and the content stored in it will not be lost after power failure. The storage device 223 may include any type of non-temporary storage device, which is used to store data, programs and other information for a long time. Since the processor 221 cannot directly read the instructions and data in the storage device 223, when the processor 221 executes a read (or load) command, it actually temporarily loads the instructions and / or data stored in the storage device 223 into the memory 222, and then the processor 221 performs memory access and other operations on the memory 222 through the operating system. The storage device 223 may include at least one such as a solid state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive.

[0124] It is to be understood that the environment structure illustrated in the embodiment of the present application does not constitute a specific limitation on the device 600. In other embodiments of the present application, the device 600 may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or a combination of software and hardware.

[0125] based on Figure 2 The example system architecture diagram described in the present application embodiment provides a schematic flowchart of a memory allocation method, see Figure 3A , this method can be applied to Figure 2 Memory allocation is performed in the system architecture shown.

[0126] Step S301: receiving a first memory request from an application.

[0127] Specifically, the first memory request includes a target memory space value. The size of the target memory space value is arbitrary, such as 2MB, 3MB, etc. The first memory request can be issued by an application, and the receiving operation is performed by a processor. Exemplarily, the application issues an instruction in a user state to apply for a first memory request of the size of the target memory space value, and calls the interface provided by the interface module to access the kernel state. The processor receives the instruction of the application and executes it, and receives the first memory request of the application.

[0128] Step S302: Determine a virtual address matching the target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the virtual address.

[0129] Specifically, in an embodiment of the present application, the virtual address has different alignment types according to different byte boundaries, and the determined virtual address matching the target memory space value is different. Furthermore, the byte boundary alignment type includes a first space value alignment and a second space value alignment, and the byte boundary alignment type of the virtual address includes a first space value alignment and a second space value alignment, and the target virtual address includes a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment. Among them, the first space value or the second space value is usually determined based on the size of the page granularity, and the first space value is greater than the second space value. The embodiment of the present application does not impose any limitation on this, as long as the first space value and the second space value can reflect the corresponding relationship with the size of the page granularity.

[0130] For example, in some embodiments of the invention, if the page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, if the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, if the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB.

[0131] In a possible implementation, the first space value alignment means that the lower M bits of the address are all 0, and the second space value alignment means that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N. Therefore, when the byte boundary of the address satisfies the first space value alignment, the second space value alignment must be satisfied. For example, based on the case where the page granularity is 4KB, the first space value alignment is 2MB alignment, that is, the lower 21 bits of the address are all 0, and the second space value alignment is 64KB alignment, that is, the lower 16 bits of the address are all 0. For example, when expressed in hexadecimal, 2MB alignment means that a hexadecimal value is required, and all the lower 21 bits are 0, for example: 0xFFFFFFDC91200000 meets 2MB alignment; 0xFFFFFFDC91300000 does not meet 2MB alignment; 0xFFFFFFDC91200002 does not meet 2MB alignment; 64KB alignment means that a hexadecimal value is required, and all the lower 16 bits are 0, for example: 0xFFFFFFDC91370000 meets 64KB alignment; 0xFFFFFFDC91378000 does not meet 64KB alignment; 0xFFFFFFDC91370002 does not meet 64KB alignment. Therefore, when the byte boundary of the address meets 2MB alignment, it must meet 64KB alignment.

[0132] Due to different alignment types of byte boundaries, there may be two different situations for determining a virtual address that matches the target memory space value. In one possible implementation, a segment of virtual addresses with a size equal to the target memory space value and a byte boundary that satisfies the alignment of the first space value is applied in the virtual memory space, and then it is determined whether the application is successful. If the application is successful, the first virtual address that matches the target memory space value is obtained; in another possible implementation, if the application fails, a segment of virtual addresses with a size equal to the target memory space value and a byte boundary that satisfies the alignment of the second space value is applied again, and then it is determined whether the application is successful. If the application is successful, the second virtual address that matches the target memory space value is obtained. See . Figure 3B , Figure 3B A schematic diagram of a process for determining a virtual address that matches a target memory space value provided by an embodiment of the present application, the method process of how to determine a virtual address that matches a target memory space value from a virtual memory space in the above step S302 may specifically include the following steps: Figure 3B Steps S3021-S3026 shown in .

[0133] Step S3021: Apply for a continuous virtual address in the memory that has not yet been mapped.

[0134] Step S3022: Apply for a virtual address whose size is the target memory space value and whose byte boundaries meet the alignment of the first space value.

[0135] Step S3023: Determine whether the application is successful. If the application is successful, the process ends after obtaining the first virtual address that matches the target memory space value; if the application fails, proceed to step S3024.

[0136] Step S3024: Apply for a virtual address whose size is the target memory space value and whose byte boundaries meet the alignment of the second space value.

[0137] Step S3025: Determine whether the application is successful. If the application is successful, the process ends after obtaining the first virtual address that matches the target memory space value; if the application fails, proceed to step S3026.

[0138] Step S3026: Find a virtual address of a size equal to the target memory space value, that is, Figure 1B The original process is not improved and ends when the application is successful.

[0139] Specifically, based on the virtual address found that matches the target memory space value, the target virtual address to be mapped is determined therein. Since the virtual address that matches the target memory space value includes a first virtual address and a second virtual address, there may be two different situations in which the target virtual address to be mapped is determined therein. In one possible implementation, a virtual address to be mapped that matches the size of the first space value is searched for. If found, the virtual address to be mapped that matches the size of the first space value is determined as the target virtual address; in another possible implementation, if not found, a virtual address to be mapped that matches the size of the second space value is searched for. If found, the virtual address to be mapped that matches the size of the second space value is determined as the target virtual address. It should be noted that the byte boundary type of the target virtual address is consistent with the byte boundary of the first virtual address or the second virtual address.

[0140] It should be noted that the above step S302 may be executed by the operating system through the system call module and the memory management module in the kernel state, and the embodiment of the present application does not specifically limit this.

[0141] Step S303: Determine the target physical address to be mapped from the physical memory space, and determine whether the size and byte boundary of the target virtual address and the target physical address meet the first condition.

[0142] Specifically, the operating system can use the memory management module to search for a physical address that matches the size of the first space value or the second space value in the physical address space of the memory as much as possible. If the physical addresses of the above two space value sizes are not found in the physical address space, a physical address of a smaller fixed space value size (for example, 4KB) can also be searched. It should be noted that the physical addresses found above all refer to a continuous address space, which is used to determine the target physical address to be mapped. Furthermore, a physical address page table can be created, and the found physical address can be passed into the above physical address page table from top to bottom according to the size of the space value, and the physical address currently pointed to by the pointer in the above physical address page table can be determined as the target physical address in the above step S303. The operating system can track the allocation of physical memory by managing the physical address page table.

[0143] Further, based on the first condition, it is determined whether the size and byte boundary of the target virtual address and the target physical address meet the first condition. Since the first condition includes the first alignment condition and the second alignment condition, there may be two different situations. In one possible implementation, it is determined whether the size of the target virtual address and the target physical address are both the first space value and the byte boundary meets the first space value alignment, that is, the first alignment condition; in another possible implementation, if the first alignment condition is not met, it is determined whether the size of the target virtual address and the target physical address are both the second space value and the byte boundary meets the second space value alignment, that is, the second alignment condition. Among them, when the first condition is judged, it is necessary to determine whether the space value size and byte boundary of the target physical address and the target virtual address meet the conditions to ensure that when the CPU performs memory access, the corresponding target physical address can be accessed according to the target virtual address. For example, when only the byte boundary is aligned and the space value size does not meet the conditions, such as the virtual address is 2MB, and the physical address is 1.5MB, then the CPU accesses according to the 2MB value, and there will be a problem of accessing non-existent space. Therefore, the judgment of the above first condition enables the CPU to access the address space with a size of the first space value when performing memory access, thereby avoiding access to non-existent space.

[0144] Optionally, the alignment type of the byte boundary may also include more types of space value sizes, that is, the first condition may not only include the above-mentioned first alignment condition and the second alignment condition, but may further include other alignment conditions (i.e., judging whether both the space value size and the byte boundary satisfy the other alignment conditions). For example, the number of alignment conditions may depend on the number of types of memory pools of different units provided in the memory resources, or be related to the number of types of memory pools. It is understandable that when the alignment type of the byte boundary includes more types of alignment space values, more rounds of alignment condition judgments may be required (i.e., more types of space value sizes and alignment judgments). For specific judgments on the size or alignment of the space value, reference may be made to the above-mentioned judgments on the size and alignment of the first space value or the second space value, which will not be repeated here.

[0145] Step S304: If the first condition is met, determine the attribute parameters that match the first condition.

[0146] Specifically, based on the different first alignments that are satisfied, the attribute parameters that are determined to match the first condition are also different. For example, the attribute parameters can be used to indicate that the physical address stored in a single page table entry corresponds to pages of multiple different sizes (such as 64KB, 2MB, 32MB, etc.). In one possible implementation, if the first alignment condition is satisfied, a first attribute parameter that matches the first alignment condition is determined, and the first attribute parameter is used to indicate that the page corresponding to the physical address stored in the single page table entry is a large page of a size of the first space value. In another possible implementation, if the second alignment condition is satisfied, a second attribute parameter that matches the second alignment condition is determined, and the second attribute parameter is used to indicate that the page corresponding to the physical address stored in the single page table entry is a continuous page of a size of the second space value.

[0147] Step S305: creating a page table matching the attribute parameters, and establishing a mapping relationship between the target virtual address and the target physical address.

[0148] Specifically, based on the attribute parameters determined above, a page table with attributes matching the first condition can be created, thereby establishing a mapping relationship between the target virtual address and the target physical address. Since the size of the physical address that can be mapped by a single page table entry of the page table matches the first condition, and the first condition includes the alignment type of the byte boundary (byte boundaries of different sizes can be set according to different application scenarios), therefore, in the process of mapping the virtual address to the physical address in the embodiment of the present application, a single page table entry can map physical pages of different attributes under different requirements, which can effectively improve the efficiency of page table query when the CPU accesses the memory and reduce the TLB Miss rate. For example, a single page table entry can map a large page or a continuous page, so that the mapping relationship between the virtual address and the physical address can be established using fewer page table entries, so that the page table level queried when the CPU accesses the memory is reduced or the number of page tables is reduced. Exemplarily, when the embodiments of the present application are applied in an application scenario of a direct memory access buffer (DMA-BUF), and the alignment type of the byte boundary corresponds to a larger value, the number of page table entries can be reduced, the number of valid TLB page tables can be increased, and the TLB miss rate can be reduced, so that the physical address can be accessed faster when direct memory access is performed using the fast buffer TLB, thereby improving the addressing performance of the CPU.

[0149] In a possible implementation, L-level page tables are created in sequence, and the attribute parameters matching the first condition are passed to the current page table in the L-level page tables step by step, and based on the target virtual address and the corresponding page table entry in the current page table, the corresponding next-level page table is searched; when the L-th level page table in the L-level page table is created, the attribute parameters matching the first condition are passed to the L-th level page table, and it is determined whether the passed-in attribute parameters are the first attribute parameters; if so, based on the target virtual address and the corresponding page table entry in the L-th level page table, the corresponding physical page is searched and the target physical address is passed to the physical page, and a next-level page table is established. The mapping relationship between the target physical address and the L-th level page table is determined to determine the mapping relationship between the target virtual address and the target physical address; if not, based on the target virtual address and the corresponding page table entry in the L-th level page table, the corresponding L+1 page table is searched; the L+1 level page table is created, and then based on the target virtual address and the corresponding page table entry in the L+1 page table, the corresponding physical page is searched and the target physical address is transferred to the physical page, and the mapping relationship between the target physical address and the L+1 level page table is established to determine the mapping relationship between the target virtual address and the target physical address. Wherein, L is a positive integer, and the physical address range that can be mapped by the L-th level page table is greater than the physical address range that can be mapped by the L+1 level page table. Creating a multi-level page table can improve the efficiency of memory management. When only part of the virtual address space needs to be mapped, only the required page table level can be mapped without allocating a page table for the entire address space, thereby saving memory space. At the same time, when performing address conversion, only a relatively small page table level needs to be accessed without traversing the entire page table structure, thereby reducing the number of memory accesses and increasing the memory conversion speed to improve memory access efficiency. It should be noted that the creation of the page table and the input of the attribute parameters may be performed simultaneously or in a certain order, and the embodiment of the present application does not specifically limit this.

[0150] Exemplarily, there are usually multiple types of L-level page tables, which may include but are not limited to three-level page tables and four-level page tables. For example, when the L-level page table is a three-level page table, the first-level page table is a page global directory (Page Global Directory, PGD), the second-level page table is a page upper directory (Page Upper Directory, PUD), the third-level page table is a page middle directory (Page Middle Directory, PMD), and the fourth-level page table is a direct page table (Page Table, PT). Any entry in the above page tables is a page table entry (Page Table Entry, PTE), which is used to store a virtual page number (such as a page table page number), a page frame address bit (such as the address corresponding to the physical memory), and an attribute (such as an attribute parameter of the page table).

[0151] For example, when the created page table is a three-level page table, see Figure 3C , Figure 3CA simplified schematic diagram of a three-level page table mapping provided in an embodiment of the present application.

[0152] like Figure 3C As shown, MMU 2211 maps virtual addresses to physical addresses through page tables. Specifically, a PGD page table is created, and the corresponding PUD page table is searched based on the target virtual address and the corresponding page table entry in the PGD page table, and the attribute parameters are passed into the PGD page table; a PUD page table is created, and the corresponding PMD page table is searched based on the target virtual address and the corresponding page table entry in the PUD page table, and the attribute parameters are passed into the PUD page table; a PMD page table is created, and the attribute parameters are passed into the PMD page table. It is determined whether the attribute parameter passed in is the first attribute parameter. If so, based on the target virtual address and the corresponding page table entry in the PMD page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the PMD page table is established, thereby establishing a mapping relationship between the target virtual address and the target physical address; if not, based on the target virtual address and the corresponding page table entry in the PMD page table, the corresponding PT page table is searched; a PT page table is created, and based on the target virtual address and the corresponding page table entry in the PT page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the PT page table is established, thereby establishing a mapping relationship between the target virtual address and the target physical address.

[0153] Exemplarily, when the L-level page table is a four-level page table, the first-level page table is a page global directory (PGD), the second-level page table is a page fourth-level directory (P4D), the third-level page table is a page upper directory (PUD), the fourth-level page table is a page middle directory (PMD), and the fifth-level page table is a direct page table (PT). Any entry in the above page tables is a page table entry (PTE), which is used to store a virtual page number (such as a page table page number), a page frame address bit (such as the address corresponding to the physical memory), and an attribute (such as an attribute parameter of the page table). When the created page table is a four-level page table, please refer to Figure 3D , Figure 3D A simplified schematic diagram of a four-level page table mapping provided in an embodiment of the present application.

[0154] like Figure 3DAs shown, MMU 2211 maps virtual addresses to physical addresses through page tables. Specifically, a PGD page table is created, and the corresponding P4D page table is searched based on the target virtual address and the corresponding page table entry in the PGD page table, and the attribute parameters are passed into the PGD page table; a P4D-level page table is created, and the corresponding PUD page table is searched based on the target virtual address and the corresponding page table entry in the P4D page table, and the attribute parameters are passed into the P4D page table; a PUD page table is created, and the corresponding PMD page table is searched based on the target virtual address and the corresponding page table entry in the PUD page table, and the attribute parameters are passed into the PUD page table; a PMD page table is created, and the attribute parameters are passed into the PMD page table. It is determined whether the attribute parameter passed in is the first attribute parameter. If so, based on the target virtual address and the corresponding page table entry in the PMD page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the PMD page table is established, thereby establishing a mapping relationship between the target virtual address and the target physical address; if not, based on the target virtual address and the corresponding page table entry in the PMD page table, the corresponding PT page table is searched; a PT page table is created, and based on the target virtual address and the corresponding page table entry in the PT page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the PT page table is established, thereby establishing a mapping relationship between the target virtual address and the target physical address.

[0155] It should be noted that the above Figure 3C and Figure 3D A possible process of page table mapping in the method provided in the embodiment of the present application, when L is any other positive integer, the steps of creating a page table to establish a mapping relationship between the target virtual address and the target physical address are similar, and can refer to the above Figure 3C and Figure 3D The steps are not described one by one here.

[0156] In one possible implementation, when the created page table is a four-level page table, see Figure 4 , Figure 4 An example flow chart of performing dynamic memory allocation based on a DMA-BUF mechanism with a 4KB page granularity provided in an embodiment of the present application, the specific steps are as follows:

[0157] Step S401: receiving a memory request from an application and making a system call.

[0158] Step S402: Execute a system call to start a memory mapping operation.

[0159] Step S403: Determine a virtual address that matches the target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the virtual address.

[0160] Specifically, in step S403, different virtual addresses that match the target memory space value can be determined according to different alignment types of different byte boundaries. Furthermore, the byte boundary alignment type includes a first space value alignment and a second space value alignment, and correspondingly, the byte boundary alignment type of the virtual address includes a first space value alignment and a second space value alignment. Since the embodiment of the present application is based on a page granularity of 4KB, the corresponding sizes of the first space value and the second space value are 2MB and 64KB respectively, then the byte boundary alignment type of the virtual address includes 2MB alignment and 64KB alignment. Therefore, the virtual address that matches the target memory space value found from the virtual memory space includes a first virtual address and a second virtual address, wherein the byte boundary of the first virtual address is 2MB aligned, that is, the lower 21 bits of the first virtual address are all 0, and the byte boundary of the second virtual address is 64KB aligned, that is, the lower 16 bits of the second virtual address are all 0. It should be noted that the specific implementation steps of finding a virtual address that matches the target memory space value in step 3 can be referred to above. Figure 3B The relevant description in will not be repeated here.

[0161] Furthermore, the target virtual address is determined based on the virtual address that matches the target memory space value found in the virtual memory space. Since the virtual address that matches the target memory space value may be of two different types, such as a first virtual address and a second virtual address, there may be two different situations for determining the target virtual address. In one possible implementation, when the virtual address that matches the target memory space value found is the first virtual address, a virtual address to be mapped with a space value size of 2MB is searched. If found, the virtual address to be mapped with a space value size of 2MB and a byte boundary that satisfies the 2MB alignment is determined as the target virtual address; if not found, a virtual address to be mapped with a space value size of 64KB is searched. If found, the virtual address to be mapped with a space value size of 64KB and a byte boundary that satisfies the 2MB alignment is determined as the target virtual address. In another possible implementation, when the virtual address found that matches the target memory space value is the second virtual address, a search is made for a virtual address to be mapped whose space value size is 2MB. If found, the virtual address to be mapped whose space value size is 2MB and whose byte boundaries satisfy the 64KB alignment is determined as the target virtual address. If not found, a search is made for a virtual address to be mapped whose space value size is 64KB. If found, the virtual address to be mapped whose space value size is 64KB and whose byte boundaries satisfy the 64KB alignment is determined as the target virtual address.

[0162] Step S404: Determine the target physical address to be mapped from the physical memory space.

[0163] Exemplarily, the operating system searches for a 2MB or 64KB space value physical address in the physical address space of the memory through the memory management module, and the physical address is a continuous address space. A physical address page table is created, and the physical address is passed to the physical address page table from top to bottom according to the space value size, and the pointer points to the physical address in the physical address page table as the target physical address.

[0164] Step S405: Determine whether the size and byte boundary of the target virtual address and the target physical address meet the first condition.

[0165] Specifically, in Figure 4 In the corresponding embodiment, the above step S405 may specifically include step S4051, and may further include step S4052, wherein the first condition includes a first alignment condition and a second alignment condition, wherein the first alignment condition is that the sizes of the target virtual address and the target physical address are both the first space value and the byte boundary meets the first space value alignment, and the second alignment condition is that the sizes of the target virtual address and the target physical address are both the second space value and the byte boundary meets the second space value alignment. Based on the first condition, there are two possible implementations S4051 and S4052: In one possible implementation, it is determined whether the sizes and byte boundaries of the target virtual address and the target physical address meet the first alignment condition, that is, S4051: it is determined whether the sizes of the target virtual address and the target physical address are both 2MB and the byte boundary meets the 2MB alignment, if yes, it proceeds to step S4061; in another possible implementation, if no, it proceeds to step S4052: it is determined whether the sizes of the target virtual address and the target physical address are both 64KB and the byte boundary meets the 64KB alignment, that is, the second alignment condition.

[0166] Step S406: If the first condition is met, determine the attribute parameters that match the first condition.

[0167] Specifically, in Figure 4 In the corresponding embodiment, the above-mentioned step S406 may specifically include step S4061 or step S4062. Since the first condition may include a first alignment condition and a second alignment condition, exemplarily, if the first alignment condition is met, the attribute parameter matching the first alignment condition is determined, that is, S4061: determine the first attribute parameter matching the first alignment condition, and the first attribute parameter is used to indicate that the page corresponding to the physical address stored in a single page table entry is a large page with a size of 2MB; if the second alignment condition is met, determine the attribute parameter matching the second alignment condition, that is, S4062: determine the second attribute parameter matching the second alignment condition, and the second attribute parameter is used to indicate that the page corresponding to the physical address stored in a single page table entry is a continuous page with a size of 64KB.

[0168] Step S407: Create a first-level page table, search for a corresponding second-level page table based on the target virtual address and the corresponding page table entry in the first-level page table, and pass the attribute parameters into the first-level page table.

[0169] Step S408: Create a second-level page table, search for a corresponding third-level page table based on the target virtual address and the corresponding page table entry in the second-level page table, and pass the attribute parameters into the second-level page table.

[0170] Step S409: Create a third-level page table, search for a corresponding fourth-level page table based on the target virtual address and the corresponding page table entry in the third-level page table, and pass the attribute parameters into the third-level page table.

[0171] Step S410: Create a fourth-level page table, and pass attribute parameters into the fourth-level page table.

[0172] Step S411: Determine whether the attribute parameter passed in is the first attribute parameter. If yes, proceed to step S4121.

[0173] Step S412: Figure 4 In the corresponding embodiment, the above step S412 may specifically include step S4121 or step S4122. There are two possible situations based on the attribute parameters passed into the fourth-level page table. In one possible implementation, when the attribute parameter passed in is the first attribute parameter, step S4121 is performed: based on the target virtual address and the corresponding page table entry in the fourth-level page table, the corresponding physical page is searched and the target physical address is passed into the physical page, and a mapping relationship between the target physical address and the fourth-level page table is established, thereby establishing a mapping relationship between the target virtual address and the target physical address. In another possible implementation, when the attribute parameter passed in is not the first attribute parameter, step S4122 is performed: based on the target virtual address and the corresponding page table entry in the fourth-level page table, the corresponding fifth page table is searched.

[0174] Step S413: Create a fifth-level page table, and based on the target virtual address and the corresponding page table entry in the fifth-level page table, find the corresponding physical page and pass the target physical address into the physical page, establish a mapping relationship between the target physical address and the fifth-level page table, and thus establish a mapping relationship between the target virtual address and the target physical address.

[0175] The above detailed description of the method of the embodiment of the present application. It is understandable that, in order to implement the corresponding functions mentioned above, each device includes a hardware structure and / or software module corresponding to the execution of each function. In combination with the units and steps of the examples described in the embodiments disclosed herein, the present application can be implemented in the form of hardware or a combination of hardware and computer software. Whether a function is executed in the form of hardware or computer software driving hardware depends on the specific application and design constraints of the technical solution. Professional and technical personnel can use different methods to implement the described functions for each specific application, but such implementation should not be considered to be beyond the scope of the present application. The following provides related equipment of the embodiment of the present application.

[0176] The embodiment of the present application can divide the functional modules of the device according to the above method example. For example, each functional module can be divided according to each function, or two or more functions can be integrated into one module. The above integrated module can be implemented in the form of hardware or software functional module.

[0177] In the case of dividing each functional module into corresponding functional modules, Figure 5 A possible logical structure diagram of a device is shown, and the device may be a device for executing the above-mentioned memory allocation method. The device 500 may include a receiving unit 501, a first determining unit 502, a second determining unit 503, and a mapping unit 504. Among them:

[0178] The receiving unit 501 is configured to receive a first memory request from an application program, wherein the first memory request includes a target memory space value.

[0179] The first determining unit 502 is used to determine a virtual address matching the aforementioned target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the aforementioned virtual address.

[0180] The second determination unit 503 is used to determine the target physical address to be mapped from the physical address, and determine whether the size and byte boundary of the aforementioned target virtual address and the aforementioned target physical address meet the first condition, wherein the aforementioned first condition includes the alignment type of the byte boundary. If the first condition is met, determine the attribute parameter matching the first condition.

[0181] The mapping unit 504 is used to create a page table matching the attribute parameters and establish a mapping relationship between the target virtual address and the target physical address.

[0182] In one possible implementation, the alignment type of the byte boundary includes a first space value alignment and a second space value alignment; the aforementioned target virtual address includes a virtual address that satisfies the aforementioned first space value alignment or a virtual address that satisfies the aforementioned second space value alignment; wherein the aforementioned first space value or the aforementioned second space value is determined based on the size of the page granularity, and the aforementioned first space value is greater than the aforementioned second space value.

[0183] In a possible implementation, the first space value is aligned so that the lower M bits of the address are all 0, the aforementioned second space value is aligned so that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N.

[0184] In a possible implementation, the aforementioned page granularity is 4KB, the aforementioned first space value is 2MB, and the aforementioned second space value is 64KB; or, the aforementioned page granularity is 16KB, the aforementioned first space value is 8MB, and the aforementioned second space value is 2MB; or, the aforementioned page granularity is 64KB, the aforementioned first space value is 32MB, and the aforementioned second space value is 2MB. The embodiment of the present application does not specifically limit the size of the page granularity, and the sizes of the first space value and the second space value vary accordingly with different page granularities.

[0185] In a possible implementation manner, the first determining unit 502 is specifically configured to:

[0186] Apply for a virtual address from the virtual memory space whose size is the target memory space value and whose byte boundaries meet the alignment of the first space value; determine whether the application is successful, and if so, obtain a first virtual address that matches the target memory space value.

[0187] In a possible implementation manner, the first determining unit 502 is specifically configured to:

[0188] If the application fails, then reapply for a virtual address of the size of the aforementioned target memory space value and the byte boundary of which satisfies the alignment of the aforementioned second space value; determine whether the application is successful, and if the application is successful, obtain a second virtual address that matches the aforementioned target memory space value. In a possible implementation, the aforementioned determination of the target virtual address to be mapped, the aforementioned first determination unit 502 is specifically used to:

[0189] Search for a virtual address to be mapped that matches the size of the aforementioned first space value; if found, determine the virtual address to be mapped that matches the size of the aforementioned first space value as the aforementioned target virtual address; if not found, search for a virtual address to be mapped that matches the size of the aforementioned second space value; if found, determine the virtual address to be mapped that matches the size of the aforementioned second space value as the aforementioned target virtual address.

[0190] In a possible implementation manner, the second determining unit 503 is specifically configured to:

[0191] Find a physical address that matches the size of the first space value or the second space value; create a physical address page table, and pass the physical addresses that match the size of the first space value and the second space value into the physical address page table from top to bottom according to the size of the space value; determine the physical address in the physical address page table pointed to by the pointer as the target physical address.

[0192] In a possible implementation manner, the second determining unit 503 is specifically configured to:

[0193] Determine whether the size and byte boundary of the aforementioned target virtual address and the aforementioned target physical address satisfy a first alignment condition, wherein the first alignment condition includes that the size of the aforementioned target virtual address and the aforementioned target physical address is the aforementioned first space value, and the byte boundary satisfies the aforementioned first space value alignment.

[0194] If the first condition is met, the attribute parameters matching the first condition are determined, and the second determination unit 503 is specifically used to:

[0195] If the aforementioned first alignment condition is met, a first attribute parameter matching the aforementioned first alignment condition is determined, wherein the aforementioned first attribute parameter is used to indicate that the page corresponding to the physical address stored in the single page table entry is a large page with a size of the aforementioned first space value.

[0196] In a possible implementation manner, the second determining unit 503 is specifically configured to:

[0197] If the aforementioned first alignment condition is not met, it is determined whether the size and byte boundary of the aforementioned target virtual address and the aforementioned target physical address meet the second alignment condition, and the aforementioned second alignment condition includes that the size of the aforementioned target virtual address and the aforementioned target physical address is the aforementioned second space value, and the byte boundary meets the aforementioned second space value alignment.

[0198] If the first condition is met, the attribute parameters matching the first condition are determined, and the second determination unit 503 is specifically used to:

[0199] If the aforementioned second alignment condition is met, a second attribute parameter matching the aforementioned second alignment condition is determined, wherein the aforementioned second attribute parameter is used to indicate that the page corresponding to the physical address stored in the single page table entry is a continuous page of a size equal to the aforementioned second space value.

[0200] In a possible implementation manner, the mapping unit 504 is specifically configured to:

[0201] Create L-level page tables in sequence, pass the aforementioned attribute parameters that match the aforementioned first condition to the current page table in the aforementioned L-level page tables step by step, and search for the corresponding next-level page table based on the aforementioned target virtual address and the corresponding page table entry in the current page table; when the L-th level page table in the aforementioned L-level page table is created, pass the aforementioned attribute parameters that match the aforementioned first condition to the aforementioned L-th level page table, and determine whether the passed-in attribute parameters are the aforementioned first attribute parameters; if so, search for the corresponding physical page based on the aforementioned target virtual address and the corresponding page table entry in the aforementioned L-th level page table, and pass the aforementioned target physical address to the physical page, establish a mapping relationship between the aforementioned target physical address and the aforementioned L-th level page table, and thereby establish a mapping relationship between the aforementioned target virtual address and the aforementioned target physical address. If not, based on the aforementioned target virtual address and the corresponding page table entry in the aforementioned L-level page table, the corresponding L+1 page table is searched; the aforementioned L+1-level page table is created, and based on the aforementioned target virtual address and the corresponding page table entry in the aforementioned L+1 page table, the corresponding physical page is searched and the aforementioned target physical address is passed into the physical page, and a mapping relationship between the aforementioned target physical address and the aforementioned L+1-level page table is established.

[0202] In a possible implementation, the physical address range mapped by the aforementioned L-th level page table is larger than the physical address range mapped by the aforementioned L+1-th level page table, where L is a positive integer.

[0203] It should be noted that the division of modules in the embodiment of the present application is schematic and may be just a logical function division. There may be other division methods in actual implementation, and the embodiment of the present application does not make any specific limitations on this.

[0204] It should also be noted that the specific functions of each unit in the device 500 described in the embodiment of the present application can be found in the above Figure 2-Figure 4 The relevant description in the embodiments described in will not be repeated here.

[0205] Figure 6 is a schematic diagram of a possible hardware structure of a device provided in an embodiment of the present application. The device 600 may be implemented as or included in Figure 2 In the system architecture 200.

[0206] like Figure 6As shown, the device 600 includes a processor 221, a memory 222, and a storage device 223. The processor 221 can execute the code or instructions of the computer program loaded from the memory 222; the memory 222 stores the resources required for the computer to run, including, for example, the assembly code, variables, heap, stack and other data obtained after the computer program is compiled; the storage device 223 can be used to store data persistently. The processor 221, the memory 222 and the storage device 223 are connected to each other through the bus 224, so that efficient data transmission and communication can be achieved between the components.

[0207] Exemplarily, the processor 221 may be a general and / or special processing component with various processing and computing capabilities, and may run some examples including but not limited to an operating system, a file system or an application program, etc., to control multiple hardware or software elements connected to the processor 221, and may process various data and perform operations. For example, the processor 221 may load instructions or data stored in the storage device 223 into the memory 222, and call the instructions or data that need to be calculated to the processor 221 for calculation. When the calculation is completed, the processor 221 temporarily stores the result in the memory 222, and stores the instructions or data that need to be stored for a long time in the storage device 223. Optionally, the processor 221 may include one or more processing units (also referred to as processing cores), for example: the processor 221 may include one or more of a central processing unit (CPU), an application processing unit (application processor, AP), a modem processing unit, a graphics processing unit (graphics processing unit, GPU), an image signal processing unit (image signal processor, ISP), a video codec unit, a digital signal processing unit (digital signal processor, DSP), a baseband processing unit and a neural-network processing unit (neural-network processing unit, NPU), etc. The different processing units may be independent devices or integrated into one or more devices. For a multi-core processor, each physical core corresponds to a memory management unit (MMU).

[0208] Figure 6Schematically represents an MMU 2211 and a TLB 2212 cache included in a processor 221. Exemplarily, the MMU 2211 performs address translation to map the virtual address of the page addressed by the process to the physical address of the corresponding frame in the memory 222. Optionally, the TLB 2212 cache is used to store the most recent address translation results, and cache the mapping relationship between the virtual address and the physical address. When the processor 221 accesses the memory, it will first search for the mapping of the virtual address and the physical address in the TLB 2212 cache. If a matching mapping is found, the physical address can be directly accessed without accessing the main memory or external memory, so as to complete the address translation operation faster. However, if the required mapping cannot be found in the TLB 2212, a TLB miss will occur, and the processor 221 will map the virtual address to the physical address through the MMU 2211. Once the correct mapping information is obtained, the processor will store it in the TLB 2212 so that it can be directly used in future accesses. Among them, the cooperation between MMU 2211 and the memory management module 214 in the operating system is very close, and the function of virtual memory management can be realized for the memory management module 214. Exemplarily, the memory management module 214 is responsible for maintaining and managing data structures such as page tables and segment tables, and communicating with MMU 2211 to provide interfaces for allocating and reclaiming memory. MMU 2211 is responsible for converting logical addresses and performing access rights checks based on the page table and segment table information provided by the memory management module. When pages are moved between different physical memory locations, MMU 2211 manages the entries of the corresponding page tables, thereby updating the page tables as needed.

[0209] Exemplarily, the memory 222 is usually a power-off volatile memory, and the content stored thereon will be lost when the power is off, and it can also be called a main memory. The memory 222 in the present application includes a readable and writable operating memory, which is used to temporarily store the operation data in the processor 221, and to exchange data with the storage device 223 or other external memory, and can be used as a storage medium for temporary data of the operating system or other running programs. For example, the operating system running on the processor 221 transfers the data to be calculated from the internal memory 222 to the processor 221 for calculation, and when the calculation is completed, the processor 221 transmits the result.

[0210] The memory 222 may include one or more of a dynamic random access memory (DRAM), a static random access memory (SRAM), a synchronous dynamic random access memory (SDRAM), etc. Among them, DRAM includes double data rate synchronous dynamic random access memory (Double Data Rate Synchronous Dynamic Random Access Memory, DDR SDRAM), referred to as DDR, second-generation double data rate synchronous dynamic random access memory (DDR2), third-generation double data rate synchronous dynamic random access memory (DDR3), fourth-generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 4, LPDDR4) and fifth-generation low power double data rate synchronous dynamic random access memory (Low Power Double Data Rate 5, LPDDR5), etc.

[0211] Exemplarily, the storage device 223 is a non-volatile memory, and the content stored therein will not be lost after power failure. The storage device 223 may include any type of non-transitory storage device, which is used for long-term storage of data, programs and other information. Since the processor 221 cannot directly read the instructions and data in the storage device 223, when the processor 221 executes the read (or load) command, it is actually to temporarily load the instructions and / or data stored in the storage device 223 into the memory 2222, and then the processor 221 performs memory access and other operations on the memory 222 through the operating system. The storage device 223 may include at least one such as a solid-state drive, a hard disk drive, a magnetic disk drive, or an optical disk drive. The storage device 223 is connected to other components of the device 600 via the bus 224, and the processor 221 can load the program stored in the above-mentioned storage device 2232 into the memory 222 to execute the method described in the above-mentioned possible embodiment.

[0212] It should be noted that the device 600 illustrated in the embodiment of the present application may include more or fewer components than shown in the figure, or combine some components, or split some components, or arrange the components differently. The components shown in the figure may be implemented in hardware, software, or any combination of software and hardware.

[0213] An embodiment of the present application also provides a computer-readable storage medium, wherein the computer-readable storage medium may store a program, and when the program is executed by a computing device, it implements part or all of the steps of any one of the memory allocation methods recorded in the above method embodiments.

[0214] An embodiment of the present application also provides a computer program, which includes instructions. When the computer program is executed by a computing device, the computing device can execute part or all of the steps of any one of the above-mentioned memory allocation methods.

[0215] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0216] It should be noted that, for the aforementioned method embodiments, for the sake of simplicity of description, they are all expressed as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the described order of actions, because according to the present application, some steps may be performed in other orders or simultaneously, or some steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application. It should also be noted that the features and functions of two or more devices disclosed in the present invention can be concretized in one device. Conversely, the features and functions of a device described above can be further divided into being concretized by multiple devices.

[0217] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the present application is generated in whole or in part. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions can be transmitted from a website site, computer, server or data center to another website site, computer, server or data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line) or wireless (e.g., infrared, wireless, microwave, etc.) mode. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that includes one or more available media integrated. The available medium can be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state disk (SSD)), etc.

[0218] Those skilled in the art can understand that to implement all or part of the processes in the above-mentioned embodiments, the processes can be completed by computer programs to instruct related hardware, and the programs can be stored in computer-readable storage media. When the programs are executed, they can include the processes of the above-mentioned method embodiments. The aforementioned storage media include: ROM or random access memory RAM, magnetic disk or optical disk and other media that can store program codes.

[0219] In short, the above is only an embodiment of the technical solution of this application, and is not intended to limit the protection scope of this application. Any modification, equivalent replacement, improvement, etc. made according to the disclosure of this application shall be included in the protection scope of this application.

Claims

1. A memory allocation method, characterized in that: Applied to electronic equipment, the method comprises: receiving a first memory request from an application, wherein the first memory request includes a target memory space value; Determine a virtual address matching the target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the virtual address; Determine a target physical address to be mapped from the physical memory space, and determine whether the size and byte boundary of the target virtual address and the target physical address meet a first condition, wherein the first condition includes an alignment type of a byte boundary; If the first condition is met, determining the attribute parameters matching the first condition; A page table matching the attribute parameters is created, and a mapping relationship between the target virtual address and the target physical address is established.

2. The method according to claim 1, characterized in that The alignment type of the byte boundary includes a first space value alignment and a second space value alignment; the target virtual address includes a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment; wherein the first space value or the second space value is determined based on the size of the page granularity, and the first space value is greater than the second space value.

3. The method according to claim 2, characterized in that The first space value is aligned so that the lower M bits of the address are all 0, and the second space value is aligned so that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N.

4. The method according to claim 2 or 3, characterized in that: The page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB.

5. The method according to any one of claims 2 to 4, characterized in that: Determining a virtual address matching the target memory space value from the virtual memory space includes: Apply for a virtual address segment from the virtual memory space, the size of which is equal to the target memory space value and the byte boundary of which satisfies the alignment of the first space value; Determine whether the application is successful. If the application is successful, obtain a first virtual address that matches the target memory space value.

6. The method according to claim 5, characterized in that Determining a virtual address matching the target memory space value from the virtual memory space includes: If the application fails, reapply for a virtual address whose size is the target memory space value and whose byte boundary satisfies the alignment of the second space value; Determine whether the application is successful. If the application is successful, obtain a second virtual address that matches the target memory space value.

7. The method according to claim 5 or 6, characterized in that: The determining of the target virtual address to be mapped includes: Find a virtual address to be mapped that matches the size of the first space value; If found, the to-be-mapped virtual address that matches the size of the first space value is determined as the target virtual address; If not found, searching for a virtual address to be mapped that matches the size of the second space value; If found, the to-be-mapped virtual address that matches the size of the second space value is determined as the target virtual address.

8. The method according to any one of claims 2 to 4, characterized in that: The determining of the target physical address to be mapped includes: Finding a physical address that matches the size of the first space value or the second space value; Create a physical address page table, and transfer the physical addresses matching the first space value and the second space value from top to bottom into the physical address page table according to the space value size; The physical address in the physical address page table pointed to by the pointer is determined as the target physical address.

9. The method according to claim 7 or 8, characterized in that: The determining whether the size and byte boundary of the target virtual address and the target physical address meet the first condition includes: Determine whether the size and byte boundary of the target virtual address and the target physical address meet a first alignment condition, wherein the first alignment condition includes that the size of the target virtual address and the target physical address is the first space value, and the byte boundary meets the first space value alignment; If the first condition is met, determining the attribute parameters matching the first condition includes: If the first alignment condition is met, a first attribute parameter matching the first alignment condition is determined, wherein the first attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a large page having a size of the first space value.

10. The method according to claim 9, characterized in that The determining whether the size and byte boundary of the target virtual address and the target physical address meet the first condition includes: If the first alignment condition is not met, determining whether the size and byte boundary of the target virtual address and the target physical address meet a second alignment condition, wherein the second alignment condition includes that the size of the target virtual address and the target physical address is the second space value, and the byte boundary meets the second space value alignment; If the first condition is met, determining the attribute parameters matching the first condition further includes: If the second alignment condition is met, a second attribute parameter matching the second alignment condition is determined, wherein the second attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a continuous page having a size of the second space value.

11. The method according to claim 9 or 10, characterized in that: The step of creating a page table matching the attribute parameters comprises: Create L-level page tables in sequence, transfer the attribute parameters matching the first condition to the current page table in the L-level page tables level by level, and search for the corresponding next-level page table based on the target virtual address and the corresponding page table entry in the current page table; When creating an L-th level page table in the L-level page tables, transferring the attribute parameter matching the first condition into the L-th level page table, and determining whether the transferred attribute parameter is the first attribute parameter; If yes, based on the target virtual address and the corresponding page table entry in the L-th level page table, find the corresponding physical page and transfer the target physical address to the physical page, so as to establish a mapping relationship between the target physical address and the L-th level page table; If not, searching the corresponding L+1th page table based on the target virtual address and the corresponding page table entry in the Lth level page table; Create the L+1th level page table, find the corresponding physical page based on the target virtual address and the corresponding page table entry in the L+1th page table, and transfer the target physical address to the physical page, so as to establish a mapping relationship between the target physical address and the L+1th level page table.

12. The method according to claim 11, characterized in that The physical address range mapped by the L-th level page table is larger than the physical address range mapped by the L+1-th level page table, where L is a positive integer.

13. A memory allocation device, characterized in that: include: A receiving unit, configured to receive a first memory request from an application, wherein the first memory request includes a target memory space value; A first determining unit, configured to determine a virtual address matching the target memory space value from the virtual memory space, and determine a target virtual address to be mapped from the virtual address; a second determination unit, configured to determine a target physical address to be mapped from the physical address, and determine whether the size and byte boundary of the target virtual address and the target physical address meet a first condition, wherein the first condition includes an alignment type of a byte boundary; if the first condition is met, determine an attribute parameter matching the first condition; A mapping unit is used to create a page table matching the attribute parameters and establish a mapping relationship between the target virtual address and the target physical address.

14. The device according to claim 13, characterized in that The alignment type of the byte boundary includes a first space value alignment and a second space value alignment; the target virtual address includes a virtual address that satisfies the first space value alignment or a virtual address that satisfies the second space value alignment; wherein the first space value or the second space value is determined based on the size of the page granularity, and the first space value is greater than the second space value.

15. The device according to claim 14, characterized in that The first space value is aligned so that the lower M bits of the address are all 0, and the second space value is aligned so that the lower N bits of the address are all 0, M and N are both positive integers, and M is greater than N.

16. The method according to claim 13 or 14, characterized in that The page granularity size is 4KB, the first space value size is 2MB, and the second space value size is 64KB; or, the page granularity size is 16KB, the first space value size is 8MB, and the second space value size is 2MB; or, the page granularity size is 64KB, the first space value size is 32MB, and the second space value size is 2MB.

17. The device according to any one of claims 14 to 16, characterized in that: The first determining unit is specifically configured to: Apply for a virtual address from the virtual memory space whose size is the target memory space value and whose byte boundaries meet the alignment of the first space value; determine whether the application is successful, and if so, obtain a first virtual address that matches the target memory space value.

18. The device according to claim 17, characterized in that The first determining unit is specifically configured to: If the application fails, then reapply for a virtual address whose size is the target memory space value and whose byte boundaries meet the alignment of the second space value; determine whether the application is successful. If the application is successful, obtain a second virtual address that matches the target memory space value.

19. The device according to claim 17 or 18, characterized in that Specifically used for: Search for a virtual address to be mapped that matches the size of the first space value; if found, determine the virtual address to be mapped that matches the size of the first space value as the target virtual address; if not found, search for a virtual address to be mapped that matches the size of the second space value; if found, determine the virtual address to be mapped that matches the size of the second space value as the target virtual address.

20. The device according to any one of claims 14 to 16, characterized in that: The second determining unit is specifically configured to: Search for a physical address that matches the size of the first space value or the second space value; create a physical address page table, and pass the physical addresses that match the size of the first space value and the second space value into the physical address page table from top to bottom according to the size of the space value; determine the physical address in the physical address page table pointed to by the pointer as the target physical address.

21. The device according to claim 19 or 20, characterized in that The second determining unit is specifically configured to: Determine whether the size and byte boundary of the target virtual address and the target physical address meet a first alignment condition, wherein the first alignment condition includes that the size of the target virtual address and the target physical address is the first space value, and the byte boundary meets the first space value alignment; If the first condition is met, determining the attribute parameter matching the first condition, the second determining unit is specifically configured to: If the first alignment condition is met, a first attribute parameter matching the first alignment condition is determined, wherein the first attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a large page having a size of the first space value.

22. The device according to claim 21, characterized in that The second determining unit is specifically configured to: If the first alignment condition is not met, determining whether the size and byte boundary of the target virtual address and the target physical address meet a second alignment condition, wherein the second alignment condition includes that the size of the target virtual address and the target physical address is the second space value, and the byte boundary meets the second space value alignment; If the first condition is met, determining the attribute parameter matching the first condition, the second determining unit is specifically configured to: If the second alignment condition is met, a second attribute parameter matching the second alignment condition is determined, wherein the second attribute parameter is used to indicate that a page corresponding to a physical address stored in a single page table entry is a continuous page having a size of the second space value.

23. The device according to claim 21 or 22, characterized in that The mapping unit is specifically used for: Create L-level page tables in sequence, pass the attribute parameters matching the first condition to the current page table in the L-level page tables step by step, and search for the corresponding next-level page table based on the target virtual address and the corresponding page table entry in the current page table; when creating the L-th level page table in the L-level page table, pass the attribute parameters matching the first condition to the L-th level page table, and determine whether the passed-in attribute parameters are the first attribute parameters; if so, search for the corresponding physical page based on the target virtual address and the corresponding page table entry in the L-th level page table and pass the target physical address to the physical page, and establish a mapping relationship between the target physical address and the L-th level page table; if not, search for the corresponding L+1th page table based on the target virtual address and the corresponding page table entry in the L-th level page table; create the L+1th level page table, search for the corresponding physical page based on the target virtual address and the corresponding page table entry in the L+1th page table and pass the target physical address to the physical page, and establish a mapping relationship between the target physical address and the L+1th level page table.

24. The device according to claim 22, characterized in that The physical address range mapped by the L-th level page table is larger than the physical address range mapped by the L+1-th level page table, where L is a positive integer.

25. An electronic device, characterized in that: It comprises a processor and a memory, wherein the memory is used to store programs and various data, and the processor is used to call the program code stored in the memory so that the electronic device executes the method as claimed in any one of claims 1 to 12.

26. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program runs on the electronic device, the electronic device executes the method according to any one of claims 1 to 12.

27. A computer program, characterized in that The computer program comprises instructions, and when the computer program is executed by the electronic device, the electronic device executes the method according to any one of claims 1 to 12.

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