GPIO control circuit and chip

Abstract

The invention relates to the technical field of analog integrated circuit design, and discloses a GPIO (General Purpose Input / Output) control circuit and a chip, and the GPIO control circuit comprises a voltage stabilizer circuit, a power-on reset circuit and a detection circuit. The voltage regulator circuit is configured to output a voltage signal; the power-on reset circuit is connected with the voltage stabilizer circuit and is configured to output a control signal with time delay according to the voltage signal; the detection circuit is connected with the power-on reset circuit and the GPIO interface and is configured to output an indication signal under the action of the control signal, and the indication signal is used for indicating the working state of the GPIO interface. By setting the control signal with time delay, it can be ensured that power-on of the voltage signal is completed within the time delay duration, and then the corresponding control signal is output, so that the detection circuit outputs the indication signal to indicate the GPIO interface to work. Therefore, when the GPIO interface starts to work, the power-on of the voltage signal is completed, so that the problem of power failure in the power-on process of the voltage signal is solved.

Description

Technical Field

[0001] The present application relates to the technical field of analog integrated circuit design, for example, to a GPIO control circuit and chip. Background Art

[0002] At present, for chips used in small electronic devices, in order to ensure long-term endurance, low-power working mode is particularly important. The general power supply system has both high-power power supply and low-power power supply, which are used to support the high-performance mode and low-power mode of the system respectively. Some retention (data retention) and RAM (Random Access Memory) data are hung in low-power mode. In order to support more peripheral interfaces in low-power mode, the system will also hang GPIO (General Purpose Input / Output) under low-power power supply. However, due to the low power consumption requirements of the low-power power supply itself and limited driving capabilities, when powering on, the circuits hung under the low-power power supply, including IO and IO-related detection and control circuits, need to be given priority consideration.

[0003] Traditional GPIO detection logic such as Figure 1 As shown, under the action of the battery voltage VBAT, the LDOLP (Low Dropout Regulator-Low Power) outputs a voltage signal VDDLP, which is detected by the IPOC circuit and generates an indication signal PORE of the VDDIO domain. VDDIO is the power supply voltage for the IO port. In the low power mode, the indication signal PORE controls the operation of multiple GPIOs.

[0004] In the process of implementing the embodiments of the present disclosure, it is found that there are at least the following problems in the related art:

[0005] In the related art, the control signal controls the operation of multiple GPIOs. When the voltage signal VDDLP output by LDOLP is powered on, the voltage signal VDDLP flips from low to high. At this time, the Level Shifters in multiple GPIOs start to flip at the same time. When the load becomes larger and the voltage signal is not driven enough, a power-off voltage Vdrop will occur. Figure 2 As shown, the normal power-on of the signal is affected. If the power-off voltage Vdrop is too large, the voltage signal may fail to power on, causing the GPIO to not work properly.

[0006] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present application, and therefore may include information that does not constitute the prior art known to ordinary technicians in the field. Summary of the invention

[0007] In order to provide a basic understanding of some aspects of the disclosed embodiments, a brief summary is given below. The summary is not an extensive review, nor is it intended to identify key / critical components or delineate the scope of protection of these embodiments, but rather serves as a prelude to the detailed description that follows.

[0008] The embodiments of the present disclosure provide a GPIO control circuit and a chip to solve the problem that the voltage signal output by the LDOLP is powered off during the power-on process.

[0009] In some embodiments, the GPIO control circuit includes: a voltage regulator circuit, configured to output a voltage signal; a power-on reset circuit, connected to the voltage regulator circuit, configured to output a delayed control signal based on the voltage signal; a detection circuit, respectively connected to the power-on reset circuit and the GPIO interface, configured to output an indication signal under the action of the control signal, and the indication signal is used to indicate the working status of the GPIO interface.

[0010] Optionally, the power-on reset circuit includes: a voltage detection circuit connected to the voltage regulator circuit and configured to output a detection signal based on the voltage signal; a first inverter connected to the voltage detection circuit and configured to invert the detection signal; a delay circuit connected to the first inverter and configured to delay the output signal of the first inverter, thereby outputting a control signal with a delay.

[0011] Optionally, the voltage detection circuit includes: a first resistor, a second resistor, a third resistor, a first PMOS tube, a second PMOS tube, a third PMOS tube, a first NMOS tube, and a second NMOS tube; the first end of the first resistor, the first end of the second resistor, and the source of the first PMOS tube are all connected to the voltage signal, and the second end of the first resistor and the gate of the first NMOS tube are all grounded; the second end of the second resistor is connected to the drain of the first NMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the second NMOS tube; the source of the first NMOS tube is grounded; the drain of the first PMOS tube is connected to the source of the second PMOS tube and the source of the third PMOS tube; the drain of the second PMOS tube, the drain of the second NMOS tube, and the gate of the third PMOS tube are all connected, as the output end of the voltage detection circuit, connected to the input end of the first inverter, and outputting a detection signal; the source of the second NMOS tube is grounded; the drain of the third PMOS tube is connected to the first end of the third resistor; and the second end of the third resistor is grounded.

[0012] Optionally, the delay circuit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; the gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the sixth PMOS tube, and the gate of the third NMOS tube are all connected to the output end of the first inverter and grounded; the source of the fourth PMOS tube and the source of the seventh PMOS tube are both connected to the voltage signal; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; the fifth PMOS tube is connected to the output end of the first inverter ... gate of the sixth PMOS tube and the gate of the third NMOS tube are connected to the output end of the first inverter; the source of the fourth PMOS tube and the source of the seventh PMOS tube are connected to the voltage signal; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; the fifth PMOS The drain of the S tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth NMOS tube, the drain of the seventh PMOS tube, and the input end of the second inverter; the source of the third NMOS tube, the source and drain of the fourth NMOS tube are all grounded; the gate of the seventh PMOS tube is connected to the output end of the second inverter and the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the input end of the fifth inverter; the output end of the fifth inverter is used to output a control signal with a delay.

[0013] Optionally, by controlling the size of the fourth NMOS transistor, the delay time of the control signal can be adjusted.

[0014] Optionally, the detection circuit includes: a port circuit connected to the power-on reset circuit and configured to increase the drive of the control signal; an indication circuit connected to the port circuit and the GPIO interface respectively, and configured to output an indication signal under the action of the control signal after the drive is increased.

[0015] Optionally, the port circuit includes: a sixth inverter and a seventh inverter; the input end of the sixth inverter is connected to the power-on reset circuit; and the output end of the sixth inverter is connected to the input end of the seventh inverter.

[0016] Optionally, the indicating circuit includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a fifth NMOS tube, and a sixth NMOS tube; the input end of the eighth inverter is connected to the port circuit, and the output end of the eighth inverter is connected to the input end of the ninth inverter; the output end of the ninth inverter is connected to the source of the fifth NMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, the gate of the tenth PMOS tube, and the gate of the sixth NMOS tube, and grounded; the drain of the fifth NMOS tube is grounded, the gate of the fifth NMOS tube is connected to the drain of the tenth PMOS tube, the drain of the sixth NMOS tube, and the input end of the tenth inverter; the source of the eighth PMOS tube is connected to the IO domain voltage, the drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube; the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the source of the sixth NMOS tube is grounded; the output end of the tenth inverter is connected to the input end of the eleventh inverter; the output end of the eleventh inverter is connected to the GPIO interface.

[0017] Optionally, the number of GPIO interfaces is greater than ten.

[0018] In some embodiments, the chip includes: a GPIO control circuit as described above.

[0019] The GPIO control circuit and chip provided in the embodiments of the present disclosure can achieve the following technical effects:

[0020] In the disclosed embodiment, the GPIO control circuit includes a voltage regulator circuit, a power-on reset circuit and a detection circuit. The power-on reset circuit is used to perform power-on detection on the voltage signal output by the voltage regulator circuit, and output a control signal with a delay. Within the delay time, it can be ensured that after the voltage signal is powered on, the corresponding control signal is output, so that the detection circuit outputs an indication signal to indicate that the GPIO interface is working. Therefore, by setting a control signal with a delay, when the GPIO interface starts to work, the voltage signal has been powered on, thereby solving the problem of power failure during the power-on process of the voltage signal. In addition, since the control signal has a certain delay, the discreteness of the flipping point is smaller when the detection circuit detects and flips the output, the indication signal output by each corner is more accurate, and the system reliability is higher.

[0021] The above general description and the following description are exemplary and explanatory only and are not intended to limit the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] One or more embodiments are exemplarily described by corresponding drawings, which do not limit the embodiments. Elements with the same reference numerals in the drawings are shown as similar elements, and the drawings do not constitute a scale limitation, and wherein:

[0023] Figure 1 It is a schematic diagram of the framework of the traditional GPIO control circuit;

[0024] Figure 2 It is a schematic diagram of the power-on condition of the voltage signal of the traditional GPIO control circuit;

[0025] Figure 3 It is a schematic diagram of a GPIO control circuit provided by an embodiment of the present disclosure;

[0026] Figure 4 is a schematic diagram of another GPIO control circuit provided by an embodiment of the present disclosure;

[0027] Figure 5 is a circuit diagram of a power-on reset circuit in a GPIO control circuit provided by an embodiment of the present disclosure;

[0028] Figure 6 It is a circuit diagram of a detection circuit in a GPIO control circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0029] In order to be able to understand the features and technical contents of the embodiments of the present disclosure in more detail, the implementation of the embodiments of the present disclosure is described in detail below in conjunction with the accompanying drawings. The attached drawings are for reference only and are not used to limit the embodiments of the present disclosure. In the following technical description, for the convenience of explanation, a full understanding of the disclosed embodiments is provided through multiple details. However, one or more embodiments can still be implemented without these details. In other cases, to simplify the drawings, well-known structures and devices can be simplified for display.

[0030] The terms "first", "second", etc. in the technical solutions described in this application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so as to describe the embodiments of the disclosed embodiments described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions.

[0031] Unless otherwise stated, the term "plurality" means two or more.

[0032] In the embodiment of the present disclosure, the character " / " indicates that the preceding and following objects are in an "or" relationship. For example, A / B indicates: A or B.

[0033] The term "and / or" is a description of the association relationship between objects, indicating that three relationships can exist. For example, A and / or B means: A or B, or, A and B.

[0034] The term "correspondence" may refer to an association relationship or a binding relationship. The correspondence between A and B means that there is an association relationship or a binding relationship between A and B.

[0035] Combination Figure 3 As shown, an embodiment of the present disclosure provides a GPIO control circuit, including: a voltage regulator circuit LDOLP, a power-on reset circuit POR and a detection circuit IPOC. The voltage regulator circuit LDOLP is configured to output a voltage signal VDDLP. The power-on reset circuit POR is connected to the voltage regulator circuit LDOLP, and is configured to output a delayed control signal PORLP according to the voltage signal VDDLP. The detection circuit IPOC is respectively connected to the power-on reset circuit POR and the GPIO interface, and is configured to output an indication signal PORE under the action of the control signal PORLP, and the indication signal PORE is used to indicate the working state of the GPIO interface. Among them, Figure 3 The GPIO×N in the figure represents that the indication signal PORE is used to indicate the working status of N GPIO interfaces.

[0036] In the disclosed embodiment, the GPIO control circuit includes a voltage regulator circuit LDOLP, a power-on reset circuit POR and a detection circuit IPOC. The voltage regulator circuit LDOLP outputs a voltage signal VDDLP under the action of the battery voltage VBAT. The power-on reset circuit POR is used to perform power-on detection on the voltage signal VDDLP output by the voltage regulator circuit LDOLP, and output a control signal PORLP with a delay. Within the delay time, it can be ensured that after the voltage signal VDDLP is powered on, the corresponding control signal PORLP is output, so that the detection circuit IPOC outputs an indication signal PORE to indicate that the GPIO interface is working. Therefore, by setting the control signal PORLP with a delay, when the GPIO interface starts to work, the voltage signal VDDLP has been powered on, thereby solving the problem of power failure during the power-on process of the voltage signal VDDLP. In addition, since the control signal PORLP has a certain delay, the detection circuit IPOC has a smaller discreteness of the flip point when detecting and flipping the output, and the indication signal PORE output by each corner is more accurate, and the system reliability is higher.

[0037] Optionally, combined Figure 4 As shown, the detection circuit IPOC is connected to the voltage regulator circuit LDOLP, and the GPIO interface is connected to the voltage regulator circuit LDOLP. The detection circuit IPOC and the GPIO interface are also connected to the IO domain voltage VDDIO respectively.

[0038] In this embodiment, the voltage signal VDDLP output by the voltage regulator circuit LDOLP can also be used as the power supply voltage for the electronic components in the detection circuit IPOC and the GPIO interface. At the same time, the detection circuit IPOC and the GPIO interface are also connected to the IO domain voltage VDDIO as the power supply voltage for the GPIO interface.

[0039] Optionally, combined Figure 5 As shown, the power-on reset circuit POR includes: a voltage detection circuit 51, a first inverter INV1 and a delay circuit 52. The voltage detection circuit 51 is connected to the voltage regulator circuit LDOLP and is configured to output a detection signal according to the voltage signal VDDLP. The first inverter INV1 is connected to the voltage detection circuit 51 and is configured to invert the detection signal. The delay circuit 52 is connected to the first inverter INV1 and is configured to delay the output signal of the first inverter INV1, thereby outputting a delayed control signal PORLP.

[0040] In this embodiment, the voltage detection circuit 51 is configured to detect the voltage signal VDDLP. When the voltage signal VDDLP is higher than or equal to the voltage threshold, the output detection signal is a high level. When the voltage signal VDDLP is lower than the voltage threshold, the output detection signal is a low level. Since the delay circuit 52 will reverse the signal while realizing the delay, it is necessary to first invert the detection signal by setting the first inverter INV1. After the detection signal is inverted by the first inverter INV1, the delay circuit 52 outputs the delayed control signal PORLP. When the detection signal is high, the control signal PORLP is also high. When the detection signal is low, the control signal PORLP is also low. By controlling the delay time, the voltage signal VDDLP can be powered on when the delay circuit 52 outputs the control signal PORLP.

[0041] Optionally, combined Figure 5As shown, the voltage detection circuit 51 includes: a first resistor R1, a second resistor R2, a third resistor R3, a first PMOS transistor PM1, a second PMOS transistor PM2, a third PMOS transistor PM3, a first NMOS transistor NM1, and a second NMOS transistor NM2. The first end of the first resistor R1, the first end of the second resistor R2, and the source of the first PMOS transistor PM1 are all connected to the voltage signal VDDLP, and the second end of the first resistor R1 and the gate of the first NMOS transistor NM1 are all grounded; the second end of the second resistor R2 is connected to the drain of the first NMOS transistor NM1, the gate of the first PMOS transistor PM1, the gate of the second PMOS transistor PM2, and the gate of the second NMOS transistor NM2; the source of the first NMOS transistor NM1 is grounded; the drain of the first PMOS transistor PM1 is connected to the source of the second PMOS transistor PM2 and the source of the third PMOS transistor PM3; the drain of the second PMOS transistor PM2, the drain of the second NMOS transistor NM2, and the gate of the third PMOS transistor PM3 are all connected as the output end of the voltage detection circuit 51, connected to the input end of the first inverter INV1, and output a detection signal; the source of the second NMOS transistor NM2 is grounded; the drain of the third PMOS transistor PM3 is connected to the first end of the third resistor R3; and the second end of the third resistor R3 is grounded.

[0042] Optionally, combined Figure 5As shown, the delay circuit 52 includes: a fourth PMOS transistor PM4, a fifth PMOS transistor PM5, a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a third NMOS transistor NM3, a fourth NMOS transistor NM4, a second inverter INV2, a third inverter INV3, a fourth inverter INV4, and a fifth inverter INV5. The gate of the fourth PMOS transistor PM4, the gate of the fifth PMOS transistor PM5, the gate of the sixth PMOS transistor PM6, and the gate of the third NMOS transistor NM3 are all connected to the output end of the first inverter INV1 and are grounded; the source of the fourth PMOS transistor PM4 and the source of the seventh PMOS transistor PM7 are all connected to the voltage signal VDDLP; the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5; the drain of the fifth PMOS transistor PM5 is connected to the source of the sixth PMOS transistor PM6; the drain of the sixth PMOS transistor PM6 is connected to the drain of the third NMOS transistor NM3, the drain of the fourth NMOS transistor PM5, and the drain of the sixth PMOS transistor PM6. The gate of the OS transistor NM4, the drain of the seventh PMOS transistor PM7, and the input end of the second inverter INV2 are all connected; the source of the third NMOS transistor NM3, and the source and drain of the fourth NMOS transistor NM4 are all grounded; the gate of the seventh PMOS transistor PM7 is connected to the output end of the second inverter INV2 and the input end of the third inverter INV3; the output end of the third inverter INV3 is connected to the input end of the fourth inverter INV4; the output end of the fourth inverter INV4 is connected to the input end of the fifth inverter INV5; the output end of the fifth inverter INV5 is used to output a delayed control signal PORLP.

[0043] In this embodiment, an inverter chain may be formed by providing the fourth inverter INV4 and the fifth inverter INV5, thereby increasing the driving capability of the delayed control signal PORLP.

[0044] Optionally, by controlling the size of the fourth NMOS transistor NM4 , the delay time of the control signal PORLP may be adjusted.

[0045] In this embodiment, by increasing the size of the fourth NMOS transistor NM4 in the delay circuit 52, the on-resistance during power-on can be increased, thereby outputting the control signal PORLP with power-on delay.

[0046] Optionally, combined Figure 6 As shown, the detection circuit IPOC includes: a port circuit 61 and an indication circuit 62. The port circuit 61 is connected to the power-on reset circuit POR and is configured to increase the drive of the control signal PORLP. The indication circuit 62 is connected to the port circuit 61 and the GPIO interface respectively, and is configured to output the indication signal PORE under the action of the control signal PORLP after the drive is increased.

[0047] In this embodiment, the driving of the control signal PORLP can be increased through the port circuit 61, thereby improving the driving ability of the control signal PORLP. The control signal PORLP acts on the indication circuit 62, and can output the indication signal PORE of the corresponding IO domain. When the control signal PORLP is at a high level, the indication signal PORE is at a low level to indicate that the GPIO interface starts to work; when the control signal PORLP is at a low level, the indication signal PORE is at a high level to indicate that the GPIO interface does not work.

[0048] Optionally, combined Figure 6 As shown, the port circuit 61 includes: a sixth inverter INV6 and a seventh inverter INV7. The input end of the sixth inverter INV6 is connected to the power-on reset circuit POR; the output end of the sixth inverter INV6 is connected to the input end of the seventh inverter INV7.

[0049] Optionally, combined Figure 6 As shown, the indication circuit 62 includes: an eighth inverter INV8, a ninth inverter INV9, a tenth inverter INV10, an eleventh inverter INV11, an eighth PMOS tube PM8, a ninth PMOS tube PM9, a tenth PMOS tube PM10, a fifth NMOS tube NM5, and a sixth NMOS tube NM6. The input end of the eighth inverter INV8 is connected to the port circuit 61, and the output end of the eighth inverter INV8 is connected to the input end of the ninth inverter INV9; the output end of the ninth inverter INV9 is connected to the source of the fifth NMOS tube NM5, the gate of the eighth PMOS tube PM8, the gate of the ninth PMOS tube PM9, the gate of the tenth PMOS tube PM10, and the gate of the sixth NMOS tube NM6, and is grounded; the drain of the fifth NMOS tube NM5 is grounded, and the gate of the fifth NMOS tube NM5 is connected to the drain of the tenth PMOS tube PM10, the gate of the ninth PMOS tube PM9, the gate of the tenth PMOS tube PM10, and the gate of the sixth NMOS tube NM6. The drain of the sixth NMOS tube NM6 and the input end of the tenth inverter INV10 are both connected; the source of the eighth PMOS tube PM8 is connected to the IO domain voltage VDDIO, and the drain of the eighth PMOS tube PM8 is connected to the source of the ninth PMOS tube PM9; the drain of the ninth PMOS tube PM9 is connected to the source of the tenth PMOS tube PM10; the source of the sixth NMOS tube NM6 is grounded; the output end of the tenth inverter INV10 is connected to the input end of the eleventh inverter INV11; and the output end of the eleventh inverter INV11 is connected to the GPIO interface.

[0050] In this embodiment, the IO domain voltage VDDIO is a power supply voltage for the GPIO interface. The tenth inverter INV10 and the eleventh inverter INV11 can further increase the driving of the indication signal PORE, thereby strengthening the control capability of the GPIO interface and achieving control of more GPIO interfaces.

[0051] Optionally, the number N of GPIO interfaces is greater than ten.

[0052] The GPIO control circuit provided in the embodiment of the present disclosure detects the voltage signal VDDLP output by the voltage regulator circuit LDOLP through the power-on reset circuit POR. If the voltage signal VDDLP is higher than or equal to the voltage threshold, it means that the voltage signal VDDLP has been powered on, and the delayed control signal PORLP output by the power-on reset circuit POR is high level. Under the action of the high level signal, the detection circuit IPOC outputs the low level indication signal PORE of the IO domain, indicating that the GPIO interface is working. If the voltage signal VDDLP is lower than the voltage threshold, it means that the voltage signal VDDLP has not been powered on, and the delayed control signal PORLP output by the power-on reset circuit POR is low level. Under the action of the low level signal, the detection circuit IPOC outputs the high level indication signal PORE of the IO domain, indicating that the GPIO interface is turned off. Therefore, in the embodiment of the present disclosure, due to the delay time of the control signal PORLP, it is ensured that the voltage signal VDDLP has been powered on when the indication signal PORE is output, and even if multiple GPIO interfaces work at the same time, the voltage signal VDDLP will not be seriously powered off, so the voltage signal VDDLP will not have a power-on problem. In addition, since the control signal PORLP has a certain delay, the discreteness of the flip point of the detection circuit IPOC is smaller when detecting and flipping the output, and the PORE control signal PORLP output by each corner is more accurate and more reliable.

[0053] An embodiment of the present disclosure also provides a chip, comprising the GPIO control circuit as described above.

[0054] The chip provided by the embodiment of the present disclosure adopts the GPIO control circuit as described above, which does not increase the area and burden of the IPOC, has a simple structure, ensures the reliability and robustness of power-on in a low-power working mode, and can meet the needs of large-scale mass production.

[0055] The above description and accompanying drawings fully illustrate the embodiments of the present disclosure so that those skilled in the art can practice them. Other embodiments may include structural, logical, electrical, process and other changes. The embodiments represent possible changes only. Unless explicitly required, separate components and functions are optional, and the order of operation may vary. The parts and features of some embodiments may be included in or replace the parts and features of other embodiments. Moreover, the words used in this application are only used to describe the embodiments and are not used to limit the technical solutions recorded in this application. As used in the technical solutions recorded in this application, unless the context clearly indicates, the singular forms of "a", "an" and "the" are intended to include plural forms as well. Similarly, the term "and / or" as used in this application refers to any and all possible combinations of listings containing one or more associated ones. In addition, when used in the present application, the term "comprise" and its variants "comprises" and / or comprising refer to the presence of stated features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components and / or groups thereof. In the absence of further restrictions, the elements defined by the sentence "comprising a ..." do not exclude the presence of other identical elements in the process, method or device comprising the elements. In this article, each embodiment may focus on the differences from other embodiments, and the same and similar parts between the various embodiments may refer to each other. For the methods, products, etc. disclosed in the embodiments, if they correspond to the method part disclosed in the embodiments, then the relevant parts can refer to the description of the method part.

[0056] The flowchart and block diagram in the accompanying drawings show the possible architecture, function and operation of the system, method and computer program product according to the embodiment of the present disclosure. In this regard, each box in the flowchart or block diagram can represent a module, a program segment or a part of the code, and the module, the program segment or a part of the code contains one or more executable instructions for realizing the specified logical function. In some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two consecutive boxes can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. In the description corresponding to the flowchart and the block diagram in the accompanying drawings, the operations or steps corresponding to different boxes can also occur in a different order from the order disclosed in the description, and sometimes there is no specific order between different operations or steps. For example, two consecutive operations or steps can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, which can depend on the functions involved. Each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, may be implemented by a dedicated hardware-based system that performs the specified functions or actions, or may be implemented by a combination of dedicated hardware and computer instructions.

Claims

1. A GPIO control circuit, characterized in that: include: a voltage regulator circuit configured to output a voltage signal; A power-on reset circuit is connected to the voltage regulator circuit and is configured to output a control signal with a delay according to the voltage signal; The detection circuit is connected to the power-on reset circuit and the GPIO interface respectively, and is configured to output an indication signal under the action of the control signal, wherein the indication signal is used to indicate the working state of the GPIO interface.

2. The GPIO control circuit according to claim 1, characterized in that: The power-on reset circuit includes: a voltage detection circuit connected to the voltage regulator circuit and configured to output a detection signal according to the voltage signal; A first inverter, connected to the voltage detection circuit, configured to invert the detection signal; The delay circuit is connected to the first inverter and is configured to delay the output signal of the first inverter, thereby outputting a delayed control signal.

3. The GPIO control circuit according to claim 2, characterized in that: The voltage detection circuit includes: a first resistor, a second resistor, a third resistor, a first PMOS transistor, a second PMOS transistor, a third PMOS transistor, a first NMOS transistor, and a second NMOS transistor; The first end of the first resistor, the first end of the second resistor, and the source of the first PMOS tube are all connected to the voltage signal, and the second end of the first resistor and the gate of the first NMOS tube are all grounded; the second end of the second resistor is connected to the drain of the first NMOS tube, the gate of the first PMOS tube, the gate of the second PMOS tube, and the gate of the second NMOS tube; the source of the first NMOS tube is grounded; the drain of the first PMOS tube is connected to the source of the second PMOS tube and the source of the third PMOS tube; the drain of the second PMOS tube, the drain of the second NMOS tube, and the gate of the third PMOS tube are all connected as the output end of the voltage detection circuit, connected to the input end of the first inverter, and output a detection signal; the source of the second NMOS tube is grounded; the drain of the third PMOS tube is connected to the first end of the third resistor; and the second end of the third resistor is grounded.

4. The GPIO control circuit according to claim 2, characterized in that: The delay circuit includes: a fourth PMOS tube, a fifth PMOS tube, a sixth PMOS tube, a seventh PMOS tube, a third NMOS tube, a fourth NMOS tube, a second inverter, a third inverter, a fourth inverter, and a fifth inverter; The gate of the fourth PMOS tube, the gate of the fifth PMOS tube, the gate of the sixth PMOS tube, and the gate of the third NMOS tube are all connected to the output end of the first inverter and are grounded; the source of the fourth PMOS tube and the source of the seventh PMOS tube are all connected to the voltage signal; the drain of the fourth PMOS tube is connected to the source of the fifth PMOS tube; the drain of the fifth PMOS tube is connected to the source of the sixth PMOS tube; the drain of the sixth PMOS tube is connected to the drain of the third NMOS tube, the gate of the fourth NMOS tube, the drain of the seventh PMOS tube, and the input end of the second inverter; the source of the third NMOS tube, the source and drain of the fourth NMOS tube are all grounded; the gate of the seventh PMOS tube is connected to the output end of the second inverter and the input end of the third inverter; the output end of the third inverter is connected to the input end of the fourth inverter; the output end of the fourth inverter is connected to the input end of the fifth inverter; the output end of the fifth inverter is used to output a control signal with delay.

5. The GPIO control circuit according to claim 4, characterized in that: By controlling the size of the fourth NMOS tube, the delay time of the control signal can be adjusted.

6. The GPIO control circuit according to claim 1, characterized in that: The detection circuit includes: The port circuit is connected to the power-on reset circuit and is configured to increase the drive of the control signal; The indication circuit is connected to the port circuit and the GPIO interface respectively, and is configured to output an indication signal under the action of the control signal after the driving is increased.

7. The GPIO control circuit according to claim 6, characterized in that: The port circuit includes: a sixth inverter and a seventh inverter; The input end of the sixth inverter is connected to the power-on reset circuit; the output end of the sixth inverter is connected to the input end of the seventh inverter.

8. The GPIO control circuit according to claim 6, characterized in that: The indicating circuit includes: an eighth inverter, a ninth inverter, a tenth inverter, an eleventh inverter, an eighth PMOS tube, a ninth PMOS tube, a tenth PMOS tube, a fifth NMOS tube, and a sixth NMOS tube; The input end of the eighth inverter is connected to the port circuit, and the output end of the eighth inverter is connected to the input end of the ninth inverter; the output end of the ninth inverter is connected to the source of the fifth NMOS tube, the gate of the eighth PMOS tube, the gate of the ninth PMOS tube, the gate of the tenth PMOS tube, and the gate of the sixth NMOS tube, and is grounded; the drain of the fifth NMOS tube is grounded, and the gate of the fifth NMOS tube is connected to the drain of the tenth PMOS tube, the drain of the sixth NMOS tube, and the input end of the tenth inverter; the source of the eighth PMOS tube is connected to the IO domain voltage, and the drain of the eighth PMOS tube is connected to the source of the ninth PMOS tube; the drain of the ninth PMOS tube is connected to the source of the tenth PMOS tube; the source of the sixth NMOS tube is grounded; the output end of the tenth inverter is connected to the input end of the eleventh inverter; and the output end of the eleventh inverter is connected to the GPIO interface.

9. The GPIO control circuit according to any one of claims 1 to 8, characterized in that: The number of GPIO interfaces is greater than 10.

10. A chip, characterized in that: include: The GPIO control circuit according to any one of claims 1 to 9.

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