Communication method and device based on UART and 1-WIRE bus

Abstract

The invention discloses a communication method and device based on a UART (Universal Asynchronous Receiver / Transmitter) and a 1-WI RE bus, a UART end is provided with a TX pin and is butted with a connecting end of a 1-WI RE end, and the communication method comprises the following steps: starting a 1-WI RE host mode of the UART end; after the UART end sends a reset pulse to the 1-WI RE end, a response pulse is obtained; the UART end judges whether to execute data transceiving or not according to a comparison result of the response pulse and the reset pulse; and when it is judged that data receiving and transmitting need to be executed, the UART end sends data to the 1-WI RE end or receives data from the 1-WI RE end. After the scheme of the invention is used, a corresponding 1-WI RE bus interface does not need to be configured on the host, the increase of cost is avoided, and the bus communication based on the 1-WI RE protocol is realized under the condition that the 1-WI RE bus interface is not configured.

Description

Technical Field

[0001] The present invention relates to the field of bus and device communication, and in particular to a communication method and device based on UART and 1-WIRE bus. Background Art

[0002] Embedded system, also known as embedded computer system, is a special computer system centered on application and based on modern computer technology, which can flexibly develop hardware modules according to user needs. In embedded systems, 1-WIRE bus is a bus used for interactive connection between integrated circuits and other peripheral devices. 1-WIRE bus is a peripheral serial expansion bus technology proposed by DALLAS Corporation of the United States, which is different from SPI and I2C serial data communication methods. It uses a single signal line to transmit both clock and data, and the data transmission is bidirectional. It has many advantages such as saving I / O port lines, simple structure, low cost, and easy bus expansion and maintenance.

[0003] However, the 1-WIRE bus is not a common interface that general MCUs are equipped with. Therefore, if you need to use the 1-WIRE bus protocol to communicate with related devices, you need to add an additional 1-WIRE bus interface module, which will increase the cost of the device. Summary of the invention

[0004] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes a communication method based on UART and 1-WIRE bus, which can be directly connected to a 1-WIRE device through a GPIO interface of the UART itself, without the need for an additional 1-WIRE bus interface module, and can use the pull-up resistor inside the GPIO interface itself, without the need for an additional external pull-up resistor, so as to communicate with the 1-WIRE device, thereby greatly reducing the additional device cost overhead.

[0005] The present invention also provides a communication device based on UART and 1-WIRE bus for applying the above communication method based on UART and 1-WIRE bus.

[0006] The present invention also provides a computer device for implementing the above communication method based on UART and 1-WIRE bus.

[0007] The present invention also provides a computer-readable storage medium.

[0008] According to the first aspect of the present invention, the communication method based on UART and 1-WIRE bus is characterized in that the UART end is applied to communicate with the 1-WIRE end, wherein the UART end has a TX pin, and the TX pin is electrically connected to the connection end of the 1-WIRE end; the communication method based on UART and 1-WIRE bus includes:

[0009] Enable 1-WIRE host mode on the UART side;

[0010] After the UART terminal sends a reset pulse to the 1-WIRE terminal, a response pulse is obtained;

[0011] The UART terminal determines whether to perform data transmission and reception with the 1-WIRE terminal according to the comparison result of the response pulse and the reset pulse;

[0012] When the UART end determines that data needs to be sent and received with the 1-WIRE end, the UART end sends data to the 1-WIRE end or receives data from the 1-WIRE end.

[0013] According to some embodiments of the present invention, when the UART end receives data from the 1-WIRE end, it includes:

[0014] The UART end obtains the byte sent by the 1-WIRE end;

[0015] If the byte contains bit 0, it is determined that the data represented by the byte is data 0, and the interrupt flag bit of receiving data 0 is set;

[0016] If the byte does not include bit 0, it is determined that the data represented by the byte is data 1, and the data 1 received interrupt flag is set.

[0017] According to some embodiments of the present invention, when the UART end sends data to the 1-WIRE end, it includes:

[0018] If data 1 needs to be sent, the first register is set to 1, and the UART end pulls up the TX pin level through the internal pull-up resistor and maintains it for a first preset time; the first register is used to send data 1;

[0019] If data 0 needs to be sent, the second register is set to 1, and the UART end pulls the TX pin level low and maintains it for a second preset time; the second register is used to send data 0.

[0020] According to some embodiments of the present invention, the step of enabling the 1-WIRE host mode of the UART terminal includes:

[0021] Based on the 1-WIRE communication protocol, key parameters of the UART terminal are configured, wherein the key parameters include baud rate, data width, stop bit and priority output bit;

[0022] A pull-up resistor is configured inside the TX pin of the UART terminal so that the electrical connection terminal between the UART terminal and the 1-WIRE terminal maintains a high level in an idle state.

[0023] According to some embodiments of the present invention, the UART end determines whether to perform data transmission and reception with the 1-WIRE end according to the received value, including:

[0024] The UART terminal compares the value of the reset pulse with the received value;

[0025] If the reset pulse is not equal to the received value, it is determined that the UART end has received the response pulse, and the UART end performs a response interrupt operation, and then the UART end implements data transmission and reception;

[0026] If the reset pulse is equal to the received value, it is determined that the UART end has not received the response pulse, and the UART end resends the reset pulse to the 1-WIRE end.

[0027] According to some embodiments of the present invention, the UART terminal performs a response interrupt operation, including:

[0028] After the UART end sets the interrupt flag, the UART end clears the interrupt flag.

[0029] According to the second aspect of the present invention, the communication device based on UART and 1-WIRE bus is characterized in that it includes a 1-WIRE end and a UART end: the UART end has a TX pin, and the TX pin is electrically connected to the 1-WIRE end through a single wire; the UART end is used to execute the communication method based on UART and 1-WIRE bus as described in any one of the above embodiments.

[0030] The computer device according to an embodiment of the third aspect of the present invention is characterized in that it further comprises:

[0031] one or more processors;

[0032] Memory;

[0033] One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the communication method based on UART and 1-WIRE bus as described in any one of the above embodiments are implemented.

[0034] According to the computer-readable storage medium of the embodiment of the fourth aspect of the present invention, a computer program is stored thereon, characterized in that when the computer program is executed by a processor, the steps of the communication method based on UART and 1-WIRE bus as described in any one of the above embodiments are implemented.

[0035] The communication method and device based on UART and 1-WIRE bus according to the embodiment of the present invention have at least the following beneficial effects:

[0036] By first opening the 1-WIRE host mode of the UART end, and then sending a reset pulse from the UART end to the 1-WIRE end, obtaining a response pulse, and then judging whether to perform data transmission and reception with the 1-WIRE end according to the comparison result of the received response pulse and the reset pulse, and only when the UART end determines that it is necessary to perform data transmission and reception with the 1-WIRE end, the UART end sends or receives data to the 1-WIRE end, thereby realizing a communication design method that fits the communication protocol of the 1-WIRE bus at the UART end, that is, simulating the protocol timing of the 1-WIRE bus at the UART end, thereby realizing the reset pulse and response detection, data reception and transmission functions generated between the UART end and the 1-WIRE end, and making the host device using this method only need to electrically connect the TX pin of the UART end to the connection end of the 1-WIRE end when communicating with the slave device through the bus, and use the pull-up resistor of the TX pin of the UART end itself, without configuring another 1-WIRE end. RE bus interface and external pull-up resistor, thereby saving IO ports and avoiding the increase of device costs, avoiding the additional device cost expenses due to the incompatibility of communication ports and communication protocols, and at the same time, the method only uses the TX pin of the UART end, which not only simplifies the hardware connection structure and saves hardware costs, but also uses the TX pin single-line communication compared to the method of using the TX pin and RX pin of the UART end at the same time, reducing the interference of hardware connection problems on communication signals, thereby improving the quality of communication signals. In addition, the method also provides an automated data processing and warning terminal, including: a data received 0 interrupt flag, a data received 1 interrupt flag, and a response interrupt flag, so as to provide users with corresponding prompts during the communication process, allowing users to communicate with 1-WI RE devices more conveniently, and the use of flags is helpful for the software programming implementation of the communication method.

[0037] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0039] Figure 1 The overall flow diagram of the communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0040] Figure 2 A connection diagram of a communication device based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0041] Figure 3 A schematic diagram of a flow chart of generating a reset pulse and responding to a detection in a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0042] Figure 4 A timing diagram of a reset pulse generated and a response pulse received by a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0043] Figure 5 A schematic diagram of a process of receiving data in a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0044] Figure 6 A timing diagram of receiving data of a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0045] Figure 7 A schematic diagram of a data transmission process of a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention;

[0046] Figure 8 4 is a timing diagram of sending data in a communication method based on UART and 1-WIRE bus according to an embodiment of the present invention. DETAILED DESCRIPTION

[0047] Embodiments of the present invention are described in detail below, examples of which are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and cannot be understood as limiting the present invention.

[0048] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0049] In the description of the present invention, "several" means one or more, "more" means more than two, "greater than", "less than", "exceed" etc. are understood as not including the number itself, and "above", "below", "within" etc. are understood as including the number itself. If there is a description of "first" or "second", it is only used for the purpose of distinguishing the technical features, and cannot be understood as indicating or implying the relative importance or implicitly indicating the number of the indicated technical features or implicitly indicating the order of the indicated technical features.

[0050] In the description of the present invention, unless otherwise clearly defined, terms such as setting, installing, connecting, etc. should be understood in a broad sense, and technicians in the relevant technical field can reasonably determine the specific meanings of the above terms in the present invention based on the specific content of the technical solution.

[0051] The following is combined with Figure 1-8 , describes in detail the communication method and device based on UART and 1-WIRE bus according to an embodiment of the present invention.

[0052] Reference Figure 1 The present invention proposes a communication method based on UART and 1-WIRE bus, which is applied to the UART end communicating with the 1-WIRE end, referring to Figure 2 , wherein the UART end has a TX pin, and the TX pin is electrically connected to the connection end of the 1-WI RE end; refer to Figure 1 The present invention proposes a communication method based on UART and 1-WIRE bus, comprising:

[0053] Step S100: Turn on the 1-WIRE host mode of the UART terminal;

[0054] Step S200: After the UART terminal sends a reset pulse to the 1-WI RE terminal, a response pulse is obtained;

[0055] Step S300: The UART terminal determines whether to perform data transmission and reception with the 1-WIRE terminal according to the comparison result of the response pulse and the reset pulse;

[0056] Step S400: When the UART end determines that data needs to be sent or received with the 1-WI RE end, the UART end sends data to the 1-WI RE end or receives data from the 1-WI RE end.

[0057] Specifically, in the present embodiment, step S100: turning on the 1-WI RE host mode of the UART end refers to configuring the UART end for communication in the host mode, including electrically connecting the TX pin of the UART end to the connection end of the 1-WI RE end, and configuring the key parameters of the UART end based on the 1-WI RE communication protocol, including: baud rate, data width, stop bit, and priority output bit, etc., so as to achieve the effect of making the UART end the master device in the bus communication and the 1-WI RE end the slave device in the bus communication during communication.

[0058] Step S200: After the UART end sends a reset pulse to the 1-WI RE end, the response pulse is obtained, which means that the UART end, as the master device of the communication, sends a 0XF0 byte to the 1-WI RE end as the slave device to form a suitable reset pulse, and receives the reception value formed by the response pulse automatically fed back by the 1-WI RE end. That is, according to the protocol of the 1-WI RE bus, the reset pulse is sent by the host to put all devices connected to the bus in the initial state to ensure the synchronization and consistency of the communication. Therefore, the UART end as the master device first needs to generate a reset pulse by pulling down the single bus for 480 to 960us (that is, sending a 0XF0 byte to the 1-WI RE end as the slave device to form a suitable reset pulse), and then the UART end releases the bus and enters the receiving mode. When the UART end as the master device releases the bus, a rising edge from a low level to a high level will be generated on the bus, and the 1-WI RE slave device is allowed to wait for 15 to 60us.

[0059] Step S300: The UART end determines whether to perform data transmission and reception with the 1-WI RE end according to the comparison result of the response pulse and the reset pulse, which means that the UART end automatically compares the values ​​of the reset pulse sent in step S200 and the received response pulse according to the software program inside the host. According to the characteristics of the main line communication, if the values ​​of the reset pulse and the response pulse are equal, the UART end does not perform data transmission and reception with the 1-WI RE end; if the values ​​of the reset pulse and the response pulse are not equal, the UART end performs data transmission and reception with the 1-WI RE end. That is, according to the protocol of the 1-WI RE bus, when the 1-WI RE end device as a slave device detects the rising edge generated by the UART end when releasing the bus in step S200, if the 1-WI RE end as a slave device is ready for communication, the 1-WI RE end pulls down the single bus for 60 to 240us to form a response pulse, and the response pulse is not equal to the reset pulse sent by the UART end in step S200. Therefore, the response pulse automatically received by the UART end when entering the receiving mode is not equal to the reset pulse sent by the UART end; if the 1-WI RE end as a slave device is not ready for communication, the 1-WI RE end does not perform any response operation. At this time, the response pulse automatically received by the UART end when entering the receiving mode is the reset pulse sent by the UART end in step S200. Therefore, by comparing the response pulse automatically received by the UART end when entering the receiving mode and the reset pulse sent by the UART end in step S200 through the internal software program of the UART end, whether the values ​​are equal, it can be determined whether the 1-WI RE end as a slave device is ready for communication. Whether the 1-WI RE end performs a response operation, that is, whether the 1-WI RE end is ready for communication, if the response pulse and the reset pulse values ​​are not equal, it means that the 1-WI RE end is ready for communication, and the data transmission and reception between the UART end and the 1-WI RE end is executed; if the response pulse and the reset pulse values ​​are equal, it means that the 1-WI RE end is not ready for communication, and the data transmission and reception between the UART end and the 1-WI RE end is not executed, and the UART end re-executes the operation steps such as sending the reset pulse, that is, re-executes step S200 and step S300.

[0060] Step S400: When the UART end determines that it needs to perform data transmission and reception with the 1-WI RE end, the UART end sends data to the 1-WI RE end or receives data from the 1-WI RE end, which means that only when the UART end as the master device receives a response pulse from the 1-WI RE end as the slave device, which is not equal to the reset pulse value, indicating that the single-bus device is ready, the UART end will perform the data transmission and reception operation. Based on the communication protocol of the 1-WI RE bus, when the master device UART end needs to send data, that is, initiate write 1 and write 0 signals, the slave device 1-WI RE end needs to be able to recognize these signals; when the master device UART end initiates a read data signal, the slave device 1-WI RE end needs to send data back to the UART end.

[0061] By first opening the 1-WI RE host mode of the UART end, and then sending a reset pulse from the UART end to the 1-WI RE end, obtaining a response pulse, and then judging whether to perform data transmission and reception with the 1-WI RE end according to the comparison result of the received response pulse and the reset pulse, and only when the UART end determines that it is necessary to perform data transmission and reception with the 1-WI RE end, the UART end sends or receives data to the 1-WI RE end, thereby realizing a communication design method that fits the communication protocol of the 1-WI RE bus at the UART end, that is, simulating the protocol timing of the 1-WI RE bus at the UART end, thereby realizing the reset pulse and response detection, data reception and transmission functions generated between the UART end and the 1-WI RE end, and enabling the host device using this method to communicate with the slave device through the bus, only the TX pin of the UART end needs to be connected to the 1-WI RE end. The bus communication can be completed by electrically connecting the connection end of the RE end, and the pull-up resistor of the TX pin of the UART end is used, without configuring an additional 1-WIRE bus interface and an external pull-up resistor, thereby saving IO ports and avoiding an increase in device costs, and avoiding additional device cost expenses due to the incompatibility of the communication port and the communication protocol. At the same time, the method only uses the communication method of the TX pin of the UART end, which not only simplifies the hardware connection structure and saves hardware costs, but also uses the TX pin single-line communication compared to the method of using the TX pin and RX pin of the UART end at the same time, thereby reducing the interference of hardware connection problems on communication signals, thereby improving the quality of communication signals.

[0062] Reference Figure 5 and Figure 6 Further, in some embodiments of the present invention, step S400: when the UART terminal receives data from the 1-WIRE terminal, includes:

[0063] Step S410: The UART end obtains the byte sent by the 1-WIRE end;

[0064] Step S421: if the byte contains bit 0, determine that the data represented by the byte is data 0, and set the interrupt flag bit for receiving data 0;

[0065] Step S422: If the byte does not contain bit 0, the data represented by the byte is determined to be data 1, and the data 1 received interrupt flag is set.

[0066] Specifically, in this embodiment, refer to Figure 5 When the UART end as the master device receives a byte sent by the 1-WIRE end, the UART end will automatically detect whether the currently received byte has bit0, thereby determining whether the data represented by the byte is data 0 or data 1. If the byte received by the UART end is 0XFE or less, that is, the received byte has bit0, then the data represented by the byte is determined to be data 0, and the UART end sets the data 0 received interrupt flag, that is, the data 0 received interrupt flag is set to 1; if the bytes received by the UART end are always 0XFF, that is, the received bytes are all bit1 without bit0, then the data represented by the byte is determined to be data 1, and the UART end sets the data 1 received interrupt flag, that is, the data 1 received interrupt flag is set to 1. Specifically, according to the 1-WIRE bus communication protocol, the time slot when the UART end of the master device receives bytes needs to last at least 60us. When the master device UART end receives data, the master device UART end first pulls down the single bus level for at least 1us, then the master device UART end releases the single bus and enters the receiving mode, preparing to read the corresponding signal sent to the single bus from the slave device 1-WIRE end. After the slave device 1-WIRE end detects the falling edge generated by the master device UART end first pulling down the single bus level for at least 1us, it starts to output the signal to the bus and maintains it for 15us. Therefore, the process from pulling down the single bus to reading data at the master device UART end must be completed within 15us. If the master device UART end reads that the single bus is at a low level, it is determined that data 0 is received. If the master device UART end reads that the single bus is at a high level, it is determined that data 1 is received. For example, refer to Figure 6, the baud rate of the UART end as the master device is configured to 115200Hz, the data length is 8bit, and 1bit is used as the stop bit. When the master device UART end reads data 0, the master device UART end first pulls down the single bus for 8.7us, and then releases the single bus, that is, executes the Start byte, and then the slave device 1-WI RE detects the falling edge generated by the UART end first pulling down the single bus level for at least 1us, then pulls down the single bus and maintains it for 17.4us (including the 8.7us when the host UART end starts to pull it down). Therefore, the byte received by the master device UART end is 0xFE, so it is determined that the data represented by the byte is data 0 and the data 0 interrupt flag is set; when the master device UART end reads data 1, the master device also first pulls down the single bus for 8.7us, and then releases the single bus. Then, after the 1-WI RE slave detects the falling edge generated by the UART end first pulling down the single bus level for at least 1us, it pulls up the single bus and maintains it for 17.4us (including the 8.7us when the host UART end starts to pull it down). Therefore, the byte received by the master device UART end is 0xFF, and it is determined that the data represented by the byte is data 1 and the data 1 interrupt flag is set. Therefore, according to the operation method and timing when the UART end receives data, all time periods conform to the time interval specified by the 1-WIRE bus communication protocol, so that the UART end can accurately read data from the 1-WIRE end based on the 1-WIRE communication protocol.

[0067] Reference Figure 7 and Figure 8 , further, in some embodiments of the present invention, step S400: when the UART end sends data to the 1-WIRE end, includes:

[0068] Step S441: if data 1 needs to be sent, the first register is set to 1, and the UART end pulls the TX pin level high and maintains it for a first preset time; the first register is used to send data 1;

[0069] Step S442: If data 0 needs to be sent, the second register is set to 1, and the UART end pulls the TX pin level low and maintains it for a second preset time; the second register is used to send data 0.

[0070] Specifically, in this embodiment, refer to Figure 7, when the UART end of the master device needs to send a byte, first determine whether the data to be sent is 1. If the byte to be sent is data 1, the first register used to send data 1 is set to 1, and the UART end of the master device will pull up the TX pin through its internal pull-up resistor and maintain the time specified by the 1-WI RE bus protocol; if the byte to be sent is data 0, the second register used to send data 0 is set to 1, and the UART end of the master device will pull down the TX pin and maintain the time specified by the 1-WI RE bus protocol. More specifically, according to the 1-WI RE bus communication protocol, the UART end of the master device sends bytes in two situations: sending data 0 and sending data 1. When sending data 0, the UART end of the master device needs to pull down the single bus as a start signal, and then maintain a low level for at least 60us. This time is to ensure that the 1-WI RE end of the slave device can sample the signal on the single bus in time. Then, the master device UART end releases the single bus, waits for the single bus to recover to a high level state under the pull-up resistor inside the TX pin, and then can transmit the next bit; when sending data 1, the start signal is that the master device UART end pulls the single bus low for at least 1us, and then the master device UART end releases the single bus, and the single bus recovers to a high level state under the pull-up resistor inside the TX pin. The process from pulling low to recovering to a high level must be completed within 15us, and then wait for the slave device to sample, and the waiting time lasts for at least 15us. For example, refer to Figure 8 , the baud rate of the UART end as the master device is configured to 115200Hz, the data length is 8bit, and the stop bit is 1bit. When the UART end sends data 0, the register used to send data 0 is set to 1, and the UART end will pull down the single bus for 8.7us, that is, execute the Start bit, so as to meet the interval specified by the protocol, and then the slave device 1-WI RE end will sample at the corresponding time window of 69.6us; when the UART end sends data 1, the register used to send data 1 is set to 1, and the UART end will first pull down the single bus for 8.7us as the start signal, that is, execute the Start bit, and then pull the single bus to a high level within 8.7us, and maintain the high level state for at least 78.3us, waiting for the slave device to sample, so as to meet the interval specified by the protocol, and then the slave device 1-WI RE end will sample at the corresponding time window of 69.6us. Therefore, according to the operation method and timing when the UART terminal sends data, all time periods conform to the time interval specified by the 1-WIRE bus communication protocol, so that the UART terminal can accurately send data to the 1-WIRE terminal based on the 1-WIRE communication protocol.

[0071] Reference Figure 1Further, in some embodiments of the present invention, step S100: turning on the 1-WIRE host mode of the UART terminal includes:

[0072] Step S110: Based on the 1-WIRE communication protocol, configure the key parameters of the UART terminal, the key parameters including: baud rate, data width, stop bit and priority output bit;

[0073] Step S120: configuring an internal pull-up resistor of the TX pin of the UART terminal so that the electrical connection terminal between the UART terminal and the 1-WIRE terminal maintains a high level in an idle state.

[0074] Specifically, in this embodiment, for example, based on the 1-WIRE communication protocol, the UART terminal can be configured as: 9600HZ baud rate, 8bit data width, 1bit stop bit, least significant bit output first (LSB). And the TX pin is configured with an internal pull-up resistor to ensure that when the UART terminal turns on the 1-WIRE host mode, the TX pin will become an open-drain mode, that is, to ensure that the connection end between the TX pin and the 1-WIRE terminal maintains a high level in the idle state. This ensures that the subsequent transceiver steps based on the 1-WIRE communication protocol can proceed smoothly.

[0075] Reference Figure 3 and Figure 4 Further, in some embodiments of the present invention, step S300: the UART end determines whether to perform data transmission and reception with the 1-WIRE end according to the received value, including:

[0076] Step S310: The UART terminal compares the value of the reset pulse with the received value;

[0077] Step S321: If the reset pulse is not equal to the received value, it is determined that the UART end receives the response pulse, and the UART end performs a response interrupt operation, and then the UART end implements data transmission and reception;

[0078] Step S322: If the reset pulse is equal to the received value, it is determined that the UART terminal has not received the response pulse, and the UART terminal resends the reset pulse to the 1-WIRE terminal.

[0079] Specifically, in this embodiment, refer to Figure 3, in step S100: after turning on the 1-WIRE host mode of UART, the UART end sets the register for generating the reset pulse to 1, thereby sending a 0XF0 byte to the single bus to form a suitable reset pulse and receiving the corresponding response pulse, and then the UART end automatically compares the value of the reset pulse sent and the received response pulse based on the program logic of the host to see if they are equal. If they are equal, it is determined that there is no 1-WIRE slave device to respond, and the reset pulse is resent, and the above operation is repeated; if they are not equal, it is determined that the UART end receives the response pulse, and the UART end performs the response interrupt operation, and then the UART end implements the transmission and reception of data. Specifically, according to the 1-WIRE bus communication protocol, the UART end as the master device first needs to generate a reset pulse by pulling down the single bus for 480 to 960us (that is, sending a 0XF0 byte to the 1-WIRE end as the slave device to form a suitable reset pulse), and then the UART end releases the bus and enters the receiving mode. When the UART end of the master device releases the bus, a rising edge from a low level to a high level will be generated on the bus, and the 1-WI RE slave device will be allowed to wait for 15 to 60us. When the 1-WI RE end device as a slave device detects the rising edge generated by the UART end when the bus is released, if the 1-WI RE end as a slave device is ready for communication, the 1-WI RE end will pull down the single bus for 60 to 240us to form a response pulse. The response pulse is not equal to the reset pulse sent by the UART end. Therefore, the response pulse automatically received by the UART end in the receive mode at this time is not equal to the reset pulse sent by the UART end. If the 1-WI RE end as a slave device is not ready for communication, the 1-WI RE end The RE end does not perform any response operation. At this time, the response pulse automatically received by the UART end when entering the receiving mode is the reset pulse sent by the UART end. Therefore, by comparing the values ​​of the response pulse automatically received by the UART end when entering the receiving mode and the reset pulse sent by the UART end through the internal software program of the UART end, it can be determined whether the 1-WI RE end as a slave device performs a response operation, that is, whether the 1-WI RE end is ready for communication. If the values ​​of the response pulse and the reset pulse are not equal, it means that the 1-WI RE end is ready for communication, and the data transmission and reception between the UART end and the 1-WI RE end is executed; if the values ​​of the response pulse and the reset pulse are equal, it means that the 1-WI RE end is not ready for communication, and the data transmission and reception between the UART end and the 1-WI RE end is not executed, and the UART end re-executes the operation steps such as sending the reset pulse, that is, re-executes steps S200 and S300. For example, referring to Figure 4, the baud rate of the UART end as the master device is configured to 9600Hz, the data length is 8bit, 1bit stop bit, and a reset pulse is sent, that is, a byte of 0xF0. The UART end sends a reset pulse to pull down the single bus for 521us, and then the UART end allows the slave device 1-WI RE to wait for 52.1us, so that the Data4 position is 1. When the 1-WI RE end device as the slave device detects the rising edge generated by the UART end when releasing the bus (that is, the rising edge between the Data3 bit and the Data4 bit), the slave device 1-WI RE generates a response pulse to pull down the single bus for 208.4us, so that the Data5 bit and Data6 bit are 0, so that the byte received by the UART end is 0x90. The reset pulse value 0XF0 sent is not equal to the response pulse value 0X90 received. Therefore, it can be judged that the 1-WI RE slave device successfully responds. If the slave device 1-WI RE If the RE end does not respond, does not generate a response pulse, and does not pull down the single bus for 208.4us, the Data5 bit and the Data6 bit remain at 1, so that the byte received by the UART end is 0xF0, and the reset pulse value 0XF0 sent is equal to the response pulse value 0XF0 received, so it can be determined that the 1-WI RE slave device has not responded. In addition, all the above times are consistent with the time interval specified by the above 1-WI RE communication protocol, so that the UART end can accurately generate reset pulses and response pulses with the 1-WI RE end based on the 1-WI RE communication protocol by simulating the relevant timing of the 1-WI RE bus protocol, so that the UART end can accurately determine whether the slave 1-WI RE end responds and determines whether the UART end further performs data transmission and reception.

[0080] Reference Figure 3 Further, in some embodiments of the present invention, step S321: the UART terminal performs a response interrupt operation, including:

[0081] The UART end sets the response interrupt flag first, and then clears the response interrupt flag.

[0082] Specifically, in this embodiment, when the 1-WI RE slave device successfully responds and the UART end determines that the response pulse is received, the UART end sets the response interrupt flag, that is, sets the response interrupt flag to 1, and then the UART end enters the state of preparing to send and receive data, at which time the response interrupt flag is cleared, that is, the response interrupt flag is set to 0. By setting the response interrupt flag when the UART end determines that the response pulse is received, when the UART end determines that the response pulse is received, the user can be notified that the response from the slave 1-WI RE end has been received, and the subsequent execution of the receiving and sending operations is convenient, and the use of the response interrupt flag can also enable the UART end to directly compare the reset pulse value sent with the response pulse value received at the hardware level, thereby improving the real-time performance of data comparison and reducing the CPU operation time.

[0083] By implementing the above method, the hardware and software design of using UART to simulate the 1-WIRE bus interface is completed. The master device simulated by serial UART can communicate data with the slave device of the standard 1-WIRE bus based on the 1-WIRE communication protocol.

[0084] Reference Figure 2 The present invention also proposes a communication device based on UART and 1-WI RE bus, including a 1-WI RE terminal and a UART terminal: the UART terminal has a TX pin, and the TX pin is electrically connected to the 1-WI RE terminal through a single wire; the UART terminal is used to: execute any embodiment of the above-mentioned communication method based on UART and 1-WI RE bus.

[0085] Specifically, in the present embodiment, bus communication can be completed by electrically connecting the TX pin of the UART end to the connection end of the 1-WIRE end, and the TX pin of the UART end uses its own pull-up resistor, without configuring another 1-WIRE bus interface and an external pull-up resistor, thereby saving IO ports and avoiding the increase of device costs, avoiding the additional device cost overhead due to the incompatibility of the communication port and the communication protocol, and at the same time, the present method only uses the communication mode of the TX pin of the UART end, which not only simplifies the hardware connection structure and saves hardware costs, but also uses the TX pin single-line communication compared to the mode of using the TX pin and RX pin of the UART end at the same time, reducing the interference of hardware connection problems on the communication signal, thereby improving the quality of the communication signal. In addition, by configuring the internal pull-up resistor of the TX pin, it is ensured that when the UART end turns on the 1-WIRE host mode, the TX pin will become an open-drain mode, that is, it is ensured that the TX pin and the connection end of the 1-WIRE end maintain a high level when in an idle state. Thereby ensuring that the receiving and sending steps based on the 1-WIRE communication protocol can proceed smoothly.

[0086] The present invention also proposes a computer device, comprising: one or more processors; a memory; and one or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the distribution network architecture analysis method as described above are implemented.

[0087] The present invention also proposes a computer-readable storage medium on which a computer program is stored. When the computer program is executed by a processor, the steps of the distribution network architecture analysis method as described above are implemented.

[0088] It will be appreciated by those skilled in the art that all or part of the steps for implementing the above-mentioned embodiments can be accomplished by hardware, or by a program to instruct the relevant hardware to accomplish, and the program can be stored in a computer-readable storage medium. In the context of the present invention, the computer-readable medium can be considered to be tangible and non-temporary. Non-limiting examples of non-temporary tangible computer-readable media include non-volatile memory circuits (e.g., flash memory circuits, erasable programmable read-only memory circuits, or mask read-only memory circuits), volatile memory circuits (e.g., static random access memory circuits or dynamic random access memory circuits), magnetic storage media (e.g., analog or digital tapes or hard disk drives), and optical storage media (e.g., CDs, DVDs, or Blu-ray discs), etc. The program code for implementing the method of the present invention can be written in any combination of one or more programming languages. These program codes can be provided to a processor or controller of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that the program code, when executed by the processor or controller, enables the functions / operations specified in the flow chart and / or block diagram to be implemented. The program code may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

[0089] In addition, although each operation is described in a specific order, this should be understood as requiring such operation to be performed in the specific order shown or in a sequential order, or requiring that all illustrated operations should be performed to obtain desired results. Under certain circumstances, multitasking and parallel processing may be advantageous. Similarly, although some specific implementation details are included in the above discussion, these should not be interpreted as limiting the scope of the present invention. Some features described in the context of a separate embodiment can also be implemented in a single implementation in combination. On the contrary, the various features described in the context of a single implementation can also be implemented in multiple implementations individually or in any suitable sub-combination mode.

[0090] The embodiments of the present invention are described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments. Various changes can be made within the knowledge scope of ordinary technicians in the technical field without departing from the purpose of the present invention.

Claims

1. A communication method based on UART and 1-WIRE bus, characterized in that: A UART end used for communicating with a 1-WIRE end, wherein the UART end has a TX pin, and the TX pin is electrically connected to a connection end of the 1-WIRE end; the communication method based on the UART and 1-WIRE bus includes: Enable 1-WIRE host mode on the UART side; After the UART terminal sends a reset pulse to the 1-WIRE terminal, a response pulse is obtained; The UART terminal determines whether to perform data transmission and reception with the 1-WIRE terminal according to the comparison result of the response pulse and the reset pulse; When the UART end determines that data needs to be sent and received with the 1-WIRE end, the UART end sends data to the 1-WIRE end or receives data from the 1-WIRE end.

2. The communication method based on UART and 1-WIRE bus according to claim 1, characterized in that: When the UART end receives data from the 1-WIRE end, it includes: The UART end obtains the byte sent by the 1-WIRE end; If the byte contains bit 0, it is determined that the data represented by the byte is data 0, and the interrupt flag bit of receiving data 0 is set; If the byte does not include bit 0, it is determined that the data represented by the byte is data 1, and the data 1 received interrupt flag is set.

3. The communication method based on UART and 1-WIRE bus according to claim 1, characterized in that: When the UART terminal sends data to the 1-WIRE terminal, it includes: If data 1 needs to be sent, the first register is set to 1, and the UART end pulls up the level of the TX pin and maintains it for a first preset time; the first register is used to send data 1; If data 0 needs to be sent, the second register is set to 1, and the UART end pulls the TX pin level low and maintains it for a second preset time; the second register is used to send data 0.

4. The communication method based on UART and 1-WIRE bus according to claim 1, characterized in that: The 1-WIRE host mode of the UART terminal is enabled, including: Based on the 1-WIRE communication protocol, key parameters of the UART terminal are configured, wherein the key parameters include baud rate, data width, stop bit and priority output bit; An internal pull-up resistor of the TX pin of the UART terminal is configured so that the electrical connection terminal between the UART terminal and the 1-WIRE terminal maintains a high level in an idle state.

5. The communication method based on UART and 1-WIRE bus according to claim 1, characterized in that: The UART end determines whether to perform data transmission and reception with the 1-WIRE end according to the received value, including: The UART terminal compares the value of the reset pulse with the received value; If the reset pulse is not equal to the received value, it is determined that the UART end has received the response pulse, and the UART end performs a response interrupt operation, and then the UART end implements data transmission and reception; If the reset pulse is equal to the received value, it is determined that the UART end has not received the response pulse, and the UART end resends the reset pulse to the 1-WIRE end.

6. The communication method based on UART and 1-WIRE bus according to claim 5, characterized in that: The UART end performs a response interrupt operation, including: After the UART end sets the response interrupt flag, the UART end clears the response interrupt flag.

7. A communication device based on UART and 1-WIRE bus, characterized in that: It includes a 1-WIRE end and a UART end: the UART end has a TX pin, and the TX pin is electrically connected to the 1-WIRE end through a single wire; the UART end is used to execute the communication method based on UART and 1-WIRE bus as described in any one of claims 1-6.

8. A computer device, characterized in that: Also includes: one or more processors; Memory; One or more programs, wherein the one or more programs are stored in the memory and are configured to be executed by the one or more processors, and when the programs are executed by the processors, the steps of the communication method based on UART and 1-WIRE bus as described in any one of claims 1-6 are implemented.

9. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the communication method based on UART and 1-WIRE bus as described in any one of claims 1 to 6 are implemented.

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