Anti-interference I2C slave module and communication system

Abstract

The invention discloses an anti-interference I2C slave module and a communication system, and relates to the technical field of I2C communication. The module comprises a clock processing module, a reset processing module, a slave control module and a register read-write module, the clock processing module is used for generating a first clock signal and a first data signal according to a received serial clock signal and a received serial data signal, negating the serial clock signal and the serial data signal, and sending the negated serial clock signal and the negated serial data signal to the register read-write module; generating a second clock signal and a second data signal; the reset processing module is electrically connected with the clock processing module, and the reset processing module is used for filtering the reset signal to obtain an anti-interference reset signal; the slave control module is electrically connected with the clock processing module and the reset processing module respectively; and the register read-write module is electrically connected with the clock processing module and the slave control module respectively. According to the anti-interference I2C slave module provided by the embodiment of the invention, the influence of online burrs on a system can be avoided.

Description

Technical Field

[0001] The present invention relates to the technical field of I2C communication, and in particular to an anti-interference I2C slave module and a communication system. Background Art

[0002] The information transmission of the I2C bus requires mutual responses between the host and the slave. The communication devices are highly interactive, so glitches on the line can easily affect the transmission of I2C. In the case of unstable power supply, glitches are very easy to form on the line, which is extremely detrimental to the transmission of information. If glitches occur on the line signal during the idle phase, resulting in the generation of an error signal, incorrect data transmission may occur. If glitches occur on the reset signal itself, the entire circuit may be completely reset. Moreover, the existing I2C bus does not perform certain processing on the reset signal inside the module, which also results in the reset signal glitches during data transmission, which may cause the entire circuit to reset abnormally. Summary of the invention

[0003] The present invention aims to solve at least one of the technical problems existing in the prior art. To this end, the present invention proposes an anti-interference I2C slave module and a communication system, which can avoid the influence of line glitches on the system.

[0004] In a first aspect, an anti-interference I2C slave module according to an embodiment of the present invention includes:

[0005] A clock processing module, configured to generate a first clock signal and a first data signal according to a received serial clock signal and a serial data signal, and invert the serial clock signal and the serial data signal to generate a second clock signal and a second data signal;

[0006] a reset processing module, electrically connected to the clock processing module, and configured to filter a reset signal according to the first clock signal, the first data signal, and the second data signal to obtain an anti-interference reset signal;

[0007] A slave control module, electrically connected to the clock processing module and the reset processing module respectively, and the slave control module is used for performing logic processing;

[0008] The register read-write module is electrically connected to the clock processing module and the slave control module respectively, and the register read-write module is used for performing read-write operations.

[0009] According to some embodiments of the present invention, the clock processing module includes a first inversion unit and a second inversion unit; the first inversion unit includes a first branch and a second branch connected in parallel, the first branch is used to generate the first clock signal according to the serial clock signal, and the second branch includes a first inverter, and the first inverter is used to invert the serial clock signal to generate the second clock signal; the second inversion unit includes a third branch and a fourth branch connected in parallel, the third branch is used to generate the first data signal according to the serial data signal, and the fourth branch includes a second inverter, and the second inverter is used to invert the serial data signal to generate the second data signal.

[0010] According to some embodiments of the present invention, the reset processing module includes:

[0011] A reset delay unit, used for performing delay filtering processing on the reset signal to generate a delayed reset signal;

[0012] a reset generating unit, configured to generate an online start transition signal and an online stop transition signal according to the first clock signal, the first data signal and the second data signal, and to generate the anti-interference reset signal and the transition indication signal according to the online start transition signal, the online stop transition signal and the delayed reset signal;

[0013] The restart generating unit is used to generate an online restart signal according to the first clock signal, the jump indication signal, the second data signal and the delayed reset signal.

[0014] According to some embodiments of the present invention, the reset delay unit includes a plurality of delays connected in series and a plurality of first OR gates connected in series, the delays corresponding to the first OR gates one by one, the plurality of delays are used to delay the reset signal multiple times, each of the delays generates a corresponding delayed signal, the first of the first OR gates performs an OR operation on the reset signal and the delayed signal of the first of the delays to generate an OR operation signal, each of the remaining first OR gates is used to perform an OR operation on the OR operation signal output by the previous first OR gate and the delayed signal of the corresponding delay to generate a corresponding OR operation signal, and the OR operation signal generated by the last of the first OR gates is the delayed reset signal.

[0015] According to some embodiments of the present invention, the reset delay unit includes three delayers connected in series and three first OR gates connected in series, the input end of the first delayer is electrically connected to the reset signal, the output end of the first delayer outputs the first delayed signal, the input end of the second delayer is electrically connected to the output end of the first delayer, the output end of the second delayer outputs the second delayed signal, the input end of the third delayer is electrically connected to the output end of the second delayer, the output end of the third delayer outputs the third delayed signal, the first input end of the first first OR gate is electrically connected to the reset signal, the second input end of the first first OR gate is electrically connected to the output end of the first delayer, the first input end of the second first OR gate is electrically connected to the output end of the first first OR gate, the second input end of the second first OR gate is electrically connected to the output end of the second delayer, the first input end of the third first OR gate is electrically connected to the output end of the second first OR gate, the second input end of the third first OR gate is electrically connected to the output end of the third delayer, and the output end of the third first OR gate outputs the delayed reset signal.

[0016] According to some embodiments of the present invention, the reset generation unit includes: a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, an XOR gate, a second OR gate, a third OR gate, a third inverter, a fourth inverter, a fifth inverter, a first flip-flop, and a second flip-flop;

[0017] The input end of the third inverter is electrically connected to the first clock signal, the output end of the third inverter is electrically connected to the first input end of the first AND gate, the second input end of the first AND gate is electrically connected to the first input end of the XOR gate, the output end of the first AND gate is electrically connected to the first input end of the second OR gate, the second input end of the XOR gate is electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is electrically connected to the first clock signal, the output end of the second AND gate is electrically connected to the second input end of the second OR gate, the output end of the second OR gate is electrically connected to the input end of the first trigger, the reset end of the first trigger is electrically connected to the delayed reset signal, the trigger end of the first trigger is electrically connected to the second data signal, the output end of the first trigger is electrically connected to the first input end of the third AND gate, and the second input end of the third AND gate is electrically connected to the first clock signal. the clock signal is electrically connected to the output end of the third AND gate and the first input end of the third OR gate; the input end of the fifth inverter is electrically connected to the first clock signal, the output end of the fifth inverter is electrically connected to the first input end of the fourth AND gate, the second input end of the fourth AND gate is electrically connected to the second input end of the XOR gate, the output end of the fourth AND gate is electrically connected to the second input end of the third OR gate, the output end of the third OR gate is electrically connected to the input end of the second trigger, the reset end of the second trigger is electrically connected to the delayed reset signal, the trigger end of the second trigger is electrically connected to the first data signal, the output end of the second trigger is electrically connected to the second input end of the XOR gate, the output end of the XOR gate is electrically connected to the first input end of the fifth AND gate, the second input end of the fifth AND gate is electrically connected to the delayed reset signal, the output end of the fifth AND gate outputs the anti-interference reset signal, and the output end of the XOR gate outputs the jump indication signal.

[0018] According to some embodiments of the present invention, the restart generation unit includes:

[0019] a sixth AND gate, wherein a first input terminal of the sixth AND gate is electrically connected to the first clock signal, and a second input terminal of the sixth AND gate is electrically connected to the transition indication signal;

[0020] A third trigger, an input terminal of the third trigger is electrically connected to the output terminal of the sixth AND gate, a reset terminal of the third trigger is electrically connected to the delayed reset signal, a trigger terminal of the third trigger is electrically connected to the second data signal, and an output terminal of the third trigger outputs the online restart signal.

[0021] According to some embodiments of the present invention, the slave control module includes:

[0022] A slave state machine, electrically connected to the reset processing module;

[0023] A slave data channel selection module, electrically connected to the slave state machine and the register read-write module respectively;

[0024] The slave address update module is electrically connected to the slave data channel selection module.

[0025] According to some embodiments of the present invention, there are two register read / write modules, which are used to write data into corresponding registers according to received read commands, and to send data of corresponding registers according to received write commands.

[0026] In a second aspect, an anti-interference communication system according to an embodiment of the present invention includes the anti-interference I2C slave module described in the above-mentioned embodiment.

[0027] The anti-interference I2C slave module and communication system according to the embodiments of the present invention have at least the following beneficial effects: the reset signal is filtered by the reset processing module to solve the problem of interference of error signals on the line in the idle phase with the transmission, and the problem of interference of glitches in the reset signal with the circuit, so that data transmission is more stable.

[0028] Additional aspects and advantages of the present invention will be given in part in the following description and in part will be obvious from the following description, or will be learned through practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] The above and / or additional aspects and advantages of the present invention will become apparent and easily understood from the description of the embodiments in conjunction with the following drawings, in which:

[0030] Figure 1 A schematic diagram of the structure of an anti-interference I2C slave module according to an embodiment of the present invention;

[0031] Figure 2 is a schematic diagram of a clock processing module according to an embodiment of the present invention;

[0032] Figure 3 is a schematic diagram of a reset delay unit according to an embodiment of the present invention;

[0033] Figure 4 is a timing diagram of a reset delay unit according to an embodiment of the present invention;

[0034] Figure 5 is a schematic diagram of a reset generation unit according to an embodiment of the present invention;

[0035] Figure 6 is a timing diagram of a reset generation unit according to an embodiment of the present invention;

[0036] Figure 7 is a schematic diagram of a restart generation unit according to an embodiment of the present invention;

[0037] Figure 8 FIG. 4 is a timing diagram of a restart generation unit according to an embodiment of the present invention. DETAILED DESCRIPTION

[0038] Embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and are not to be construed as limitations on the present application. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0039] In the description of the present invention, it should be understood that descriptions involving orientations, such as up, down, front, back, left, right, etc., and orientations or positional relationships indicated are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present invention.

[0040] The terms "first", "second", "third" and "fourth" etc. in the specification and claims of the present invention and the drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but may optionally include steps or units that are not listed, or may optionally include other steps or units that are inherent to these processes, methods, products or devices.

[0041] Reference to "embodiments" in the present invention means that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present invention. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0042] I2C: The abbreviation of Inter-Integrated Circuit, translated as internal integrated circuit, is a synchronous, multi-master-slave serial communication bus invented by Philips Semiconductor in 1982. It is mainly used to connect microcontrollers and their peripherals. Its essence is a low-cost two-wire interface, including a serial clock line SCL for transmitting clock signals and a serial data line SDA for transmitting data between devices. These two lines can realize the sending and receiving of messages between devices.

[0043] The information transmission of the I2C bus requires mutual responses between the host and the slave. The communication devices are highly interactive, so glitches on the line can easily affect the transmission of I2C. In the case of unstable power supply, glitches are very easy to form on the line, which is extremely detrimental to the transmission of information. If glitches occur on the line signal during the idle phase, resulting in the generation of an error signal, incorrect data transmission may occur. If glitches occur on the reset signal itself, the entire circuit may be completely reset. Moreover, the existing I2C bus does not perform certain processing on the reset signal inside the module, which also results in the reset signal glitches during data transmission, which may cause the entire circuit to reset abnormally.

[0044] To this end, an embodiment of the present invention provides an anti-interference I2C slave module and an anti-interference communication system, which performs certain filtering processing on the reset signal through the reset processing module to solve the interference problem of online error signals on transmission in the idle stage and the interference problem of burrs on the circuit caused by the reset signal, thereby making data transmission more stable.

[0045] The following is combined with Figure 1-8 , the anti-interference I2C slave module and the anti-interference communication system of the embodiments of the present invention are described in detail.

[0046] On the one hand, the embodiment of the present invention provides an anti-interference I2C slave module, such as Figure 1As shown, it includes a clock processing module 100, a reset processing module 200, a slave control module 300 and a register read-write module 400, wherein the clock processing module 100 is used to generate a first clock signal (clk_scl) and a first data signal (clk_sda) according to the received serial clock signal (SCL_I) and the serial data signal (SDA_I), and invert the serial clock signal (SCL_I) and the serial data signal (SDA_I) to generate a second clock signal (clk_scl_b) and a second data signal (clk_sda_b); the reset processing module 200 and the clock processing module 100, the reset processing module 200 is used to filter the reset signal (rst_n) according to the first clock signal (clk_scl), the first data signal (clk_sda) and the second data signal (clk_sda_b) to obtain an anti-interference reset signal (i2c_rst_n); the slave control module 300 is electrically connected to the clock processing module 100 and the reset processing module 200, and the slave control module 300 is used to perform logic processing; the register read-write module 400 is electrically connected to the clock processing module 100 and the slave control module 300, and the register read-write module 400 is used to perform read and write operations.

[0047] Specifically, the clock processing module 100 processes the SCL_I and SDA_I signals input to the I2C slave, generates corresponding signals clk_scl and clk_sda, and generates their negated signals clk_scl_b and clk_sda_b. The reset processing module 200 generates an anti-interference reset signal (i2c_rst_n) according to the signals (clk_scl, clk_sda and clk_sda_b) output by the clock processing module 100. The generation of the anti-interference reset signal (i2c_rst_n) depends on the online stop jump signal (sto_st) and the online start jump signal (sta_st), which is equivalent to indicating the busy state of the online. The slave control module 300 performs logical processing related to the I2C protocol, including slave output data signal generation, slave address update, and slave data channel selection. When reading data, the register read / write module 400 writes the received data into the corresponding register according to the received command code and outputs it to the corresponding analog port. When writing data, the register read / write module 400 sends the data of the corresponding register according to the received command code.

[0048] Furthermore, if Figure 2As shown, in some embodiments of the present invention, the clock processing module 100 includes a first inverting unit and a second inverting unit; the first inverting unit includes a first branch and a second branch in parallel, the first branch is used to generate a first clock signal (clk_scl) according to a serial clock signal (SCL_I), and the second branch includes a first inverter A1, and the first inverter A1 is used to invert the serial clock signal (clk_scl_b) to generate a second clock signal (clk_scl_b); the second inverting unit includes a third branch and a fourth branch in parallel, the third branch is used to generate a first data signal (clk_sda) according to a serial data signal (SDA_I), and the fourth branch includes a second inverter A2, and the second inverter A2 is used to invert the serial data signal (SDA_I) to generate a second data signal (clk_sda_b). By inverting the serial clock signal and the serial data signal, it is convenient for the subsequent control reset processing module 200 to process the reset signal.

[0049] Furthermore, if Figure 1 As shown, in some embodiments of the present invention, the reset processing module 200 includes a reset delay unit 210, a reset generation unit 220 and a restart generation unit 230. The reset delay unit 210 is used to perform delay filtering processing on the reset signal (rst_n) to generate a delayed reset signal (dev_rst_n); the reset generation unit 220 is used to generate an online start jump signal (sta_st) and an online stop jump signal (sto_st) according to the first clock signal (clk_scl), the first data signal (clk_sda) and the second data signal (clk_sda_b). ), and generates an anti-interference reset signal (i2c_rst_n) according to the online start jump signal (sta_st), the online stop jump signal (sto_st) and the delayed reset signal (dev_rst_n), and sends it to the slave control module 300; the restart generation unit 230 is used to generate an online restart signal (i2c_sta) according to the first clock signal (clk_scl), the jump indication signal (sta_stb), the second data signal (clk_sda_b) and the delayed reset signal (dev_rst_n), and sends it to the slave control module 300.

[0050] Specifically, when the reset signal (rst_n) is input to the I2C slave, the reset delay unit 210 is first subjected to delay filtering processing to generate a delayed reset signal (dev_rst_n). This filtering can only filter out low-level glitches. By delaying the reset signal (rst_n) and then performing or processing, low-level glitches are filtered out. In this example, the circuit and timing of the reset delay unit 210 are as follows: Figure 3 and Figure 4As shown, this filtering process can prevent a very short reset pulse from appearing on the line and causing the entire circuit to reset.

[0051] Specifically, Figure 3 As shown, in this example, the reset delay unit 210 includes a plurality of delays connected in series and a plurality of first OR gates connected in series, the delays correspond to the first OR gates one by one, the plurality of delays are used to delay the reset signal multiple times, each delay generates a corresponding delayed signal, the first first OR gate generates an OR signal after performing an OR operation on the reset signal (rst_n) and the delayed signal (rst_n_dly0) of the first delayer, and each of the remaining first OR gates is used to perform an OR operation on the OR signal output by the previous first OR gate and the delayed signal of the corresponding delayer, and generate a corresponding OR signal, and the OR signal generated by the last first OR gate is a delayed reset signal (dev_rst_n).

[0052] For example, if the number of delayers and the first OR gates are both three, Figure 3 As shown, the three delays are D1, D2 and D3, and the three first OR gates are U11, U12 and U13. The reset delay unit 210 includes three delays (D1, D2 and D3) connected in series and three first OR gates (U11, U12 and U13) connected in series. The input end of the first delay D1 is electrically connected to the reset signal (rst_n), and the output end of the first delay D1 outputs the first delayed signal (rst_n_dly0). The input end of the second delay D2 is electrically connected to the output end of the first delay D1, and the output end of the second delay D2 outputs the second delayed signal (rst_n_dly1). The input end of the third delay D3 is electrically connected to the output end of the second delay D2, and the output end of the third delay D3 outputs the third delayed signal (rst_n_dly 2), the first input end of the first first OR gate U11 is electrically connected to the reset signal (rst_n), the second input end of the first first OR gate U11 is electrically connected to the output end of the first delayer D1, the first input end of the second first OR gate U12 is electrically connected to the output end of the first first OR gate U11, the second input end of the second first OR gate U12 is electrically connected to the output end of the second delayer D2, the first input end of the third first OR gate U13 is electrically connected to the output end of the second first OR gate U12, the second input end of the third first OR gate U13 is electrically connected to the output end of the third delayer D3, and the output end of the third first OR gate U13 outputs the delayed reset signal (dev_rst_n). It should be noted that the specific number of delayers and first OR gates can be adjusted according to actual conditions, and is not specifically limited here.

[0053] like Figure 4As shown in FIG. 1 , it is a timing diagram of the reset delay unit 210 filtering the reset signal (rst_n), which can intuitively show the actual filtering situation. The filtering is mainly performed by delaying and adding or processing. The sum of the delay times (delay0, delay1, delay2) is the glitch width that can be filtered out, or the processing determines that it can only filter out glitches in the low-level direction. In practical applications, if the reset signal is unstable due to unstable power supply, the entire circuit may be reset. This filtering process can filter out glitches within a certain width, greatly avoiding this problem.

[0054] After the reset signal (rst_n) is delayed and filtered to generate the delayed reset signal (dev_rst_n), the reset generation unit 220 is required to generate an anti-interference reset signal (i2c_rst_n), which is equivalent to a busy status flag on the line. The circuit and timing of the reset generation unit 220 are as follows: Figure 5 and Figure 6 As shown. The anti-interference reset signal (i2c_rst_n) is mainly generated based on the online start jump signal (sta_st) and the online stop jump signal (sto_st) XOR, and the delayed reset signal (dev_rst_n). The timing of this signal is as follows Figure 6 As shown, the level is high between start and stop, and low between stop and start. The online start transition signal (sta_st) changes its level each time it recognizes the online start, and the stop transition signal (sto_st) changes its level each time it recognizes the online stop.

[0055] Specifically, Figure 5As shown, in this example, the reset generation unit 220 includes: a first AND gate Q1, a second AND gate Q2, a third AND gate Q3, a fourth AND gate Q4, a fifth AND gate Q5, an XOR gate U2, a second OR gate U3, a third OR gate U4, a third inverter A3, a fourth inverter A4, a fifth inverter A5, a first trigger REG0 and a second trigger REG1; wherein the input end of the third inverter A3 is electrically connected to the first clock signal (clk_scl), the output end of the third inverter A3 is electrically connected to the first input end of the first AND gate Q1, the second input end of the first AND gate Q1 is electrically connected to the first input end of the XOR gate U2, and the output end of the first AND gate Q1 is electrically connected to the second OR gate U3. The first input terminal of the gate U3 is electrically connected, the second input terminal of the XOR gate U2 is electrically connected to the input terminal of the fourth inverter A4, the output terminal of the fourth inverter A4 is electrically connected to the first input terminal of the second AND gate Q2, the second input terminal of the second AND gate Q2 is electrically connected to the first clock signal (clk_scl), the output terminal of the second AND gate Q2 is electrically connected to the second input terminal of the second OR gate U3, the output terminal of the second OR gate U3 is electrically connected to the input terminal of the first trigger REG0, the reset terminal of the first trigger REG0 is electrically connected to the delayed reset signal (dev_rst_n), and the trigger terminal of the first trigger REG0 is electrically connected to the second data signal (clk_sda_b) , the output end of the first flip-flop REG0 is electrically connected to the first input end of the third AND gate Q3, the second input end of the third AND gate Q3 is electrically connected to the first clock signal (clk_scl), and the output end of the third AND gate Q3 is electrically connected to the first input end of the third OR gate U4; the input end of the fifth inverter A5 is electrically connected to the first clock signal (clk_scl), the output end of the fifth inverter A5 is electrically connected to the first input end of the fourth AND gate Q4, the second input end of the fourth AND gate Q4 is electrically connected to the second input end of the XOR gate U2, the output end of the fourth AND gate Q4 is electrically connected to the second input end of the third OR gate U4, and the output end of the third OR gate U4 is electrically connected to the second flip-flop REG1 The input end of the second trigger REG1 is electrically connected to the delayed reset signal (dev_rst_n), the trigger end of the second trigger REG1 is electrically connected to the first data signal (clk_sda), the output end of the second trigger REG1 is electrically connected to the second input end of the XOR gate U2, the output end of the XOR gate U2 is electrically connected to the first input end of the fifth AND gate Q5, the second input end of the fifth AND gate Q5 is electrically connected to the delayed reset signal (dev_rst_n), the output end of the fifth AND gate Q5 outputs an anti-interference reset signal (i2c_rst_n), and the output end of the XOR gate U2 also outputs a jump indication signal (sta_stb).

[0056] like Figure 5As shown, regarding the generation of the online start jump signal (sta_st) and the online stop jump signal (sto_st), the present application provides a special design idea: for the generation of the online start jump signal (sta_st), the timing logic always block uses the rising edge of the data negation signal (clk_sda_b) as the trigger condition, when sta_st=1 and clk_scl=0 or sto_st=0 and clk_scl=1, sta_st is 1, otherwise it is 0; for the generation of the stop jump signal (sto_st), the timing logic always block uses the rising edge of the data signal (clk_sda) as the trigger condition, when sta_st=1 and clk_scl=1 or sto_st=1 and clk_scl=0, sto_st is 1, otherwise it is 0. Using a new anti-interference reset signal (i2c_rst_n) to perform reset processing before starting each transmission can filter out the impact of all actions on the transmission during the idle phase of the line, which can greatly improve the anti-interference performance of the I2C slave.

[0057] At the same time, the reset processing module 200 also generates an online restart signal (i2c_sta) through the restart generation unit 230. The circuit and timing of the restart generation unit 230 are as follows: Figure 7 and Figure 8 As shown. Specifically, the restart generation unit 230 includes a sixth AND gate Q6 and a third trigger REG2, the first input end of the sixth AND gate Q6 is electrically connected to the first clock signal (clk_scl), the second input end of the sixth AND gate Q6 is electrically connected to the jump indication signal (sta_stb), the input end of the third trigger REG2 is electrically connected to the output end of the sixth AND gate Q6, the reset end of the third trigger REG2 is electrically connected to the delayed reset signal (dev_rst_n), the trigger end of the third trigger REG2 is electrically connected to the second data signal (clk_sda_b), and the output end of the third trigger REG2 outputs the online restart signal (i2c_sta). In the restart generation unit 230, the timing logic always block uses the rising edge of the data negation signal (clk_sda_b) as a trigger condition to generate an online restart signal (i2c_sta).

[0058] Furthermore, if Figure 1 As shown, in some embodiments of the present invention, the slave control module 300 includes:

[0059] The slave state machine 310 is electrically connected to the reset processing module 200;

[0060] The slave data channel selection module 320 is electrically connected to the slave state machine 310 and the register read / write module 400 respectively;

[0061] The slave address updating module 330 is electrically connected to the slave data channel selecting module 320 .

[0062] The slave control module 300 is used to perform logic processing related to the I2C protocol, including generating a slave output data signal through the slave state machine 310, updating the slave address through the slave address update module 330, and selecting a slave data channel through the slave data channel selection module 320.

[0063] Furthermore, if Figure 1 As shown, in some embodiments of the present invention, there are two register read-write modules 400, namely register read-write module 0 and register read-write module 1. The register read-write module 400 is used to write data to the corresponding register according to the received read command and output it to the corresponding analog port. The register read-write module 400 is also used to send the data of the corresponding register according to the received write command.

[0064] According to the anti-interference I2C slave module of the embodiment of the present invention, the reset signal is filtered by the reset processing module 200 to solve the interference problem of the error signal on the line in the idle stage to the transmission, and the interference problem of the burr of the reset signal to the circuit, so that the data transmission is more stable. In addition, the technical solution of the present application does not need to use a high-frequency clock, thereby reducing power consumption.

[0065] On the other hand, an embodiment of the present invention further provides an interference-resistant communication system, including the interference-resistant I2C slave module described in the above-mentioned embodiment.

[0066] The embodiments of the present invention are described in detail above with reference to the accompanying drawings, but the present invention is not limited to the above embodiments, and various changes can be made within the knowledge scope of ordinary technicians in the relevant technical field without departing from the purpose of the present invention.

Claims

1. An anti-interference I2C slave module, characterized in that: include: A clock processing module, configured to generate a first clock signal and a first data signal according to a received serial clock signal and a serial data signal, and invert the serial clock signal and the serial data signal to generate a second clock signal and a second data signal; a reset processing module, electrically connected to the clock processing module, and configured to filter a reset signal according to the first clock signal, the first data signal, and the second data signal to obtain an anti-interference reset signal; A slave control module, electrically connected to the clock processing module and the reset processing module respectively, and the slave control module is used for performing logic processing; The register read-write module is electrically connected to the clock processing module and the slave control module respectively, and the register read-write module is used for performing read-write operations.

2. The anti-interference I2C slave module according to claim 1, characterized in that: The clock processing module includes a first inversion unit and a second inversion unit; the first inversion unit includes a first branch and a second branch connected in parallel, the first branch is used to generate the first clock signal according to the serial clock signal, the second branch includes a first inverter, the first inverter is used to invert the serial clock signal to generate the second clock signal; the second inversion unit includes a third branch and a fourth branch connected in parallel, the third branch is used to generate the first data signal according to the serial data signal, the fourth branch includes a second inverter, the second inverter is used to invert the serial data signal to generate the second data signal.

3. The anti-interference I2C slave module according to claim 1, characterized in that: The reset processing module comprises: A reset delay unit, used for performing delay filtering processing on the reset signal to generate a delayed reset signal; a reset generating unit, configured to generate an online start transition signal and an online stop transition signal according to the first clock signal, the first data signal and the second data signal, and to generate the anti-interference reset signal and the transition indication signal according to the online start transition signal, the online stop transition signal and the delayed reset signal; The restart generating unit is used to generate an online restart signal according to the first clock signal, the jump indication signal, the second data signal and the delayed reset signal.

4. The anti-interference I2C slave module according to claim 3, characterized in that: The reset delay unit includes a plurality of delays connected in series and a plurality of first OR gates connected in series. The delays correspond to the first OR gates one by one. The plurality of delays are used to delay the reset signal multiple times. Each of the delays generates a corresponding delayed signal. The first of the first OR gates performs an OR operation on the reset signal and the delayed signal of the first delay to generate an OR operation signal. Each of the remaining first OR gates is used to perform an OR operation on the OR operation signal output by the previous first OR gate and the delayed signal of the corresponding delay to generate a corresponding OR operation signal. The OR operation signal generated by the last of the first OR gates is the delayed reset signal.

5. The anti-interference I2C slave module according to claim 4, characterized in that: The reset delay unit includes three delayers connected in series and three first OR gates connected in series, the input end of the first delayer is electrically connected to the reset signal, the output end of the first delayer outputs the first delayed signal, the input end of the second delayer is electrically connected to the output end of the first delayer, the output end of the second delayer outputs the second delayed signal, the input end of the third delayer is electrically connected to the output end of the second delayer, the output end of the third delayer outputs the third delayed signal, the first input end of the first first OR gate is electrically connected to the reset signal, the second input end of the first first OR gate is electrically connected to the output end of the first delayer, the first input end of the second first OR gate is electrically connected to the output end of the first first OR gate, the second input end of the second first OR gate is electrically connected to the output end of the second delayer, the first input end of the third first OR gate is electrically connected to the output end of the second first OR gate, the second input end of the third first OR gate is electrically connected to the output end of the third delayer, and the output end of the third first OR gate outputs the delayed reset signal.

6. The anti-interference I2C slave module according to claim 3, characterized in that: The reset generation unit includes: a first AND gate, a second AND gate, a third AND gate, a fourth AND gate, a fifth AND gate, an XOR gate, a second OR gate, a third OR gate, a third inverter, a fourth inverter, a fifth inverter, a first trigger and a second trigger; The input end of the third inverter is electrically connected to the first clock signal, the output end of the third inverter is electrically connected to the first input end of the first AND gate, the second input end of the first AND gate is electrically connected to the first input end of the XOR gate, the output end of the first AND gate is electrically connected to the first input end of the second OR gate, the second input end of the XOR gate is electrically connected to the input end of the fourth inverter, the output end of the fourth inverter is electrically connected to the first input end of the second AND gate, the second input end of the second AND gate is electrically connected to the first clock signal, the output end of the second AND gate is electrically connected to the second input end of the second OR gate, the output end of the second OR gate is electrically connected to the input end of the first trigger, the reset end of the first trigger is electrically connected to the delayed reset signal, the trigger end of the first trigger is electrically connected to the second data signal, the output end of the first trigger is electrically connected to the first input end of the third AND gate, and the second input end of the third AND gate is electrically connected to the first clock signal. the clock signal is electrically connected to the output end of the third AND gate and the first input end of the third OR gate; the input end of the fifth inverter is electrically connected to the first clock signal, the output end of the fifth inverter is electrically connected to the first input end of the fourth AND gate, the second input end of the fourth AND gate is electrically connected to the second input end of the XOR gate, the output end of the fourth AND gate is electrically connected to the second input end of the third OR gate, the output end of the third OR gate is electrically connected to the input end of the second trigger, the reset end of the second trigger is electrically connected to the delayed reset signal, the trigger end of the second trigger is electrically connected to the first data signal, the output end of the second trigger is electrically connected to the second input end of the XOR gate, the output end of the XOR gate is electrically connected to the first input end of the fifth AND gate, the second input end of the fifth AND gate is electrically connected to the delayed reset signal, the output end of the fifth AND gate outputs the anti-interference reset signal, and the output end of the XOR gate outputs the jump indication signal.

7. The anti-interference I2C slave module according to claim 6, characterized in that: The restart generation unit comprises: a sixth AND gate, wherein a first input terminal of the sixth AND gate is electrically connected to the first clock signal, and a second input terminal of the sixth AND gate is electrically connected to the transition indication signal; A third trigger, an input terminal of the third trigger is electrically connected to the output terminal of the sixth AND gate, a reset terminal of the third trigger is electrically connected to the delayed reset signal, a trigger terminal of the third trigger is electrically connected to the second data signal, and an output terminal of the third trigger outputs the online restart signal.

8. The anti-interference I2C slave module according to claim 1, characterized in that: The slave control module comprises: A slave state machine, electrically connected to the reset processing module; A slave data channel selection module, electrically connected to the slave state machine and the register read-write module respectively; The slave address update module is electrically connected to the slave data channel selection module.

9. The anti-interference I2C slave module according to claim 1, characterized in that: There are two register read / write modules, which are used to write data into corresponding registers according to received read commands, and are also used to send data of corresponding registers according to received write commands.

10. An anti-interference communication system, characterized in that: It comprises the anti-interference I2C slave module as described in any one of claims 1-9.

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