Multi-chip layout optimization method and device based on multi-objective optimization algorithm

Abstract

The present invention discloses a multi-chip layout optimization method and device based on a multi-objective optimization algorithm, comprising: constructing target optimization functions and constraints for chip temperature, inter-chip transmission delay, total area, and inter-chip communication power consumption; iteratively solving the target optimization functions based on the constraints using the NSWOA algorithm to obtain Pareto frontiers for each target optimization function; determining a compromise solution based on the Pareto frontiers using the MHA algorithm; determining the placement of the chip based on the compromise solution, adjusting the orientation according to the pin function and the connection requirements between functional modules, and obtaining a result with the minimum total wiring length based on the shortest total interconnect length, thereby obtaining the optimal layout of the multi-chip. The present invention can effectively improve the performance and integration of the multi-chip system in 2.5D packaging by optimizing the multi-chip layout.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a multi-chip layout optimization method and device based on a multi-objective optimization algorithm. Background Art

[0002] Traditional single-chip designs, plagued by high design complexity and cost, limited process flexibility, low manufacturing yield, and high production costs, are gradually being replaced by multi-chip systems. Based on 2.5D packaging, multiple chiplets (CPU, GPU, NPU, etc.) are placed on a silicon interposer. These chiplets can utilize a variety of different manufacturing technologies and processes, forming a heterogeneous system that achieves higher performance and lower energy consumption while ensuring inter-chip communication performance.

[0003] However, advances in packaging technology also present numerous challenges, such as the layout of highly integrated chiplet systems. Existing layout optimization techniques primarily focus on single objectives, such as minimizing system area or transmission delay, which can lead to undesirable consequences. This single-objective layout optimization technique is no longer applicable to highly integrated chiplet systems, which require consideration of physical parameters across multiple chips (such as temperature, transmission delay, total area, and communication power consumption). Therefore, a multi-chiplet layout optimization method is urgently needed to optimize the layout and effectively improve the performance and integration of multi-chiplet systems. Summary of the Invention

[0004] In order to address the above-mentioned deficiencies in the prior art, embodiments of the present application provide a multi-chip layout optimization method and apparatus based on a multi-objective optimization algorithm to improve the performance and integration of a multi-chip system in a 2.5D package.

[0005] According to a first aspect of an embodiment of the present application, a multi-chip layout optimization method based on a multi-objective optimization algorithm is provided, comprising:

[0006] Construct the target optimization functions and constraints for chiplet temperature, inter-chiplet transmission delay, total area, and inter-chiplet communication power consumption respectively;

[0007] Based on the constraints, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function;

[0008] Based on the Pareto front, a compromise solution is determined using the MHA algorithm;

[0009] The placement of the chip is determined according to the compromise solution, and the orientation is adjusted according to the pin function and the connection requirements between functional modules. The total wiring length is minimized based on the shortest total interconnect length, thereby obtaining the optimal layout of multiple chiplets.

[0010] According to a second aspect of an embodiment of the present application, a multi-chip layout optimization device based on a multi-objective optimization algorithm is provided, comprising:

[0011] A construction module is used to construct the target optimization functions and constraints for chip temperature, inter-chip transmission delay, total area, and inter-chip communication power consumption respectively;

[0012] A solving module, configured to iteratively solve the objective optimization function using the NSWOA algorithm based on the constraint conditions, and obtain the Pareto frontier of each objective optimization function;

[0013] A determination module, configured to determine a compromise solution based on the Pareto front using an MHA algorithm;

[0014] The optimization module is used to determine the placement position of the chip according to the compromise solution, adjust the position according to the pin function and the connection requirements between functional modules, and obtain the result of minimizing the total wiring length based on the shortest total interconnection length, thereby obtaining the optimal layout of multiple chiplets.

[0015] According to a third aspect of the embodiments of the present application, there is provided an electronic device, including:

[0016] one or more processors;

[0017] a memory for storing one or more programs;

[0018] When the one or more programs are executed by the one or more processors, the one or more processors implement the method as described in the first aspect.

[0019] The technical solutions provided by the embodiments of the present application may have the following beneficial effects:

[0020] The present invention optimizes the chip layout through a multi-objective optimization algorithm, effectively solving key problems in the layout, such as local high temperature, uneven transmission delay, large overall area and high communication power consumption, and achieving a compromise optimal solution among temperature, transmission delay, total area and communication power consumption, making the chip layout more efficient and reliable.

[0021] The present invention first constructs a multi-objective optimization function and constraints; uses the NSWOA algorithm to iteratively solve the objective optimization function, obtaining the Pareto frontier of each objective optimization function; then uses the MHA algorithm to determine a compromise solution; thereby determining the placement of the core particles; and finally, determining the optimal layout of multiple core particles based on the shortest total length of the connection between the core particles. This effectively solves key issues such as local high temperature, uneven transmission delay, large overall area, and high communication power consumption in existing solutions for single-objective optimization of multi-core particle layout, making the multi-core particle layout more efficient and reliable. Compared with single-objective layout optimization, the present invention has stronger adaptability and can be flexibly adjusted for different types and sizes of 2.5D packages.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the present application and, together with the description, serve to explain the principles of the present application.

[0024] Figure 1 The figure is a flowchart showing a multi-chip layout optimization method based on a multi-objective optimization algorithm according to an exemplary embodiment.

[0025] Figure 2 The figure is a block diagram showing a multi-chip layout optimization device based on a multi-objective optimization algorithm according to an exemplary embodiment. DETAILED DESCRIPTION

[0026] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0027] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in this application are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0028] Figure 1 FIG. 1 is a flow chart showing a multi-chip layout optimization method based on a multi-objective optimization algorithm according to an exemplary embodiment. Figure 1 As shown, the method may include the following steps:

[0029] S1: Construct the target optimization functions and constraints for chiplet temperature, inter-chiplet transmission delay, total area, and inter-chiplet communication power consumption respectively;

[0030] Specifically, 1) the core temperature f T : Indicates the temperature of the chip in working state. Too high temperature will affect the performance and reliability of the chip, and may even cause permanent damage to the chip.

[0031] The objective function of the core particle temperature is expressed as:

[0032] ;

[0033] in, is the core particle temperature; } represents the lower left corner coordinate and upper right corner coordinate of core particle n; is the ambient temperature; is the power consumption of the ith chip; is the thermal resistance; is the effective area of ​​the ith core particle; is the heat transfer coefficient between the i-th and j-th core particles; is the temperature of the jth core particle; is the distance between the i-th and j-th core particles, expressed as ;

[0034] Core temperature constraint: The core temperature cannot exceed a certain threshold to prevent overheating. The constraint is expressed as:

[0035] ;

[0036] Where T max is the maximum temperature threshold.

[0037] 2) Inter-chip transmission delay f D : Indicates the time required for data transmission between different cores. The lower the transmission delay, the faster the system response speed.

[0038] The objective function of the inter-core transmission delay is expressed as:

[0039] ;

[0040] Among them, f D Inter-core transmission delay; is the transmission rate between the i-th and j-th core particles;

[0041] Inter-core transmission delay constraint: To ensure the performance of the entire system, the inter-core transmission delay must be less than a certain threshold. The constraint is expressed as:

[0042] ;

[0043] Among them D max is the maximum threshold for transmission delay.

[0044] 3) Total area f A : Indicates the area occupied by the entire 2.5D package. The smaller the area, the higher the integration.

[0045] The objective function of the total area is expressed as:

[0046] ;

[0047] Where, f A is the total area;

[0048] Total area constraint: The total area of ​​the core particle cannot exceed the maximum threshold of the total area of ​​the chip. The constraint is expressed as:

[0049] ;

[0050] in is the total area of ​​the chip.

[0051] 4) Inter-chiplet communication power consumption f P : Indicates the power consumed by communication between different chiplets. The lower the power consumption, the higher the energy efficiency of the system.

[0052] The objective function of the inter-chiplet communication power consumption is expressed as:

[0053] ;

[0054] Among them, f P is the power consumption of inter-chiplet communication; is the communication frequency between the i-th and j-th core particles.

[0055] Inter-chiplet communication power consumption constraint: To achieve good system performance, the inter-chiplet communication power consumption needs to be less than a certain threshold. The constraint is expressed as:

[0056] ;

[0057] Among them, P max is the maximum threshold of communication power consumption.

[0058] Compared with the traditional optimization that only considers a single goal, this embodiment significantly improves the overall optimization effect of the chip layout by collaboratively optimizing the above four goals, thereby more effectively achieving the optimal layout.

[0059] S2: Based on the constraints, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function. This step includes the following sub-steps:

[0060] S21: Read the parameters of the chip: the position of the chip, the ambient temperature, the power consumption of the chip, the thermal resistance; the effective area of ​​the chip, the thermal conductivity between the chips, the temperature of the chips, the distance between the chips, the transmission rate between the chips, and the communication frequency between the chips;

[0061] Specifically, read the core particle parameters:

[0062] Position of core particles X t =[ { x 1 , y 1 , x 1 ' , y 1 ' }.....{ x n , y n , x n ' , y n ' } ] ; Ambient temperature ; Power consumption of the i-th chip Thermal resistance ; The effective area of ​​the i-th core particle ;The thermal conductivity between the i-th and j-th core particles ; Temperature of the jth core particle ; The distance between the i-th and j-th core particles ; Transmission rate between the i-th and j-th core particles ; Communication frequency between the i-th and j-th core particles ;

[0063] S22: Initialize the NSWOA algorithm parameters, select the initial population, and initialize according to the constraints;

[0064] Specifically, the NSWOA algorithm parameters are initialized, the initial population is selected, and initialization is performed according to the constraints. Specifically, the NSWOA algorithm parameters are initialized and the initial population is selected. Specifically, the population size N, the maximum number of iterations T, and the whale position information X(t) of the NSWOA algorithm are initialized, the corresponding fitness value of each whale is calculated, the whales are sorted according to the size of the fitness value, and a population size of N whales is selected as the initial population.

[0065] S23: Update the current optimal solution through the shrinking and encircling mechanism, spiral mechanism, and search and foraging mechanism of the NSWOA algorithm. In each iteration, it is necessary to calculate each objective optimization function to evaluate the fitness and identify the current optimal solution.

[0066] 3) Specifically, the current optimal solution is updated through the shrinking and encircling mechanism, spiral mechanism, and search and foraging mechanism of the NSWOA algorithm. In each iteration, the target optimization function f is calculated. T 、f D 、f A 、f P Perform fitness evaluation and identify the current optimal solution.

[0067] Shrinking and surrounding mechanism:

[0068] When hunting, humpback whales need to surround their prey and first determine the location of the prey. The following mathematical model is proposed:

[0069]

[0070] in:

[0071]

[0072] Where: represents the best whale position vector so far; represents the current whale position vector; t is the current iteration number; A and C are the representation coefficients; and is a random number between [0,1]; a is a control parameter, which decreases linearly from 2 to 0 as the number of iterations increases; T is the maximum number of iterations.

[0073] Screw mechanism:

[0074] According to the hunting behavior of humpback whales, they swim towards their prey in a spiral motion, and the mathematical model is:

[0075]

[0076] Where: l is a random number between [-1,1], b is a parameter representing the degree of spiral, Indicates the distance between the whale and its prey.

[0077] In addition to swimming towards prey in a spiral shape, whales also shrink the circle. Therefore, in this model, it is assumed that P i The probability of choosing the shrinking and surrounding mechanism and 1-P i The probability of choosing the spiral model to update the position of the whale is as follows:

[0078]

[0079] When attacking prey, the mathematical model sets a decreasing value of a as it approaches the prey, so that the fluctuation range of A also decreases with a. During the iteration process, as the value of a decreases from 2 to 0, A is a random value in the range [-a, a]. When the value of A is in the range [-1, 1], the whale's next position can be anywhere between its current position and the prey's. The algorithm sets the attack on the prey when A < 1.

[0080] Search foraging mechanism:

[0081] To ensure that all whales can fully search the solution space, we choose to update the whale positions according to the distance between them to achieve the purpose of global random search. The established mathematical model is as follows: in, is the randomly selected whale position vector. The algorithm sets A≥1 to randomly select a search agent and update the positions of other whales according to the randomly selected whale position, forcing the whale to deviate from the prey and find a more suitable prey to achieve global search.

[0082] S24: Repeat the above S21-S23 until the maximum number of iterations T is reached, and the Pareto frontiers of the four objectives are obtained.

[0083] The NSWOA algorithm used in this embodiment has a strong global search capability and does not rely on gradient information. It performs well in processing the above-mentioned nonlinear, multi-objective, and high-dimensional optimization problems.

[0084] S3: Based on the Pareto front, a compromise solution is determined using the MHA algorithm;

[0085] S31: For the objective function, each Pareto optimal solution has a corresponding set of values. Suppose there are n sets of solutions on the Pareto frontier, and we get a matrix M, where each row corresponds to a solution.

[0086] Specifically, preprocessing: For the four objective functions above, each Pareto optimal solution has a set of corresponding values. Assume there are n solutions on the Pareto frontier, and obtain an n×4 matrix M, where each row corresponds to a solution.

[0087]

[0088] S32: By combining the matrix M with three different weight matrices W Q 、W K and W V Multiply to calculate the Query, Key, and Value of each solution;

[0089] Specifically, Query: Each input element (such as a word, character, etc.) has a Query vector. The Query vector represents the information or features we are looking for. When calculating the attention weight, the Query is used to match the Key to determine which elements to focus on and their importance. Key: Each input element also has a Key vector. The Key vector represents the characteristics or content of the element. The Key is used to match the Query and calculate the similarity or correlation between the two to determine which elements are important to the current Query. Value: Each input element also has a Value vector. The Value vector represents the actual information or feature value. After the attention weights are calculated, these weights are used to weight the Value to generate the final output.

[0090] Calculate Query, Key and Value: By combining M with three different weight matrices W Q 、W K and W V Multiply to calculate the query, key, and value of each solution. The above three weight matrices are learned during the model training process. The mathematical model is as follows:

[0091]

[0092] Among them, Q, K and V are the query, key and value of all solutions respectively.

[0093] Calculate the attention weight: Calculate the dot product of each solution's query and all solution keys, and then normalize it through the softmax function to obtain the attention weight of each solution to other solutions. The mathematical model is as follows:

[0094] Among them, d k It is the dimension of Key, which is used to scale the size of the dot product to prevent the gradient disappearance problem caused by the dot product being too large.

[0095] The detailed process of mathematical model training is as follows:

[0096] a) Read a large amount of historical data of the above core particle.

[0097] b) Initialize the weight matrix W Q 、W K and W V , these weight matrices are randomly initialized.

[0098] c) Perform forward propagation using steps 2) and 3) above to calculate Q, K, V, and attention weights.

[0099] d) Define a loss function to measure the difference between the model's prediction and the true compromise solution. Use the Euclidean distance between the model's predicted compromise solution and the true compromise solution as the loss. The mathematical model is as follows:

[0100]

[0101] in, and are the values ​​of the compromise solution predicted by the model and the true compromise solution on the i-th target, respectively.

[0102] e) Back propagation and weight update: Calculate the loss function with respect to W Q 、W K and W V The gradient of Q , ∇W K and ∇W V , and then use these gradients to update the weight matrix. The update formula is as follows:

[0103]

[0104] in, is the learning rate, which determines the step size of each update.

[0105] f) Repeat the above steps (forward propagation, loss calculation, backpropagation, and weight update), each iteration needs to traverse all the training data until the model performance meets the requirements or the maximum number of iterations.

[0106] S33: By calculating the dot product of the query of each solution and the key of all solutions, and then normalizing it through the softmax function, the attention weight of each solution to other solutions is obtained;

[0107] Specifically, Query and Key are vectors generated by the model's input data or the output of the previous layer. The dot product of Query and Key is calculated by measuring the correlation or similarity between each solution and other solutions. The larger the dot product value, the stronger the relationship between the solutions. Then, all dot products are normalized by the softmax function so that the sum of the attention weights between all solutions is 1. The role of Softmax is to convert these dot products into probability distributions, which facilitates the subsequent weighted summation of different solutions. By calculating dot products and softmax operations, the model can dynamically assign different attention weights based on the similarity or importance between solutions. This mechanism enables the model to flexibly focus on different solutions according to task requirements. This approach can effectively capture the dependencies between different solutions and improve the performance of the model in complex tasks.

[0108] S34: Select the solution with the highest attention weight as the compromise solution;

[0109] Specifically, the solution with the highest score (weight) is selected from the attention weights of all solutions as the final compromise. This compromise selection focuses attention on the solution that contributes most to the final decision, helping the model make more accurate choices.

[0110] S35: Based on the predicted compromise solution and the true compromise solution, calculate the loss function, backpropagate, and update the Query, Key, and Value.

[0111] Specifically, loss functions (such as mean squared error and cross entropy) measure the difference between the predicted compromise solution and the actual compromise solution. By calculating this loss value, the model can determine the deviation between the predicted result and the target value. The backpropagation algorithm then propagates the loss value back from the output layer, and optimization methods such as gradient descent are used to adjust the model parameters, including the query, key, and value. These parameter updates help the model learn better and improve prediction performance.

[0112] Through backpropagation and parameter updates, the model gradually adjusts the query, key, and value, optimizing the final compromise solution selection, allowing the model to better approximate the true solution. This design can adaptively adjust the solution selection method based on the input data and target task, thereby improving the model's generalization ability and accuracy.

[0113] The MHA algorithm uses data-driven training to obtain the corresponding weight matrix. Compared to calculating the optimal compromise solution based on fixed weights for four objectives, MHA enhances information capture, can update objective weights in real time, and is more adaptable. This makes the compromise solution for multi-objective optimization more accurate and efficient, while also being able to handle complex relationships between different objectives, significantly improving the overall performance of the optimization process.

[0114] S4: Determine the placement of the chip according to the compromise solution, adjust the orientation according to the pin function and the connection requirements between functional modules, and obtain the minimum total wiring length based on the shortest total interconnection length, thereby obtaining the optimal layout of multiple chiplets.

[0115] Specifically, according to the compromise solution, the level of the chiplets to be arranged is determined according to the number of interconnection lines. As shown in Table 1, the more interconnection lines a chiplet has, the higher its level. The placement of the chiplets is determined based on the priority arrangement standard. The orientation is then adjusted based on the pin function and the connection requirements between functional modules. The total wiring length is minimized based on the shortest total interconnection line length, thereby obtaining the optimal layout of multiple chiplets.

[0116] Table 1 is the core particle classification table:

[0117]

[0118] S41: The connection length is calculated by summing the distances of all pin locations between each pair of die:

[0119]

[0120] Where N is the number of core particles, Pi and Pj are the pin positions of core particles i and j respectively, and ‖p1-p2‖ is the Euclidean distance between two pins;

[0121] Specifically, by calculating the connection length between each pair of chiplets, we can ensure that the distance between the pins of the chiplets is minimized during layout optimization, thereby reducing the total length of the interconnects. This effectively reduces routing complexity and signal latency. By calculating the distance between each pair of pins, we can comprehensively evaluate the interconnect lengths of different chiplet layouts, rather than just considering the distance between individual pins, thereby ensuring a more reasonable layout.

[0122] S42: Initialization: Randomly select the placement orientation of each core particle, the placement orientation of the core particle is: 0°, 90°, 180°, 270°;

[0123] Specifically, random initialization can break the local optimal solution during the optimization process, providing multiple possible layout starting points and more options for subsequent optimization. By initializing multiple different layout solutions, the search space is expanded, which helps to find a more optimal layout solution.

[0124] S43: Iterative optimization: In each iteration, a core particle is randomly selected and its placement is changed, the pin position of the core particle is updated, and the new connection length is calculated;

[0125] The conditions for accepting a new solution are: if the new connection length is less than the current length, the new solution is accepted; otherwise, no change is made; the solution after the maximum number of iterations is taken as the final solution, thereby obtaining the optimal orientation of each core particle and the final optimal layout.

[0126] Specifically, in each iteration, a randomly selected coreparticle is tried, and its placement orientation is changed (for example, from 0° to 90°, or from 180° to 270°). Based on the new placement orientation, the coreparticle's pin position set is updated. The new total connection length, L', is calculated. If the new connection length, L', is less than the current connection length, L, the new solution is accepted, with the coreparticle's new placement orientation as the current solution; otherwise, the original solution is retained. This process is repeated until the maximum number of iterations is reached. Finally, the placement solution at the end of the iteration is considered the optimal layout.

[0127] Through these designs, it is possible to effectively balance computational complexity and solution accuracy during the optimization process, thereby improving the efficiency and quality of integrated circuit layout and ultimately obtaining a more optimized chip layout.

[0128] It can be seen from the above embodiments that the present application is due to the fact that the current multi-core layout optimization is mainly to optimize a single target, only considering the minimization of system area or only considering the minimization of transmission delay, which may cause some adverse effects, thereby greatly reducing the performance of the multi-core system. Therefore, the present application proposes a multi-core layout optimization method based on a multi-objective optimization algorithm, firstly obtaining the Pareto frontier of each objective optimization function through the NSWOA algorithm, then using the MHA algorithm to determine the compromise solution to determine the position of the core, and finally adjusting the placement orientation to obtain the optimal multi-core layout solution. Compared with the single-target layout optimization, the present invention takes into account the four most critical targets in the multi-core system at the same time, thereby significantly improving the performance and integration of the multi-core system in the 2.5D package; the method of the present invention has strong adaptability and can be flexibly adjusted for 2.5D packages of different types and sizes.

[0129] Corresponding to the aforementioned embodiment of the multi-chip layout optimization method based on the multi-objective optimization algorithm, the present application also provides an embodiment of a multi-chip layout optimization device based on the multi-objective optimization algorithm.

[0130] Figure 2 FIG. 1 is a block diagram of a multi-chip layout optimization device based on a multi-objective optimization algorithm according to an exemplary embodiment. Figure 2 , the device comprises:

[0131] Construction module 1 is used to construct the target optimization functions and constraints for chip temperature, inter-chip transmission delay, total area and inter-chip communication power consumption respectively;

[0132] Solving module 2, configured to iteratively solve the objective optimization function using the NSWOA algorithm based on the constraint conditions, and obtain the Pareto frontier of each objective optimization function;

[0133] A determination module 3 is configured to determine a compromise solution based on the Pareto front using an MHA algorithm;

[0134] The optimization module 4 is used to determine the placement position of the chip according to the compromise solution, adjust the position according to the pin function and the connection requirements between functional modules, and obtain the result of minimizing the total wiring length based on the shortest total interconnection length, thereby obtaining the optimal layout of multiple chiplets.

[0135] Regarding the apparatus in the above embodiment, the specific manner in which each module performs operations has been described in detail in the embodiment of the method, and will not be elaborated here.

[0136] For the device embodiments, since they basically correspond to the method embodiments, the relevant parts can be referred to the partial description of the method embodiments. The device embodiments described above are merely schematic, wherein the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the present application scheme. A person of ordinary skill in the art can understand and implement it without paying any creative work.

[0137] Accordingly, the present application also provides an electronic device, comprising: one or more processors; a memory for storing one or more programs; when the one or more programs are executed by the one or more processors, the one or more processors implement the multi-core layout optimization method based on the multi-objective optimization algorithm as described above.

[0138] Accordingly, the present application also provides a computer-readable storage medium having computer instructions stored thereon, which, when executed by a processor, implement the multi-chip layout optimization method based on the multi-objective optimization algorithm as described above.

[0139] Those skilled in the art will readily conceive of other embodiments of the present application after considering the specification and practicing the contents disclosed herein. This application is intended to cover any variations, uses, or adaptations of the present application that follow the general principles of this application and include common knowledge or customary techniques in the art that are not disclosed in this application.

[0140] It will be understood that the present application is not limited to the exact construction that has been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof.

Claims

1. A multi-chip layout optimization method based on a multi-objective optimization algorithm, characterized in that: include: Construct the target optimization functions and constraints for chiplet temperature, inter-chiplet transmission delay, total area, and inter-chiplet communication power consumption respectively; Based on the constraints, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of each objective optimization function; Based on the Pareto front, a compromise solution is determined using the MHA algorithm; Determine the placement of the chiplets based on the compromise solution, adjust the orientation based on the pin functions and the connection requirements between functional modules, and obtain the minimum total wiring length based on the shortest total interconnect length, thereby obtaining the optimal layout of the multiple chiplets; Wherein, based on the Pareto front, the MHA algorithm is used to determine the compromise solution, including: For the objective function, each Pareto optimal solution has a corresponding set of values. Suppose there are m sets of solutions on the Pareto frontier, and we get a matrix M, where each row corresponds to a solution. By combining the matrix M with three different weight matrices W Q 、W K and W V Multiply to calculate the Query, Key, and Value of each solution; By calculating the dot product of the query of each solution and the key of all solutions, and then normalizing it through the softmax function, the attention weight of each solution to other solutions is obtained; Select the solution with the highest attention weight as the compromise solution; Based on the predicted compromise solution and the actual compromise solution, calculate the loss function, backpropagate, and update the Query, Key, and Value.

2. The method according to claim 1, characterized in that The objective function of the core particle temperature is expressed as: ； ； in, is the core particle temperature; } represents the lower left corner coordinate and upper right corner coordinate of core particle n; n is the number of core particles; is the ambient temperature; is the power consumption of the ith chip; is the thermal resistance; is the effective area of ​​the ith core particle; is the heat transfer coefficient between the i-th and j-th core particles; is the temperature of the jth core particle; is the distance between the i-th and j-th core particles, expressed as ; The constraints are expressed as: ； Where T max is the maximum temperature threshold.

3. The method according to claim 1, characterized in that The objective function of the inter-core transmission delay is expressed as: ； ； in, f D Inter-core transmission delay; Indicates the lower left corner coordinate and upper right corner coordinate of core particle n; n is the number of core particles; is the transmission rate between the i-th and j-th core particles; is the distance between the i-th and j-th core particles, expressed as ; The constraints are expressed as: ； Among them D max is the maximum threshold for transmission delay.

4. The method according to claim 1, wherein The objective function of the total area is expressed as: ； ； Where, f A is the total area; Indicates the lower left corner coordinate and upper right corner coordinate of core particle n; n is the number of core particles; The constraints are expressed as: ； in is the maximum threshold of the total chip area.

5. The method according to claim 1, wherein The objective function of the inter-chiplet communication power consumption is expressed as: ； ； in, f P is the power consumption of inter-chiplet communication; Indicates the lower left corner coordinate and upper right corner coordinate of core particle n; n is the number of core particles; is the communication frequency between the i-th and j-th core particles; is the distance between the i-th and j-th core particles, expressed as ; The constraints are expressed as: ； Among them, P max is the maximum threshold of communication power consumption.

6. The method according to claim 1, wherein Based on the constraints, the objective optimization function is iteratively solved using the NSWOA algorithm to obtain the Pareto frontier of the multi-objective optimization function, including: S21: Read the parameters of the chip: the position of the chip, the ambient temperature, the power consumption of the chip, the thermal resistance; the effective area of ​​the chip, the thermal conductivity between the chips, the temperature of the chips, the distance between the chips, the transmission rate between the chips, and the communication frequency between the chips; S22: Initialize the NSWOA algorithm parameters, select the initial population, and initialize according to the constraints; S23: Update the current optimal solution through the shrinking and encircling mechanism, spiral mechanism, and search and foraging mechanism of the NSWOA algorithm. In each iteration, each objective optimization function needs to be calculated to evaluate the fitness and identify the current optimal solution. S24: Repeat the above S21-S23 until the maximum number of iterations is reached, and the Pareto frontiers of the four objectives are obtained.

7. The method according to claim 1, characterized in that The placement of the chiplets is determined based on the compromise solution. The orientation is adjusted according to the pin functions and the connection requirements between functional modules. The total wiring length is minimized based on the shortest total interconnect length, thereby obtaining the optimal layout of multiple chiplets, including: The connection length is calculated by summing the distances of all pin locations between each pair of die: Where N is the number of core particles, Pi and Pj are the pin positions of core particles i and j respectively, and ‖p1-p2‖ is the Euclidean distance between two pins; Initialization: Randomly select the placement orientation of each core particle, the placement orientation of the core particle is: 0°, 90°, 180°, 270°; Iterative optimization: In each iteration, a core particle is randomly selected and its placement is changed. The pin position of the core particle is updated, and the new connection length is calculated. The condition for accepting a new solution is: if the new connection length is less than the current length, the new solution is accepted; otherwise, it remains unchanged. The solution after iterating to the set maximum number of iterations is taken as the final solution. In this way, the optimal position of each core particle is obtained, and the final optimal layout is obtained.

8. A multi-chip layout optimization device based on a multi-objective optimization algorithm, characterized in that: include: A construction module is used to construct the target optimization functions and constraints for chip temperature, inter-chip transmission delay, total area, and inter-chip communication power consumption respectively; A solving module, configured to iteratively solve the objective optimization function using the NSWOA algorithm based on the constraint conditions, and obtain the Pareto frontier of each objective optimization function; A determination module, configured to determine a compromise solution based on the Pareto front using an MHA algorithm; An optimization module is used to determine the placement of the chiplets according to the compromise solution, adjust the positions according to the pin functions and the connection requirements between functional modules, and obtain the result of minimizing the total wiring length based on the shortest total interconnection length, thereby obtaining the optimal layout of multiple chiplets; Wherein, based on the Pareto front, the MHA algorithm is used to determine the compromise solution, including: For the objective function, each Pareto optimal solution has a corresponding set of values. Suppose there are m sets of solutions on the Pareto frontier, and we get a matrix M, where each row corresponds to a solution. By combining the matrix M with three different weight matrices W Q 、W K and W V Multiply to calculate the Query, Key, and Value of each solution; By calculating the dot product of the query of each solution and the key of all solutions, and then normalizing it through the softmax function, the attention weight of each solution to other solutions is obtained; Select the solution with the highest attention weight as the compromise solution; Based on the predicted compromise solution and the actual compromise solution, calculate the loss function, backpropagate, and update the Query, Key, and Value.

9. An electronic device, characterized in that: include: one or more processors; a memory for storing one or more programs; When the one or more programs are executed by the one or more processors, the one or more processors implement the method according to any one of claims 1 to 7.

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