Driving circuit of display panel

Abstract

The invention provides a driving circuit of a display panel, which comprises a current generating circuit and a current control circuit, the current generating circuit generates at least one current to drive a light emitting diode, and the current control circuit controls the current generating circuit to generate the current and controls the current generating circuit to generate a smaller current in an initial stage. And after the initial stage, the current generating circuit is controlled to generate relatively large current. Besides, the current control circuit controls the current generation circuit to generate current in a plurality of cycles, each cycle has an initial stage, the current control circuit controls the current generation circuit to generate current in the initial stage of one of every N cycles of the plurality of cycles, and N is greater than or equal to 2.

Description

Technical Field

[0001] The present invention relates to a driving circuit, and in particular to a driving circuit of a display panel. Background Art

[0002] Display devices have become essential equipment for electronic products to display information. Display devices have evolved from liquid crystal display devices to light-emitting diode display devices, such as sub-millimeter light-emitting diode (Mini LED) display devices and micro light-emitting diode (Micro LED) display devices. As a display element, light-emitting diodes can improve the display quality of display devices. The brightness of the light generated by existing light-emitting diode display devices cannot be close to the Gamma curve, that is, the brightness of the grayscale displayed by existing light-emitting diode display devices cannot be close to the Gamma curve, such as the Gamma2.2 curve, especially the brightness of low grayscale, which limits the display quality of light-emitting diode display devices.

[0003] In view of the above problems in the prior art, the present invention provides a driving circuit for a display panel, which drives a light emitting diode to generate light, and the brightness of the light can be close to the Gamma curve, so as to improve the display quality of the light emitting diode display device. Summary of the invention

[0004] An object of the present invention is to provide a driving circuit for a display panel, which drives a light emitting diode to generate light with low power in an initial driving stage, so that the brightness of the light corresponding to the low gray scale can be close to the Gamma curve, thereby improving the display quality of the light emitting diode display device.

[0005] The present invention provides a driving circuit of a display panel, which includes a current generating circuit and a current control circuit. The current generating circuit generates a first current and a second current, and the first current is smaller than the second current. The current control circuit controls the current generating circuit to generate the first current and the second current according to a clock signal. The current control circuit controls the current generating circuit to generate the first current in an initial stage according to the clock signal, and controls the current generating circuit to generate the first current and the second current after the initial stage.

[0006] The present invention further provides a driving circuit for a display panel, which includes a current generating circuit and a current control circuit. The current generating circuit generates at least one current, and the current control circuit controls the current generating circuit to generate current in multiple cycles according to a clock signal, each cycle having an initial stage, and the current control circuit controls the current generating circuit to generate current in the initial stage of one cycle in every N cycles of the multiple cycles, where N is greater than or equal to 2.

[0007] The present invention further provides a driving circuit for a display panel, which includes a current generating circuit and a current control circuit. The current generating circuit generates at least one current, and the current control circuit controls the current generating circuit to generate current in multiple cycles according to a clock signal, each cycle has multiple sub-cycles, each sub-cycle has an initial stage, and the current control circuit controls the current generating circuit to generate current in the initial stage of one of the multiple sub-cycles. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1 is a schematic diagram of an embodiment of the driving architecture of the present invention;

[0009] Figure 2 is a block diagram of an embodiment of a controller and a driver of the present invention;

[0010] Figure 3 is a block diagram of an embodiment of a driving circuit of the present invention;

[0011] Figure 4 is a timing diagram of an embodiment of a driving circuit of the present invention;

[0012] Figure 5 It is the Gamma2.2 grayscale curve;

[0013] Fig. 6A is a timing diagram of an embodiment of a driving circuit of the present invention;

[0014] Figure 6B is a timing diagram of an embodiment of a driving circuit of the present invention;

[0015] Fig. 7A is a timing diagram of an embodiment of a driving circuit of the present invention;

[0016] Figure 7B is a timing diagram of an embodiment of a driving circuit of the present invention;

[0017] Figure 8 is a block diagram of an embodiment of a controller and a driver of the present invention;

[0018] Fig. 9 is a timing diagram of an embodiment of a driving circuit of the present invention;

[0019] Fig.10 is a block diagram of an embodiment of a controller and a driver of the present invention;

[0020] Fig.11 is a timing diagram of an embodiment of a driving circuit of the present invention; and

[0021] Fig.12 FIG. 4 is a timing diagram of a driving circuit according to an embodiment of the present invention.

[0022] Description of Figure Numbers:

[0023] 10 Display Panel

[0024] 2 Drivers

[0025] 4 Display components

[0026] 11 Input Interface

[0027] 13. Enabling circuit

[0028] 15 Buffer

[0029] 17 Data conversion circuit

[0030] 18 Register

[0031] 19 Adjustment circuit

[0032] 26 Enable circuit

[0033] 27 Storage Circuit

[0034] 29 Driving Circuit

[0035] 90 Current Control Circuit

[0036] 91 Comparison Circuit

[0037] 93 Judgment Circuit

[0038] 94 Cycle Counter

[0039] 96 Clock Counter

[0040] 95 Level conversion circuit

[0041] 99 Current generating circuit DETAILED DESCRIPTION

[0042] In order to have a further understanding and recognition of the features and effects of the present invention, preferred embodiments and detailed descriptions are provided as follows:

[0043] Certain words are used in the specification and claims to refer to specific components. However, those skilled in the art of the present invention should understand that manufacturers may use different terms to refer to the same component. Moreover, the specification and claims do not use the difference in name as a way to distinguish components, but use the overall technical difference of the components as the criterion for distinction. The term "including" mentioned throughout the specification and claims is an open term and should be interpreted as "including but not limited to". Furthermore, the term "coupled" includes any direct and indirect connection means. Therefore, if the text describes a first device coupled to a second device, it means that the first device can be directly connected to the second device, or can be indirectly connected to the second device through other devices or other connection means.

[0044] See also Figure 1 and Figure 2 , Figure 1 is a schematic diagram of an embodiment of the driving architecture of the present invention; Figure 2 FIG. 1 is a block diagram of an embodiment of a controller and a driver of the present invention. Figure 1 , Figure 2 As shown, the driving architecture includes a controller 1 and a plurality of drivers 2 to drive the sub-pixels of a plurality of pixels of the display panel 10 to display images. The plurality of drivers 2 are arranged in a plurality of rows, and each driver 2 is coupled to a plurality of display elements 4 to drive the plurality of display elements 4 to emit light, and the display elements 4 are sub-pixels. In one embodiment of the present invention, the display elements 4 may be sub-millimeter light emitting diodes, micro light emitting diodes, or light emitting diodes.

[0045] The controller 1 is coupled to the plurality of drivers 2, and transmits an input data Din, a timing signal DCK, a clock signal PWMCLK and an enable signal EN to the driver 2. In one embodiment of the present invention, the plurality of drivers 22 are all coupled to a bus, the controller 1 transmits the input data Din to the bus, and the plurality of drivers 2 receive the input data Din via the bus. The input data Din may be a serial data and include a plurality of pixel data. The plurality of drivers 2 receive the input data Din at different times, so that the pixel data received by each of the plurality of drivers 2 is different. For example, when one driver 2 receives the input data Din, the other drivers 2 do not receive the input data Din, and after the driver 2 receives one pixel data of the input data Din, it drives another driver 2 to receive the input data Din, so as to receive another pixel data of the input data Din. Since the two drivers 2 receive the input data Din at different times, the pixel data of the input data Din received by the two drivers 2 are different, so as to drive the plurality of display elements 14 of the display panel 10 to generate light of different brightness. In one embodiment of the present invention, the controller 1 may be an independent chip. Since the plurality of drivers 2 are arranged in multiple rows, the pixels arranged in rows and columns on the display panel 10 can be controlled.

[0046] See also Figure 2 , the controller 1 includes an input interface 11, an enable circuit 13, a buffer 15, a timing controller 16, a data conversion circuit 17, a register 18 and an adjustment circuit 19. The controller 1 is coupled to a host, such as a microprocessor of an electronic product, to receive input data Din, signals, control commands or related control parameters. The input interface 11 receives input data Din, signals, control commands or control parameters. The enable circuit 13 is coupled to the input interface 11, and enables the input interface 11 according to a received enable signal, driving the input interface 11 to receive input data Din, signals, control commands or control parameters.

[0047] The buffer 15 is coupled to the input interface 11 and the data conversion circuit 17. The input interface 11 transmits input data Din to the buffer 15. The buffer 15 buffers the input data Din and transmits the buffered input data Din to the data conversion circuit 17 to convert the input data Din, for example, converting 6-bit data into 10-bit data or converting 8-bit data into 12-bit data. The data conversion circuit 17 transmits the converted input data Din to the driver 2 via the bus. In one embodiment of the present invention, the data conversion circuit 17 can be incorporated into the timing controller 16. The register 18 is coupled to the input interface 11, the timing controller 16 and the adjustment circuit 19. The input interface 11 transmits control parameters to the register 18. The register 18 stores the control parameters and provides the control parameters to the timing controller 16 and the adjustment circuit 19. The timing controller 16 generates an enable signal EN and a timing signal DCK and transmits them to the driver 2. The adjustment circuit 19 generates an adjustment signal to the driver 2 according to the control parameters so as to adjust the strength of multiple driving signals generated by the driver 2. In an embodiment of the present invention, the adjustment signal may be a voltage, and the intensity of the driving signal is adjusted by changing the intensity of the voltage.

[0048] See also Figure 2 , each driver 2 includes an enable circuit 26, a storage circuit 27 and a drive circuit 29. The enable circuit 26 receives an enable signal EN, and enables the storage circuit 27 to receive input data Din according to the timing signal DCK according to the enable signal EN. The drive circuit 29 couples the storage circuit 27 and the display element 4, and generates a plurality of drive signals according to the clock signal PWMCLK and the input data Din received by the storage circuit 27 to drive the display element 4 to generate light so as to display an image. When the first driver 2 drives the display element 4, the enable circuit 26 of the first driver 2 will disable the storage circuit 27 of the first driver 2, and send an enable signal EN to the enable circuit 26 of the second driver 2 to perform the above-mentioned action, and drive the display element 4 coupled to the second driver 2, and so on.

[0049] See also Figure 3 , Figure 3 FIG. 1 is a block diagram of an embodiment of a driving circuit of the present invention. Figure 3As shown, the storage circuit 27 is coupled to the enable circuit 26 and receives the input data Din and the timing signal DCK. The enable circuit 26 enables the storage circuit 27 according to the received enable signal, drives the storage circuit 27 to receive the input data Din according to the timing signal DCK, and stores the input data Din. The driving circuit 29 includes a current control circuit 90, a clock counter 96, and a current generating circuit 99. One end of the display element 4 is coupled to a supply voltage VDD, and the other end thereof is coupled to the current generating circuit 99. The current generating circuit 99 generates a current as a driving signal to drive the display element 4. The current generating circuit 99 includes a plurality of switches M and a plurality of current sources I. One end of each switch M is respectively coupled to the other end of each display element 14, and each current source I is coupled between the other end of each switch M and a ground terminal. The current source I can be controlled by a reference voltage V to adjust the intensity of the current generated by the current source I. In one embodiment of the present invention, the adjustment signal generated by the adjustment circuit 19 can be the reference voltage V.

[0050] See also Figure 3 The current control circuit 90 includes a plurality of comparison circuits 91 and a plurality of level conversion circuits 95. The plurality of comparison circuits 91 are coupled to the storage circuit 27 and the clock counter 96. The clock counter 96 receives the clock signal PWMCLK, counts the clock signal PWMCLK and outputs a count signal, which is a count value. The count signal changes with the count of the clock counter 96. In one embodiment of the present invention, a clock generation circuit may be further included, which generates the clock signal PWMCLK, and the frequency of the clock signal PWMCLK can be changed. Each comparison circuit 91 receives the count signal and the pixel data of the input data Din stored in the storage circuit 27, and compares the count signal with the pixel data. When the pixel data is greater than the count signal, the comparison circuit 91 outputs a control signal with a driving level, such as a high level. In another embodiment of the present invention, when the pixel data is less than the count signal, the comparison circuit 91 outputs a control signal with a driving level. The level conversion circuit 95 is coupled to the comparison circuit 91, and converts the level of the control signal output by the comparison circuit 91. In one embodiment of the present invention, the level conversion circuit 95 may not be required. As described above, the comparison circuit 91 is coupled to the current generating circuit 99 to control the current generating circuit 99 .

[0051] The control signal generated by the comparison circuit 91 is used to control the switch M of the current generating circuit 99 to generate current, and the current flows through the display element 4 to generate light. As can be seen from the above description, the time when the comparison circuit 91 continues to generate the driving level of the control signal is the driving time, which is also the conduction time, that is, the time of driving the display element 4, which determines the brightness of the display element 4. The brightness is determined by the conduction time and the intensity of the current. This embodiment uses a common anode structure to drive the display element 4, but the present invention is not limited to this. The display element 4 can also be driven using a common cathode structure. The detailed description is as follows. The clock counter 96 counts based on a fixed number, such as 4096. The clock counter 96 counts the clock signal PWMCLK every time it reaches 4096, and then re-counts, which is a cycle, indicating that the maximum value of the count signal is 4096, and 4096 is equivalent to 12-bit data. The comparison circuit 91 compares the count signal with the pixel data to generate a control signal with a high level (driving level). To give an example, if the pixel data is 1900, when the value of the counting signal is not greater than 1900, the comparison circuit 91 generates a control signal with a driving level to control the current generating circuit 99 to generate current; when the value of the counting signal is greater than 1900, the comparison circuit 91 generates a control signal with a low level until the value of the counting signal is equal to 4096, which is one cycle.

[0052] See also Figure 4 , Figure 4 FIG. 4 is a timing diagram of a driving circuit according to an embodiment of the present invention. Figure 4 The timing diagram represents the driving circuit driving the same pixel during four frames. In this embodiment, there are 10 cycles in one frame period, that is, the clock counter 96 counts 10 times 4096, which also means that the storage circuit 27 updates the pixel data once every 10 cycles. This embodiment uses a 12-bit clock signal PWMCLK to drive the display element 4 to display 8-bit grayscale (256 grayscales) as an example for explanation. The first pixel data of the input data Din is 00F. For the sake of convenience, it is assumed that the brightness of the light generated by the display element 4 is the 15th grayscale. The control signal SW of the current control circuit 90 will control the current generating circuit 99 to generate current during the period from the 1st clock to the 15th clock of each cycle. It means that the current control circuit 90 controls the current generating circuit to generate current according to the clock signal PWMCLK in the said period.

[0053] See also Figure 5 , Figure 5 is the Gamma2.2 grayscale curve. Figure 5As shown, the brightness of the low grayscale of the Gamma2.2 curve is quite concentrated and close, such as grayscale 1 to grayscale 20. The present invention further discloses other driving circuits to drive the brightness of the light generated by the display element to be more consistent with the Gamma2.2 curve. The driving circuit of the present invention drives the light-emitting diode to generate light with low electric energy in the initial stage of the cycle, so that the brightness of the light in the initial stage will be reduced, so that the brightness of the light corresponding to the low grayscale can be consistent with the Gamma2.2 curve. The initial stage refers to the clock signal PWMCLK corresponding to the first few clocks of the cycle, for example, the period from the first clock to the ninth clock is the initial stage, and the initial stage can be defined according to demand. It can be seen that each cycle has an initial stage.

[0054] See also Fig. 6A , Fig. 6A FIG. 1 is a timing diagram of an embodiment of the driving circuit of the present invention. Figure 4 The difference in implementation is that the current control circuit 90 controls the current generating circuit 99 to generate current in the initial stage of one of the four cycles Cycle. In this embodiment, the initial stage is the first to ninth pulses of the cycle corresponding to the clock signal PWMCLK. The first pixel data of the input data Din is 00F. The control signal SW of the current control circuit 90 controls the current generating circuit 99 to generate current in the initial stage of the first cycle and during the 10th to 15th pulses. The control signal SW does not control the current generating circuit 99 to generate current in the initial stage of the second to fourth cycles (the first to ninth pulses), and only controls the current generating circuit 99 to generate current during the 10th to 15th pulses. The control method of the current control circuit 90 in the fifth cycle is the same as that in the first cycle. From the above, it can be seen that the current control circuit 90 can control the current generating circuit 99 to generate the current in the initial stage of one cycle in every N cycles of the cycle. It is not limited to providing current in the initial stage of a specific cycle in every N cycles, as long as one in every N cycles is sufficient, N is greater than or equal to 2, and N can be set according to demand.

[0055] See also Figure 6B , Figure 6B FIG. 1 is a timing diagram of an embodiment of the driving circuit of the present invention. Fig. 6AThe difference in implementation is that the first pixel data of the input data Din is 004. For the sake of explanation, it is assumed that this indicates that the brightness of the light generated by the display element 4 is the 4th gray level. The control signal SW of the current control circuit 90 controls the current generating circuit 99 to generate current during the period from the 1st clock to the 4th clock in the initial stage of the first cycle, and the control signal SW does not control the current generating circuit 99 to generate current during the initial stage (the 1st clock to the 9th clock) of the second cycle to the 4th cycle. The control method of the current control circuit 90 in the fifth cycle is the same as that in the first cycle.

[0056] See also Figure 3 The driving circuit 29 further includes a cycle counter 94, which is coupled to the clock counter 96 and receives a counting signal to count the number of cycles. For example, if the count value of the counting signal is 4096, one cycle is counted. The cycle counter 94 drives the comparison circuit 91 of the current control circuit 90 to output a control signal at the initial stage of one cycle in every N cycles to control the current generating circuit 99 to generate current, for example Fig. 6A and Figure 6B The first cycle and the fifth cycle of the embodiment output a control signal to control the current generating circuit 99 to generate current. The cycle counter 94 will count again when it counts to a predetermined number of cycles, for example, 4 cycles. Each time it counts to the second to fourth cycles, the control comparison circuit does not output a control signal in the initial stage. As mentioned above, the comparison circuit 91 compares the count value with the pixel data to determine the driving time of the cycle. The driving time includes a first driving time and a second driving time. The first driving time is the time in the initial stage, that is, the time when the current control circuit 90 controls the current generating circuit 99 to generate current in the initial stage, and the second driving time is the time when the current control circuit 90 controls the current generating circuit 99 to generate current outside the initial stage.

[0057] See also Fig. 7A , Fig. 7A FIG. 1 is a timing diagram of an embodiment of the driving circuit of the present invention. Figure 4 The difference in implementation is that each cycle Cycle includes four sub-cycles, and each sub-cycle also corresponds to a fixed number of pulses of the clock signal PWMCLK, for example, 4096 pulses. The frequency of the clock signal PWMCLK in this embodiment is Fig. 6AThe 4 times of the frequency of the clock signal PWMCLK of the embodiment is equivalent to dividing one cycle into 4 equal parts. The current control circuit 90 controls the current generating circuit 99 to generate current in the initial stage of one of the four sub-cycles. In this embodiment, the initial stage is the first to ninth pulses of the sub-cycle corresponding to the clock signal PWMCLK. The first pixel data of the input data Din is 004. The control signal SW controls the current generating circuit 99 to generate current during the first to fourth pulses of the initial stage of the first sub-cycle of each cycle Cycle. The control signal SW does not control the current generating circuit 99 to generate current in the initial stages of the second to fourth sub-cycles.

[0058] See also Figure 7B , Figure 7B 1 is a timing diagram of an embodiment of the driving circuit of the present invention. The second pixel data of the input data Din is 00F. The control signal SW controls the current generating circuit 99 to generate current during the period from the 1st clock to the 9th clock and the period from the 10th clock to the 15th clock in the initial stage of the first sub-cycle of each cycle Cycle. The control signal SW does not control the current generating circuit 99 to generate current during the initial stage from the second sub-cycle to the fourth sub-cycle, and only controls the current generating circuit 99 to generate current during the period from the 10th clock to the 15th clock. As can be seen from the above, the current control circuit 90 can control the current generating circuit 99 to generate current in the initial stage of one of the multiple sub-cycles, and is not limited to providing current in the initial stage of a specific sub-cycle, as long as one of the multiple sub-cycles is sufficient.

[0059] See also Figure 4 The comparison circuit 91 compares the count value with the pixel data to determine the driving time of the sub-cycle. The driving time includes a first driving time and a second driving time. The first driving time is the time in the initial stage, that is, the time when the current control circuit 90 controls the current generating circuit 99 to generate current in the initial stage. The second driving time is the time when the current control circuit 90 controls the current generating circuit 99 to generate current outside the initial stage. The cycle counter 94 receives the counting signal to count the number of sub-cycles. For example, when the count value of the counting signal received is 4096, 1 ​​sub-cycle is counted. The cycle counter 94 drives the comparison circuit 91 of the current control circuit 90 to output a control signal in the initial stage of one of the multiple sub-cycles of the cycle to control the current generating circuit 99 to generate current, for example Fig. 7A and Figure 7B The first sub-cycle of the embodiment. The cycle counter 94 will restart counting when it counts to a predetermined number of sub-cycles, for example, 4 sub-cycles. Each time it counts to the second to fourth sub-cycles, the control comparison circuit 91 does not output a control signal in the initial stage.

[0060] See also Figure 8 , Figure 8 It is a block diagram of an embodiment of the controller and driver of the present invention. The current generating circuit 99 of this embodiment includes a plurality of first current circuits and a plurality of second current circuits, each of the first current circuits includes a switch M11 and a current source I, each of the second current circuits includes a switch M12 and a current source nI, the current source I is smaller than the current source nI, the first current circuit generates a first current, the second current circuit generates a second current, and the first current is smaller than the second current. The comparison circuit 91 of the current control circuit 90 compares the count value with the pixel data to determine the driving time of the cycle, the driving time includes a first driving time and a second driving time, the first driving time is at the initial stage of the cycle, and the comparison circuit 91 outputs a first control signal in the first driving time to control the first current circuit of the current generating circuit 99 to generate the first current, and outputs a first control signal and a second control signal in the second driving time to control the first current circuit and the second current circuit of the current generating circuit 99 to generate the first current and the second current. As can be seen from the above, the current control circuit 90 controls the current generating circuit 99 to generate the first current and the second current according to the clock signal PWMCLK. The current control circuit 90 further includes a judgment circuit 93. The judgment circuit 93 is coupled to the clock counter 96 and the comparison circuit 91, and drives the comparison circuit 91 to control the current generating circuit 99 to generate the first current and the second current according to the count value of the clock signal PWMCLK. When the judgment circuit 93 judges that the count value reaches a predetermined value, such as 9, it can be known that the initial stage has passed, that is, the control comparison circuit can output the second control signal.

[0061] See also Fig. 9 , Fig. 9 FIG. 1 is a timing diagram of an embodiment of the driving circuit of the present invention. Figure 4 The difference in implementation is that the current control circuit 90 only outputs the control signal SW1 to the current generating circuit 99 to generate the first current in the initial stage of each cycle, and outputs the first control signal SW1 and the second control signal SW2 to the current generating circuit 99 to generate the first current and the second current after the initial stage. That is, the display element is driven in a low power mode in the initial stage of each cycle.

[0062] See also Fig.10 , Fig.10 FIG. 1 is a block diagram of an embodiment of a controller and a driver of the present invention. Fig.10 As shown, this embodiment is combined with Figure 3 and Figure 8 Example. Fig.11As shown, the current control circuit 90 controls the current generating circuit 99 to generate the first current in the initial stage of one cycle of every two cycles, and does not control the current generating circuit 99 to generate the first current in the other cycle. After the initial stage, the current control circuit 90 controls the current generating circuit 99 to generate the first current and the second current. Fig.12 As shown, each cycle Cycle includes two sub-cycles, and the current control circuit 90 controls the current generating circuit 99 to generate the first current in the initial stage of one of the two sub-cycles, and controls the current generating circuit 99 to generate the first current and the second current after the initial stage of each sub-cycle.

[0063] However, what is described above is only a preferred embodiment of the present invention and is not intended to limit the scope of implementation of the present invention. All equivalent changes and modifications based on the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A driving circuit for a display panel, characterized in that: Include: a current generating circuit, generating a first current and a second current, wherein the first current is smaller than the second current; and A current control circuit controls the current generating circuit to generate the first current and the second current according to a clock signal; The current control circuit controls the current generating circuit to generate the first current in an initial stage according to the clock signal, and controls the current generating circuit to generate the first current and the second current after the initial stage.

2. The driving circuit according to claim 1, characterized in that: The current control circuit controls the current generating circuit in a cycle according to the clock signal, and the cycle has the initial stage. The current control circuit controls the current generating circuit to generate the first current in the initial stage of the cycle, and controls the current generating circuit to generate the first current and the second current after the initial stage.

3. The driving circuit according to claim 2, characterized in that: The current control circuit determines a first driving time and a second driving time of the cycle according to a pixel data, the first driving time is located in the initial stage of the cycle, the current control circuit controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

4. The driving circuit according to claim 3, characterized in that: The current control circuit comprises: A comparison circuit is coupled to the current generating circuit, compares a count value of the clock signal with the pixel data to determine the first driving time and the second driving time, and controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

5. The driving circuit according to claim 4, characterized in that: The current control circuit comprises: A judgment circuit is coupled to the comparison circuit, and drives the comparison circuit to control the current generation circuit to generate the first current and the second current according to a count value of the clock signal.

6. The driving circuit according to claim 4, characterized in that: Also includes: A clock counter is coupled to the comparison circuit, and counts a plurality of clocks of the clock signal to generate the count value.

7. The driving circuit according to claim 1, characterized in that: The current generating circuit further comprises: a first current circuit, generating the first current; and A second current circuit generates the second current.

8. A driving circuit for a display panel, characterized in that: Include: a current generating circuit, generating at least one current; and A current control circuit controls the current generating circuit to generate the current in multiple cycles according to a clock signal, each of the cycles has an initial stage, and the current control circuit controls the current generating circuit to generate the current in the initial stage of one cycle in every N cycles of the multiple cycles, where N is greater than or equal to 2.

9. The driving circuit according to claim 8, characterized in that: The current control circuit determines a first driving time and a second driving time of each cycle according to a pixel data, the first driving time is in the initial stage, the current control circuit controls the current generating circuit to generate the current during the first driving time, and controls the current generating circuit to generate the current during the second driving time.

10. The driving circuit according to claim 9, characterized in that: The current control circuit comprises: A comparison circuit is coupled to the current generating circuit, compares a count value of the clock signal with the pixel data to determine the first driving time and the second driving time, and controls the current generating circuit to generate the current during the first driving time and controls the current generating circuit to generate the current during the second driving time.

11. The driving circuit according to claim 10, characterized in that: Also includes: A clock counter is coupled to the comparison circuit, and counts a plurality of clocks of the clock signal to generate the count value.

12. The driving circuit according to claim 8, characterized in that: Also includes: A cycle counter counts the multiple cycles and drives the current control circuit to control the current generating circuit to generate the current in the initial stage of one cycle in every N cycles of the multiple cycles.

13. The driving circuit according to claim 8, characterized in that: The at least one current includes a first current and a second current, the first current is smaller than the second current, the current control circuit controls the current generating circuit to generate the first current in the initial stage of one cycle in every N cycles, and controls the current generating circuit to generate the first current and the second current after the initial stage of each cycle.

14. The driving circuit according to claim 13, characterized in that: The current control circuit determines a first driving time and a second driving time according to a pixel data, the first driving time is in the initial stage, the current control circuit controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

15. The driving circuit according to claim 14, characterized in that: The current control circuit comprises: A comparison circuit is coupled to the current generating circuit, compares a count value of the clock signal with the pixel data to determine the first driving time and the second driving time, and controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

16. The driving circuit according to claim 15, characterized in that: The current control circuit comprises: A judgment circuit is coupled to the comparison circuit, and drives the comparison circuit to control the current generation circuit to generate the first current and the second current according to a count value of the clock signal.

17. A driving circuit for a display panel, characterized in that: Include: a current generating circuit, generating at least one current; and A current control circuit controls the current generating circuit to generate the current in multiple cycles according to a clock signal, each cycle has multiple sub-cycles, each sub-cycle has an initial stage, and the current control circuit controls the current generating circuit to generate the current in the initial stage of a sub-cycle of the multiple sub-cycles.

18. The driving circuit according to claim 17, characterized in that: The current control circuit determines a first driving time and a second driving time of each sub-cycle according to a pixel data, the first driving time is in the initial stage, the current control circuit controls the current generating circuit to generate the current during the first driving time, and controls the current generating circuit to generate the current during the second driving time.

19. The driving circuit according to claim 18, characterized in that: The current control circuit comprises: A comparison circuit is coupled to the current generating circuit, compares a count value of the clock signal with the pixel data to determine the first driving time and the second driving time, and controls the current generating circuit to generate the current during the first driving time and controls the current generating circuit to generate the current during the second driving time.

20. The driving circuit according to claim 19, characterized in that: Also includes: A clock counter is coupled to the comparison circuit, and counts a plurality of clocks of the clock signal to generate the count value.

21. The driving circuit according to claim 17, characterized in that: Also includes: A cycle counter counts the plurality of sub-cycles and drives the current control circuit to control the current generating circuit to generate the current at the initial stage of one of the plurality of sub-cycles.

22. The driving circuit according to claim 17, characterized in that: The at least one current includes a first current and a second current, the first current is smaller than the second current, the current control circuit controls the current generating circuit to generate the first current in the initial stage of a sub-cycle among the multiple sub-cycles, and controls the current generating circuit to generate the first current and the second current after the initial stage of each sub-cycle.

23. The driving circuit according to claim 22, characterized in that: The current control circuit determines a first driving time and a second driving time according to a pixel data, the first driving time is in the initial stage, the current control circuit controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

24. The driving circuit according to claim 23, characterized in that: The current control circuit comprises: A comparison circuit is coupled to the current generating circuit, compares a count value of the clock signal with the pixel data to determine the first driving time and the second driving time, and controls the current generating circuit to generate the first current during the first driving time, and controls the current generating circuit to generate the first current and the second current during the second driving time.

25. The driving circuit according to claim 24, characterized in that: The current control circuit comprises: A judgment circuit is coupled to the comparison circuit, and drives the comparison circuit to control the current generation circuit to generate the first current and the second current according to a count value of the clock signal.

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