Display panel, preparation method and display device

Abstract

The invention provides a display panel, a preparation method and a display device.The display panel comprises a substrate and at least one pixel circuit formed on the substrate, and each pixel circuit comprises a driving circuit, a light-emitting control circuit and a write-in and storage circuit, the orthographic projection of the first end of the write-in and storage circuit on the substrate is not overlapped with the orthographic projection of the control end of the drive circuit on the substrate. The write-in and storage circuit comprises the capacitor, and the first end of the write-in and storage circuit can also be understood that one end of the capacitor and the control end of the driving circuit are not overlapped on the substrate, so that stray capacitance is not easy to generate between the write-in and storage circuit and the driving circuit, and the grid voltage of the driving circuit is not easy to influence; the stable output of the driving circuit is ensured, so that the problem of flicker under a low-brightness and low-gray-scale picture is solved.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a preparation method thereof, and a display device. Background Art

[0002] In an organic light emitting diode (OLED) display product, a display panel generally includes a substrate and a plurality of pixels located on the substrate. Each pixel includes a pixel circuit and a light emitting element. The pixel circuit is coupled to the light emitting element and is used to drive the light emitting element to emit light, so that the display panel displays a picture. The pixel circuit generally includes: a control circuit and a drive circuit. The control circuit and the circuit are stacked on the substrate, and the control circuit includes a capacitor. The inventor of the present application found that since the control circuit includes a capacitor, the capacitor and the gate of the drive circuit have an overlapping area on the substrate, which will generate parasitic capacitance. The parasitic capacitance will affect the gate voltage of the drive circuit, which will cause flickering problems under low brightness and low grayscale pictures. Summary of the invention

[0003] In view of this, the purpose of the present application is to provide a display panel and a manufacturing method, and a display device to partially or completely solve the technical problems existing in the background technology.

[0004] Based on the above purpose, the present application provides a display panel, including a base substrate and at least one pixel circuit formed on the base substrate, wherein the pixel circuit includes a driving circuit, a light emitting control circuit, and a writing and storage circuit;

[0005] The driving circuit comprises a control end, a first end, and a second end, which are respectively connected to the first node, the second node, and the fourth node, and are used to control a driving current flowing through the first end of the driving circuit and the second end of the driving circuit for driving the light-emitting element to emit light;

[0006] The light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal;

[0007] A writing and storage circuit, comprising a first terminal and at least one second terminal, wherein the first terminal of the writing and storage circuit is connected to the control terminal of the driving circuit; and is used to write a data signal into the first terminal of the driving circuit under the control of a scanning signal, and store a voltage at the control terminal of the driving circuit;

[0008] The orthographic projection of the first end of the writing and storage circuit on the base substrate does not overlap with the orthographic projection of the control end of the driving circuit on the base substrate.

[0009] Optionally, there is a first distance between the orthographic projection of the first end of the writing and storage circuit on the substrate and the orthographic projection of the control end of the driving circuit on the substrate, and the first distance is greater than 0 μm.

[0010] Optionally, the light emitting control circuit includes:

[0011] The first light emitting control circuit is used to apply a first power supply voltage to the first end of the driving circuit under the control of a light emitting control signal.

[0012] Optionally, the writing and storage circuit includes: a first transistor, a first capacitor and a second capacitor, the control electrode of the first transistor is connected to the first scanning signal terminal, the first electrode of the first transistor is connected to the data signal input terminal, the second end of the first transistor is connected to the first node, the first electrode of the first capacitor is connected to the first node, the second electrode of the first capacitor is connected to the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to the first power supply voltage.

[0013] Optionally, the first light-emitting control circuit includes a second transistor, the control electrode of the second transistor is connected to the second scanning signal terminal for receiving a second scanning signal, the first electrode of the second transistor is connected to the first power supply voltage terminal for receiving the first power supply voltage, and the second electrode of the second transistor is electrically connected to the second node.

[0014] Optionally, the driving circuit includes a third transistor, the control electrode of the third transistor is electrically connected to the first node as the control end of the driving circuit, the first electrode of the third transistor is electrically connected to the second node as the third end of the driving circuit, and the second electrode of the third transistor is electrically connected to the third node as the second end of the driving circuit.

[0015] Optionally, an orthographic projection of a control electrode of the third transistor on the substrate does not overlap with an orthographic projection of a second electrode of the first transistor on the substrate.

[0016] Optionally, the light emitting control circuit includes:

[0017] A first light emitting control circuit, used for applying a first power supply voltage to a first end of the driving circuit under the control of a light emitting control signal;

[0018] The second light emitting control circuit is used to apply the driving current from the second end of the driving circuit to the first electrode of the light emitting element under the control of the light emitting control signal.

[0019] Optionally, the first light-emitting control circuit includes a first transistor, the control electrode of the first transistor is connected to the light-emitting control end and is used to receive the light-emitting control signal, the first electrode of the first transistor is connected to the first power supply voltage end and is used to receive the first power supply voltage, and the second electrode of the first transistor is electrically connected to the second node.

[0020] Optionally, the second light-emitting control circuit includes a sixth transistor, the control electrode of the sixth transistor is used to receive the light-emitting control signal, the first electrode of the sixth transistor is used to receive the driving current from the second end of the driving circuit, and the second electrode of the sixth transistor is electrically connected to the fourth node.

[0021] Optionally, the write and storage circuit includes: a second transistor and a storage capacitor, the control electrode of the second transistor is connected to the first write signal terminal, the first electrode of the second transistor is connected to the data signal input terminal, the second electrode of the second transistor is connected to the first terminal of the driving transistor, the first electrode of the storage capacitor is connected to the first power supply voltage, and the second electrode of the storage capacitor is connected to the first node.

[0022] Optionally, an orthographic projection of the control electrode of the third transistor on the substrate does not overlap with an orthographic projection of the second electrode of the second transistor on the substrate.

[0023] Optionally, the pixel circuit further comprises a first reset circuit, and the first reset circuit is used to apply a first reset voltage to the first electrode of the light-emitting element under the control of a first reset signal;

[0024] The first reset circuit includes a fourth transistor, a control electrode of the fourth transistor is connected to the first reset signal terminal for receiving a first reset signal, a first electrode of the fourth transistor is connected to the first reset voltage terminal for receiving a first reset voltage, and a second electrode of the fourth transistor is connected to a fourth node.

[0025] Optionally, the pixel circuit further comprises a first reset circuit, and the first reset circuit is used to apply a first reset voltage to the first electrode of the light-emitting element under the control of a first reset signal;

[0026] The first reset circuit includes a seventh transistor, a control electrode of the seventh transistor is connected to the first reset signal terminal for receiving a first reset signal, a first electrode of the seventh transistor is connected to the first reset voltage terminal for receiving a first reset voltage, and a second electrode of the seventh transistor is connected to a fourth node.

[0027] Optionally, the pixel circuit further includes a second reset circuit, configured to apply a second reset voltage to the control terminal of the drive circuit under the control of a second reset signal;

[0028] The second reset circuit includes a fifth transistor, a control electrode of the fifth transistor is connected to the second reset signal terminal, a first electrode of the fifth transistor is connected to the second reset voltage terminal, and a second electrode of the fifth transistor is connected to the control electrode of the driving transistor.

[0029] Optionally, the pixel circuit further includes a compensation circuit, and the compensation circuit is used to connect the control end of the driving circuit with the first end of the driving circuit under the control of a compensation signal;

[0030] The compensation circuit includes a fourth transistor, a control electrode of the fourth transistor is connected to the compensation control signal terminal for receiving the compensation control signal, a first electrode of the fourth transistor is connected to the first terminal of the drive circuit, and a second electrode of the fourth transistor is connected to the control terminal of the drive circuit.

[0031] Optionally, an orthographic projection of the second electrode of the fourth transistor on the substrate does not overlap with an orthographic projection of the control electrode of the driving transistor on the substrate.

[0032] Optionally, the pixel circuit further includes a second writing circuit, and the second writing circuit is used to write a second data signal into the first end of the driving circuit under the control of a second writing signal.

[0033] The second write circuit includes an eighth transistor, the control electrode of the eighth transistor is connected to the second write signal terminal for receiving a second write signal, the first electrode of the eighth transistor is connected to the second data signal input terminal, and the second electrode of the eighth transistor is connected to the first terminal of the driving transistor.

[0034] Based on the same inventive concept, the present application also provides a method for preparing a display panel, comprising:

[0035] A pixel circuit is formed on a substrate, wherein:

[0036] The pixel circuit includes a driving circuit, a light emitting control circuit, and a writing and storage circuit;

[0037] The driving circuit comprises a control end, a first end, and a second end, which are respectively connected to the first node, the second node, and the fourth node, and are used to control a driving current flowing through the first end of the driving circuit and the second end of the driving circuit for driving the light-emitting element to emit light;

[0038] The light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal;

[0039] A writing and storage circuit, comprising a first terminal and at least one second terminal, wherein the first terminal is connected to the control terminal of the driving circuit; and is used to write a data signal into the first terminal of the driving circuit under the control of a scanning signal, and store a voltage of the control terminal of the driving circuit;

[0040] The orthographic projection of the first end of the writing and storage circuit on the base substrate does not overlap with the orthographic projection of the control end of the driving circuit on the base substrate.

[0041] Based on the same inventive concept, the present application also provides a display device, comprising: a display panel as described in any one of the above items.

[0042] As can be seen from the above, the present application provides a display panel, a preparation method, and a display device, wherein the display panel includes a substrate and at least one pixel circuit formed on the substrate, the pixel circuit includes a driving circuit, a light-emitting control circuit, and a writing and storage circuit, the driving circuit includes a control end, a first end, and a second end, which are respectively connected to a first node, a second node, and a fourth node, and are used to control the current flowing through the first end and the second end of the driving circuit for driving the light-emitting element to emit light; the light-emitting control end circuit is used to drive the current to flow through the light-emitting element under the control of a light-emitting control signal; the writing and storage circuit is used to write a falling data signal into the first end of the driving circuit under the control of a scanning signal, and store the voltage of the control end of the driving circuit; wherein the orthographic projection of the first end of the writing and storage circuit on the substrate substrate does not overlap with the orthographic projection of the control end of the driving circuit on the substrate substrate. Since the write and storage circuit includes a capacitor, the first end of the write and storage circuit can also be understood as one end of the capacitor not overlapping with the control end of the drive circuit on the substrate. In this way, parasitic capacitance is not easily generated between the write and storage circuit and the drive circuit, and thus it is not easy to affect the gate voltage of the drive circuit, which better guarantees the stable output of the drive circuit, thereby solving the problem of flickering in low-brightness and low-grayscale images to a certain extent. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the present application or related technologies, the drawings required for use in the embodiments or related technical descriptions are briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0044] Figure 1 A schematic diagram of an exemplary wiring structure of a display panel is shown.

[0045] Figure 2 An exemplary pixel circuit schematic diagram is shown.

[0046] Figure 3 A schematic cross-sectional structure diagram of an exemplary pixel circuit on a substrate is shown.

[0047] Figure 4 A schematic diagram of the pixel circuit structure of an embodiment of the present application is shown.

[0048] Figure 5 A schematic diagram of a wiring structure of a display panel according to an embodiment of the present application is shown.

[0049] Figure 6 A schematic diagram of a film layer interface of an exemplary display panel provided in an embodiment of the present application is shown.

[0050] Figure 7A-7J A schematic diagram of the graphic structure of each level of an exemplary display panel provided in the present application is shown in FIG.

[0051] Figure 7H An exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0052] Figure 8 A schematic diagram of the pixel circuit structure of another embodiment of the present application is shown.

[0053] Fig. 9 FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the present application.

[0054] Fig.10 A schematic diagram of a wiring structure of a display panel according to another embodiment of the present application is shown.

[0055] Fig.11 A schematic diagram of a partial film layer interface of an exemplary display panel provided in another embodiment of the present application is shown.

[0056] Figure 12A-12E FIG. 4 is a schematic diagram of a partial hierarchical graphic structure of a display panel according to another exemplary embodiment of the present application.

[0057] Fig.12F An exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0058] Fig.13 A schematic diagram of the pixel circuit structure of another embodiment of the present application is shown.

[0059] Fig.14 FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the present application.

[0060] Fig.15 A schematic diagram of a wiring structure of a display panel according to another embodiment of the present application is shown.

[0061] Fig.16A schematic diagram of a partial film layer interface of an exemplary display panel provided in another embodiment of the present application is shown.

[0062] Figure 17A-17E A schematic diagram of a partial hierarchical graphic structure of a display panel according to another exemplary embodiment of the present application is shown in FIG.

[0063] Fig.17F An exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0064] Fig.18 A flow chart of a method for preparing a display panel according to an embodiment of the present application is shown.

[0065] Fig.19 A schematic diagram of the hardware structure of an electronic device provided by this embodiment is shown. DETAILED DESCRIPTION

[0066] In order to make the objectives, technical solutions and advantages of the present application more clearly understood, the present application is further described in detail below in combination with specific embodiments and with reference to the accompanying drawings.

[0067] It should be noted that, unless otherwise defined, the technical terms or scientific terms used in the embodiments of the present application should be the usual meanings understood by people with ordinary skills in the field to which the present application belongs. The "first", "second" and similar words used in the embodiments of the present application do not represent any order, quantity or importance, but are only used to distinguish different components. "Including" or "comprising" and similar words mean that the elements or objects appearing in front of the word cover the elements or objects listed after the word and are equivalent, without excluding other elements or objects. "Connecting" or "connected" and similar words are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0068] In the circuit provided in the embodiment of the present application, the first node, the second node, and the third node do not represent actual existing components, but represent the junction points of related electrical connections in the circuit diagram, that is, these nodes are nodes formed by the equivalent junction points of related electrical connections in the circuit diagram.

[0069] The "low level" of the pixel circuit provided in the embodiment of the present application refers to a level that can turn on the operated transistor included therein, and correspondingly, the "high level" refers to a level that cannot turn on the operated transistor included therein (i.e., the transistor is turned off).

[0070] The control electrode of each transistor provided in the embodiment of the present application is the gate of the transistor, the first electrode is one of the source and drain of the transistor, and the second electrode is the other of the source and drain of the transistor. Since the source and drain of the transistor can be symmetrical in structure, the source and drain thereof can be structurally indistinguishable, that is, the first electrode and the second electrode of the transistor in the embodiment of the present application can be structurally indistinguishable. Exemplarily, in the case where the transistor is a P-type transistor, the first electrode of the transistor is the source and the second electrode is the drain; Exemplarily, in the case where the transistor is an N-type transistor, the first electrode of the transistor is the drain and the second electrode is the source.

[0071] Figure 1 A schematic diagram of an exemplary wiring structure of a display panel is shown.

[0072] Figure 2 An exemplary pixel circuit schematic diagram is shown.

[0073] like Figure 1 As shown, the display panel includes a base substrate and at least one pixel circuit formed on the base substrate. Figure 2As shown, exemplarily, the pixel circuit is a 4T2C circuit, that is, the pixel circuit is composed of 4 transistors and 2 capacitors. The pixel circuit includes a write transistor M1, a control transistor M2, a drive transistor M3, a first capacitor C1, a second capacitor C2 and a reset transistor M4. The write transistor M1, the first capacitor and the second capacitor are configured to write the data signal DATA to the first end of the drive transistor M3 under the control of the scan signal and store the voltage of the control end of the drive circuit; the control electrode of the write transistor M1 is connected to the first scan signal end G1, the first electrode of the write transistor M1 is connected to the data signal input end DATA, the second electrode of the write transistor M1 is connected to the first node, the first electrode of the first capacitor is connected to the first node, the second electrode of the first capacitor is connected to the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to the first power supply voltage VDD. The control transistor M2 is used to apply the first power supply voltage to the first end of the drive circuit under the control of the light emitting control signal. The control electrode of the control transistor M2 is connected to the second scan signal terminal G2 for receiving the second scan signal, the first electrode of the control transistor M2 is connected to the first power supply voltage terminal VDD for receiving the first power supply voltage, and the second electrode of the control transistor M2 is electrically connected to the second node. The driving transistor M3 includes a control electrode, a first electrode, and a second electrode, which are respectively connected to the first node, the second node, and the fourth node, and are used to control the driving current flowing through the first end of the driving circuit and the second end of the driving circuit for driving the light-emitting element OLED to emit light. The reset transistor M4 is used to apply a first reset voltage to the first electrode of the light-emitting element OLED under the control of a first reset signal; the control electrode of the reset transistor M4 is connected to the first reset signal terminal G3 for receiving the first reset signal, the first electrode of the reset transistor M4 is connected to the first reset voltage terminal VSS for receiving the first reset voltage, and the second electrode of the reset transistor M4 is connected to the fourth node.

[0074] Figure 3 A schematic cross-sectional structure diagram of an exemplary pixel circuit on a substrate is shown.

[0075] like Figure 3As shown, the write transistor M1, the control transistor M2, the drive transistor M3, the first capacitor C1, the second capacitor C2 and the reset transistor M4 are sequentially stacked on the substrate. As can be seen from the figure, the control electrode of the drive transistor M3 is connected to the second electrode of the write transistor M1, and the control electrode of the drive transistor M3 and the control electrode of the write transistor M1 have an overlapping area Area1, so a parasitic capacitor C3 is generated between the drive transistor M3 and the write transistor M1, and because the control electrode of the drive transistor M3 is connected to the lower plate of the first capacitor C1, the parasitic capacitor C3 will affect the control electrode voltage of the drive transistor M3, and the voltage change of the control electrode of the drive transistor M3 causes the light-emitting voltage of the OLED display panel to change, causing the flickering problem under low-brightness and low-grayscale images.

[0076] Figure 4 A schematic diagram of the pixel circuit structure of an embodiment of the present application is shown.

[0077] Figure 5 A schematic diagram of a wiring structure of a display panel according to an embodiment of the present application is shown.

[0078] like Figure 2 , Figure 4 and Figure 5 As shown, in order to solve the problem of flickering under low brightness and low grayscale images caused by parasitic capacitance causing the light emitting voltage of the display panel to change. The present application provides a display panel, including a substrate and at least one pixel circuit formed on the substrate. Exemplarily, in this embodiment, the pixel circuit is a 4T2C circuit, that is, the pixel circuit is composed of 4 transistors and 2 capacitors. Figure 2 and Figure 4 As shown, the pixel circuit includes a driving circuit 101 , a light emitting control circuit 102 , and a writing and storage circuit 103 .

[0079] like Figure 2 , Figure 4 and Figure 5As shown, the writing and storage circuit 103 includes a first terminal and at least one second terminal, the first terminal of the writing and storage circuit 103 is connected to the control terminal of the driving circuit 101; and is used to write the data signal into the first terminal of the driving circuit 101 under the control of the scanning signal, and store the voltage of the control terminal of the driving circuit 101. The writing and storage circuit 103 includes: a first transistor M1, a first capacitor and a second capacitor, the control electrode of the first transistor M1 is connected to the first scanning signal terminal G1, the first electrode of the first transistor M1 is connected to the data signal input terminal, the second terminal of the first transistor M1 is connected to the first node N1, the first electrode of the first capacitor is connected to the first node N1, the second electrode of the first capacitor is connected to the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to the first power supply voltage.

[0080] Specifically, the control electrode of the first transistor M1 is used to write the data signal into the first node N1 under the action of the first scan signal, and the first capacitor is used to store the capacitance of the first node N1. The first electrode of the second capacitor is connected to the second node N2, and the second capacitor is used to store the capacitance of the second node N2.

[0081] Furthermore, if Figure 2 , Figure 4 and Figure 5 As shown, the light emitting control circuit 102 is used to make the driving current flow through the light emitting element 105 under the control of the light emitting control signal. The light emitting control circuit 102 includes: a first light emitting control circuit 1021, used to apply the first power supply voltage to the first end of the driving circuit 101 under the control of the light emitting control signal. The first light emitting control circuit 1021 includes a second transistor M2, the control electrode of the second transistor M2 is connected to the second scanning signal terminal G2, and is used to receive the second scanning signal, the first electrode of the second transistor M2 is connected to the first power supply voltage terminal, and is used to receive the first power supply voltage, and the second electrode of the second transistor M2 is electrically connected to the second node N2.

[0082] Specifically, the second transistor M2 is used to write the first power supply voltage into the second node N2 or into the first electrode of the driving transistor under the action of the second scanning signal.

[0083] Furthermore, if Figure 2 , Figure 4 and Figure 5As shown, the driving circuit 101 includes a control terminal, a first terminal, and a second terminal, which are respectively connected to the first node N1, the second node N2, and the fourth node N4, and are used to control the driving current flowing through the first terminal of the driving circuit 101 and the second terminal of the driving circuit 101 for driving the light-emitting element 105 to emit light. The driving circuit 101 includes a third transistor M3, the control electrode of the third transistor M3 is electrically connected to the first node N1 as the control terminal of the driving circuit 101, the first electrode of the third transistor M3 is electrically connected to the second node N2 as the third terminal of the driving circuit 101, and the second electrode of the third transistor M3 is electrically connected to the third node N3 as the second terminal of the driving circuit 101.

[0084] Specifically, the third transistor M3 writes the voltage of the second node N2 into the fourth node N4 under the control of the potential of the first node N1.

[0085] Furthermore, if Figure 2 , Figure 4 and Figure 5 As shown, the pixel circuit also includes a first reset circuit 104, which is used to apply a first reset voltage to the first electrode of the light-emitting element 105 under the control of a first reset signal; the first reset circuit 104 includes a fourth transistor M4, the control electrode of the fourth transistor M4 is connected to the first reset signal terminal G3, for receiving the first reset signal, the first electrode of the fourth transistor M4 is connected to the first reset voltage terminal VSS, for receiving the first reset voltage, and the second electrode of the fourth transistor M4 is connected to the fourth node N4.

[0086] Specifically, under the action of the first reset signal, the fourth transistor M4 writes the first reset voltage into the fourth node N4 to reset the potential of the fourth node N4.

[0087] Figure 6 A schematic diagram of a film layer interface of an exemplary display panel provided in an embodiment of the present application is shown.

[0088] Figure 7A-7J A schematic diagram of the graphic structure of each level of an exemplary display panel provided in the present application is shown in FIG.

[0089] like Figure 7A-7J As shown, combined Figure 6 , exemplarily, the display panel includes a buffer layer NW, a semiconductor layer poly (exemplarily, the conductive layer Gate may include an active layer AA of a TFT), a first gate insulating layer (located between the active layer AA and the gate GT, Figure 6The first conductive layer Gate (exemplarily, the first conductive layer Gate may include the gate GT of the TFT and the gate line connected to the gate GT), the second conductive layer Metal1, the third conductive layer Metal2, the fourth conductive layer Metal3, the fifth conductive layer Metal4, and the sixth conductive layer Metal5. Among them, the source and drain of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 of the pixel circuit are arranged in the same layer, and the active layer AA of the first transistor M1, the second transistor M2, the third transistor M3 and the fourth transistor M4 is arranged in the same layer. The first capacitor and the second capacitor are arranged between the fourth conductive layer Metal3 and the sixth conductive layer Metal5. Among them, the substrate material includes inorganic materials and / or metal materials with the ability to block water and oxygen, and the inorganic material can be selected from at least one of SiNx, a-Si, and P-Si.

[0090] Based on the above embodiments, it can be known that the write and storage circuit 103 includes a first transistor M1, a first capacitor and a second capacitor. The drive circuit 101 includes a third transistor M3. Since one plate of the first capacitor is connected to the control electrode of the third transistor M3, if the control electrode of the third transistor M3 overlaps with the other plate of the first transistor M1, a parasitic capacitance will be generated, thereby affecting the control voltage of the third transistor M3, that is, the display voltage of the display panel. Therefore, the orthographic projection of the first end of the write and storage circuit 103 on the substrate substrate does not overlap with the orthographic projection of the control end of the drive circuit 101 on the substrate substrate.

[0091] It can also be understood that one plate of the first transistor M1 in the writing and storage circuit 103 does not overlap with the control electrode of the driving transistor. In this way, parasitic capacitance is not easily generated, and the gate voltage of the driving circuit 101 is not easily affected, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low-brightness and low-grayscale images.

[0092] Furthermore, there is a first distance between the orthographic projection of the first end of the writing and storage circuit 103 on the substrate and the orthographic projection of the control end of the driving circuit 101 on the substrate, and the first distance is greater than 0 μm.

[0093] Exemplarily, the first end in the write and storage circuit 103 can be the first electrode of the first capacitor. By making the positive projection of the first electrode of the first capacitor on the substrate substrate not overlap with the positive projection of the control electrode of the driving transistor on the substrate substrate, and also having a first distance D, it is not easy to generate parasitic capacitance between the first capacitor and the driving transistor, and it is not easy to affect the gate voltage of the driving circuit 101, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low-brightness and low-grayscale images. The range of the first distance can be 0μm to 0.5μm. The optimal value of the first distance is: 0.1μm.

[0094] Furthermore, the orthographic projection of the control electrode of the third transistor M3 on the substrate substrate does not overlap with the orthographic projection of the second electrode of the second transistor M2 on the substrate substrate. The orthographic projection of the second electrode of the fourth transistor M4 on the substrate substrate does not overlap with the orthographic projection of the control electrode of the driving transistor on the substrate substrate. In this way, the second transistor M2 and one electrode plate of the fourth transistor do not overlap with the orthographic projection of the control electrode of the driving transistor on the substrate substrate, and due to the stable operation of the control voltage of the driving transistor, signal interference will not be caused by overlap.

[0095] For example, Fig. 7A As shown, the display panel includes an active layer poly formed on a substrate by a one-time patterning process, forming a Fig. 7A The shape in the figure is formed by using a single patterning process to form a first conductive layer Gate on the active layer poly, forming a Figure 7B The shape shown in FIG. 1 is formed by using a single patterning process to form a second conductive layer Metal1 on top of the first conductive layer Gate, forming a Figure 7C A third conductive layer Metal2 is formed on top of the second conductive layer Metal1 by a patterning process to form a Fig.7D The shape shown in FIG. 1 is formed by forming a fourth conductive layer Metal3 on top of the third conductive layer Metal2 using a patterning process to form a Fig. 7E The shape shown; the capacitor structure film layer MIM is formed by a single patterning process on the fourth conductive layer Metal3 to form a Figure 7F The shape shown; the fifth conductive layer Metal4 is formed by a patterning process above the capacitor structure film layer MIM to form a Figure 7G The conductive layer CTOP is formed by a patterning process on top of the fifth conductive layer Metal4 to form a Figure 7H The shape shown in the figure; the sixth conductive layer Metal5 (ie, OLED anode) is formed by a single patterning process on the conductive layer CTOP to form a Figure 7J Shape shown.

[0096] Figure 7HAn exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0097] like Figure 2 and Figure 7H As shown, the timing setting of the pixel circuit of the present application is divided into 5 stages, the first stage is the initialization of the N1 node, the second stage is the self-discharge reading threshold voltage Vth, the third stage is the data writing and the OLED anode reset, the fourth stage is the OLED light emission, and the fifth stage is the OLED does not emit light. In the first stage, the first transistor M1, the second transistor M2, the third transistor M3, and the fourth transistor M4 are turned on, G2 is a low potential control M2 to turn on, the VDD voltage is written to the M3 source, G1 is a low potential control first transistor M1 to turn on, the N1 node writes the reset low voltage V1, G3 is a high potential control fourth transistor M4 to turn on, the current flowing into N4 will flow into VSS through the fourth transistor M4. In the second stage, G1 and G2 are high potential controls to turn off the first transistor M1 and the second transistor M2, and G3 is high potential controls to turn on the fourth transistor M4. Because the second transistor M2 is turned off, the source of the driving tube is in a floating state, and its voltage will decrease. At this time, due to the effect of the capacitor, the voltage difference between the N1 node and the source of the driving tube will remain unchanged, so the voltage of the N1 node will decrease as the source voltage of the driving tube decreases. When the threshold voltage of the driving tube increases to V1, the discharge stops. In the third stage, G2 is high potential controls to turn off the second transistor M2, G1 is low potential controls to turn on M1, and G3 is high potential controls to turn on the fourth transistor M4. Data and VSS are written to the N1 and N4 nodes respectively. In the fourth stage, G1 is high potential controls to turn off the first transistor M1, G3 is low potential controls to turn off the fourth transistor M4, and G2 is low potential controls to turn on the fourth transistor M4. After the current passes through the OLED, it starts to emit light. In the fifth stage, G1 and G2 are high potential controls to turn off the first transistor M1 and the second transistor M2. At this time, no current passes through the OLED, and the OLED does not emit light.

[0098] In summary, if there is an overlapping area Area1 between the N4 node (M1) and the C1 lower plate capacitor (M3) connected to the control electrode of the driving tube due to the design, then the N1 node and the N4 node will generate a parasitic capacitance C3. Since the N4 node is always supplied with a low voltage by the power supply in the non-OLED light-emitting stage, the low point of the N4 node in the second stage will pull down the potential of the N1 node due to the existence of the parasitic capacitance C3. Therefore, in the second stage, the N1 node potential is <V1. Therefore, when the Data signal is written to the N1 node in the third stage, the N1 node potential Data1 <Data. Finally, when the OLED emits light in the fourth stage, since the N1 node is <Data, the current Ioled at the time of just emitting light becomes larger (see the current calculation formula below). Later, since the voltages of the N2 and N4 nodes are higher in the light-emitting stage, the N1 node is continuously coupled to raise it, which eventually causes the display screen to show an effect of first bright and then dark, that is, flickering Flicker. This phenomenon is more obvious under low-brightness and low-grayscale images.

[0099] Ioled=1 / 2μcW / L

(VDD-Data1)

[0100] Wherein μ is the mobility, c is the gate oxide capacitance, W and L are the width and length of the driving channel, VDD is the anode voltage, Data is the corresponding voltage of the display screen input, and Data1 is a voltage less than Data. Therefore, in the present application, by optimizing the control electrode area of ​​the driving crystal, M1 and the driving transistor have no overlapping area, which is not easy to generate parasitic capacitance, and is not easy to affect the gate voltage of the driving circuit, thereby ensuring the stable output of the driving circuit, thereby solving the flickering problem under low brightness and low grayscale screens.

[0101] Figure 8 A schematic diagram of the pixel circuit structure of another embodiment of the present application is shown.

[0102] Fig. 9 FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the present application.

[0103] Fig.10 A schematic diagram of a wiring structure of a display panel according to another embodiment of the present application is shown.

[0104] like Figure 8 , Fig. 9 and Fig.10 As shown, in order to solve the problem of flickering under low brightness and low grayscale images caused by parasitic capacitance causing the light emitting voltage of the display panel to change. The present application provides a display panel, including a substrate and at least one pixel circuit formed on the substrate. Exemplarily, in this embodiment, the pixel circuit is a 7T1C circuit, that is, the pixel circuit is composed of 7 transistors and 1 capacitor. Fig.10 and Figure 8As shown, the pixel circuit includes a driving circuit 101 , a light emitting control circuit 102 , and a writing and storage circuit 103 .

[0105] like Figure 8 , Fig. 9 and Fig.10 As shown, the writing and storage circuit 103 includes a first terminal and at least one second terminal, the first terminal of the writing and storage circuit 103 is connected to the control terminal of the driving circuit 101; and is used to write the data signal into the first terminal of the driving circuit 101 under the control of the scanning signal, and store the voltage of the control terminal of the driving circuit 101. The writing and storage circuit 103 includes: a second transistor M2 and a storage capacitor, the control electrode of the second transistor M2 is connected to the first writing signal terminal SC_P, the first electrode of the second transistor M2 is connected to the data signal input terminal VDATA, the second electrode of the second transistor M2 is connected to the first terminal of the driving transistor, the first electrode of the storage capacitor is connected to the first power supply voltage, and the second electrode of the storage capacitor is connected to the first node N1.

[0106] Specifically, the control electrode of the second transistor M2 is used to write the data signal into the second node N2 under the action of the first write signal, and the storage capacitor is used to store the capacitance of the first node N1.

[0107] Furthermore, if Figure 8 , Fig. 9 and Fig.10 As shown, the light emitting control circuit 102 is used to make the driving current flow through the light emitting element 105 under the control of the light emitting control signal. The light emitting control circuit 102 includes: a first light emitting control circuit 1021, used to apply the first power supply voltage to the first terminal of the driving circuit 101 under the control of the light emitting control signal; a second light emitting control circuit 1022, used to apply the driving current from the second terminal of the driving circuit 101 to the first electrode of the light emitting element 105 under the control of the light emitting control signal. Optionally, the first light emitting control circuit 1021 includes a first transistor M1, the control electrode of the first transistor M1 is connected to the light emitting control terminal and is used to receive the light emitting control signal, the first electrode of the first transistor M1 is connected to the first power supply voltage terminal and is used to receive the first power supply voltage, and the second electrode of the first transistor M1 is electrically connected to the second node N2. Optionally, the second light emitting control circuit 1022 includes a sixth transistor M6, a control electrode of the sixth transistor M6 is used to receive the light emitting control signal, a first electrode of the sixth transistor M6 is used to receive the driving current from the second end of the driving circuit 101, and a second electrode of the sixth transistor M6 is electrically connected to the fourth node N4.

[0108] Specifically, the first transistor M1 is used to write the first power supply voltage into the second node N2 or the first electrode of the driving transistor under the action of the light emitting control signal. The sixth transistor M6 is used to write the second terminal current of the driving circuit 101 into the fourth node N4 under the light emitting control signal.

[0109] Furthermore, if Figure 8 , Fig. 9 and Fig.10 As shown, the driving circuit 101 includes a control terminal, a first terminal, and a second terminal, which are respectively connected to the first node N1, the second node N2, and the fourth node N4, and are used to control the driving current flowing through the first terminal of the driving circuit 101 and the second terminal of the driving circuit 101 for driving the light-emitting element 105 to emit light. The driving circuit 101 includes a third transistor M3, the control electrode of the third transistor M3 is electrically connected to the first node N1 as the control terminal of the driving circuit 101, the first electrode of the third transistor M3 is electrically connected to the second node N2 as the third terminal of the driving circuit 101, and the second electrode of the third transistor M3 is electrically connected to the third node N3 as the second terminal of the driving circuit 101.

[0110] Specifically, the third transistor M3 writes the voltage of the second node N2 into the fourth node N4 under the control of the potential of the first node N1.

[0111] Furthermore, if Figure 8 , Fig. 9 and Fig.10 As shown, the pixel circuit also includes a first reset circuit 104, and the first reset circuit 104 is used to apply a first reset voltage to the first electrode of the light-emitting element 105 under the control of a first reset signal; the first reset circuit 104 includes a seventh transistor M7, and the control electrode of the seventh transistor M7 is connected to the first reset signal terminal for receiving the first reset signal, the first electrode of the seventh transistor M7 is connected to the first reset voltage terminal for receiving the first reset voltage, and the second electrode of the seventh transistor M7 is connected to the fourth node N4.

[0112] Specifically, under the action of the first reset signal, the seventh transistor M7 writes the first reset voltage into the fourth node N4 to reset the potential of the fourth node N4.

[0113] Furthermore, if Figure 8 , Fig. 9 and Fig.10As shown, the pixel circuit also includes a second reset circuit 106, which is used to apply a second reset voltage to the control end of the driving circuit 101 under the control of a second reset signal; the second reset circuit 106 includes a fifth transistor M5, the control electrode of the fifth transistor M5 is connected to the second reset signal terminal SC_N(n1), the first electrode of the fifth transistor M5 is connected to the second reset voltage terminal VREF1, and the second electrode of the fifth transistor M5 is connected to the control electrode of the driving transistor.

[0114] Specifically, the fifth transistor M5 writes the second reset voltage into the first node N1 under the control of the second reset signal.

[0115] Furthermore, if Figure 8 , Fig. 9 and Fig.10 As shown, the pixel circuit also includes a compensation circuit 107, and the compensation circuit 107 is used to connect the control end of the driving circuit 101 to the first end of the driving circuit 101 under the control of a compensation signal; the compensation circuit 107 includes a fourth transistor M4, and the control electrode of the fourth transistor M4 is connected to the compensation control signal end SC_N(n) for receiving the compensation control signal, the first electrode of the fourth transistor M4 is connected to the first end of the driving circuit 101, and the second electrode of the fourth transistor M4 is connected to the control end of the driving circuit 101.

[0116] Specifically, the fourth transistor M4 conducts between the control electrode and the second end of the driving transistor under the control of the compensation signal.

[0117] Fig.11 A schematic diagram of a partial film layer interface of an exemplary display panel provided in another embodiment of the present application is shown.

[0118] Figure 12A-12E FIG. 4 is a schematic diagram of a partial hierarchical graphic structure of a display panel according to another exemplary embodiment of the present application.

[0119] like Figure 12A-12E As shown, combined Fig.11 , exemplarily, the display panel includes a buffer layer NW, a semiconductor layer poly (exemplarily, the conductive layer Gate may include an active layer AAT of a TFT) sequentially stacked in a direction away from the substrate Si Fig.11 Not shown in the figure, please refer to Figure 6 ), a first gate insulating layer (located between the active layer AA and the gate GT, Fig.11The first conductive layer Gate (illustratively, the first conductive layer Gate may include the gate GT of the TFT and the gate line connected to the gate GT), the second conductive layer Metal1, the third conductive layer Metal2, and the fourth conductive layer Metal3. The source and drain of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 of the pixel circuit are arranged in the same layer as the active layer poly, and the gate of the first transistor M1, the second transistor M2, the third transistor M3, the fourth transistor M4, the fifth transistor M5, the sixth transistor M6, and the seventh transistor M7 of the pixel circuit are arranged in the same layer as the first conductive layer Gate, and the storage capacitor is arranged above the first conductive layer Gate. Among them, the substrate material includes inorganic materials and / or metal materials with the ability to block water and oxygen, and the inorganic material can be selected from at least one of SiNx, a-Si, and P-Si.

[0120] Based on the above embodiments, it can be known that the write and storage circuit 103 includes a second transistor M2 and a storage capacitor. The drive circuit 101 includes a third transistor M3. Since one plate of the storage capacitor is connected to the control electrode of the third transistor M3, if the control electrode of the third transistor M3 overlaps with the other plate of the first transistor M1, a parasitic capacitance will be generated, thereby affecting the control voltage of the third transistor M3, that is, the display voltage of the display panel. Therefore, the orthographic projection of the first end of the write and storage circuit 103 on the substrate substrate does not overlap with the orthographic projection of the control end of the drive circuit 101 on the substrate substrate.

[0121] It can also be understood that one plate of the second transistor M2 in the writing and storage circuit 103 does not overlap with the control electrode of the driving transistor. In this way, parasitic capacitance is not easily generated, and the gate voltage of the driving circuit 101 is not easily affected, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low-brightness and low-grayscale images.

[0122] Furthermore, there is a first distance between the orthographic projection of the first end of the writing and storage circuit 103 on the substrate and the orthographic projection of the control end of the driving circuit 101 on the substrate, and the first distance is greater than 0 μm.

[0123] Exemplarily, the first end in the write and storage circuit 103 can be the first electrode of the storage capacitor. By making the positive projection of the first electrode of the storage capacitor on the substrate substrate not overlap with the positive projection of the control electrode of the driving transistor on the substrate substrate, and also having a first distance, it is not easy to generate parasitic capacitance between the storage capacitor and the driving transistor, and it is not easy to affect the gate voltage of the driving circuit 101, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low-brightness and low-grayscale images. The range of the first distance can be 0μm to 10μm. Exemplarily, the optimal value of the first distance is: 8.6μm.

[0124] For example, Fig. 12A As shown, the display panel includes an active layer poly formed on a substrate by a one-time patterning process, forming a Fig. 12A The shape in the figure is formed by using a single patterning process to form a first conductive layer Gate on the active layer poly, forming a Fig. 12B The shape shown in FIG. 1 is formed by using a single patterning process to form a second conductive layer Metal1 on top of the first conductive layer Gate, forming a Fig. 12C A third conductive layer Metal2 is formed on top of the second conductive layer Metal1 by a patterning process to form a Fig.12D The shape shown in FIG. 1 is formed by forming a fourth conductive layer Metal3 on top of the third conductive layer Metal2 using a patterning process to form a Fig.12E Shape shown.

[0125] Fig.12F An exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0126] like Fig. 9 and Fig.12FAs shown, the timing setting of the pixel circuit of the present application is divided into 5 stages. The first stage is the initialization of the N1 node, the second stage is the self-discharge reading of the threshold voltage Vth, the third stage is the data writing and the OLED anode reset, the fourth stage is the OLED light emission, and the fifth stage is the OLED does not emit light. In the first stage, the first transistor M1, the second transistor M2, the third transistor M3, and the seventh transistor M7 are turned on. After EM is low potential control M1 is turned on, the VDD voltage is written to the M3 source. SC_P is low potential control second transistor M2 is turned on, N1 node writes reset low voltage V1, SC_P is low potential control seventh transistor M7 is turned on, the current flowing into N4 will flow into VREF2 through the seventh transistor M7. SC_N(n1) and SC_N(n) are high level fifth transistor M5 and fourth transistor M4 are turned off. In the second stage, SC_P and EM are high potentials to control the first transistor M1 and the second transistor M2 to be turned off, SC_P is high potential to control the seventh transistor M7 to be turned off, SC_N(n1) and SC_N(n) are low levels, the fifth transistor M5 writes VREF1 into the N1 node and the fourth transistor M4 is turned on to align the potential of the N1 node with that of the N3 node. Because the second transistor M2 is turned off, the source of the driving tube is in a floating state, and its voltage will decrease. At this time, due to the effect of the capacitor, the voltage difference between the N1 node and the source of the driving tube will remain unchanged, so the voltage of the N1 node will decrease as the source voltage of the driving tube decreases, and the discharge stops when the threshold voltage of the driving tube increases to EM. Among them, in the third stage, EM is high potential to control the second transistor M2M1 to be turned off, SC_P is low potential to control M2 to be turned on, SC_P is low potential to control the seventh transistor M7 to be turned on, and VDATA and VREF2 are written into the N1 and N4 nodes respectively. SC_N(n1) and SC_N(n) are high levels, the fifth transistor M5 and the fourth transistor M4 are turned off. In the fourth stage, SC_P is a high potential to control the second transistor M2 to be turned off, SC_P is a high potential to control the seventh transistor M7 to be turned off, and EM is a low potential to control the sixth transistor M6 to be turned on, and the current passes through the OLED and starts to emit light. In the fifth stage, SC_P and EM are high potentials to control the first transistor M1 and the second transistor M2 to be turned off, at this time no current passes through the OLED, and the OLED does not emit light.

[0127] Fig.13 A schematic diagram of the pixel circuit structure of another embodiment of the present application is shown.

[0128] Fig.14 FIG. 2 is a schematic diagram of a pixel circuit according to another embodiment of the present application.

[0129] Fig.15 A schematic diagram of a wiring structure of a display panel according to another embodiment of the present application is shown.

[0130] like Fig.13 , Fig.14 and Fig.15 As shown, in order to solve the problem of flickering under low brightness and low grayscale images caused by parasitic capacitance causing the light emitting voltage of the display panel to change. The present application provides a display panel, including a substrate and at least one pixel circuit formed on the substrate. Exemplarily, in this embodiment, the pixel circuit is an 8T1C circuit, that is, the pixel circuit is composed of 8 transistors and 1 capacitor. Fig.15 and Fig.13 As shown, the pixel circuit includes a driving circuit 101 , a light emitting control circuit 102 , and a writing and storage circuit 103 .

[0131] like Fig.13 , Fig.14 and Fig.15 As shown, the writing and storage circuit 103 includes a first terminal and at least one second terminal, the first terminal of the writing and storage circuit 103 is connected to the control terminal of the driving circuit 101; and is used to write the data signal into the first terminal of the driving circuit 101 under the control of the scanning signal, and store the voltage of the control terminal of the driving circuit 101. The writing and storage circuit 103 includes: a second transistor T2 and a storage capacitor, the control electrode of the second transistor T2 is connected to the first writing signal terminal SC_P, the first electrode of the second transistor T2 is connected to the data signal input terminal VDATA, the second electrode of the second transistor T2 is connected to the first terminal of the driving transistor, the first electrode of the storage capacitor is connected to the first power supply voltage, and the second electrode of the storage capacitor is connected to the first node N1.

[0132] Specifically, the control electrode of the second transistor T2 is used to write the data signal into the second node N2 under the action of the first write signal, and the storage capacitor is used to store the capacitance of the first node N1.

[0133] Furthermore, if Fig.13 , Fig.14 and Fig.15As shown, the light emitting control circuit 102 is used to make the driving current flow through the light emitting element 105 (OLED) under the control of the light emitting control signal. The light emitting control circuit 102 includes: a first light emitting control circuit 1021, used to apply the first power supply voltage to the first end of the driving circuit 101 under the control of the light emitting control signal; a second light emitting control circuit 1022, used to apply the driving current from the second end of the driving circuit 101 to the first electrode of the light emitting element 105 (OLED) under the control of the light emitting control signal. Optionally, the first light emitting control circuit 1021 includes a first transistor T1, the control electrode of the first transistor T1 is connected to the light emitting control end and is used to receive the light emitting control signal, the first electrode of the first transistor T1 is connected to the first power supply voltage end and is used to receive the first power supply voltage, and the second electrode of the first transistor T1 is electrically connected to the second node N2. Optionally, the second light emitting control circuit 1022 includes a sixth transistor T6, a control electrode of the sixth transistor T6 is used to receive the light emitting control signal, a first electrode of the sixth transistor T6 is used to receive the driving current from the second end of the driving circuit 101, and a second electrode of the sixth transistor T6 is electrically connected to the fourth node N4.

[0134] Specifically, the first transistor T1 is used to write the first power supply voltage into the second node N2 or the first electrode of the driving transistor under the action of the light emitting control signal. The sixth transistor T6 is used to write the second terminal current of the driving circuit 101 into the fourth node N4 under the light emitting control signal.

[0135] Furthermore, if Fig.13 , Fig.14 and Fig.15 As shown, the driving circuit 101 includes a control terminal, a first terminal, and a second terminal, which are respectively connected to the first node N1, the second node N2, and the fourth node N4, and are used to control the driving current flowing through the first terminal of the driving circuit 101 and the second terminal of the driving circuit 101 for driving the light-emitting element 105OLED to emit light. The driving circuit 101 includes a third transistor T3, the control electrode of the third transistor T3 is electrically connected to the first node N1 as the control terminal of the driving circuit 101, the first electrode of the third transistor T3 is electrically connected to the second node N2 as the third terminal of the driving circuit 101, and the second electrode of the third transistor T3 is electrically connected to the third node N3 as the second terminal of the driving circuit 101.

[0136] Specifically, the third transistor T3 writes the voltage of the second node N2 into the fourth node N4 under the control of the potential of the first node N1.

[0137] Furthermore, if Fig.13 , Fig.14and Fig.15 As shown, the pixel circuit also includes a first reset circuit 104, and the first reset circuit 104 is used to apply a first reset voltage to the first electrode of the light-emitting element 105 (OLED) under the control of a first reset signal; the first reset circuit 104 includes a seventh transistor T7, the control electrode of the seventh transistor T7 is connected to the first reset signal terminal for receiving the first reset signal, the first electrode of the seventh transistor T7 is connected to the first reset voltage terminal for receiving the first reset voltage, and the second electrode of the seventh transistor T7 is connected to the fourth node N4.

[0138] Specifically, under the action of the first reset signal, the seventh transistor T7 writes the first reset voltage into the fourth node N4 to reset the potential of the fourth node N4.

[0139] Furthermore, if Fig.13 , Fig.14 and Fig.15 As shown, the pixel circuit also includes a second reset circuit 106, which is used to apply a second reset voltage to the control end of the driving circuit 101 under the control of a second reset signal; the second reset circuit 106 includes a fifth transistor T5, the control electrode of the fifth transistor T5 is connected to the second reset signal terminal SC_N(n1), the first electrode of the fifth transistor T5 is connected to the second reset voltage terminal VREF1, and the second electrode of the fifth transistor T5 is connected to the control electrode of the driving transistor.

[0140] Specifically, the fifth transistor T5 writes the second reset voltage into the first node N1 under the control of the second reset signal.

[0141] Furthermore, if Fig.13 , Fig.14 and Fig.15 As shown, the pixel circuit also includes a compensation circuit 107, and the compensation circuit 107 is used to connect the control end of the driving circuit 101 to the first end of the driving circuit 101 under the control of a compensation signal; the compensation circuit 107 includes a fourth transistor T4, the control electrode of the fourth transistor T4 is connected to the compensation control signal end SC_N(n) for receiving the compensation control signal, the first electrode of the fourth transistor T4 is connected to the first end of the driving circuit 101, and the second electrode of the fourth transistor T4 is connected to the control end of the driving circuit 101.

[0142] Specifically, the fourth transistor T4 conducts between the control electrode and the second end of the driving transistor under the control of the compensation signal.

[0143] Furthermore, if Fig.13 , Fig.14 and Fig.15As shown, the pixel circuit further includes a second writing circuit 108, and the second writing circuit 108 is used to write the second data signal into the first end of the driving circuit 101 under the control of the second writing signal. The second writing circuit 108 includes an eighth transistor T8, the control electrode of the eighth transistor T8 is connected to the second writing signal end, and is used to receive the second writing signal, the first electrode of the eighth transistor T8 is connected to the second data signal input end VDATA, and the second electrode of the eighth transistor T8 is connected to the first end of the driving transistor.

[0144] Specifically, the eighth transistor T8 writes the second data signal into the second node N2 under the control of the second write signal SC_P*.

[0145] Fig.16 A schematic diagram of a partial film layer interface of a display panel according to another exemplary embodiment provided in the embodiments of the present application is shown.

[0146] Figure 17A-17E FIG. 2 is a schematic diagram of a partial hierarchical graphic structure of another exemplary embodiment of the present application. Figure 17A-17E As shown, combined Fig.16 , exemplarily, the display panel includes a buffer layer NW, a semiconductor layer poly (exemplarily, the conductive layer Gate may include an active layer AAT of a TFT) sequentially stacked in a direction away from the substrate Si Fig.16 Not shown in the figure, please refer to Figure 6 ), a first gate insulating layer (located between the active layer AA and the gate GT, Fig.16 The first conductive layer Gate (exemplarily, the first conductive layer Gate may include the gate GT of the TFT and the gate line connected to the gate GT), the second conductive layer Metal1, the third conductive layer Metal2, and the fourth conductive layer Metal3. The source and drain of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor T5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 of the pixel circuit are arranged in the same layer as the active layer poly, and the gate of the first transistor T1, the second transistor T2, the third transistor T3, the fourth transistor T4, the fifth transistor YT5, the sixth transistor T6, the seventh transistor T7, and the eighth transistor T8 of the pixel circuit are arranged in the same layer as the first conductive layer Gate, and the storage capacitor is arranged above the first conductive layer Gate. Among them, the substrate material includes inorganic materials and / or metal materials with the ability to block water and oxygen, and the inorganic material can be selected from at least one of SiNx, a-Si, and P-Si.

[0147] Based on the above embodiments, it can be known that the write and storage circuit 103 includes a second transistor T2 and a storage capacitor. The drive circuit 101 includes a third transistor T3. Since one plate of the storage capacitor is connected to the control electrode of the third transistor T3, if the control electrode of the third transistor T3 overlaps with the other plate of the first transistor T1, a parasitic capacitance will be generated, thereby affecting the control voltage of the third transistor T3, that is, the display voltage of the display panel. Therefore, the orthographic projection of the first end of the write and storage circuit 103 on the substrate substrate does not overlap with the orthographic projection of the control end of the drive circuit 101 on the substrate substrate.

[0148] It can also be understood that one plate of the second transistor T2 in the writing and storage circuit 103 does not overlap with the control electrode of the driving transistor. In this way, parasitic capacitance is not easily generated, and the gate voltage of the driving circuit 101 is not easily affected, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low-brightness and low-grayscale images.

[0149] Furthermore, there is a first distance between the orthographic projection of the first end of the writing and storage circuit 103 on the substrate and the orthographic projection of the control end of the driving circuit 101 on the substrate, and the first distance is greater than 0 μm.

[0150] Exemplarily, the first end in the write and storage circuit 103 can be the first electrode of the storage capacitor. By making the positive projection of the first electrode of the storage capacitor on the substrate substrate not overlap with the positive projection of the control electrode of the driving transistor on the substrate substrate, and also having a first distance, it is not easy to generate parasitic capacitance between the storage capacitor and the driving transistor, and it is not easy to affect the gate voltage of the driving circuit 101, thereby ensuring the stable output of the driving circuit 101, thereby solving the problem of flickering under low brightness and low grayscale images. The range of the first distance can be 0μm to 10μm. The optimal value of the first distance is: 8.6μm.

[0151] For example, Fig.17A As shown, the display panel includes an active layer poly formed on a substrate by a one-time patterning process, forming a Fig.17A The shape in the figure is formed by using a single patterning process to form a first conductive layer Gate on the active layer poly, forming a Fig. 17B The shape shown in FIG. 1 is formed by using a single patterning process to form a second conductive layer Metal1 on top of the first conductive layer Gate, forming a Fig. 17C The shape shown in FIG. 1 is formed by forming a third conductive layer Metal2 on the second conductive layer Metal1 film layer by a single patterning process to form a Fig.17D The shape shown in FIG. 1 is formed by forming a fourth conductive layer Metal3 on top of the third conductive layer Metal2 using a patterning process to form a Fig.17E Shape shown.

[0152] Fig.17F An exemplary driving timing diagram of an exemplary pixel circuit provided in the present application is shown.

[0153] like Fig.14 and Fig.17FAs shown, the timing setting of the pixel circuit of the present application is divided into 5 stages. The first stage is the initialization of the N1 node, the second stage is the self-discharge reading threshold voltage Vth, the third stage is the data writing and the OLED anode reset, the fourth stage is the OLED light emission, and the fifth stage is the OLED does not emit light. In the first stage, the first transistor T1, the second transistor T2, the third transistor T3, and the seventh transistor T7 are turned on. After EM is low potential control M1 is turned on, the VDD voltage is written to the M3 source. SC_P is low potential control second transistor T2 is turned on, N1 node writes reset low voltage V1, SC_P is low potential control seventh transistor T7 is turned on, the current flowing into N4 will flow into VREF2 through the seventh transistor T7. SC_N(n1) and SC_N(n) are high level fifth transistor T5 and fourth transistor T4 are turned off. In the second stage, SC_P and EM are high potentials to control the first transistor T1 and the second transistor T2 to be turned off, SC_P is high potential to control the seventh transistor T7 to be turned off, SC_N(n1) and SC_N(n) are low levels, the fifth transistor T5 writes VREF1 into the N1 node and the fourth transistor T4 is turned on to align the potential of the N1 node with that of the N3 node. Because the second transistor T2 is turned off, the source of the driving tube is in a floating state, and its voltage will decrease. At this time, due to the effect of the capacitor, the voltage difference between the N1 node and the source of the driving tube will remain unchanged, so the voltage of the N1 node will decrease as the source voltage of the driving tube decreases, and the discharge stops when the threshold voltage of the driving tube increases to EM. Among them, in the third stage, EM is high potential to control the second transistor T2M1 to be turned off, SC_P is low potential to control M2 to be turned on, SC_P is low potential to control the seventh transistor T7 to be turned on, and VDATA and VREF2 are written into the N1 and N4 nodes respectively. SC_N(n1) and SC_N(n) are high levels, the fifth transistor T5 and the fourth transistor T4 are turned off. At the moment before light emission (that is, before the fourth stage), the N2 node is reset and the reset voltage DVH is written. Because before the reset, after the N2 node is written with Data, M2 is closed and N2 is in a floating state. Therefore, in order to reduce the coupling effect of the voltage drop of the N2 node on N1, N2 is reset before light emission, and the voltage of DVH is different from the VData voltage. In the fourth stage, SC_P is a high potential to control the second transistor T2 to be turned off, SC_P is a high potential to control the seventh transistor T7 to be turned off, and EM is a low potential to control the sixth transistor T6 to be turned on, and the current passes through the OLED and starts to emit light. In the fifth stage, SC_P and EM are high potentials to control the first transistor T1 and the second transistor T2 to be turned off. At this time, no current passes through the OLED and the OLED does not emit light.

[0154] Fig.18 A flow chart of a method for preparing a display panel according to an embodiment of the present application is shown.

[0155] like Fig.18As shown, based on the same inventive concept, the present application also provides a method for preparing a display panel, comprising the following steps:

[0156] Step 102: forming a pixel circuit on a substrate, wherein the pixel circuit includes a driving circuit, a light emitting control circuit, and a writing and storage circuit;

[0157] Step 104, the driving circuit includes a control end, a first end, and a second end, which are respectively connected to the first node, the second node, and the fourth node, and are used to control a driving current flowing through the first end of the driving circuit and the second end of the driving circuit to drive the light-emitting element to emit light;

[0158] Step 106, the light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal;

[0159] Step 108, a writing and storage circuit, comprising a first end and at least one second end, wherein the first end is connected to the control end of the driving circuit; and is used to write a data signal into the first end of the driving circuit under the control of a scanning signal, and to store the voltage of the control end of the driving circuit; wherein the orthographic projection of the first end of the writing and storage circuit on the substrate substrate does not overlap with the orthographic projection of the control end of the driving circuit on the substrate substrate.

[0160] Specifically, the display panel includes a substrate and at least one pixel circuit formed on the substrate, the pixel circuit includes a driving circuit, a light emitting control circuit and a writing and storage circuit, the driving circuit includes a control end, a first end and a second end, respectively connected to a first node, a second node and a fourth node, and used to control the current flowing through the first end and the second end of the driving circuit for driving the light emitting element to emit light; the light emitting control end circuit is used to drive the current to flow through the light emitting element under the control of the light emitting control signal; the writing and storage circuit is used to write the falling data signal into the first end of the driving circuit under the control of the scanning signal, and store the voltage of the control end of the driving circuit; wherein the positive projection of the first end of the writing and storage circuit on the substrate substrate does not overlap with the positive projection of the control end of the driving circuit on the substrate substrate. Since the writing and storage circuit includes a capacitor, the first end of the writing and storage circuit can also be understood as one end of the capacitor not overlapping with the control end of the driving circuit on the substrate substrate, so that parasitic capacitance is not easily generated between the writing and storage circuit and the driving circuit, and thus it is not easy to affect the gate voltage of the driving circuit, ensuring the stable output of the driving circuit, thereby solving the problem of flickering under low brightness and low grayscale images.

[0161] Based on the same inventive concept, the present application also provides a display device, comprising: a display panel as described in any one of the above items.

[0162] The display device may be: an LED display, an OLED display, a mobile phone, a tablet computer, a television, a monitor, a laptop computer, a digital photo frame, a navigator, or any other product or component with a display function, but the embodiments of the present disclosure are not limited thereto.

[0163] It should be noted that the method of the embodiment of the present application can be performed by a single device, such as a computer or server. The method of this embodiment can also be applied to a distributed scenario and completed by multiple devices cooperating with each other. In the case of such a distributed scenario, one of the multiple devices can only perform one or more steps in the method of the embodiment of the present application, and the multiple devices will interact with each other to complete the described method.

[0164] It should be noted that the above describes some embodiments of the present application. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recorded in the claims can be performed in an order different from that in the above embodiments and still achieve the desired results. In addition, the processes depicted in the accompanying drawings do not necessarily require the specific order or continuous order shown to achieve the desired results. In some embodiments, multitasking and parallel processing are also possible or may be advantageous.

[0165] Based on the same inventive concept, corresponding to any of the above-mentioned embodiments, the present application also provides an electronic device, including a memory, a processor, and a computer program stored in the memory and executable on the processor, wherein when the processor executes the program, a method for preparing a display panel described in any of the above embodiments is implemented.

[0166] Fig.19 A more specific schematic diagram of the hardware structure of an electronic device provided in this embodiment is shown, and the device may include: a processor 1010, a memory 1020, an input / output interface 1030, a communication interface 1040, and a bus 1050. The processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040 are connected to each other through the bus 1050 in the device.

[0167] The processor 1010 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application-specific integrated circuit (ASIC), or one or more integrated circuits, and is used to execute relevant programs to implement the technical solutions provided in the embodiments of this specification.

[0168] The memory 1020 may be implemented in the form of ROM (Read Only Memory), RAM (Random Access Memory), static storage device, dynamic storage device, etc. The memory 1020 may store an operating system and other application programs. When the technical solutions provided in the embodiments of this specification are implemented by software or firmware, the relevant program codes are stored in the memory 1020 and are called and executed by the processor 1010.

[0169] The input / output interface 1030 is used to connect the input / output module to realize information input and output. The input / output module can be configured in the device as a component (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0170] The communication interface 1040 is used to connect a communication module (not shown) to realize communication interaction between the device and other devices. The communication module can realize communication through a wired mode (such as USB, network cable, etc.) or a wireless mode (such as mobile network, WIFI, Bluetooth, etc.).

[0171] The bus 1050 includes a path that transmits information between the various components of the device (eg, the processor 1010, the memory 1020, the input / output interface 1030, and the communication interface 1040).

[0172] It should be noted that, although the above device only shows the processor 1010, the memory 1020, the input / output interface 1030, the communication interface 1040 and the bus 1050, in the specific implementation process, the device may also include other components necessary for normal operation. In addition, it can be understood by those skilled in the art that the above device may also only include the components necessary for implementing the embodiments of the present specification, and does not necessarily include all the components shown in the figure.

[0173] The electronic device of the above embodiment is used to implement a corresponding method for manufacturing a display panel in any of the above embodiments, and has the beneficial effects of the corresponding method embodiment, which will not be described in detail here.

[0174] Based on the same inventive concept, corresponding to any of the above-mentioned embodiment methods, the present application also provides a non-transitory computer-readable storage medium, wherein the non-transitory computer-readable storage medium stores computer instructions, and the computer instructions are used to enable the computer to execute a method for preparing a display panel as described in any of the above embodiments.

[0175] The computer-readable medium of this embodiment includes permanent and non-permanent, removable and non-removable media, and information storage can be implemented by any method or technology. Information can be computer-readable instructions, data structures, modules of programs, or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read-only memory (ROM), electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, read-only compact disk read-only memory (CD-ROM), digital versatile disk (DVD) or other optical storage, magnetic cassettes, magnetic tape magnetic disk storage or other magnetic storage devices or any other non-transmission media that can be used to store information that can be accessed by a computing device.

[0176] The computer instructions stored in the storage medium of the above embodiment are used to enable the computer to execute a method for manufacturing a display panel as described in any of the above embodiments, and have the beneficial effects of the corresponding method embodiments, which will not be repeated here.

[0177] Those skilled in the art should understand that the discussion of any of the above embodiments is merely illustrative and is not intended to imply that the scope of the present application (including the claims) is limited to these examples. In line with the concept of the present application, the technical features in the above embodiments or different embodiments may be combined, the steps may be implemented in any order, and there are many other variations of the different aspects of the embodiments of the present application as described above, which are not provided in detail for the sake of simplicity.

[0178] In addition, to simplify the description and discussion, and in order not to make the embodiments of the present application difficult to understand, the known power supply / ground connection with the integrated circuit (IC) chip and other components may or may not be shown in the provided drawings. In addition, the device can be shown in the form of a block diagram to avoid making the embodiments of the present application difficult to understand, and this also takes into account the fact that the details of the implementation of these block diagram devices are highly dependent on the platform to be implemented in the embodiments of the present application (that is, these details should be fully within the scope of understanding of those skilled in the art). In the case of elaborating specific details (e.g., circuits) to describe exemplary embodiments of the present application, it is obvious to those skilled in the art that the embodiments of the present application can be implemented without these specific details or when these specific details are changed. Therefore, these descriptions should be considered to be illustrative rather than restrictive.

[0179] Although the present application has been described in conjunction with specific embodiments of the present application, many replacements, modifications and variations of these embodiments will be apparent to those skilled in the art from the foregoing description. For example, other memory architectures (e.g., dynamic RAM (DRAM)) may use the embodiments discussed.

[0180] The embodiments of the present application are intended to cover all such substitutions, modifications and variations that fall within the broad scope of the appended claims. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the embodiments of the present application should be included in the scope of protection of the present application.

Claims

1. A display panel, characterized in that: It includes a base substrate and at least one pixel circuit formed on the base substrate, wherein the pixel circuit includes a driving circuit, a light emitting control circuit, and a writing and storage circuit; The driving circuit comprises a control end, a first end, and a second end, which are respectively connected to the first node, the second node, and the fourth node, and are used to control a driving current flowing through the first end of the driving circuit and the second end of the driving circuit for driving the light-emitting element to emit light; The light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal; A writing and storage circuit, comprising a first terminal and at least one second terminal, wherein the first terminal of the writing and storage circuit is connected to the control terminal of the driving circuit; and is used to write a data signal into the first terminal of the driving circuit under the control of a scanning signal, and store a voltage at the control terminal of the driving circuit; The orthographic projection of the first end of the writing and storage circuit on the base substrate does not overlap with the orthographic projection of the control end of the driving circuit on the base substrate.

2. The display panel according to claim 1, characterized in that: There is a first distance between the orthographic projection of the first end of the writing and storage circuit on the base substrate and the orthographic projection of the control end of the driving circuit on the base substrate, and the first distance is greater than 0 μm.

3. The display panel according to claim 1, characterized in that: The light emitting control circuit comprises: The first light emitting control circuit is used to apply a first power supply voltage to the first end of the driving circuit under the control of a light emitting control signal.

4. The display panel according to claim 1, characterized in that: The writing and storage circuit includes: a first transistor, a first capacitor and a second capacitor, the control electrode of the first transistor is connected to the first scanning signal terminal, the first electrode of the first transistor is connected to the data signal input terminal, the second end of the first transistor is connected to the first node, the first electrode of the first capacitor is connected to the first node, the second electrode of the first capacitor is connected to the first electrode of the second capacitor, and the second electrode of the second capacitor is connected to the first power supply voltage.

5. The display panel according to claim 4, characterized in that: The first light-emitting control circuit includes a second transistor, the control electrode of the second transistor is connected to the second scanning signal terminal for receiving the second scanning signal, the first electrode of the second transistor is connected to the first power supply voltage terminal for receiving the first power supply voltage, and the second electrode of the second transistor is electrically connected to the second node.

6. The display panel according to claim 2, characterized in that: The driving circuit includes a third transistor, the control electrode of the third transistor is electrically connected to the first node as the control end of the driving circuit, the first electrode of the third transistor is electrically connected to the third end and the second node of the driving circuit, and the second electrode of the third transistor is electrically connected to the third node as the second end of the driving circuit.

7. The display panel according to claim 6, characterized in that: The orthographic projection of the control electrode of the third transistor on the substrate does not overlap with the orthographic projection of the second electrode of the first transistor on the substrate.

8. The display panel according to claim 6, characterized in that: The light emitting control circuit comprises: A first light emitting control circuit, used for applying a first power supply voltage to a first end of the driving circuit under the control of a light emitting control signal; The second light emitting control circuit is used to apply the driving current from the second end of the driving circuit to the first electrode of the light emitting element under the control of the light emitting control signal.

9. The display panel according to claim 8, characterized in that: The first light-emitting control circuit includes a first transistor, the control electrode of the first transistor is connected to the light-emitting control end and is used to receive the light-emitting control signal, the first electrode of the first transistor is connected to the first power supply voltage end and is used to receive the first power supply voltage, and the second electrode of the first transistor is electrically connected to the second node.

10. The display panel according to claim 8, characterized in that: The second light emitting control circuit includes a sixth transistor, a control electrode of the sixth transistor is used to receive the light emitting control signal, a first electrode of the sixth transistor is used to receive the driving current from the second end of the driving circuit, and a second electrode of the sixth transistor is electrically connected to the fourth node.

11. The display panel according to claim 6, characterized in that: The writing and storage circuit includes: a second transistor and a storage capacitor, the control electrode of the second transistor is connected to the first writing signal terminal, the first electrode of the second transistor is connected to the data signal input terminal, the second electrode of the second transistor is connected to the first terminal of the driving transistor, the first electrode of the storage capacitor is connected to the first power supply voltage, and the second electrode of the storage capacitor is connected to the first node.

12. The display panel according to claim 11, characterized in that: The orthographic projection of the control electrode of the third transistor on the substrate does not overlap with the orthographic projection of the second electrode of the second transistor on the substrate.

13. The display panel according to claim 3, characterized in that: The pixel circuit further comprises a first reset circuit, the first reset circuit being used to apply a first reset voltage to a first electrode of the light emitting element under the control of a first reset signal; The first reset circuit includes a fourth transistor, a control electrode of the fourth transistor is connected to the first reset signal terminal for receiving a first reset signal, a first electrode of the fourth transistor is connected to the first reset voltage terminal for receiving a first reset voltage, and a second electrode of the fourth transistor is connected to a fourth node.

14. The display panel according to claim 3, characterized in that: The pixel circuit further comprises a first reset circuit, the first reset circuit being used to apply a first reset voltage to a first electrode of the light emitting element under the control of a first reset signal; The first reset circuit includes a seventh transistor, a control electrode of the seventh transistor is connected to the first reset signal terminal for receiving a first reset signal, a first electrode of the seventh transistor is connected to the first reset voltage terminal for receiving a first reset voltage, and a second electrode of the seventh transistor is connected to a fourth node.

15. The display panel according to claim 3, characterized in that: The pixel circuit further comprises a second reset circuit, which is used to apply a second reset voltage to the control terminal of the driving circuit under the control of a second reset signal; The second reset circuit includes a fifth transistor, a control electrode of the fifth transistor is connected to the second reset signal terminal, a first electrode of the fifth transistor is connected to the second reset voltage terminal, and a second electrode of the fifth transistor is connected to the control electrode of the driving transistor.

16. The display panel according to claim 3, characterized in that: The pixel circuit further comprises a compensation circuit, wherein the compensation circuit is used to connect the control terminal of the driving circuit to the first terminal of the driving circuit under the control of a compensation signal; The compensation circuit includes a fourth transistor, a control electrode of the fourth transistor is connected to the compensation control signal terminal for receiving the compensation control signal, a first electrode of the fourth transistor is connected to the first terminal of the drive circuit, and a second electrode of the fourth transistor is connected to the control terminal of the drive circuit.

17. The display panel according to claim 16, characterized in that: The orthographic projection of the second electrode of the fourth transistor on the substrate does not overlap with the orthographic projection of the control electrode of the driving transistor on the substrate.

18. The display panel according to claim 11, characterized in that: The pixel circuit further includes a second writing circuit, wherein the second writing circuit is used to write a second data signal into the first end of the driving circuit under the control of a second writing signal; The second write circuit includes an eighth transistor, the control electrode of the eighth transistor is connected to the second write signal terminal for receiving a second write signal, the first electrode of the eighth transistor is connected to the second data signal input terminal, and the second electrode of the eighth transistor is connected to the first terminal of the driving transistor.

19. A method for preparing a display panel, characterized in that: include: A pixel circuit is formed on a substrate, wherein: The pixel circuit includes a driving circuit, a light emitting control circuit, and a writing and storage circuit; The driving circuit comprises a control end, a first end, and a second end, which are respectively connected to the first node, the second node, and the fourth node, and are used to control a driving current flowing through the first end of the driving circuit and the second end of the driving circuit for driving the light-emitting element to emit light; The light emitting control circuit is used to make the driving current flow through the light emitting element under the control of the light emitting control signal; A writing and storage circuit, comprising a first terminal and at least one second terminal, wherein the first terminal is connected to the control terminal of the driving circuit; and is used to write a data signal into the first terminal of the driving circuit under the control of a scanning signal, and store a voltage of the control terminal of the driving circuit; The orthographic projection of the first end of the writing and storage circuit on the base substrate does not overlap with the orthographic projection of the control end of the driving circuit on the base substrate.

20. A display device, characterized in that: include: The display panel according to any one of claims 1 to 18.

Images