Gate driver

Abstract

The invention relates to a gate driver. The gate driver is electrically connected to the time schedule controller, and the gate driver comprises N levels of gate driving circuits. The nth-stage gate drive circuit comprises an output signal setting module electrically connected to the time schedule controller and the intermediate endpoint. During the full-gate synchronization period, the output signal setting module sets the nth-level pixel gate signal according to the full-gate synchronization enabling signal transmitted by the time schedule controller. In the nth single-stage scanning period in the rotation scanning period, the output signal setting module selectively sets the nth column scanning state signal and the nth pixel grid signal according to the voltage of the intermediate end point. The round scanning period comprises N stages of single-stage scanning periods respectively corresponding to the N stages of gate drive circuits.

Description

Technical Field

[0001] The invention relates to a gate driver, and in particular to a gate driver that can be used with a gate built-in circuit technology. Background Art

[0002] See also Figure 1 , which is a schematic diagram of a display device. The display device 10 includes: a timing controller 103, a source driver 105, a gate driver 107, and a display panel 101. The type of the display panel 101 is not limited. For example, the display panel can be a cholesterol liquid crystal display panel or a general liquid crystal panel. The timing controller 103 is electrically connected to the source driver 105 and the gate driver 107, and the source driver 105 and the gate driver 107 are both electrically connected to the display panel 101.

[0003] This document uses an uppercase variable M to represent the total number of rows of the pixel array on the display panel, an uppercase variable N to represent the total number of columns of the pixel array on the display panel, and a lowercase variable n to represent one of the columns of the pixel array. Variables n, N, and M are all positive integers, and n≤N. In addition, to simplify the description, this document uses the same symbols to represent signal lines and signals transmitted on the signal lines. For example, after the timing controller 103 generates a gate driver control signal to the gate driver 107, the gate driver 107 will generate N-level pixel gate signals G[1]~G[N]. And the N-level pixel gate signals G[1]~G[N] are respectively transmitted to the display panel 101 through the pixel gate signal lines G[1]~G[N].

[0004] The pixel gate signal line G[n] is simultaneously connected to the M pixels located in the nth column in the pixel array. When the gate driver 107 controls the pixel gate signal G[n] to generate a pulse, the M pixels located in the nth column on the display panel 101 will be enabled synchronously. Therefore, the pixel gate signal G[n] can be seen as a signal used to enable the M pixel transistors PXL(1,n) to PXL(M,n) located in the nth column in the pixel array.

[0005] The connection method and signal control relationship between the timing controller 103, the source driver 105, the gate driver 107, and the display panel 101 are not described in detail herein. This article only focuses on the method in which the gate driver 107 generates N-level pixel gate signals G[1] to G[N].

[0006] See also Figure 2, which is a schematic diagram of a gate driver. The gate driver 107 includes: N gate driving circuits gtCKT[1]~gtCKT[N]. The gate driving circuits gtCKT[1]~gtCKT[N] are respectively used to generate N levels of pixel gate signals G[1]~G[N]. The gate driver control signals received by the gate driving circuits gtCKT[1]~gtCKT[N] from the timing controller 103 can be divided into two categories: one is the timing control signals of each level provided along with the N levels of different gate driving circuits gtCKT[1]~gtCKT[N]; the other is the synchronous timing control signals synchronously provided to the gate driving circuits gtCKT[1]~gtCKT[N]. In addition, the gate driving circuits gtCKT[1]~gtCKT[N] also simultaneously receive multiple constant voltages with different voltage values ​​(for example, supply voltage, ground voltage, etc.).

[0007] The pixel array is controlled with a frame period Tframe as the cycle. Figure 3 , which is a waveform diagram of N-level pixel gate signals G[1]~G[N] generated by the gate driver during the frame period Tframe when used with a cholesterol liquid crystal panel. Figure 3 The horizontal axis is time, and the vertical axis is the change of the N-level pixel gate signal G[1]~G[N]. The frame period Tframe is between time points t1~t10. The frame period Tframe includes: the positive reset period Reset+ between time points t1~t2, the negative reset period Reset- between time points t2~t3, the waiting period Wait between time points t3~t4, the common swing period (Com swing duration) ComSwing1 between time points t4~t5, the positive scan period Scan+ between time points t5~t6, the common swing period ComSwing2 between time points t6~t7, the negative scan period Scan- between time points t7~t8, the positive end period End+ between time points t8~t9, and the negative end period End- between time points t9~t10.

[0008] Depend on Figure 3 It can be seen that in the same frame period Tframe, there are some periods during which the N-level pixel gate signals G[1]~G[N] need to synchronously generate pulses. For example, the positive reset period Reset+, the negative reset period Reset-, the waiting period Wait, the common swing period Com swing, the positive end period End+, and the negative end period End-. This article refers to the period during which the N-level pixel gate signals G[1]~G[N] need to synchronously generate pulses as the full gate synchronization period (duration ofall gate one) DURall-sync.

[0009] On the other hand, in the same frame period Tframe, there are some periods when the pixel gate signals G[1]~G[N] need to generate pulses in sequence according to the order of columns n=1~N. For example, the positive scanning period Scan+. This article refers to the period when the N-level pixel gate signals G[1]~G[N] need to generate pulses in sequence as the round-robin scanning period DURall-scan.

[0010] When the gate driver generates N levels of pixel gate signals G[1]~G[N] for use in a general liquid crystal panel, the timing relationship is slightly different from that of a cholesterol liquid crystal panel. When a general liquid crystal panel is in a normal operation mode, the gate driver needs to control the pixel gate signals G[1]~G[N] to generate pulses in sequence according to the column order n=1~N during the frame period Tframe; and before the general liquid crystal panel is about to shut down, the gate driver needs to control the N levels of pixel gate signals G[1]~G[N] to generate pulses synchronously.

[0011] Although the gate driver does not drive a general LCD panel by repeatedly generating pulses and scanning in a synchronous manner during the frame period Tframe, its overall operation process can still be divided into two requirements: synchronous generation and reception of pulses and continuous scanning.

[0012] In order to provide users with a better visual experience, display devices are developing towards narrow-frame technology. To this end, display device manufacturers have begun to integrate gate drivers directly into thin-film transistor arrays. That is, a pixel array and a gate driver 107 are simultaneously provided on the display panel. This technology of providing a gate driver 107 on a display panel to save the area occupied by the screen frame is called a gate driver on array (GoA). In a display device using GoA technology, because the N-level pixel gate signals G[1]~G[N] are designed on the side of the display panel, the display device manufacturer cannot continue the past practice of directly receiving the N-level pixel gate signals G[1]~G[N] generated by the timing controller 103.

[0013] At present, the display device using GoA technology can only generate pulses on the N-level pixel gate signal lines G[1] to G[N] in sequence during the round-robin scanning period DURall-scan. However, the display device using GoA technology at present is still unable to synchronously generate pulses of the N-level pixel gate signals G[1] to G[N] during the full gate synchronization period DURall-sync. Therefore, the function of the display device using GoA technology at present is still not perfect. Summary of the invention

[0014] The present invention relates to a gate driver that can be used with GOA technology. The two embodiments provided in the present disclosure can control N-level pixel gate signals G[1]~G[N] to generate pulses in a synchronous or round-robin manner in response to the requirements of the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan.

[0015] According to one aspect of the present invention, a gate driver electrically connected to a timing controller is provided. The gate driver includes: N-level gate driving circuits. The n-th level gate driving circuit in the N-level gate driving circuit includes: an output signal setting module. The output signal setting module is electrically connected to the timing controller and the intermediate endpoint. During the full gate synchronization period, the N-level gate driving circuit synchronously sets the N-level pixel gate signal according to the full gate synchronization enable signal transmitted by the timing controller. During the n-level single-level scanning period in the continuous scanning period, the output signal setting module selectively sets the n-level column scanning state signal and the n-level pixel gate signal in the N-level pixel gate signal in response to the voltage of the intermediate endpoint. The continuous scanning period includes N-level single-level scanning periods corresponding to the N-level gate driving circuits respectively. n and N are positive integers, and n is less than or equal to N.

[0016] In order to better understand the above and other aspects of the present invention, embodiments are given below and described in detail with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 , which is a schematic diagram of a display device;

[0018] Figure 2 , which is a schematic diagram of a gate driver;

[0019] Figure 3 , which is a waveform diagram of N-level pixel gate signals G[1] to G[N] generated by the gate driver during one frame period Tframe when used with a cholesterol liquid crystal panel;

[0020] Figure 4 , which is a schematic diagram of various signals related to the first embodiment of the n-th stage gate driving circuit gtCKT[n] of the present disclosure;

[0021] Figure 5 , which is a block diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] of the present disclosure;

[0022] Figure 6 , which is a circuit diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure;

[0023] Figure 7, which is a waveform diagram of a signal related to the n-th stage pixel gate signal G[n] generated by the first embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure;

[0024] Figures 8A to 8C , which is a schematic diagram of the states of DURall-sync at different stages during the full gate synchronization period according to the first embodiment of the n-th stage gate driving circuit gtCKT[n] conceived by the present disclosure;

[0025] Figures 9A to 9D , which is a schematic diagram of the states of the n-stage gate driving circuit gtCKT[n] at different stages during the n-stage single-stage scanning period DURscan[n] according to the first embodiment of the disclosed concept;

[0026] Fig.10 , which is a schematic diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, and a method for reducing leakage current;

[0027] Fig.11 , which is a first embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, with two sets of voltage stabilizing circuit schematics;

[0028] Fig.12 , which is a schematic diagram of various signals related to the second embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure;

[0029] Fig.13 , which is a block diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] of the present disclosure;

[0030] Fig.14 , which is a circuit diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure;

[0031] Fig.15 , which is a waveform diagram of a signal related to the n-th stage pixel gate signal G[n] generated by a second embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure;

[0032] Figures 16A to 16C , which is a schematic diagram of the states of DURall-sync at different stages during the full gate synchronization period according to the second embodiment of the n-th stage gate driving circuit gtCKT[n] conceived by the present disclosure;

[0033] Figures 17A to 17C, which is a schematic diagram of the states of the n-th stage gate driving circuit gtCKT[n] at different stages during the n-th stage single-stage scanning period DURscan[n] according to the second embodiment of the disclosed concept;

[0034] Fig.18 , which is a schematic diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, and a method for reducing leakage current;

[0035] Fig.19 , which is a second embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, with two sets of voltage stabilizing circuit schematics; and

[0036] Fig. 20 , which is a schematic diagram of the n-th gate driving circuit gtCKT[n] proposed according to the present disclosure.

[0037] Wherein, the reference numerals are:

[0038] 10: Display device

[0039] 103: Timing controller

[0040] 107: Gate Driver

[0041] 105: Source driver

[0042] 101: Display Panel

[0043] G[1], G[n], G[N], G[n-1], G[n+1]: pixel gate signal (line)

[0044] gtCKT[1],gtCKT[n],gtCKT[N],gtCKT[np],gtCKT[nq],gtCKT[n+p],gtCKT[n+q]: Gate drive circuit

[0045] Tframe: frame period

[0046] Reset+: Positive reset period

[0047] Reset-: Negative reset period

[0048] Wait: Waiting period

[0049] ComSwing1, ComSwing2: shared swing period

[0050] Scan+: During positive scanning

[0051] Scan-: Negative scanning period

[0052] End+: Positive end period

[0053] End-: Negative end period

[0054] t1~t10: time point

[0055] ST[np]: (np)th level column scan status signal (line)

[0056] ST[n]: nth level column scan status signal (line)

[0057] ST[n+q]: (n+q)th level column scanning status signal (line)

[0058] HC[k]: Select signal (line) column by column

[0059] XON_C: Full gate synchronization period signal (line)

[0060] XON_S: Full gate synchronization enable signal (line)

[0061] rstST: Intermediary endpoint reset signal (line)

[0062] LC, LC-a, LC-b: Regulated terminal supply voltage (signal line)

[0063] VSSQ: Intermediate terminal ground voltage (signal line)

[0064] VSSG: pixel gate ground voltage (signal line)

[0065] VGHD: Gate supply voltage (signal line)

[0066] H: Positive voltage value

[0067] L-: minimum negative voltage value

[0068] L: The second lowest negative voltage value

[0069] ST[n-1]: (n-1)th level column scan status signal (line)

[0070] ST[n+1]: (n+1)th level column scan status signal (line)

[0071] C[n]: Capacitance

[0072] NDmd[n]: mediator endpoint

[0073] NDstb[n]: voltage regulation endpoint

[0074] nmuCKT[n]: intermediate endpoint pull-up circuit

[0075] ssCKT[n]: Status signal setting circuit

[0076] gsCKT[n]: Gate signal setting circuit

[0077] stbMDL[n],stbMDL-a[n],stbMDL-b[n]: voltage regulator module

[0078] stbsCKT[n]: voltage regulation endpoint setting circuit

[0079] stbCKT[n]: voltage stabilization circuit

[0080] nmdCKT[n]: Intermediary endpoint pull-down circuit

[0081] Tnmu[n]: intermediate terminal pull-up transistor

[0082] Tss[n]: Status signal setting transistor

[0083] Tgs1[n], Tgs2[n]: Gate signal setting transistor

[0084] Tf1[n], Tf2[n], Tf3[n], Tf4[n], Tf5[n], Tf6[n]: voltage regulator endpoint setting transistors Tnmstb[n], Tgstb[n], Tsstb[n]: voltage regulator transistors

[0085] Tnmd_nxt[n], Tnmd_xon[n]: intermediate endpoint pull-down transistor

[0086] Tnmd_rst[n]: Intermediary endpoint reset transistor

[0087] FM1,FM2,FM3,FM4: Select the dotted box

[0088] DURall-sync: Full gate synchronization period

[0089] DURscan[n]: duration of single-level scan at level n

[0090] STG-a1, STG-a2, STG-a3: Synchronization phase

[0091] STG-s1[n],STG-s2[n],STG-s3[n],STG-s4[n]: Scanning phase

[0092] ΔVc[n]: Capacitor voltage difference

[0093] NDints[n]: voltage regulation setting endpoint

[0094] lkgCNT_1a,lkgCNT_1b,lkgCNT_2a,lkgCNT_2b: line segment

[0095] L1a, L1b, L1c, L2a, L2b: dotted line segments DETAILED DESCRIPTION

[0096] The present invention is described in detail below with reference to the accompanying drawings and specific embodiments, but is not intended to limit the present invention.

[0097] The present disclosure aims to improve the problem that the existing technology cannot provide both the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan waveforms when using GoA. The following embodiments can be divided into two types. The first embodiment is shown in Figures 4 to 10 For the second embodiment, please refer to Figure 11~1 7. This article describes the circuit composition of the n-stage gate driving circuit gtCKT[n] of the two embodiments respectively, and illustrates the circuit behavior of the n-stage gate driving circuit gtCKT[n] with waveform diagrams. Both embodiments proposed in the present disclosure can be used with the GoA technology, and can generate pulses in the N-stage pixel gate signals G[1]~G[N] in a synchronous or alternating manner in response to the requirements of the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan.

[0098] As mentioned above, the gate driver 107 includes N gate drive circuits gtCKT[1] to gtCKT[N]. Since the internal components of the gate drive circuits [1] to gtCKT[N] are similar, the following description takes the nth gate drive circuit gtCKT[n] as an example. For ease of description, if the circuit elements or signals provided or generated individually for each column n=1 to N are individually set, the corresponding gate level will be distinguished by "[n]". If the circuit elements or signals are set simultaneously for each column n=1 to N, the additional [n] will not be marked.

[0099] According to the concept of the present disclosure, the circuit behavior of the n-th gate drive circuit gtCKT[n] is related to the gate drive circuits of the previous and next stages. In the following embodiments, variables (np) and (nq) are used to represent the previous gate drive circuit related to the n-th gate drive circuit gtCKT[n] (i.e., gate drive circuits gtCKT[np] and gtCKT[nq]); and variables (n+p) and (n+q) are used to represent the subsequent gate drive circuit related to the n-th gate drive circuit gtCKT[n] (i.e., gate drive circuits gtCKT[n+p] and gtCKT[n+q]). Wherein, n, p, and q are all positive integers, n≤N, and p and q may be equal or different.

[0100] For the sake of example, the following embodiments assume that (n+q)≤N, (n+p)≤N, 1≤(np), 1≤(nq). In actual applications, if (n+q)>N, (n+p)>N, 1>(np), 1>(nq), a timing controller is required to generate corresponding analog control signals. This application-specific change is not described in detail in this article.

[0101] First, Figures 4 to 11 The first embodiment of the present disclosure on how to design the n-th gate driving circuit gtCKT[n] is described. Figure 4 Interpret the signals related to the nth stage gate drive circuit gtCKT[n]; Figure 5 Explain the circuit composition inside the n-stage gate drive circuit gtCKT[n]; Figure 6 Explain the circuit elements and connection relationship of the n-th gate drive circuit gtCKT[n]; Figure 7 A waveform diagram is used to illustrate how the signals related to the n-th gate drive circuit gtCKT[n] change in response to the full gate synchronization period DURall-sync and the n-th single-stage scanning period DURscan[n]; Figures 8A to 8C illustrate Figure 5 The n-th gate drive circuit gtCKT[n] is in the state of the synchronization phases STG-a1, STG-a2, and STG-a3 in the full gate synchronization period DURall-sync; Figures 9A to 9D illustrate Figure 5 The n-th gate drive circuit gtCKT[n] is in the state of the scanning phases STG-s1[n], STG-s2[n], STG-s3[n], STG-s4[n] in the n-th single-stage scanning period DURscan[n]; Fig.10 Explain how to Figure 6 The n-th gate drive circuit gtCKT[n] improves the leakage current phenomenon; Fig.11 It is described how to set two sets of voltage stabilizing circuits in the n-th stage gate driving circuit gtCKT[n] of the first embodiment for the purpose of extending the life of the transistor.

[0102] See also Figure 4 , which is a schematic diagram of various signals related to the first embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure. Figure 4 In FIG. 1 , different types of signals are indicated by arrow directions. According to the different signal directions, the signals related to the n-th stage gate driver circuit gtCKT[n] can be divided into: input signals received from other circuits; and output signals transmitted to other circuits.

[0103] exist Figure 4In FIG. 1 , the input signals received by the gate drive circuit gtCKT[n] from the external circuit are located on the left side of the gate drive circuit gtCKT[n], and the arrows of these input signals are directed toward the gate drive circuit gtCKT[n]. The following briefly introduces each input signal and its purpose:

[0104] The (np)th column scanning state signal ST[np] is an input signal received by the nth gate driving circuit gtCKT[n] from the (np)th gate driving circuit gtCKT[np]; the (n+q)th column scanning state signal ST[n+q] is an input signal received by the nth gate driving circuit gtCKT[n] from the (n+q)th gate driving circuit gtCKT[n+q]; and the column selection signal (high level control signal) HC[k) received from the timing controller. The column selection signals HC[1] to HC[K] are control signals generated in turn according to different groups (kth group, k=1~K) after the timing controller groups N columns of pixel units (assuming that they are divided into K=2, 4, 6, ... groups). Variables k and K are positive integers, N is a multiple of K, and k≤K. For example, K=2, 4, 6...

[0105] Assuming that K=4, the timing controller sets the column-by-column selection signals HC[1] to HC[4] to the positive voltage value H in turn. For example, if the timing controller sets the column-by-column selection signal HC[1] to the positive voltage value H (HC[1]=H), the column-by-column selection signals HC[2] to HC[4] are set to the lowest negative voltage value L-(HC[2]=HC[3]=HC[4]=L); if the timing controller sets the column-by-column selection signal HC[2] to the positive voltage value H (HC[2]=H), the column-by-column selection signals HC[1], HC[3], and HC[4] are set to the lowest negative voltage value L (HC[1]=HC[3]=HC[4]=L), and so on.

[0106] Among them, the timing controller transmits the k=1th column-by-column selection signal HC[1] to the k=1th group of gate drive circuits gtCKT[1], gtCKT[1+K*1], gtCKT[1+K*2], etc.; transmits the k=2th column-by-column selection signal HC[2] to the k=2th group of gate drive circuits gtCKT[2], gtCKT[2+K*1], gtCKT[2+K*2], etc.; transmits the k=3th column-by-column selection signal HC[3] to the k=3th group of gate drive circuits gtCKT[3], gtCKT[3+K*1], gtCKT[3+K*2], etc.; and transmits the k=4th column-by-column selection signal HC[4] to the k=4th group of gate drive circuits gtCKT[4], gtCKT[4+K*1], gtCKT[4+K*2], etc.

[0107] According to the concept disclosed herein, when the intermediate terminal NDmd[n] is a positive voltage value H (NDmd[n]=H), the voltage of the n-th level pixel gate signal G[n] and the n-th level column scan state signal ST[n] is determined according to the column-by-column selection signal HC[k]. Moreover, the timing controller sets the column-by-column selection signal HC[k] to a positive voltage value H (HC[k]=H) during the scan stage STG-s2[n] in the n-th level single-level scan period DURscan[n]. Accordingly, the timing controller only needs to provide K column-by-column selection signals HC[1]~HC[K] as scan pulses for generating the n-th level pixel gate signal G[n]. By cyclically generating pulses, the number of input signals required for the timing controller to set the n-th level pixel gate signal G[n] to generate scan pulses can be reduced.

[0108] The change of the signal XON_C and the signal XON_S during the full gate synchronization period will be described below. Please also note that the intermediate terminal reset signal rstST is used when the display panel switches frames. That is, the intermediate terminal reset signal rstST is maintained at the lowest negative voltage value L- (for example, -12V) during the frame period Tframe, and is only at the positive voltage value H during the boundary period between the two previous and next frame periods. Therefore, the intermediate terminal reset signal rstST will not affect the circuit behavior of the gate drive circuit gtCKT[n] during the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan.

[0109] The regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD received from the voltage source or the timing controller have constant voltage values. Herein, H represents a positive voltage value, L- represents a lowest negative voltage value (e.g., -12V), and L represents a second lowest negative voltage value (e.g., -9V). Wherein, H>L>L-. In the third type of input signal received by the n-th stage gate driving circuit gtCKT[n], the regulated terminal supply voltage LC is equal to a positive voltage value (LC=H), the intermediate terminal ground voltage VSSQ is equal to a lowest negative voltage value L- (VSSQ=L-), the pixel gate ground voltage VSSG is equal to a second lowest negative voltage value L (VSSG=L), and the gate supply voltage VGHD is equal to a positive voltage value H (VGHD=H).

[0110] The input signal received by the n-th gate drive circuit gtCKT[n] can be classified according to signal purpose, signal characteristics, or whether it changes with the n=1 to N-th stages. Table 1 summarizes the classification of input signals in different ways.

[0111] Table 1

[0112]

[0113]

[0114] When classified according to the purpose, the input signal area can be roughly divided into two categories: the first is the input signal used to control whether the transistor is turned on or not (including: the (np)th column scanning state signal ST[np], the (n+q)th column scanning state signal ST[n+q], the full gate synchronization period signal XON_C, and the intermediate terminal reset signal rstST); the second is the input signal that changes the voltage of the internal terminal or output signal as the transistor is turned on (including: the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD). Please also note that the regulated terminal supply voltage LC can be used to control whether the transistor is turned on or not, and can also be used to change the internal terminal. Therefore, the regulated terminal supply voltage LC belongs to both types.

[0115] When classified according to signal characteristics, input signals can be divided into two categories: one is an input signal with a non-constant voltage (the logic level will change) (including: the (np)th level column scanning status signal ST[np], the (n+q)th level column scanning status signal ST[n+q], the full gate synchronization period signal XON_C, and the intermediate terminal reset signal rstST, the column-by-column selection signal HC[k], and the full gate synchronization enable signal XON_S); the other is an input signal with a constant voltage (including: the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD).

[0116] When classified according to whether the input signals change with the n=1 to N levels, the input signals can be divided into two categories: one is the input signals that change with the n=1 to N levels (including: the (np)th level column scanning state signal ST[np], the (n+q)th level column scanning state signal ST[n+q], and the column-by-column selection signal HC[k]); the other is the input signals that do not change with the n=1 to N levels (including: the full gate synchronization period signal XON_C, the intermediate endpoint reset signal rstST, the full gate synchronization enable signal XON_S, the regulated endpoint supply voltage LC, the intermediate endpoint ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD).

[0117] exist Figure 4In FIG. 1 , the output signal transmitted from the gate driving circuit gtCKT[n] to the external circuit is located on the right side of the gate driving circuit gtCKT[n], and the arrow direction of the output signal is emitted from the gate driving circuit gtCKT[n]. The output signal generated by the n-th stage gate driving circuit gtCKT[n] includes: the n-th stage column scanning state signal ST[n] and the n-th stage pixel gate signal G[n].

[0118] The nth-stage gate driving circuit gtCKT[n] transmits the nth-stage column scanning state signal ST[n] to the (nq)th-stage gate driving circuit gtCKT[nq] and the (n+p)th-stage gate driving circuit gtCKT[n+p]. In addition, the nth-stage gate driving circuit gtCKT[n] transmits the nth-stage pixel gate signal G[n] to the M pixel transistors PXL(1,n) to PXL(M,n) in the nth row in the pixel array.

[0119] See also Figure 5 , which is a block diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] of the present disclosure. Figure 5 It can be seen that the n-th gate driving circuit gtCKT[n] includes: an output signal setting module outSetMDL[n], an intermediate endpoint setting module nmSetMDL[n], and a voltage stabilization module stbMDL[n].

[0120] The output signal setting module outSetMDL[n] further includes: a state signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The intermediate endpoint setting module nmSetMDL[n] further includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n] and an intermediate endpoint pull-down circuit nmdCKT[n]. The voltage regulator module stbMDL[n] further includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] electrically connected to each other.

[0121] The circuit elements in the output signal setting module outSetMDL[n] are all related to the voltage of the output signal (the n-th pixel gate signal G[n] and / or the n-th column scanning state signal ST[n]). The circuit elements in the intermediate terminal setting module nmSetMDL[n] are all related to the voltage of the intermediate terminal NDmd[n]. The circuit elements in the voltage regulating module stbMDL[n] are all related to the voltage of the voltage regulating terminal NDstb[n].

[0122] Please also see Figure 4 , 5 .Apart from Figure 4 In addition to the input and output signals related to other circuit elements, Figure 5 The terminals located inside the n-th gate driving circuit gtCKT[n] are also shown, for example, the intermediate terminal NDmd[n] and the voltage regulating terminal NDstb[n].

[0123] In the intermediate terminal setting module nmSetMDL[n], one end of the capacitor C[n] is electrically connected to the intermediate terminal NDmd[n], and the other end is electrically connected to the n-th level pixel gate signal line G[n]. The intermediate terminal pull-up circuit nmuCKT[n] receives the gate supply voltage VGHD and the (np)-th level column scanning state signal ST[np], and the intermediate terminal pull-up circuit nmuCKT[n] is electrically connected to the intermediate terminal NDmd[n].

[0124] In the output signal setting module outSetMDL[n], the state signal setting circuit ssCKT[n] receives the column-by-column selection signal HC[k], and the state signal setting circuit ssCKT[n] is electrically connected to the intermediate terminal NDmd[n] and the n-th level column scanning state signal line ST[n]. The gate signal setting circuit gsCKT[n] receives the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S and the full gate synchronization period signal XON_C, and the gate signal setting circuit gsCKT[n] is electrically connected to the intermediate terminal NDmd[n] and the n-th level pixel gate signal line G[n].

[0125] In the voltage regulating module stbMDL[n], the voltage regulating endpoint setting circuit stbsCKT[n] receives the voltage regulating endpoint supply voltage LC, the intermediate endpoint ground voltage signal line VSSQ and the full gate synchronization period signal XON_C, and the voltage regulating endpoint setting circuit stbsCKT[n] is electrically connected to the intermediate endpoint NDmd[n] and the voltage regulating endpoint NDstb[n]. On the other hand, the voltage regulating circuit stbCKT[n] receives the intermediate endpoint ground voltage VSSQ and the pixel gate ground voltage VSSG, and the voltage regulating circuit stbCKT[n] is electrically connected to the voltage regulating endpoint NDstb[n], the intermediate endpoint NDmd[n], the n-th column scanning state signal line ST[n] and the n-th pixel gate signal line G[n]. In addition, the intermediate terminal pull-down circuit nmdCKT[n] receives the (n+q)th level column scan status signal ST[n+q], the intermediate terminal ground voltage signal line VSSQ, the full gate synchronization period signal XON_C, and the intermediate terminal reset signal line rstST, and the intermediate terminal pull-down circuit nmdCKT[n] is electrically connected to the intermediate terminal NDmd[n].

[0126] See also Figure 6 , which is a circuit diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure. Please also refer to Figure 5 , 6For ease of explanation, Figure 6 In it is assumed that p=1 and q=1.

[0127] Based on this assumption, the nth-level gate drive circuit gtCKT[n] receives the (np)=(n-1)th-level column scan status signal ST[np]=ST[n-1] from the (np)=(n-1)th-level gate drive circuit gtCKT[np]=gtCKT[n-1]; and receives the (n+q)=(n+1)th-level column scan status signal ST[n+q]=ST[n+1] from the (n+q)=(n+1)th-level gate drive circuit gtCKT[n+q]=gtCKT[n+1]. In addition, the nth-level gate drive circuit gtCKT[n] transmits the nth-level column scan status signal ST[n] to the (nq)=(n-1)th-level gate drive circuit gtCKT[nq]=gtCKT[n-1]; and transmits the nth-level column scan status signal ST[n] to the (n+p)=(n+1)th-level gate drive circuit gtCKT[n+p]=gtCKT[n+1].

[0128] The following first describes the composition of the circuit elements in the intermediate endpoint setting module nmSetMDL[n], the output signal setting module outSetMDL[n] and the voltage regulation module stbMDL[n]. Then, the circuit elements related to each signal are described according to the different types of signals.

[0129] The intermediate endpoint setting module nmSetMDL[n] includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n], and an intermediate endpoint pull-down circuit nmdCKT[n]. The intermediate endpoint pull-up circuit nmuCKT[n] includes: an intermediate endpoint pull-up transistor Tnmu[n]; and the intermediate endpoint pull-down circuit nmdCKT[n] includes: intermediate endpoint pull-down transistors Tnmd_nxt[n], Tnmd_xon[n], and an intermediate endpoint reset transistor Tnmd_rst[n]. The following describes the connection method of the transistors in the intermediate endpoint pull-up circuit nmuCKT[n] and the intermediate endpoint pull-down circuit nmdCKT[n].

[0130] In the intermediate node pull-up circuit nmuCKT[n], the drain terminal of the intermediate node pull-up transistor Tnmu[n] receives the gate supply voltage VGHD, the control terminal receives the (n-1)th stage column scanning state signal ST[n-1], and the source terminal is electrically connected to the intermediate node NDmd[n]. Accordingly, the on / off state of the intermediate node pull-up transistor Tnmu[n] depends on the voltage of the (n-1)th stage column scanning state signal ST[n-1]. When the intermediate node pull-up transistor Tnmu[n] is turned on, the positive voltage value H (VGHD=H) of the gate supply voltage VGHD is transmitted to the intermediate node NDmd[n].

[0131] In the intermediate terminal pull-down circuit nmdCKT[n], the drain terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal receives the (n+1)th stage column scan state signal ST[n+1], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ. The drain terminal of the intermediate terminal pull-down transistor Tnmd_xon[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal receives the full gate synchronization period signal XON_C, and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ. The drain terminal of the intermediate terminal reset transistor Tnmd_rst[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal receives the intermediate terminal reset signal rstST, and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ.

[0132] Accordingly, the on / off state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th stage column scanning state signal ST[n+1]. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on, the intermediate terminal pull-down transistor Tnmd_nxt[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0133] In addition, the on / off state of the intermediate terminal pull-down transistor Tnmd_xon[n] depends on the full gate synchronization period signal XON_C. When the intermediate terminal pull-down transistor Tnmd_xon[n] is turned on, the intermediate terminal pull-down transistor Tnmd_xon[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0134] Furthermore, the on / off state of the intermediate node reset transistor Tnmd_rst[n] depends on the intermediate node reset signal rstST. When the intermediate node reset transistor Tnmd_rst[n] is turned on, the intermediate node reset transistor Tnmd_rst[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate node ground voltage VSSQ to the intermediate node NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0135] Please also note that, since the intermediate terminal reset signal rstST issued by the timing controller is the lowest negative voltage value L- (rstST = L-) during the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan, the intermediate terminal reset transistor Tnmd_rst[n] remains in the disconnected state during the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan. Therefore, when explaining the circuit behavior later, the intermediate terminal reset transistor Tnmd_rst[n] will not be repeatedly drawn.

[0136] The output signal setting module outSetMDL[n] includes: a state signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The state signal setting circuit ssCKT[n] includes: a state signal setting transistor Tss[n]); and the gate signal setting circuit gsCKT[n] includes: gate signal setting transistors Tgs1[n] and Tgs2[n].

[0137] In the state signal setting circuit ssCKT[n], the drain terminal of the state signal setting transistor Tss[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the n-th column scanning state signal line ST[n]. Accordingly, the on / off state of the state signal setting transistor Tss[n] depends on the voltage of the intermediate terminal NDmd[n]. When the state signal setting transistor Tss[n] is turned on, the voltage of the column-by-column selection signal HC[k] is transmitted to the n-th column scanning state signal ST[n]. That is, ST[n]=HC[k].

[0138] In the gate signal setting circuit gsCKT[n], the drain terminal of the gate signal setting transistor Tgs1[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the n-th level pixel gate signal line G[n]; and, the drain terminal of the gate signal setting transistor Tgs2[n] receives the full gate synchronization enable signal XON_S, the control terminal receives the full gate synchronization period signal XON_C, and the source terminal is electrically connected to the n-th level pixel gate signal line G[n].

[0139] Accordingly, the on / off state of the gate signal setting transistor Tgs1[n] depends on the voltage of the intermediate terminal NDmd[n]. When the gate signal setting transistor Tgs1[n] is turned on, the voltage of the column-by-column selection signal HC[k] is transmitted to the n-th pixel gate signal line G[n]. That is, G[n]=HC[k]. On the other hand, the on / off state of the gate signal setting transistor Tgs2[n] depends on the voltage of the signal XON_C during the full gate synchronization. When the gate signal setting transistor Tgs2[n] is turned on, the voltage of the full gate synchronization enable signal XON_S is transmitted to the n-th pixel gate signal line G[n]. That is, G[n]=XON_S.

[0140] The voltage regulator module stbMDL[n] includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] electrically connected to each other. The voltage regulator endpoint setting circuit stbsCKT[n] includes: voltage regulator endpoint setting transistors Tf1[n], Tf2[n], Tf3[n], Tf4[n], Tf5[n], Tf6[n]; the voltage regulator circuit stbCKT[n] includes: voltage regulator transistors Tnmstb[n], Tgstb[n], Tsstb[n].

[0141] In the voltage regulation endpoint setting circuit stbsCKT[n], the drain terminal and the gate terminal of the voltage regulation endpoint setting transistor Tf1[n] both receive the voltage regulation endpoint supply voltage LC, and the source terminal is electrically connected to the voltage regulation setting endpoint NDints[n]. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf1[n] depends on the voltage regulation endpoint supply voltage LC. In this article, it is assumed that the voltage regulation endpoint supply voltage LC is continuously a positive voltage value. Therefore, the voltage regulation endpoint setting transistor Tf1[n] continuously maintains the on state and transmits the positive voltage value H (LC=H) of the voltage regulation endpoint supply voltage LC to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=LC=H.

[0142] The drain terminal of the voltage regulation endpoint setting transistor Tf2[n] is electrically connected to the voltage regulation setting endpoint NDints[n], the control terminal is electrically connected to the intermediate endpoint NDmd[n], and the source terminal is electrically connected to the intermediate endpoint ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf2[n] depends on the voltage of the intermediate endpoint NDmd[n]. When the voltage regulation endpoint setting transistor Tf2[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=VSSQ=L-.

[0143] The drain terminal of the voltage regulation endpoint setting transistor Tf3[n] receives the voltage regulation endpoint supply voltage LC, the control terminal is electrically connected to the voltage regulation setting endpoint NDints[n], and the source terminal is electrically connected to the voltage regulation endpoint NDstb[n]. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf3[n] depends on the voltage of the voltage regulation setting endpoint NDints[n]. When the voltage regulation endpoint setting transistor Tf3[n] is turned on, the positive voltage value H (LC=H) of the voltage regulation endpoint supply voltage LC is transmitted to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=LC=H.

[0144] The drain terminal of the voltage regulation endpoint setting transistor Tf4[n] is electrically connected to the voltage regulation endpoint NDstb[n], the control terminal is electrically connected to the intermediate endpoint NDmd[n], and the source terminal is electrically connected to the intermediate endpoint ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf4[n] depends on the voltage of the intermediate endpoint NDmd[n]. When the voltage regulation endpoint setting transistor Tf4[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=VSSQ=L-.

[0145] The drain of the voltage regulation endpoint setting transistor Tf5[n] is electrically connected to the voltage regulation setting endpoint NDints[n], the control end is electrically connected to the full gate synchronization period signal XON_C, and the source end is electrically connected to the intermediate endpoint ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf5[n] depends on the voltage of the full gate synchronization period signal XON_C. When the voltage regulation endpoint setting transistor Tf5[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=VSSQ=L-.

[0146] The drain terminal of the voltage regulation endpoint setting transistor Tf6[n] is electrically connected to the voltage regulation endpoint NDstb[n], the control terminal is electrically connected to the full gate synchronization period signal XON_C, and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf6[n] depends on the voltage of the full gate synchronization period signal XON_C. When the voltage regulation endpoint setting transistor Tf6[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=VSSQ=L-.

[0147] In the voltage regulator circuit stbCKT[n], the drain terminal of the voltage regulator transistor Tnmstb[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ; the drain terminal of the voltage regulator transistor Tgstb[n] is electrically connected to the n-th level pixel gate signal line G[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the pixel gate ground voltage signal line VSSG; the drain terminal of the voltage regulator transistor Tsstb[n] is electrically connected to the n-th level column scan status signal line ST[n], the control terminal is electrically connected to the voltage regulator terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ.

[0148] The on / off states of the voltage stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] all depend on the voltage of the voltage stabilizing terminal NDstb[n]. When the voltage stabilizing transistor Tnmstb[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-. When the voltage stabilizing transistor Tgstb[n] is turned on, the second lowest negative voltage value L (VSSG=L) of the pixel gate ground voltage VSSG is transmitted to the n-th level pixel gate signal line G[n]. That is, G[n]=VSSQ=L-. When the voltage stabilizing transistor Tsstb[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the n-th level column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0149] The above describes the circuit elements and connection relationship within the n-th gate drive circuit gtCKT[n]. Next, according to the signal type related to the n-th gate drive circuit gtCKT[n], the circuit elements related to each signal are described. The internal signals of the n-th gate drive circuit gtCKT[n] include: signals at the intermediate terminal NDmd[n], the voltage setting terminal NDints[n], and the voltage regulating terminal NDstb[n]. Next, the transistors related to these internal signals are described in sequence.

[0150] Depend on Figure 6 It can be seen that, according to the different connection methods, the transistors electrically connected to the internal terminals can be divided into two categories: the first category is the transistors electrically connected to the internal terminals through the control terminal (i.e., the transistors controlled by the internal terminals); and the second category is the transistors electrically connected to the internal terminals through the drain terminal or the source terminal. Table 2 summarizes the transistors connected to each internal terminal (i.e., the transistors that change the voltage of the internal terminal).

[0151] Table 2

[0152]

[0153] Next, the circuit elements related to the input signals of the n-th gate driving circuit gtCKT[n] are described. As mentioned above, the input signals of the n-th gate driving circuit gtCKT[n] include: the (n+1)-th column scanning state signal ST[n+1], the (n-1)-th column scanning state signal ST[n-1], the column selection signal HC[k], the full gate synchronization period signal XON_C, the full gate synchronization enable signal XON_S, the intermediate terminal reset signal rstST, the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD.

[0154] Depend on Figure 6 It can be seen that the (n-1)th column scanning state signal line ST[n-1] is electrically connected to the control end of the intermediate endpoint pull-up transistor Tnmu[n]. Therefore, the conduction state of the intermediate endpoint pull-up transistor Tnmu[n] depends on the (n-1)th column scanning state signal ST[n-1]. In addition, the (n+1)th column scanning state signal line ST[n+1] is electrically connected to the control end of the intermediate endpoint pull-down transistor Tnmd_nxt[n]. Therefore, the conduction state of the intermediate endpoint pull-down transistor Tnmd_nxt[n] depends on the (n+1)th column scanning state signal ST[n+1].

[0155] Depend on Figure 6 It can be seen that the column-by-column selection signal line HC[k] is electrically connected to the drain terminal of the state signal setting transistor Tss[n] and the drain terminal of the gate signal setting transistor Tgs1[n]. Accordingly, when the state signal setting transistor Tss[n] is turned on, the state signal setting transistor Tss[n] will conduct the column-by-column selection signal HC[k] to the n-th column scanning state signal line ST[n], so that the voltage of the n-th column scanning state signal line ST[n] is equal to the voltage of the column-by-column selection signal HC[k]. Moreover, when the gate signal setting transistor Tgs1[n] is turned on, the gate signal setting transistor Tgs1[n] will conduct the column-by-column selection signal HC[k] to the n-th pixel gate signal line G[n], so that the voltage of the n-th pixel gate signal line G[n] is equal to the voltage of the column-by-column selection signal HC[k]. That is, G[n]=HC[k].

[0156] Depend on Figure 6It can be seen that the full gate synchronization period signal XON_C is electrically connected to the control end of the voltage regulation endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n]. Therefore, the conduction state of the voltage regulation endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] depends on the voltage of the full gate synchronization period signal XON_C.

[0157] Depend on Figure 6 It can be seen that the full gate synchronous enable signal line XON_S is electrically connected to the drain terminal of the gate signal setting transistor Tgs2[n]. Accordingly, when the gate signal setting transistor Tgs2[n] is turned on, the gate signal setting transistor Tgs2[n] will conduct the full gate synchronous enable signal XON_S to the n-th level pixel gate signal line G[n], so that the voltage of the n-th level pixel gate signal G[n] is equal to the voltage of the full gate synchronous enable signal XON_S. That is, G[n]=XON_S.

[0158] Depend on Figure 6 It can be seen that the intermediate terminal reset signal rstST is electrically connected to the control terminal of the intermediate terminal reset transistor Tnmd_rst[n]. Accordingly, the conduction state of the intermediate terminal reset transistor Tnmd_rst[n] depends on the voltage of the intermediate terminal reset signal rstST. When the intermediate terminal reset signal rstST is set to a positive voltage value H (rstST=H) by the timing controller, so that the intermediate terminal reset transistor Tnmd_rst[n] is turned on, the intermediate terminal reset transistor Tnmd_rst[n] conducts the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ.

[0159] Depend on Figure 6 It can be seen that the voltage regulator terminal supply voltage LC is electrically connected to the drain and control terminal of the voltage regulator terminal setting transistor Tf1[n], and is electrically connected to the drain of the voltage regulator terminal setting transistor Tf3[n]. Since the voltage regulator terminal supply voltage LC is maintained at a positive voltage value H (LC=H), the voltage regulator terminal setting transistor Tf1[n] remains turned on. Moreover, when the voltage regulator terminal setting transistor Tf3[n] is turned on, the voltage regulator terminal supply voltage LC is transmitted to the voltage regulator terminal NDstb[n], so that the voltage regulator terminal NDstb[n] is equal to the positive voltage value H. That is, NDstb[n]=LC=H.

[0160] Depend on Figure 6It can be seen that the intermediate terminal ground voltage VSSQ is electrically connected to the sources of the voltage regulating terminal setting transistors Tf5[n], Tf6[n], Tf2[n], Tf4[n], the voltage regulating transistors Tnmstb[n], Tsstb[n], the intermediate terminal pull-down transistor Tnmd_nxt[n], the intermediate terminal reset transistor Tnmd_rst[n], and the intermediate terminal pull-down transistor Tnmd_xon[n]. Accordingly, when the voltage regulating terminal setting transistors Tf5[n] and Tf2[n] are turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the voltage regulating setting terminal NDints[n]. That is, NDints[n]=VSSQ=L-. When the voltage regulating terminal setting transistors Tf6[n] and Tf4[n] are turned on, the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the voltage regulating terminal NDstb[n]. That is, NDstb[n]=VSSQ=L-. When any one of the voltage regulating transistor Tnmstb[n], the intermediate terminal pull-down transistors Tnmd_nxt[n], Tnmd_xon[n] and the intermediate terminal reset transistor Tnmd_rst[n] is turned on, the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the intermediate terminal NDmd[d]. That is, NDmd[d]=VSSQ=L-. When the voltage regulating transistor Tsstb[n] is turned on, the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the n-th stage column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0161] Depend on Figure 6 It can be seen that the pixel gate ground voltage VSSG is electrically connected to the source of the voltage stabilizing transistor Tgstb[n]. Accordingly, when the voltage stabilizing transistor Tgstb[n] is turned on, the voltage stabilizing transistor Tgstb[n] conducts the second lowest negative voltage value L (VSSG=L) of the pixel gate ground voltage VSSG to the n-th pixel gate signal line G[n]. That is, G[n]=VSSG=L.

[0162] Depend on Figure 6 It can be seen that the gate supply voltage VGHD is electrically connected to the drain of the intermediate node pull-up transistor Tnmu[n]. Therefore, when the intermediate node pull-up transistor Tnmu[n] is turned on, the intermediate node pull-up transistor Tnmu[n] transmits the positive voltage value H (VGHD=H) of the gate supply voltage VGHD to the intermediate node NDmd[n]. That is, NDmd[n]=VGHD=H.

[0163] The output signals of the n-th gate driving circuit gtCKT[n] are: the n-th column scanning state signal ST[n], the n-th pixel gate signal G[n]. Table 3 summarizes the circuit elements related to the output signals of the n-th gate driving circuit gtCKT[n].

[0164] Table 3

[0165]

[0166]

[0167] See also Figure 7 , which is a waveform diagram of a signal related to the n-th level pixel gate signal G[n] generated by a first embodiment of the n-th level gate driving circuit gtCKT[n] according to the present disclosure. Figure 7 The horizontal axis is time, and the vertical axis is the signal related to the n-th level pixel gate signal G[n]. Figure 7 In the figure, the dotted box FM1 represents the change of the signal related to the n-th level pixel gate signal G[n] during the full gate synchronization period DURall-sync (between time points t1 and t4); the dotted box FM2 represents the change of the signal related to the n-th level pixel gate signal G[n] during the n-th level single-level scanning period DURscan[n] (between time points t5 and t9).

[0168] The full gate synchronization period DURall-sync further includes three synchronization stages STG-a1, STG-a2, and STG-a3. The synchronization stage STG-a1 is between time points t1 and t2, the synchronization stage STG-a2 is between time points t2 and t3, and the synchronization stage STG-a3 is between time points t3 and t4. For the N-level gate drive circuits gtCKT[1]~gtCKT[N], the circuit behavior of DURall-sync during the full gate synchronization period is consistent (G[1]=…=G[N]). According to the concept of the present disclosure, the N-level pixel gate signals G[1]~G[N] will be simultaneously set to a positive voltage value H (G[1]=…=G[N]=H) in the synchronization stage STG-a2; and, in the synchronization stages STG-a1 and STG-a3, they will be simultaneously set to the second lowest negative voltage value L (G[1]=…=G[N]=L). Accordingly, the M*N pixel transistors PXL(1,1)~PXL(M,N) in the pixel array will synchronously receive the pulses of the N-level pixel gate signals G[1]~G[N] and be turned on at the same time. Therefore, the synchronous stage STG-a2 can also be called the all gate-on duration.

[0169] According to the disclosed concept, the period of the round-robin scanning period DURall-scan covers a total of N single-level scanning periods DURscan[1] to DURscan[N]. Among them, the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] includes four scanning stages: scanning stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n]. Figure 7 In the figure, the scanning stage STG-s1[n] is between the time points t5 and t6, the scanning stage STG-s2[n] is between the time points t6 and t7, the scanning stage STG-s3[n] is between the time points t7 and t8, and the scanning stage STG-s4[n] is between the time points t8 and t9.

[0170] Table 4 summarizes Figure 7 In the diagram, the voltage of each signal changes at different stages.

[0171]

[0172]

[0173] Depend on Figure 7 As can be seen from Table 4, the n-th pixel gate signal G[n] is set to a positive voltage value in the synchronization phase STG-a2 and the scanning phase STG-s2[n], and is set to the second lowest negative voltage value L or the lowest negative voltage value L- in the remaining synchronization phases STG-a1, STG-a3 and the scanning phases STG-s1[n], STG-s3[n], STG-s4[n]. It can be seen that the gate drive circuit gtCKT[n] generates synchronization pulses synchronously with other gate drive circuits gtCKT[1]~gtCKT[n-1], gtCKT[n+1]~gtCKT[N] in the synchronization phase STG-a2, and the gate drive circuit gtCKT[n] generates a scanning pulse in the n-th pixel gate signal G[n] in the scanning phase STG-s2[n] of the n-th single-stage scanning period DURscan[n].

[0174] According to the concept disclosed in the present invention, the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] will partially overlap with the single-level scanning periods DURscan[n-3], DURscan[n-2], DURscan[n-1], DURscan[n+1], DURscan[n+2], and DURscan[n+3] of the three previous and subsequent levels. Therefore, the period of the round-robin scanning period DURall-scan is equivalent to the period of (N+6) scanning stages. The following describes one by one the periods that overlap with the scanning stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n] in the n-level single-level scanning period DURscan[n], and the scanning stages respectively included in the other single-level scanning periods DURscan[n-3] to DURscan[n+3].

[0175] The scanning phase STG-s1[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s4[n-3] of the (n-3)-level single-level scanning period DURscan[n-3] corresponding to the (n-3)-level gate drive circuit gtCKT[n-3]; the scanning phase STG-s3[n-2] of the (n-2)-level single-level scanning period DURscan[n-2] corresponding to the (n-2)-level gate drive circuit gtCKT[n-2] overlaps; and the scanning phase STG-s2[n-1] of the (n-1)-level single-level scanning period DURscan[n-1] corresponding to the (n-1)-level gate drive circuit gtCKT[n-1] overlaps.

[0176] The scanning phase STG-s2[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s4[n-2] of the (n-2)-level single-level scanning period DURscan[n-2] corresponding to the (n-2)-level gate drive circuit gtCKT[n-2]; the scanning phase STG-s3[n-1] of the (n-1)-level single-level scanning period DURscan[n-1] corresponding to the (n-1)-level gate drive circuit gtCKT[n-1] overlaps; and the scanning phase STG-s1[n+1] of the (n+1)-level single-level scanning period DURscan[n+1] corresponding to the (n+1)-level gate drive circuit gtCKT[n+1] overlaps.

[0177] The scanning stage STG-s3[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning stage STG-s4[n-1] of the (n-1)-level single-level scanning period DURscan[n-1] corresponding to the (n-1)-level gate drive circuit gtCKT[n-1]; the scanning stage STG-s2[n+1] of the (n+1)-level single-level scanning period DURscan[n+1] corresponding to the (n+1)-level gate drive circuit gtCKT[n+1] overlaps; and the scanning stage STG-s1[n+2] of the (n+2)-level single-level scanning period DURscan[n+2] corresponding to the (n+2)-level gate drive circuit gtCKT[n+2] overlaps.

[0178] The scanning stage STG-s4[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning stage STG-s3[n+1] of the (n+1)-level single-level scanning period DURscan[n+1] corresponding to the (n+1)-level gate drive circuit gtCKT[n+1]; the scanning stage STG-s2[n+2] of the (n+2)-level single-level scanning period DURscan[n+2] corresponding to the (n+2)-level gate drive circuit gtCKT[n+2] overlaps; and, the scanning stage STG-s1[n+3] of the (n+3)-level single-level scanning period DURscan[n+3] corresponding to the (n+3)-level gate drive circuit gtCKT[n+3] overlaps.

[0179] As mentioned above, the input signals received by the n-th stage gate driver circuit gtCKT[n] can be divided into two categories. One type of input signal has a constant voltage value, and the other type of input signal has a logic level that varies with the various stages of the full gate synchronization period DURall-sync and the n-th stage single-stage scanning period DURscan[n]. The former includes: a regulated terminal supply voltage LC with a positive voltage value H, an intermediate terminal ground voltage VSSQ with a lowest negative voltage value L-, a pixel gate ground voltage VSSG with a second lowest negative voltage value L, and a gate supply voltage VGHD with a positive voltage value H. The latter includes: the (n-1)-th stage column scanning state signal ST[n-1], the (n+1)-th stage column scanning state signal ST[n+1], a column-by-column selection signal HC[k], a full gate synchronization enable signal XON_S, and a full gate synchronization period signal XON_C. The logic level of the input signal changes with different stages, and the internal signal and output signal of the n-th stage gate driver circuit gtCKT[n] change accordingly.

[0180] Among the input signals that change logic levels, the present disclosure assumes that the high logic level of the (n-1)th column scan state signal ST[n-1], the (n+1)th column scan state signal ST[n+1], and the column-by-column selection signal HC[k] all correspond to the positive voltage value H, and the low logic level all corresponds to the lowest negative voltage value L-. Also, it is assumed that the high logic level of the full gate synchronous enable signal XON_S corresponds to the positive voltage value H.

[0181] Please also note that the low logic level of the full gate synchronous enable signal XON_S corresponds to a negative voltage value, and the negative voltage value can be determined according to the product requirements of the display panel. To simplify the description, it is assumed here that in the first embodiment, the low logic level of the full gate synchronous enable signal XON_S corresponds to the second lowest negative voltage value L. In actual application, the negative voltage value corresponding to the low logic level of the full gate synchronous enable signal XON_S can also be the lowest negative voltage value L-or other selected negative voltage values.

[0182] The following uses Figures 8A to 8C and Figures 9A to 9D The present invention describes how the n-th gate driver circuit gtCKT[n] changes the conduction state of its internal transistors during the full gate synchronization period DURall-sync and the n-th single-stage scanning period DURscan[n] in response to changes in the (n-1)-th column scanning state signal ST[n-1], the (n+1)-th column scanning state signal ST[n+1], the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C, and how the internal signals and output signals generated by the n-th gate driver circuit gtCKT[n] are affected and changed.

[0183] See also Figures 8A to 8C , which is a schematic diagram of the states of the n-stage gate driver circuit gtCKT[n] at different stages during the full gate synchronization period DURall-sync according to the first embodiment of the disclosed concept. The following does not specifically describe input signals with fixed voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD, but only describes the influence of the changes of the (n-1)-stage column scanning state signal ST[n-1], the (n+1)-stage column scanning state signal ST[n+1], the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C on the n-stage gate driver circuit gtCKT[n].

[0184] Please also see Figure 6 , 7 , 8A. Fig. 8A for, Figure 6The state of the nth gate drive circuit gtCKT[n] in the synchronization phase STG-a1 of the full gate synchronization period DURall-sync. When the nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a1, the (n-1)th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th gate drive circuit gtCKT[n-1], the (n+1)th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, XON_S=L, and XON_C=H.

[0185] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the synchronization phase STG-a1. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the synchronization phase STG-a1 and the on / off state of the transistor.

[0186] Since the (n-1)th stage column scanning state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the disconnected state does not affect the voltage of the intermediate terminal NDmd[n].

[0187] Since the (n+1)th stage column scan state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0188] Since the signal XON_C during the full gate synchronization period is a positive voltage value H (XON_C = H), the voltage regulation endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] are all turned on. With the conduction of the voltage regulation endpoint setting transistor Tf5[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation setting endpoint NDints[n] through the voltage regulation endpoint setting transistor Tf5[n]. That is, NDints[n] = VSSQ = L-. With the conduction of the voltage regulation endpoint setting transistor Tf6[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation endpoint NDstb[n] through the voltage regulation endpoint setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0189] As the intermediate terminal pull-down transistor Tnmd_xon[n] is turned on, the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the intermediate terminal NDmd[n] through the intermediate terminal pull-down transistor Tnmd_xon[n]. That is, NDmd[n]=VSSQ=L-. Since the voltage of the intermediate terminal NDmd[n] is the lowest negative voltage value L-(NDmd[n]=VSSQ=L-), the voltage regulating terminal setting transistors Tf2[n] and Tf4[n] connected to the intermediate terminal NDmd[n] are in the disconnected state. Therefore, Fig. 8A In the embodiment, the voltage regulation endpoint setting transistor Tf2[n] in the disconnected state does not affect the voltage of the voltage regulation setting endpoint NDints[n]; and the voltage regulation endpoint setting transistor Tf4[n] in the disconnected state does not affect the voltage of the voltage regulation endpoint NDstb[n].

[0190] As the gate signal setting transistor Tgs2[n] is turned on, the second lowest negative voltage value L (XON_S=L) of the full gate synchronization enable signal XON_S is transmitted to the n-th pixel gate signal line G[n] through the gate signal setting transistor Tgs2[n]. That is, G[n]=XON_S=L.

[0191] exist Fig. 8AIn the embodiment, since the voltage regulating endpoint setting transistors Tf1[n] and Tf5[n] are both in the on state, the voltage regulating endpoint NDints[n] simultaneously receives the positive voltage value H (LC=H) of the voltage regulating endpoint supply voltage LC through the voltage regulating endpoint setting transistor Tf1[n], and receives the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ through the voltage regulating endpoint setting transistor Tf5[n]. Accordingly, the voltage regulating endpoint setting transistors Tf1[n] and Tf5[n] connected between the voltage regulating endpoint supply voltage signal line LC and the intermediate endpoint ground voltage signal line VSSQ form a voltage dividing effect between the positive voltage value H (LC=H) of the voltage regulating endpoint supply voltage LC and the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ. Therefore, the voltage of the voltage regulating endpoint NDints[n] in the synchronization stage STG-a1 is between the lowest negative voltage value L- and the positive voltage value H. That is, L- <NDints[n]<H。

[0192] In actual application, the voltage value of the voltage setting terminal NDints[n] depends on the size relationship between the voltage setting terminal transistors Tf1[n] and Tf5[n]. For example, if the sizes of the voltage setting terminal transistors Tf1[n] and Tf5[n] are the same, the voltage value of the voltage setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n] = (H+L-) / 2.

[0193] Therefore, in Fig. 8A In the embodiment of the present invention, the voltage of the voltage setting terminal NDints[n] is not enough to turn on the voltage setting terminal transistor Tf3[n]. Therefore, the voltage of the voltage setting terminal NDstb[n] is equal to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ conducted by the voltage setting terminal transistor Tf6[n] (VSSQ=L-). That is, NDstb[n]=VSSQ=L-.

[0194] In conjunction, the voltage regulator transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of the voltage regulator terminal NDstb[n] is equal to the lowest negative voltage value L- (NDstb[n] = L-). Therefore, in the synchronization stage STG-a1, the voltage regulator transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; the voltage regulator transistor Tgstb[n] does not affect the voltage of the n-th level pixel gate signal G[n]; and the voltage regulator transistor Tsstb[n] does not affect the voltage of the n-th level column scanning state signal ST[n].

[0195] exist Fig. 8AIn the example, as the intermediate terminal pull-down transistor Tnmd_xon[n] is turned on, the intermediate terminal NDmd[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ (NDmd[n]=VSSQ=L-), so that the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are both turned off, and the column-by-column selection signal HC[k] (HC[k]=L-) does not affect the voltage of the n-th level pixel gate signal G[n]. Fig. 8A In the embodiment, the state signal setting transistor Tss[n] and the voltage regulating transistor Tsstb[n] which may affect the voltage of the n-th column scanning state signal ST[n] are both disconnected. Therefore, the n-th column scanning state signal ST[n] is in a floating state in the synchronization phase STG-a1.

[0196] Table 5A summarizes Fig. 8A In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0197] Table 5A

[0198]

[0199]

[0200]

[0201] Please also see Figure 6 , 7 , 8B. Figure 8B for, when Figure 6 The state of the n-th gate drive circuit gtCKT[n] in the synchronization phase STG-a2 of the full gate synchronization period DURall-sync is shown. When the n-th gate drive circuit gtCKT[n] is in the synchronization phase STG-a2, the (n-1)-th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the positive voltage value H by the timing controller, and the full gate synchronization period signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, XON_S=H, and XON_C=H.

[0202] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the synchronization stage STG-a2. And how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the synchronization stage STG-a2 and the on / off state of the transistor.

[0203] Since the (n-1)th stage column scanning state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the disconnected state does not affect the voltage of the intermediate terminal NDmd[n].

[0204] Since the (n+1)th stage column scan state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0205] Since the signal XON_C during the full gate synchronization period is a positive voltage value H (XON_C = H), the voltage regulation endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] are all turned on. With the conduction of the voltage regulation endpoint setting transistor Tf5[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation setting endpoint NDints[n] through the voltage regulation endpoint setting transistor Tf5[n]. That is, NDints[n] = VSSQ = L-. With the conduction of the voltage regulation endpoint setting transistor Tf6[n], the lowest negative voltage value L- (VSSQ = L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation endpoint NDstb[n] through the voltage regulation endpoint setting transistor Tf6[n]. That is, NDstb[n] = VSSQ = L-.

[0206] As the intermediate terminal pull - down transistor Tnmd_xon[n] turns on, the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ is conducted to the intermediate terminal NDmd[n] through the intermediate terminal pull - down transistor Tnmd_xon[n]. That is, NDmd[n] = VSSQ = L -. Due to the fact that the voltage of the intermediate terminal NDmd[n] is the lowest negative voltage value L - (NDmd[n] = VSSQ = L -), the voltage - stabilizing terminal setting transistors Tf2[n] and Tf4[n] are in the off state during the synchronization stage STG - a2. Therefore, in Figure 8B the voltage - stabilizing terminal setting transistor Tf2[n] does not affect the voltage of the voltage - stabilizing setting terminal NDints[n]; and, the voltage - stabilizing terminal setting transistor Tf4[n] does not affect the voltage of the voltage - stabilizing terminal NDstb[n].

[0207] As the gate signal setting transistor Tgs2[n] turns on, the full - gate synchronization enable signal XON_S is conducted to the n - th stage pixel gate signal line G[n] through the gate signal setting transistor Tgs2[n]. Also, because the full - gate synchronization enable signal XON_S is a positive voltage value H (XON_S = H), at this time the n - th stage pixel gate signal G[n] is a positive voltage value H. That is, G[n] = XON_S = H.

[0208] In Figure 8B since the voltage - stabilizing terminal setting transistors Tf1[n] and Tf5[n] are both in the on state, the voltage - stabilizing setting terminal NDints[n] receives the positive voltage value H (LC = H) of the voltage - stabilizing terminal supply voltage LC through the voltage - stabilizing terminal setting transistor Tf1[n], and receives the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ through the voltage - stabilizing terminal setting transistor Tf5[n]. Accordingly, the voltage - stabilizing terminal setting transistors Tf1[n] and Tf5[n] connected between the voltage - stabilizing terminal supply voltage signal line LC and the intermediate terminal ground voltage signal line VSSQ form a voltage - dividing effect between the positive voltage value H and the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ.

[0209] Therefore, the voltage of the voltage - stabilizing setting terminal NDints[n] during the synchronization stage STG - a2 is between the lowest negative voltage value L - (VSSQ = L -) of the intermediate terminal ground voltage VSSQ and the positive voltage value H (LC = H) of the voltage - stabilizing terminal supply voltage LC. That is, L - < NDints[n] < H. And, in Figure 8BIn the embodiment of the present invention, the voltage of the voltage setting terminal NDints[n] is not enough to turn on the voltage setting terminal transistor Tf3[n]. Therefore, the voltage of the voltage setting terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ conducted by the voltage setting terminal transistor Tf6[n]. That is, NDstb[n]=VSSQ=L-.

[0210] In conjunction, the voltage-stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of the voltage-stabilizing terminal NDstb[n] connected to their control terminals is equal to the lowest negative voltage value L- (NDstb[n] = L-). Therefore, in the synchronization stage STG-a2, the voltage-stabilizing transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; the voltage-stabilizing transistor Tgstb[n] does not affect the voltage of the n-th level pixel gate signal G[n]; and the voltage-stabilizing transistor Tsstb[n] does not affect the voltage of the n-th level column scanning state signal ST[n].

[0211] exist Figure 8B In the example, as the intermediate terminal pull-down transistor Tnmd_xon[n] is turned on, the intermediate terminal NDmd[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ (NDmd[n]=VSSQ=L-), so that the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are both turned off, and the column-by-column selection signal HC[k] (HC[k]=L-) does not affect the voltage of the n-th level pixel gate signal G[n]. Figure 8B In the embodiment, the state signal setting transistor Tss[n] and the voltage regulating transistor Tsstb[n] which may affect the voltage of the n-th column scanning state signal ST[n] are both disconnected. Therefore, the n-th column scanning state signal ST[n] is in a floating state in the synchronization phase STG-a2.

[0212] Table 5B summarizes Figure 8B In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0213] Table 5B

[0214]

[0215]

[0216]

[0217] Please also see Figure 6 , 7 , 8C. Figure 8C for, Figure 6 The state of the nth gate drive circuit gtCKT[n] in the synchronization phase STG-a3 of the full gate synchronization period DURall-sync. When the nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a3, the (n-1)th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th gate drive circuit gtCKT[n-1], the (n+1)th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the positive voltage value H by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, XON_S=L, and XON_C=H.

[0218] Depend on Figure 7 As can be seen from the waveform diagram, the input signals (HC[k], ST[n-1], ST[n+1], XON_C, XON_S) have the same level in the synchronization phase STG-a1 and STG-a3. Therefore, the n-th gate drive circuit gtCKT[n] is Figure 8C The state of the n-th gate drive circuit gtCKT[n] Fig. 8A The state of the n-th stage gate drive circuit gtCKT[n] is the same as that of the n-th stage gate drive circuit gtCKT[n]. Figure 8C status.

[0219] Table 5C is summarized in Figure 8C In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0220] Table 5C

[0221]

[0222]

[0223] See also Figures 9A to 9D, which is a schematic diagram of the states of the n-stage gate driver circuit gtCKT[n] at different stages during the n-stage single-stage scan period DURscan[n] according to the first embodiment of the disclosed concept. The following does not specifically describe input signals with fixed voltage values ​​such as the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, the pixel gate ground voltage VSSG, and the gate supply voltage VGHD, but only describes the influence of the changes of the (n-1)-stage column scan state signal ST[n-1], the (n+1)-stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C on the n-stage gate driver circuit gtCKT[n].

[0224] Please also see Figure 6 , 7 , 9A. Fig.9A for, Figure 6 The state of the n-th gate drive circuit gtCKT[n] in the scanning phase STG-s1[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning phase STG-s1[n], the (n-1)-th column scanning state signal ST[n-1] is set to a positive voltage value H by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the lowest negative voltage value L- by the timing controller. That is, ST[n-1]=H, ST[n+1]=L-, HC[k]=L-, XON_S=L, and XON_C=L-.

[0225] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the scanning stage STG-s1[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the scanning stage STG-s1[n] and the on / off state of the transistor.

[0226] Since the (n-1)th column scan state signal ST[n-1] is a positive voltage value H (ST[n-1]=H) during the scan phase STG-s1[n], the intermediate terminal pull-up transistor Tnmu[n] is turned on. At this time, the intermediate terminal pull-up transistor Tnmu[n] transmits the positive voltage value H (VGHD=H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n]=VGHD=H.

[0227] Since the voltage of the intermediate terminal NDmd[n] is equal to the positive voltage value H (NDmd[n]=H), the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], and the voltage regulating terminal setting transistors Tf2[n] and Tf4[n] connected to the control terminal and the intermediate terminal NDmd[n] are all turned on during the scanning phase STG-s1[n].

[0228] Since the (n+1)th column scan state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-) in the scan phase STG-s1[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0229] The column-by-column selection signal HC[k] is at the lowest negative voltage value L-(HC[k]=L-) during the scanning phase STG-s1[n], and the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are both turned on. Therefore, the state signal setting transistor Tss[n] transmits the lowest negative voltage value L-(HC[k]=L-) of the column-by-column selection signal HC[k] to the n-th column scanning state signal line ST[n] (ST[n]=HC[k]=L-); and the gate signal setting transistor Tgs1[n] transmits the lowest negative voltage value L-(HC[k]=L-) of the column-by-column selection signal HC[k] to the n-th pixel gate signal line G[n] (G[n]=HC[k]=L-).

[0230] exist Fig.9A In the embodiment, the two ends of the capacitor C[n] are respectively set to a positive voltage value H (NDmd[n]=VGHD=H) by the intermediate terminal NDmd[n], and are set to a minimum negative voltage value L- (G[n]=HC[k]=L-) by the n-th pixel gate signal G[n]. Therefore, the capacitor C[n] will be charged during the scanning stage STG-s1[n]. In this paper, the voltage difference between the two ends of the capacitor C[n] is expressed as the capacitor voltage difference ΔVc[n].

[0231] exist Fig.9AIn [the circuit], since the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-) during the full-gate synchronization period, the voltage stabilizing endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n], whose control terminals are connected to the signal line XON_C during the full-gate synchronization period, are all turned off. Therefore, during the scanning stage STG-s1[n], the voltage stabilizing endpoint setting transistor Tf5[n] does not affect the voltage of the voltage stabilizing setting endpoint NDints[n]; the voltage stabilizing endpoint setting transistor Tf6[n] does not affect the voltage of the voltage stabilizing endpoint NDstb[n]; the intermediate endpoint pull-down transistor Tnmd_xon[n] does not affect the voltage of the intermediate endpoint NDmd[n]; and the gate signal setting transistor Tgs2[n] does not affect the voltage of the gate signal G[n] of the nth-stage pixel.

[0232] Continuing from the above, the gate signal setting transistor Tgs2[n] is turned off because its control terminal receives the signal XON_C (XON_C = L-) during the full-gate synchronization period with the lowest negative voltage value L-. Consequently, the full-gate synchronization enable signal XON_S (XON_S = L), which is set to the second lowest negative voltage value L, cannot be conducted to the gate signal line G[n] of the nth-stage pixel. In other words, at this time, the full-gate synchronization enable signal XON_S does not affect the circuit behavior of the nth-stage gate driving circuit gtCKT[n].

[0233] In Fig.9A [the circuit], since the voltage stabilizing endpoint setting transistors Tf1[n] and Tf2[n] are both in the conducting state, the voltage stabilizing setting endpoint NDints[n] receives, through the voltage stabilizing endpoint setting transistor Tf1[n], the positive voltage value H of the voltage stabilizing endpoint supply voltage LC (LC = H), and, through the voltage stabilizing endpoint setting transistor Tf2[n], the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-). Accordingly, the voltage stabilizing endpoint setting transistors Tf1[n] and Tf2[n] connected between the voltage stabilizing endpoint supply voltage signal line LC and the intermediate endpoint ground voltage signal line VSSQ form a voltage division effect.

[0234] Therefore, the voltage of the voltage stabilizing setting endpoint NDints[n] during the synchronization stage STG-a2 is between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) and the positive voltage value H of the voltage stabilizing endpoint supply voltage LC (LC = H). That is, L- < NDints[n] < H. And, in Fig.9AIn the synchronous phase STG-a2, the voltage of the voltage setting terminal NDints[n] is not enough to turn on the voltage setting terminal transistor Tf3[n]. Therefore, the voltage of the voltage setting terminal NDstb[n] in the synchronous phase STG-a2 is equal to the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ conducted by the voltage setting terminal transistor Tf4[n]. That is, NDstb[n]=VSSQ=L-.

[0235] In conjunction, the voltage-stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of the voltage-stabilizing terminal NDstb[n] connected to their control terminals is equal to the lowest negative voltage value L- (NDstb[n] = L-). Therefore, in the scanning stage STG-s1[n], the voltage-stabilizing transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; the voltage-stabilizing transistor Tgstb[n] does not affect the voltage of the n-th level pixel gate signal G[n]; and the voltage-stabilizing transistor Tsstb[n] does not affect the voltage of the n-th level column scanning state signal ST[n].

[0236] Table 6A summarizes Fig.9A In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0237] Table 6A

[0238]

[0239]

[0240] Please also see Figure 6 , 7 , 9B. Fig. 9B for, Figure 6The state of the n-th gate drive circuit gtCKT[n] in the scanning stage STG-s2[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning stage STG-s2[n], the (n-1)-th column scanning state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the positive voltage value H by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=H, XON_S=L, and XON_C=L-.

[0241] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the scanning stage STG-s2[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the scanning stage STG-s2[n] and the on / off state of the transistor.

[0242] Since the (n-1)th stage column scan state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-), the intermediate node pull-up transistor Tnmu[n] is turned off. At this time, the intermediate node pull-up transistor Tnmu[n] does not affect the voltage of the intermediate node NDmd[n].

[0243] Since the (n+1)th stage column scan state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0244] exist Fig. 9BIn this case, since the signal XON_C is set to the lowest negative voltage value L- (XON_C = L-) during the full-gate synchronization, the voltage stabilization endpoint setting transistors Tf5[n], Tf6[n], the intermediate endpoint pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] whose control terminals are connected to the signal line XON_C during the full-gate synchronization are all turned off. Therefore, during the scanning stage STG-s1[n], the voltage stabilization endpoint setting transistor Tf5[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the voltage stabilization setting endpoint NDints[n]; the voltage stabilization endpoint setting transistor Tf6[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the voltage stabilization endpoint NDstb[n]; the intermediate endpoint pull-down transistor Tnmd_xon[n] does not allow the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) to affect the voltage of the intermediate endpoint NDmd[n]; and the gate signal setting transistor Tgs2[n] does not allow the second lowest negative voltage value L of the full-gate synchronization enable signal XON_S (XON_S = L) to affect the voltage of the nth-stage pixel gate signal G[n].

[0245] In Fig. 9B this case, since the voltage stabilization endpoint setting transistors Tf1[n] and Tf2[n] are both in the conducting state, the voltage stabilization setting endpoint NDints[n] receives the positive voltage value H of the voltage stabilization endpoint supply voltage LC (LC = H) through the voltage stabilization endpoint setting transistor Tf1[n] and the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) through the voltage stabilization endpoint setting transistor Tf2[n] at the same time. Accordingly, the voltage stabilization endpoint setting transistors Tf1[n] and Tf2[n] connected between the voltage stabilization endpoint supply voltage signal line LC and the intermediate endpoint ground voltage signal line VSSQ form a voltage division effect between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ (VSSQ = L-) and the positive voltage value H of the voltage stabilization endpoint supply voltage LC (LC = H).

[0246] Therefore, the voltage of the voltage stabilization setting endpoint NDints[n] during the synchronization stage STG-a2 is between the lowest negative voltage value L- of the intermediate endpoint ground voltage VSSQ and the positive voltage value H of the voltage stabilization endpoint supply voltage LC. That is, L- < NDints[n] < H. And, in Fig. 9BIn this case, the voltage of the voltage setting terminal NDints[n] is not enough to turn on the voltage setting terminal transistor Tf3[n]. Therefore, the voltage of the voltage setting terminal NDstb[n] is equal to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ conducted by the voltage setting terminal transistor Tf4[n] (VSSQ=L-). That is, NDstb[n]=VSSQ=L-.

[0247] In conjunction, the voltage-stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all disconnected because the voltage of the voltage-stabilizing terminal NDstb[n] connected to their control terminals is equal to the lowest negative voltage value L- (NDstb[n] = L-). Therefore, in the scanning stage STG-s2[n], the voltage-stabilizing transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; the voltage-stabilizing transistor Tgstb[n] does not affect the voltage of the n-th level pixel gate signal G[n]; and the voltage-stabilizing transistor Tsstb[n] does not affect the voltage of the n-th level column scanning state signal ST[n].

[0248] As mentioned above, the intermediary endpoint NDmd[n] is Fig.9A The intermediate terminal pull-up transistor Tnmu is turned on and charged to a positive voltage value H (NDmd[n]=H). By turning on the gate signal setting transistor Tgs1[n], the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k] is transmitted to the n-th pixel gate signal line G[n] (G[n]=HC[k]=H).

[0249] As above, Fig.9A The intermediate terminal NDmd[n] will be charged to the positive voltage value H of the gate supply voltage VGHD (NDmd[n]=VGHD=H) due to the conduction of the intermediate terminal pull-up transistor Tnmu. In order to distinguish the voltage of the intermediate terminal NDmd[n] in different scanning stages STG-s1[n] and STG-s2[n], the voltage of the intermediate terminal NDmd[n] in the scanning stage STG-s1[n] and STG-s2[n] can be further represented as NDmd[n](@STG-s1[n]) and NDmd[n](@STG-s2[n]) respectively. The voltages of other signals in the scanning stage STG-s1[n] and STG-s2[n] can also be represented in a similar way.

[0250] exist Fig. 9B In the example, the intermediate terminal pull-up transistor Tnmu is disconnected, so that the intermediate terminal NDmd[n] is in a floating state during the scanning phase STG-s2[n]. At the moment when the intermediate terminal pull-up transistor Tnmu is just disconnected, the level of the intermediate terminal NDmd[n] in the floating state is temporarily maintained equal to the positive voltage value H of the scanning phase STG-s1[n].

[0251] The gate signal sets transistor Tgs1[n] to remain conductive during the scanning phase STG-s1[n], STG-s2[n], so that the voltage of the n-th level pixel gate signal G[n] during the scanning phase STG-s1[n], STG-s2[n] is equal to the voltage of the column-by-column selection signal HC[k] during the scanning phase STG-s1[n], STG-s2[n]. Furthermore, because the column-by-column selection signal HC[k] turned on by the gate signal setting transistor Tgs1[n] switches from the lowest negative voltage value L-(HC[k]=L-) in the scanning stage STG-s1[n] to the positive voltage value H(HC[k]=H) in the scanning stage STG-s2[n], the n-th level pixel gate signal G[n] also rises from the lowest negative voltage value L-(G[n](@)STG-s1[n]=L-) in the scanning stage STG-s2[n] to the positive voltage value H(G[n](@)STG-s2[n]=H) in the scanning stage STG-s2[n].

[0252] Since the capacitor C is disposed between the intermediate terminal NDmd[n] in a floating state and the n-th pixel gate signal G[n], and because the intermediate terminal NDmd[n] in a floating state still temporarily maintains a positive voltage value H equal to the scanning stage STG-s1[n], and the capacitor C has a capacitance voltage difference ΔVc[n], coupling is formed between the intermediate terminal NDmd[n] and the n-th pixel gate signal G[n]. In conjunction, the voltage NDmd[n] (@STG-s2[n]) of the intermediate terminal NDmd[n] in the scanning stage STG-s2[n] will further increase from the positive voltage value H (NDmd[n](@STG-s1[n]) = VGHD = H) of the scanning stage STG-s1[n]. At this time, the voltage NDmd[n] (@STG-s2[n]) of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] will rise to the voltage sum (H+ΔVc[n]) of the positive voltage value H plus the capacitor voltage difference ΔVc[n].

[0253] According to the above description, it can be known that the voltage NDmd[n](@STG-s2[n]) of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] can be expressed as follows, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]=VGHD+ΔVc[n]=H+ΔVc[n].

[0254] In conjunction, the voltage NDmd[n](@STG-s2[n])=H+ΔVc[n] of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] can keep the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] stably in the on state during the scanning phase STG-s2[n]. The conduction of the state signal setting transistor Tss[n] can keep the n-th level column scanning state signal ST[n] at a positive voltage value H (ST[n]=HC[k]=H). Furthermore, the conduction of the gate signal setting transistor Tgs1[n] can keep the n-th level pixel gate signal G[n] stably at a positive voltage value H (G[n]=H).

[0255] Table 6B summarizes Fig. 9B In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0256] Table 6B

[0257]

[0258]

[0259] Please also see Figure 6 , 7 , 9C. Fig. 9C for, Figure 6 The state of the n-th gate drive circuit gtCKT[n] in the scanning stage STG-s3[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning stage STG-s3[n], the (n-1)-th column scanning state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the positive voltage value H by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the lowest negative voltage value L- by the timing controller. That is, ST[n-1]=L-, ST[n+1]=H, HC[k]=L-, XON_S=L, and XON_C=L-.

[0260] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the scanning stage STG-s3[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the scanning stage STG-s3[n] and the on / off state of the transistor.

[0261] Since the (n-1)th column scan state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-) in the scan phase STG-s3[n], the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0262] Since the (n+1)th column scan state signal ST[n+1] is a positive voltage value H (ST[n+1]=H) in the scan phase STG-s3[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n], so that the intermediate terminal NDmd[n] is equal to the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ. That is, NDmd[n]=VSSQ=L-.

[0263] exist Fig. 9C In the scanning stage STG-s3[n], the voltage-stabilizing endpoint setting transistor Tf5[n] will not affect the voltage of the voltage-stabilizing endpoint NDints[n]; the voltage-stabilizing endpoint setting transistor Tf6[n] will not affect the voltage of the voltage-stabilizing endpoint NDstb[n]; the intermediate endpoint pull-down transistor Tnmd_xon[n] will not affect the voltage of the intermediate endpoint NDmd[n]; and the gate signal setting transistor Tgs2[n] will not affect the voltage of the n-th level pixel gate signal G[n].

[0264] exist Fig. 9CIn the embodiment, since the voltage stabilizing terminal setting transistor Tf1[n] is turned on and the voltage stabilizing terminal setting transistors Tf5[n] and Tf2[n] are turned off, the voltage of the voltage stabilizing terminal NDints[n] is equal to the positive voltage value H (NDints[n]=LC=H). In conjunction, the voltage stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all turned on because the voltage of the voltage stabilizing terminal NDstb[n] connected to their control terminals is equal to the positive voltage value H (NDstb[n]=H). Therefore, in the scanning stage STG-s3[n], the voltage of the intermediate terminal NDmd[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ (NDmd[n]=VSSQ=L-) as the voltage-stabilizing transistor Tnmstb[n] is turned on; the voltage of the n-th level pixel gate signal G[n] is set to the second lowest negative voltage value L of the pixel gate ground voltage VSSG (G[n]=VSSG=L) as the voltage-stabilizing transistor Tgstb[n] is turned on; and, the voltage of the n-th level column scanning status signal ST[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ (ST[n]=VSSQ=L-) as the voltage-stabilizing transistor Tsstb[n] is turned on.

[0265] As mentioned above, Fig. 9C In the embodiment, the voltage of the intermediate terminal NDmd[n] is simultaneously pulled down to the lowest negative voltage value L-(NDmd[n]=VSSQ=L-) by the voltage regulator transistor Tnmstb[n] and the intermediate terminal pull-down transistor Tnmd_nxt[n]. Therefore, the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] connected to the control end of the intermediate terminal NDmd[n] are both in the disconnected state. At this time, the lowest negative voltage value L-(HC[k]=L-) of the column-by-column selection signal HC[k] will not affect the n-th level column scanning state signal ST[n], nor will it affect the n-th level pixel gate signal G[n].

[0266] Table 6C is summarized in Fig. 9C In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0267] Table 6C

[0268]

[0269]

[0270]

[0271] Please also see Figure 6 , 7 , 9D. Fig.9D for, Figure 6 The state of the n-th gate drive circuit gtCKT[n] in the scanning stage STG-s4[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning stage STG-s4[n], the (n-1)-th column scanning state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller, and the full gate synchronization period signal XON_C is set to the lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, XON_S=L, and XON_C=L-.

[0272] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the scanning stage STG-s4[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the scanning stage STG-s4[n] and the on / off state of the transistor.

[0273] Since the (n-1)th stage column scan state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-), the intermediate node pull-up transistor Tnmu[n] is turned off. At this time, the intermediate node pull-up transistor Tnmu[n] does not affect the voltage of the intermediate node NDmd[n].

[0274] Since the (n+1)th stage column scan state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] does not affect the voltage of the intermediate terminal NDmd[n].

[0275] exist Fig.9DIn the embodiment, since the voltage stabilizing terminal setting transistor Tf1[n] is turned on and the voltage stabilizing terminal setting transistors Tf5[n] and Tf2[n] are turned off, the voltage of the voltage stabilizing terminal NDints[n] is equal to the positive voltage value H (NDints[n]=LC=H). In conjunction, the voltage stabilizing transistors Tnmstb[n], Tgstb[n], and Tsstb[n] are all turned on because the voltage of the voltage stabilizing terminal NDstb[n] connected to their control terminals is equal to the positive voltage value H (NDstb[n]=H). Therefore, in the scanning stage STG-s4[n], the voltage of the intermediate terminal NDmd[n] is set to the lowest negative voltage value L-(NDmd[n]=VSSQ=L-) as the voltage-stabilizing transistor Tnmstb[n] is turned on; the voltage of the n-th level pixel gate signal G[n] is set to the second lowest negative voltage value L (G[n]=VSSG=L) as the voltage-stabilizing transistor Tgstb[n] is turned on; and the voltage of the n-th level column scanning status signal ST[n] is set to the lowest negative voltage value L-(ST[n]=VSSQ=L-) as the voltage-stabilizing transistor Tsstb[n] is turned on.

[0276] As mentioned above, Fig.9D In the embodiment, the voltage of the intermediate terminal NDmd[n] is pulled down to the lowest negative voltage value L- (NDmd[n]=VSSQ=L-) by the voltage regulator transistor Tnmstb[n]. Therefore, the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] connected to the intermediate terminal NDmd[n] at the control end are both in the disconnected state. At this time, the lowest negative voltage value L- (HC[k]=L-) of the column-by-column selection signal HC[k] will not affect the n-th column scanning state signal ST[n], nor will it affect the n-th pixel gate signal G[n].

[0277] exist Fig.9D In the embodiment, since the full gate synchronization period signal XON_C is set to the lowest negative voltage value L- (XON_C = L-), the voltage-regulating terminal setting transistors Tf5[n], Tf6[n], the intermediate terminal pull-down transistor Tnmd_xon[n], and the gate signal setting transistor Tgs2[n] connected to the full gate synchronization period signal line XON_C at the control end are all disconnected. Therefore, in the scanning stage STG-s4[n], the voltage-regulating terminal setting transistor Tf5[n] will not affect the voltage of the voltage-regulating terminal NDints[n]; the voltage-regulating terminal setting transistor Tf6[n] will not affect the voltage of the voltage-regulating terminal NDstb[n]; the intermediate terminal pull-down transistor Tnmd_xon[n] will not affect the voltage of the intermediate terminal NDmd[n]; and the gate signal setting transistor Tgs2[n] will not affect the voltage of the n-th level pixel gate signal G[n].

[0278] Table 6D is summarized in Fig.9D In the figure, the input signals such as the (n-1)th level column scan status signal ST[n-1], the (n+1)th level column scan status signal ST[n+1], the full gate synchronization period signal XON_C, and the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0279] Table 6D

[0280]

[0281]

[0282] Table 7 summarizes the transistors in the n-stage gate drive circuit gtCKT[n] of the first embodiment. Figures 8A to 8C In Table 7, a hyphen ("-") represents that the transistor is in the off state.

[0283]

[0284]

[0285] Please also see Figure 7 , 8A ~8C, 9A~9D. Since each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to a gate signal setting transistor Tgs2[1]~Tgs2[N], and these gate signal setting transistors Tgs2[1]~Tgs2[N] are all controlled by the same full gate synchronization period signal XON_C, the behaviors of the gate signal setting transistors Tgs2[1]~Tgs2[N] are consistent.

[0286] exist Figure 7 In the full gate synchronization period, the full gate synchronization period signal XON_C is maintained at a positive voltage value H during the full gate synchronization period DURall-sync; and is maintained at the lowest negative voltage value L- during the n-th single-stage scanning period DURscan[n]. Therefore, the gate signal setting transistors Tgs2[1]~Tgs2[N], the voltage regulating terminal setting transistors Tf5[n], Tf6[n], and the intermediate terminal pull-down transistor Tnmd_xon[n] connected to the full gate synchronization period signal line XON_C at the control end are maintained in the on state during the full gate synchronization period DURall-sync; and are maintained in the off state during the round-robin scanning period DURall-scan.

[0287] When the gate signal setting transistors Tgs2[1] to Tgs2[N] maintain a conducting state during the all-gate synchronization period DURall-sync with the positive voltage value (XON_C = H) of the all-gate synchronization period signal XON_C, the voltages of the N-stage pixel gate signals G[1] to G[n] are simultaneously determined by the voltage of the all-gate synchronization enable signal XON_S. From Figure 7 It can be seen that the all-gate synchronization enable signal XON_S is set to the positive voltage value H (XON_S = H) only during the synchronization stage STG-a2 in the all-gate synchronization period DURall-sync, and is set to the second lowest negative voltage value L in the remaining stages. Thus, the timing controller can use the all-gate synchronization enable signal XON_S (XON_S = L) to synchronously set the N-stage pixel gate signals G[1] to G[N] to the positive voltage value H (G[1] =... = G[N] = H) during the synchronization stage STG-a2 in the all-gate synchronization period DURall-sync. On the other hand, by controlling the gate signal setting transistors Tgs2[1] to Tgs2[N] to maintain an off state during the n-stage single-stage scan period DURscan[n] with the lowest negative voltage value L- (XON_C = L-) of the all-gate synchronization period signal XON_C, the voltage of the all-gate synchronization enable signal XON_S does not affect the voltages of the N-stage pixel gate signals G[1] to G[N].

[0288] When the regulated voltage end point setting transistors Tf5[n], Tf6[n] maintain a conducting state during the all-gate synchronization period DURall-sync with the positive voltage value (XON_C = H) of the all-gate synchronization period signal XON_C, the conducting regulated voltage end point setting transistor Tf5[n] conducts the lowest negative voltage value (VSSQ = L-) of the intermediate end point ground voltage VSSQ to the regulated voltage setting end point NDints[n]; and, the conducting regulated voltage end point setting transistor Tf6[n] conducts the lowest negative voltage value (VSSQ = L-) of the intermediate end point ground voltage VSSQ to the regulated voltage end point NDstb[n]. Among them, the voltage of the regulated voltage setting end point NDints[n] is affected by the regulated voltage end point setting transistor Tf1[n] also connected to the regulated voltage setting end point NDints[n] and is between the lowest negative voltage value -L and the positive voltage value H (-L < NDints[n] < H); the regulated voltage end point NDstb[n] is directly set to the lowest negative voltage value L- (NDstb[n] = VSSQ = L-) by the conducting regulated voltage end point setting transistor Tf6[n].

[0289] On the other hand, when the voltage regulator endpoint setting transistors Tf5[n] and Tf6[n] remain disconnected during the n-th single-stage scan period DURscan[n] following the lowest negative voltage value L- (XON_C=L-) of the signal XON_C during the full gate synchronization period, the voltage regulator endpoint setting transistor Tf5[n] in the disconnected state will not affect the voltage of the voltage regulator setting endpoint NDints[n]; and, the voltage regulator endpoint setting transistor Tf6[n] in the disconnected state will not affect the voltage of the voltage regulator endpoint NDstb[n].

[0290] As mentioned above, [n] is used herein to represent a signal that changes with n=1 to N. According to the concept of the present disclosure, the column-by-column selection signals HC[1] to HC[K] are input signals for sequentially generating pulses after the timing controller divides the N-stage gate drive circuits gtCKT[1] to gtCKT[N] into K groups and generates pulses in sequence according to the different groups k=1 to K.

[0291] For example, when the timing controller sets the column-by-column selection signal HC[k-1] corresponding to the (n-1)th level gate drive circuit gtCKT[n-1] to the positive voltage value H (HC[k-1]=H) in the scanning stage STG-s2[n-1], the column-by-column selection signal HC[k] corresponding to the nth level gate drive circuit gtCKT[n] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th level gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L-(HC[k]=HC[k+1]=L-). When the timing controller sets the column-by-column selection signal HC[k] corresponding to the n-th gate drive circuit gtCKT[n] to the positive voltage value H (HC[k]=H) in the scanning stage STG-s2[n], the column-by-column selection signal HC[k-1] corresponding to the (n-1)-th gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)-th gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L-(HC[k-1]=HC[k+1]=L-). When the timing controller sets the column-by-column selection signal HC[k+1] corresponding to the (n+1)-th gate drive circuit gtCKT[n+1] to the positive voltage value H (HC[k+1]=H) in the scanning stage STG-s2[n+1], the column-by-column selection signal HC[k-1] corresponding to the (n-1)-th gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k] corresponding to the (n)-th gate drive circuit gtCKT[n] are set to the lowest negative voltage value L-(HC[k-1]=HC[k]=L-).

[0292] like Figure 7As shown, the column-by-column selection signal HC[k] corresponding to the n-th gate drive circuit gtCKT[n] is set to a positive voltage value H by the timing controller during the scanning phase STG-s2[n] in the n-th single-stage scanning period DURscan[n]. Fig. 9B It can be seen that when the column-by-column selection signal HC[k] corresponding to the n-th stage gate driving circuit gtCKT[n] is set to the positive voltage value H in the scanning stage STG-s2[n], the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are turned on by the voltage of the intermediate terminal NDmd[n] (NDmd[n]=H+ΔVc[n]), and then the positive voltage value H of the column-by-column selection signal HC[n] (HC[n]=H) is transmitted to the n-th stage pixel gate signal line G[n] and the n-th stage column scanning state signal line ST[n]. That is, G[n]=ST[n]=H.

[0293] Since the column-by-column selection signal HC[k] corresponding to the n-th level gate driving circuit gtCKT[n] is generated at different time periods as the levels n=1 to N are different, in this way, the timing controller can enable the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] in the n-th level gate driving circuit gtCKT[n] in the scanning phase STG-s2[n] corresponding to the n-th level gate driving circuit gtCKT[n], thereby generating the pulse of the n-th level pixel gate signal G[n] corresponding only to the n-th level and the pulse of the n-th level column scanning state signal ST[n].

[0294] Please also note that the scanning stage STG-s2[n] corresponding to the n-th level gate drive circuit gtCKT[n] is equivalent to the scanning stage STG-s3[n-1] corresponding to the (n-1)-th level gate drive circuit gtCKT[n-1]; and the scanning stage STG-s1[n+1] corresponding to the (n+1)-th level gate drive circuit gtCKT[n+1]. Therefore, the (n-1)th level pixel gate signal G[n-1] and the (n-1)th level column scanning state signal ST[n-1] corresponding to the (n-1)th level gate driving circuit gtCKT[n-1], and the (n+1)th level column scanning state signal ST[n+1] of the (n+1)th level pixel gate signal G[n+1] corresponding to the (n+1)th level gate driving circuit gtCKT[n+1], will not be set to the positive voltage value H in the same time period because the column-by-column selection signal HC[k-1] corresponding to the (n-1)th level gate driving circuit gtCKT[n-1] is the lowest negative voltage value L-(HC[k-1]=L-) and because the column-by-column selection signal HC[k+1] corresponding to the (n+1)th level gate driving circuit gtCKT[n+1] is the lowest negative voltage value L-(HC[k+1]=L-).

[0295] As mentioned above, the round-robin scanning period DURall-scan includes N single-stage scanning periods DURscan[1]~DURscan[N]. In the first embodiment of the disclosed concept, each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to four scanning stages. Therefore, in the first embodiment of the disclosed concept, the round-robin scanning period DURall-scan covers a total of (N+3) scanning stages.

[0296] like Fig. 9B As explained, the voltage value of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] is equivalent to the sum of the voltage value of the intermediate terminal NDmd[n] during the scanning phase STG-s1[n] and the capacitor voltage difference ΔVc[n]. That is, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]. It can be seen that the intermediate terminal NDmd[n] is not actually turned on to a stable voltage value during the scanning phase STG-s2[n]. Therefore, the intermediate terminal NDmd[n] can be regarded as floating during the scanning phase STG-s2[n]. In order to avoid leakage current from the intermediate terminal pull-down transistor Tnmd_nxt[n] and the voltage regulator transistor Tnmstb[n] due to the floating of the intermediate terminal NDmd[n], or even incomplete opening of the gate signal setting transistor Tgs1[n], the present disclosure can further modify the design of the gate driving circuit gtCKT[n].

[0297] Based on the consideration of reducing leakage current, it can be further improved Figure 5 The gate drive circuit gtCKT[n]. Fig.10 , which is a schematic diagram of a first embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, combined with a method of reducing leakage current phenomenon. Fig.10 Two methods (methods A and B) for reducing leakage current are shown in the figure. Please also refer to Figure 6 , 10 .

[0298] The first method to reduce the leakage current phenomenon (method A) is shown as line segment lkgCNT_1a. Figure 5 In the embodiment, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal ground voltage signal line VSSQ. Fig.10 In the embodiment, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is changed to be electrically connected to the pixel gate ground voltage signal line VSSG.

[0299] If the first embodiment does not adopt Fig.10 In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th stage column scan state signal line ST[n-1] and the intermediate terminal ground voltage signal line VSSQ, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the disconnected state, its control terminal is the lowest negative voltage value L-(ST[n-1]=L-), and its source terminal is the lowest negative voltage value L-(VSSQ=L-). At this time, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] is close to 0V, which is more likely to generate leakage current.

[0300] On the other hand, if the first embodiment adopts Fig.10 In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th column scanning state signal line ST[n-1] and the pixel gate ground voltage signal line VSSG, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal is the lowest negative voltage value L-(ST[n-1]=L-), and its source terminal is the second lowest negative voltage value L (VSSG=L). Since the pixel gate ground voltage VSSG is slightly higher than the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] presents a negative bias voltage. Therefore, by this wiring method, the chance of generating leakage current in the intermediate terminal pull-down transistor Tnmd_nxt[n] can be reduced.

[0301] The second method to reduce the leakage current phenomenon (method B) is shown as line segment lkgCNT_1b. Figure 6 In the embodiment, the source of the voltage regulator transistor Tnmstb[n] is originally electrically connected to the intermediate terminal ground voltage signal line VSSQ. Fig.10 In the embodiment, the source of the voltage regulator transistor Tnmstb[n] is changed to be electrically connected to the n-th stage column scanning state signal line ST[n].

[0302] Please also see Figure 7 , 9B , 10. When the n-th stage gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], the voltage regulator transistor Tnmstb[n] is in the disconnected state.

[0303] When the n-th gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], if according to Fig. 9B The control terminal of the voltage regulator transistor Tnmstb[n] is the lowest negative voltage value L-(NDstb[n]=VSSQ=L-) from the voltage regulator terminal NDstb[n], and its source terminal is the lowest negative voltage value L-(VSSQ=L-) from the intermediate terminal ground voltage VSSQ. Therefore, if the Fig. 9B In the connection mode, when the voltage regulator transistor Tnmstb[n] is in the scanning stage STG-s2[n] of the n-th stage gate drive circuit gtCKT[n], leakage current is easily generated because the gate-source voltage difference (ΔVgs) is close to 0V.

[0304] On the other hand, when the n-th gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], if the n-th gate drive circuit gtCKT[n] follows Fig.10 The voltage at the control end of the voltage regulator transistor Tnmstb[n] is equal to the lowest negative voltage value L-(ST[n-1]=L-) from the voltage regulator terminal NDstb[n], and the voltage at its source end is equal to the positive voltage value H (ST[n]=HC[k]=H) from the n-th column scanning state signal ST[n]. Therefore, the Fig.10 When the connection method of method B is used, when the voltage stabilizing transistor Tnmstb[n] is in the scanning stage STG-s2[n], since the positive voltage value of the n-th column scanning state signal ST[n] (ST[n]=HC[k]=H) is higher than the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the voltage stabilizing transistor Tnmstb[n] presents a negative bias voltage (ΔVgs<0). Therefore, when the connection method of method B is used, the leakage current generated in the voltage stabilizing transistor Tnmstb[n] can be reduced.

[0305] In actual application, the gate drive circuit gtCKT[n] can use only method A (line segment lkgCNT_1a), only method B (line segment lkgCNT_1b), or both methods A and B (line segments lkgCNT_1a, lkgCNT_1b) to reduce leakage current. Figures 6 to 9D The figure illustrates the generation of the n-th level pixel gate signal G[n] and the n-th level column scanning state signal ST[n].

[0306] In order to extend the circuit life (reduce TFT stress), the gate drive circuit gtCKT[n] can use two sets of voltage regulator circuits. Fig.11 , which is a first embodiment of the n-th stage gate driving circuit gtCKT[n] based on the disclosed concept, with two sets of voltage stabilizing circuit schematics. The gate driving circuit gtCKT[n] includes: a capacitor C[n], an intermediate terminal pull-up circuit nmuCKT[n], a state signal setting circuit ssCKT[n], a gate signal setting circuit gsCKT[n], a voltage stabilizing module stbMDL-a[n], stbMDL-b[n] and an intermediate terminal pull-down circuit nmdCKT[n].

[0307] exist Fig.11 In the embodiment, the voltage regulator module stbMDL-a[n] includes: a voltage regulator endpoint setting circuit stbsCKT-a[n] and a voltage regulator circuit stbCKT-a[n]. The voltage regulator module stbMDL-b[n] includes: a voltage regulator endpoint setting circuit stbsCKT-b[n] and a voltage regulator circuit stbCKT-b[n]. Figure 6 , 11 It can be seen that Fig.11 The internal components and connection methods of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are the same as Figure 6 The internal components and connection methods of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are similar to those of the voltage regulator modules stbMDL[n]. The internal components and connection methods of the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are not described in detail here.

[0308] Table 8 compares the components inside the voltage regulator modules stbMDL-a[n] and stbMDL-b[n].

[0309] Table 8

[0310]

[0311] A plurality of voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are provided in the gate drive circuit gtCKT[n], so as to prolong the life of the transistor. The timing controller can control the gate drive circuit gtCKT[n] to alternately use the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] during different frame periods Tframe.

[0312] When the timing controller sets the voltage regulator endpoint supply voltage LC-a to a positive voltage value H (LC-a=H), and sets the voltage regulator endpoint supply voltage LC-b to a low negative voltage value L (LC-b=L), the n-th stage gate driver circuit gtCKT[n] uses the voltage regulator module stbMDL-a[n] and disables the voltage regulator module stbMDL-b[n]. When the timing controller sets the voltage regulator endpoint supply voltage LC-a to a low negative voltage value L (LC-a=L), and sets the voltage regulator endpoint supply voltage LC-b to a positive voltage value H (LC-b=H), the n-th stage gate driver circuit gtCKT[n] disables the voltage regulator module stbMDL-a[n] and uses the voltage regulator module stbMDL-b[n].

[0313] Likewise, Fig.11 The nth gate drive circuit gtCKT[n] can also be used with Fig.10 Any one or two wiring methods described above to reduce leakage current. This application change is not described in detail in this article.

[0314] Then Figures 12 to 19 A second embodiment of the present disclosure on how to design the n-th gate driving circuit gtCKT[n] is described. Fig.12 Interpret the signals related to the nth stage gate drive circuit gtCKT[n]; Fig.13 Explain the circuit composition inside the n-stage gate drive circuit gtCKT[n]; Fig.14 Explain the circuit elements and connection relationship of the n-th gate drive circuit gtCKT[n]; Fig.15 A waveform diagram is used to illustrate how the signals related to the n-th gate drive circuit gtCKT[n] change in response to the full gate synchronization period DURall-sync and the n-th single-stage scanning period DURscan[n]; Figures 16A to 16C illustrate Fig.14 The n-th gate drive circuit gtCKT[n] is in the states of the respective synchronization stages STG-a1, STG-a2, STG-a3 during the full gate synchronization period DURall-sync; Figures 17A to 17C illustrate Figure 1 The n-th gate drive circuit gtCKT[n] is in the state of different scanning stages STG-s1[n], STG-s2[n], STG-s3[n] during the full gate synchronization period DURall-sync; Fig.18 Explain how to Fig.14 The n-th gate drive circuit gtCKT[n] improves the leakage current phenomenon; Fig.19 It is described how to set two sets of voltage stabilizing circuits in the n-th stage gate driving circuit gtCKT[n] of the second embodiment for the purpose of extending the life of the transistor.

[0315] See also Fig.12 , which is a schematic diagram of various signals related to the second embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure. Please also refer to Figure 4 , 12 .because Fig.12 The painting method and Figure 4 Similar, so I won't explain them one by one here. Fig.12 Signal types and uses. Figure 4 In comparison, Fig.12 More specifically, Figure 4 , 12 The difference is that the second embodiment does not set the full gate synchronization enabling signal XON_C and the pixel gate ground voltage VSSG.

[0316] See also Fig.13 , which is a block diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] of the present disclosure. Fig.13 It can be seen that the n-th gate driving circuit gtCKT[n] includes: an output signal setting module outSetMDL[n], an intermediate endpoint setting module nmSetMDL[n], and a voltage stabilization module stbMDL[n].

[0317] The output signal setting module outSetMDL[n] further includes: a state signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The intermediate endpoint setting module nmSetMDL[n] further includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n] and an intermediate endpoint pull-down circuit nmdCKT[n]. The voltage regulator module stbMDL[n] further includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] electrically connected to each other.

[0318] The circuits in the output signal setting module outSetMDL[n] are all related to the voltage of the output signal (the n-th pixel gate signal G[n] and / or the n-th column scanning state signal ST[n]). The circuits in the intermediate terminal setting module nmSetMDL[n] are all related to the voltage of the intermediate terminal NDmd[n]. The circuits in the voltage regulating module stbMDL[n] are all related to the voltage of the voltage regulating terminal NDstb[n]. Fig.13 The components and connection methods of Figure 5 They are roughly similar, so only the differences between them are explained here.

[0319] Please also see Figure 5 , 13 In short, Fig.13 The second embodiment shown does not provide the full gate synchronization period signal XON_C and the pixel gate ground voltage VSSG. Fig.13 Connection method and Figure 5 is slightly different. Figure 5 In the embodiment, the n-th pixel gate signal line G[n] is electrically connected to the voltage stabilizing circuit stbCKT[n]; but Fig.13 In the embodiment, the n-th pixel gate signal line G[n] is not electrically connected to the voltage stabilizing circuit stbCKT[n]. Figure 5 In the embodiment, the gate signal setting circuit gsCKT[n] is not electrically connected to the voltage regulation terminal NDstb[n]; however, Fig.13 In the embodiment, the gate signal setting circuit gsCKT[n] is electrically connected to the voltage regulation terminal NDstb[n].

[0320] See also Fig.14 , which is a circuit diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] according to the present disclosure. Please also refer to Fig.13 , 14 For ease of explanation, in the following circuit diagram, it will be assumed that p=1 and q=1.

[0321] Based on this assumption, the nth-level gate drive circuit gtCKT[n] receives the (np)=(n-1)th-level column scan status signal ST[np]=ST[n-1] from the (np)=(n-1)th-level gate drive circuit gtCKT[np]=gtCKT[n-1]; and receives the (n+q)=(n+1)th-level column scan status signal ST[n+q]=ST[n+1] from the (n+q)=(n+1)th-level gate drive circuit gtCKT[n+q]=gtCKT[n+1]. In addition, the nth-level gate drive circuit gtCKT[n] transmits the nth-level column scan status signal ST[n] to the (nq)=(n-1)th-level gate drive circuit gtCKT[nq]=gtCKT[n-1]; and transmits the nth-level column scan status signal ST[n] to the (n+p)=(n+1)th-level gate drive circuit gtCKT[n+p]=gtCKT[n+p].

[0322] The following first describes the composition of the circuit elements in the intermediate endpoint setting module nmSetMDL[n], the output signal setting module outSetMDL[n] and the voltage regulation module stbMDL[n]. Then, the circuit elements related to each signal are described according to the different types of signals.

[0323] The intermediate endpoint setting module nmSetMDL[n] includes: a capacitor C[n], an intermediate endpoint pull-up circuit nmuCKT[n], and an intermediate endpoint pull-down circuit nmdCKT[n]. The intermediate endpoint pull-up circuit nmuCKT[n] includes: an intermediate endpoint pull-up transistor Tnmu[n]; and the intermediate endpoint pull-down circuit nmdCKT[n] includes: intermediate endpoint pull-down transistors Tnmd_nxt[n], Tnmd_xon[n], and an intermediate endpoint reset transistor Tnmd_rst[n]. The following describes the connection method of the transistors in the intermediate endpoint pull-up circuit nmuCKT[n] and the intermediate endpoint pull-down circuit nmdCKT[n].

[0324] In the intermediate terminal pull-up circuit nmuCKT[n], the drain terminal of the intermediate terminal pull-up transistor Tnmu[n] receives the gate supply voltage VGHD, the control terminal receives the (n-1)th stage column scanning state signal ST[n-1], and the source terminal is electrically connected to the intermediate terminal NDmd[n]. Accordingly, the on / off state of the intermediate terminal pull-up transistor Tnmu[n] depends on the voltage of the (n-1)th stage column scanning state signal ST[n-1]. When the intermediate terminal pull-up transistor Tnmu[n] is turned on, the positive voltage value H (VGHD=H) of the gate supply voltage VGHD is transmitted to the intermediate terminal NDmd[n]. That is, NDmd[n]=VGHD=H.

[0325] The intermediate terminal pull-down circuit nmdCKT[n] includes: an intermediate terminal pull-down transistor Tnmd_nxt[n] and an intermediate terminal reset transistor Tnmd_rst[n]. The drain terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal receives the (n+1)th level column scan state signal ST[n+1], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ. The drain terminal of the intermediate terminal reset transistor Tnmd_rst[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal receives the intermediate terminal reset signal rstST, and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ.

[0326] Accordingly, the on / off state of the intermediate terminal pull-down transistor Tnmd_nxt[n] depends on the (n+1)th stage column scanning state signal ST[n+1]. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on, the intermediate terminal pull-down transistor Tnmd_nxt[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0327] In addition, the on / off state of the intermediate node reset transistor Tnmd_rst[n] depends on the intermediate node reset signal rstST. When the intermediate node reset signal rstST is set to a positive voltage value H (rstST=H) by the timing controller, so that the intermediate node reset transistor Tnmd_rst[n] is turned on, the intermediate node reset transistor Tnmd_rst[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate node ground voltage VSSQ to the intermediate node NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0328] Please also note that, since the intermediate terminal reset signal rstST issued by the timing controller is the lowest negative voltage value L- (rstST = L-) during the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan, the intermediate terminal reset transistor Tnmd_rst[n] remains in the off state during the full gate synchronization period DURall-sync and the round-robin scanning period DURall-scan. Therefore, the intermediate terminal reset transistor Tnmd_rst[n] will not be repeatedly drawn when explaining the circuit behavior later.

[0329] The output signal setting module outSetMDL[n] includes: a state signal setting circuit ssCKT[n] and a gate signal setting circuit gsCKT[n]. The state signal setting circuit ssCKT[n] includes: a state signal setting transistor Tss[n]); and the gate signal setting circuit gsCKT[n] includes: gate signal setting transistors Tgs1[n] and Tgs2[n].

[0330] In the state signal setting circuit ssCKT[n], the drain terminal of the state signal setting transistor Tss[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the n-th column scanning state signal line ST[n]. Accordingly, the on / off state of the state signal setting transistor Tss[n] depends on the voltage of the intermediate terminal NDmd[n]. When the state signal setting transistor Tss[n] is turned on, the voltage of the column-by-column selection signal HC[k] is transmitted to the n-th column scanning state signal ST[n]. That is, ST[n]=HC[k].

[0331] In the gate signal setting circuit gsCKT[n], the drain terminal of the gate signal setting transistor Tgs1[n] receives the column-by-column selection signal HC[k], the control terminal is electrically connected to the intermediate terminal NDmd[n], and the source terminal is electrically connected to the n-th level pixel gate signal line G[n]; the drain terminal of the gate signal setting transistor Tgs2[n] receives the full gate synchronization enable signal XON_S, the control terminal is electrically connected to the voltage regulation terminal NDstb[n], and the source terminal is electrically connected to the n-th level pixel gate signal line G[n]. Accordingly, the on / off state of the gate signal setting transistor Tgs1[n] depends on the voltage of the intermediate terminal NDmd[n].

[0332] When the gate signal setting transistor Tgs1[n] is turned on, the voltage of the column-by-column selection signal HC[k] is transmitted to the n-th pixel gate signal line G[n]. That is, G[n]=HC[k]. On the other hand, the on / off state of the gate signal setting transistor Tgs2[n] depends on the voltage of the voltage regulation terminal NDstb[n]. When the gate signal setting transistor Tgs2[n] is turned on, the voltage of the full gate synchronization enable signal XON_S is transmitted to the n-th pixel gate signal line G[n]. That is, G[n]=XON_S.

[0333] The voltage regulator module stbMDL[n] includes: a voltage regulator endpoint setting circuit stbsCKT[n] and a voltage regulator circuit stbCKT[n] electrically connected to each other. The voltage regulator endpoint setting circuit stbsCKT[n] includes: voltage regulator endpoint setting transistors Tf1[n], Tf2[n], Tf3[n], Tf4[n]; the voltage regulator circuit stbCKT[n] includes: voltage regulator transistors Tnmstb[n], Tsstb[n].

[0334] In the voltage regulation endpoint setting circuit stbsCKT[n], the drain terminal and the gate terminal of the voltage regulation endpoint setting transistor Tf1[n] both receive the voltage regulation endpoint supply voltage LC, and the source terminal is electrically connected to the voltage regulation setting endpoint NDints[n]. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf1[n] depends on the voltage regulation endpoint supply voltage LC. In this article, it is assumed that the voltage regulation endpoint supply voltage LC is continuously a positive voltage value H (LC=H). Therefore, the voltage regulation endpoint setting transistor Tf1[n] continuously maintains the on state and transmits the positive voltage value H (LC=H) of the voltage regulation endpoint supply voltage LC to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=LC=H.

[0335] The drain terminal of the voltage regulation endpoint setting transistor Tf2[n] is electrically connected to the voltage regulation setting endpoint NDints[n], the control terminal is electrically connected to the intermediate endpoint NDmd[n], and the source terminal is electrically connected to the intermediate endpoint ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf2[n] depends on the voltage of the intermediate endpoint NDmd[n]. When the voltage regulation endpoint setting transistor Tf2[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=VSSQ=L-.

[0336] The drain terminal of the voltage regulation endpoint setting transistor Tf3[n] receives the voltage regulation endpoint supply voltage LC, the control terminal is electrically connected to the voltage regulation setting endpoint NDints[n], and the source terminal is electrically connected to the voltage regulation endpoint NDstb[n]. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf3[n] depends on the voltage of the voltage regulation setting endpoint NDints[n]. When the voltage regulation endpoint setting transistor Tf3[n] is turned on, the positive voltage value (LC=H) of the voltage regulation endpoint supply voltage LC is transmitted to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=LC=H.

[0337] The drain terminal of the voltage regulation endpoint setting transistor Tf4[n] is electrically connected to the voltage regulation endpoint NDstb[n], the control terminal is electrically connected to the intermediate endpoint NDmd[n], and the source terminal is electrically connected to the intermediate endpoint ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage regulation endpoint setting transistor Tf4[n] depends on the voltage of the intermediate endpoint NDmd[n]. When the voltage regulation endpoint setting transistor Tf4[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ is transmitted to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=VSSQ=L-.

[0338] In the voltage stabilizing circuit stbCKT[n], the drain terminal of the voltage stabilizing transistor Tnmstb[n] is electrically connected to the intermediate terminal NDmd[n], the control terminal is electrically connected to the voltage stabilizing terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ; the drain terminal of the voltage stabilizing transistor Tsstb[n] is electrically connected to the n-th level column scanning state signal line ST[n], the control terminal is electrically connected to the voltage stabilizing terminal NDstb[n], and the source terminal is electrically connected to the intermediate terminal ground voltage signal line VSSQ. Accordingly, the on / off state of the voltage stabilizing transistors Tnmstb[n] and Tsstb[n] depends on the voltage of the voltage stabilizing terminal NDstb[n]. When the voltage stabilizing transistor Tnmstb[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-. When the voltage stabilizing transistor Tsstb[n] is turned on, the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ is transmitted to the n-th stage column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0339] The above describes the circuit elements and connection relationship within the n-th gate drive circuit gtCKT[n]. Next, according to the signal type related to the n-th gate drive circuit gtCKT[n], the circuit elements related to each signal are described. The internal signals of the n-th gate drive circuit gtCKT[n] include: signals at the intermediate terminal NDmd[n], the voltage setting terminal NDints[n], and the voltage regulating terminal NDstb[n]. Next, the transistors related to these internal signals are described in sequence.

[0340] Depend on Fig.14 It can be seen that, according to the different connection methods, the transistors electrically connected to the internal terminals can be divided into two categories: the first category is the transistors electrically connected to the internal terminals through the control terminal (i.e., the transistors controlled by the internal terminals); and the second category is the transistors electrically connected to the internal terminals through the drain terminal or the source terminal. Table 9 summarizes the transistors connected to each internal terminal (i.e., the transistors that change the voltage of the internal terminal).

[0341] Table 9

[0342]

[0343] Next, the circuit elements related to the input signals of the n-th gate drive circuit gtCKT[n] are described. As mentioned above, the input signals of the n-th gate drive circuit gtCKT[n] include: the (n+1)-th column scan state signal ST[n+1], the (n-1)-th column scan state signal ST[n-1], the column selection signal HC[k], the full gate synchronization enable signal XON_S, the intermediate terminal reset signal rstST, the regulated terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, and the gate supply voltage VGHD.

[0344] Depend on Fig.14 It can be seen that the (n-1)th column scanning state signal line ST[n-1] is electrically connected to the control end of the intermediate endpoint pull-up transistor Tnmu[n]. Therefore, the conduction state of the intermediate endpoint pull-up transistor Tnmu[n] depends on the (n-1)th column scanning state signal ST[n-1]. In addition, the (n+1)th column scanning state signal line ST[n+1] is electrically connected to the control end of the intermediate endpoint pull-down transistor Tnmd_nxt[n]. Therefore, the conduction state of the intermediate endpoint pull-down transistor Tnmd_nxt[n] depends on the (n+1)th column scanning state signal ST[n+1].

[0345] Depend on Fig.14 It can be seen that the column-by-column selection signal line HC[k] is electrically connected to the drain terminal of the state signal setting transistor Tss[n] and the drain terminal of the gate signal setting transistor Tgs1[n]. Accordingly, when the state signal setting transistor Tss[n] is turned on, the state signal setting transistor Tss[n] will conduct the column-by-column selection signal HC[k] to the n-th column scanning state signal line ST[n], so that the voltage of the n-th column scanning state signal line ST[n] is equal to the voltage of the column-by-column selection signal HC[k]. Moreover, when the gate signal setting transistor Tgs1[n] is turned on, the gate signal setting transistor Tgs1[n] will conduct the column-by-column selection signal HC[k] to the n-th pixel gate signal line G[n], so that the voltage of the n-th pixel gate signal line G[n] is equal to the voltage of the column-by-column selection signal HC[k]. That is, G[n]=HC[k].

[0346] Depend on Fig.14 It can be seen that the full gate synchronous enable signal line XON_S is electrically connected to the drain terminal of the gate signal setting transistor Tgs2[n]. Accordingly, when the gate signal setting transistor Tgs2[n] is turned on, the gate signal setting transistor Tgs2[n] will conduct the full gate synchronous enable signal XON_S to the n-th pixel gate signal line G[n]. That is, G[n]=XON_S.

[0347] Depend on Fig.14It can be seen that the intermediate terminal reset signal rstST is electrically connected to the control terminal of the intermediate terminal reset transistor Tnmd_rst[n]. Accordingly, the conduction state of the intermediate terminal reset transistor Tnmd_rst[n] depends on the voltage of the intermediate terminal reset signal rstST. When the intermediate terminal reset signal rstST is set to a positive voltage value H (rstST=H) by the timing controller, so that the intermediate terminal reset transistor Tnmd_rst[n] is turned on, the intermediate terminal reset transistor Tnmd_rst[n] conducts the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0348] Depend on Fig.14 It can be seen that the voltage regulator terminal supply voltage LC is electrically connected to the drain and control terminal of the voltage regulator terminal setting transistor Tf1[n], and is electrically connected to the drain of the voltage regulator terminal setting transistor Tf3[n]. Since the voltage regulator terminal supply voltage LC is maintained at a positive voltage value H (LC=H), the voltage regulator terminal setting transistor Tf1[n] remains turned on. Moreover, when the voltage regulator terminal setting transistor Tf3[n] is turned on, the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC is transmitted to the voltage regulator terminal NDstb[n]. That is, NDstb[n]=LC=H.

[0349] Depend on Fig.14 It can be seen that the intermediate terminal ground voltage VSSQ is electrically connected to the sources of the voltage regulating terminal setting transistors Tf2[n], Tf4[n], the voltage regulating transistors Tnmstb[n], Tsstb[n], the intermediate terminal pull-down transistors Tnmd_nxt[n], and the intermediate terminal reset transistors Tnmd_rst[n]. Accordingly, when the voltage regulating terminal setting transistor Tf2[n] is turned on, the voltage regulating terminal NDints[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ. That is, NDints[n]=VSSQ=L-. When the voltage regulating terminal setting transistor Tf4[n] is turned on, the voltage regulating terminal NDstb[n] is set to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ. That is, NDstb[n]=VSSQ=L-.

[0350] When any one of the voltage regulating transistor Tnmstb[n], the intermediate node pull-down transistor Tnmd_nxt[n] and the intermediate node reset transistor Tnmd_rst[n] is turned on, the intermediate node NDmd[d] is set to the lowest negative voltage value L- of the intermediate node ground voltage VSSQ. That is, NDmd[d]=VSSQ=L-.

[0351] When the voltage regulator transistor Tsstb[n] is turned on, the voltage regulator transistor Tsstb[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the n-th stage column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0352] Depend on Fig.14 It can be seen that the gate supply voltage VGHD is electrically connected to the drain of the intermediate node pull-up transistor Tnmu[n]. Therefore, when the intermediate node pull-up transistor Tnmu[n] is turned on, the intermediate node pull-up transistor Tnmu[n] transmits the positive voltage value H (VGHD=H) of the gate supply voltage VGHD to the intermediate node NDmd[n]. That is, NDmd[n]=VGHD=H.

[0353] Next, the circuit elements related to the output signal of the n-th gate drive circuit gtCKT[n] are described. The output signals of the n-th gate drive circuit gtCKT[n] are: the n-th column scanning state signal ST[n], the n-th pixel gate signal G[n]. Table 10 summarizes the circuit elements related to the output signal of the n-th gate drive circuit gtCKT[n].

[0354] Table 10

[0355]

[0356]

[0357] See also Fig.15 , which is a waveform diagram of a signal related to the n-th level pixel gate signal G[n] generated by a second embodiment of the n-th level gate driving circuit gtCKT[n] according to the present disclosure.

[0358] Fig.15 The horizontal axis is time, and the vertical axis is the signal related to the n-th level pixel gate signal G[n]. Fig.15 In the figure, the dotted box FM3 represents the change of the signal related to the n-th level pixel gate signal G[n] during the full gate synchronization period DURall-sync (between time points t1 and t4); the dotted box FM4 represents the change of the signal related to the n-th level pixel gate signal G[n] during the n-th level single-level scanning period DURscan[n] (between time points t5 and t8).

[0359] The full gate synchronization period DURall-sync further includes three synchronization phases STG-a1, STG-a2, and STG-a3. The synchronization phase STG-a1 is between time points t1 and t2, the synchronization phase STG-a2 is between time points t2 and t3, and the synchronization phase STG-a3 is between time points t3 and t4. For the N-level gate drive circuits gtCKT[1]~gtCKT[N], the circuit behaviors in the synchronization phases STG-a1, STG-a2, and STG-a3 are consistent (G[1]=…=G[N]). According to the concept of the present disclosure, the N-level pixel gate signals G[1]~G[N] will be simultaneously set to a positive voltage value H (G[1]=…=G[N]=H) in the synchronization phase STG-a2; and, in the synchronization phases STG-a1 and STG-a3, they will be simultaneously set to the second lowest negative voltage value L (G[1]=…=G[N]=L). Accordingly, the N-column pixel transistors PXL(1-M,1)-PXL(1-M,N) of the pixel array will synchronously receive the pulses of the N-level pixel gate signals G[1]-G[N] and be turned on at the same time. Therefore, the synchronous stage STG-a2 can also be called the full gate turn-on period.

[0360] According to the disclosed concept, the period of the round-robin scanning period DURall-scan covers a total of N single-level scanning periods DURscan[1] to DURscan[N]. The n-level single-level scanning period DURscan[n] corresponding to the n-level gate driving circuit gtCKT[n] includes three scanning stages: scanning stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n]. The scanning stage STG-s1[n] is between time points t5 and t6, the scanning stage STG-s2[n] is between time points t6 and t7, and the scanning stage STG-s3[n] is between time points t7 and t8.

[0361] Table 11 is summarized in Fig.15 , the voltage changes of various signals related to the n-th gate drive circuit gtCKT[n] at different stages.

[0362]

[0363]

[0364] Depend on Fig.15As can be seen from Table 11, the n-th pixel gate signal G[n] is set to a positive voltage value H (G[n]=H) in the synchronization stage STG-a2 and the scanning stage STG-s2[n], and is set to the second lowest negative voltage value L or the lowest negative voltage value L- (G[n]=L or G[n]=L-) in the remaining synchronization stages STG-a1, STG-a3 and the scanning stages STG-s1[n], STG-s3[n], STG-s4[n]. It can be seen from this that the gate drive circuit gtCKT[n] generates synchronous pulses synchronously with other gate drive circuits gtCKT[1]~gtCKT[n-1], gtCKT[n+1]~gtCKT[N] in the synchronization stage STG-a2, and, among the N-stage gate drive circuits gtCKT[1]~gtCKT[N], only the gate drive circuit gtCKT[n] controls the n-stage pixel gate signal G[n] to generate a scanning pulse in the scanning stage STG-s2[n] during the n-stage single-stage scanning period DURscan[n].

[0365] In the second embodiment of the present disclosure, the n-th level single-level scanning period DURscan[n] corresponding to the n-th level gate drive circuit gtCKT[n] partially overlaps with the single-level scanning periods DURscan[n-2], DURscan[n-1], DURscan[n+1], and DURscan[n+2] of the two previous and subsequent levels. Therefore, the period of the round-robin scanning period DURall-scan is equivalent to the period of (N+4) scanning stages. The following describes one by one the periods that overlap with the scanning stages STG-s1[n], STG-s2[n], STG-s3[n], and STG-s4[n] in the n-th level single-level scanning period DURscan[n], and the scanning stages respectively included in the other level single-level scanning periods.

[0366] The scanning phase STG-s1[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s3[n-2] of the (n-2)-level single-level scanning period DURscan[n-2] corresponding to the (n-2)-level gate drive circuit gtCKT[n-2]; and the scanning phase STG-s2[n-1] of the (n-1)-level single-level scanning period DURscan[n-1] corresponding to the (n-1)-level gate drive circuit gtCKT[n-1] overlaps.

[0367] The scanning phase STG-s2[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s3[n-1] of the (n-1)-level single-level scanning period DURscan[n-1] corresponding to the (n-1)-level gate drive circuit gtCKT[n-1]; and the scanning phase STG-s1[n+1] of the (n+1)-level single-level scanning period DURscan[n+1] corresponding to the (n+1)-level gate drive circuit gtCKT[n+1] overlaps.

[0368] The scanning phase STG-s3[n] of the n-level single-level scanning period DURscan[n] corresponding to the n-level gate drive circuit gtCKT[n] overlaps with the scanning phase STG-s2[n+1] of the (n+1)-level single-level scanning period DURscan[n+1] corresponding to the (n+1)-level gate drive circuit gtCKT[n+1]; and, the scanning phase STG-s1[n+2] of the (n+2)-level single-level scanning period DURscan[n+2] corresponding to the (n+2)-level gate drive circuit gtCKT[n+2] overlaps.

[0369] As mentioned above, the input signals received by the n-th stage gate driver circuit gtCKT[n] can be divided into two categories. One type of input signal has a constant voltage value, and the other type of input signal has a logic level that varies with each stage of the full gate synchronization period DURall-sync and the n-th stage single-stage scan period DURscan[n]. The former includes: a regulated terminal supply voltage LC with a positive voltage value H, an intermediate terminal ground voltage VSSQ with a minimum negative voltage value L-, and a gate supply voltage VGHD with a positive voltage value H. The latter includes: the (n-1)-th stage column scan state signal ST[n-1], the (n+1)-th stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], and the full gate synchronization enable signal XON_S. The logic level of the input signal changes with different stages, and the internal signal and output signal of the n-th stage gate driver circuit gtCKT[n] also change accordingly.

[0370] Among the input signals that change logic levels, the present disclosure assumes that the high logic level of the (n-1)th column scan state signal ST[n-1], the (n+1)th column scan state signal ST[n+1], and the column-by-column selection signal HC[k] all correspond to the positive voltage value H, and the low logic level all corresponds to the lowest negative voltage value L-. Also, it is assumed that the high logic level of the full gate synchronous enable signal XON_S corresponds to the positive voltage value H.

[0371] Please also note that the low logic level of the full gate synchronous enable signal XON_S corresponds to a negative voltage value, and the negative voltage value can be determined according to the product requirements of the display panel. To simplify the description, it is assumed here that in the second embodiment, the low logic level of the full gate synchronous enable signal XON_S corresponds to the second lowest negative voltage value L. In actual application, the negative voltage value corresponding to the low logic level of the full gate synchronous enable signal XON_S can also be the lowest negative voltage value L-or other selected negative voltage values.

[0372] The following uses Figures 16A to 16C and Figures 17A to 17C The present invention describes how the n-th gate driver circuit gtCKT[n] changes the conduction state of its internal transistors during the full gate synchronization period DURall-sync and the n-th single-stage scanning period DURscan[n] in response to changes in the (n-1)-th column scanning state signal ST[n-1], the (n+1)-th column scanning state signal ST[n+1], the column-by-column selection signal HC[k], the full gate synchronization enable signal XON_S, and the full gate synchronization period signal XON_C, and how the internal signals and output signals generated by the n-th gate driver circuit gtCKT[n] are affected and changed.

[0373] See also Figures 16A to 16C , which is a schematic diagram of the states of the second embodiment of the n-th stage gate driver circuit gtCKT[n] according to the present disclosure concept at each synchronization stage of the full gate synchronization period DURall-sync. The following does not specifically describe input signals with fixed voltage values ​​such as the voltage regulator terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, and the gate supply voltage VGHD, but only describes the influence of the changes of the (n-1)-th stage column scan state signal ST[n-1], the (n+1)-th stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], and the full gate synchronization enable signal XON_S on the n-th stage gate driver circuit gtCKT[n].

[0374] Please also see Fig.14 , 15 、16A. Fig.16A for, Fig.14The state of the nth gate drive circuit gtCKT[n] in the synchronization phase STG-a1 of the full gate synchronization period DURall-sync. When the nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a1, the (n-1)th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th gate drive circuit gtCKT[n-1], the (n+1)th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, and the full gate synchronization enable signal XON_S=L.

[0375] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the synchronization phase STG-a1. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the synchronization phase STG-a1 and the on / off state of the transistor.

[0376] Since the (n-1)th stage column scanning state signal ST[n-1] is the lowest negative voltage value L- (ST[n-1]=L-) in the synchronization phase STG-a1, the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the disconnected state does not affect the voltage of the intermediate terminal NDmd[n].

[0377] Since the (n+1)th stage column scanning state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-) in the synchronization phase STG-a1, the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0378] Since the voltage regulator terminal supply voltage LC is a positive voltage value H (LC=H), the voltage regulator terminal setting transistor Tf1[n] is turned on, and the voltage regulator terminal setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n]=LC=H. Since the voltage of the voltage regulator setting terminal NDints[n] is a positive voltage value H (NDints[n]=H), the voltage regulator terminal setting transistor Tf3[n] is maintained in a conductive state, and then transmits the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC to the voltage regulator terminal NDstb[n]. That is, NDstb[n]=LC=H.

[0379] Since the voltage of the voltage regulating terminal NDstb[n] is a positive voltage value H (NDstb[n]=H), the gate signal setting transistor Tgs2[n], the voltage regulating transistors Tnmstb[n], and Tsstb[n] connected to the control terminal and the voltage regulating terminal NDstb[n] are all in the on state.

[0380] The gate signal setting transistor Tgs2[n] in the on state conducts the second lowest negative voltage value L (XON_S=L) of the full gate synchronization enable signal XON_S to the n-th level pixel gate signal line G[n]. That is, G[n]=XON_S=L. The voltage regulator transistor Tnmstb[n] in the on state conducts the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-. The voltage regulator transistor Tsstb[n] in the on state conducts the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the n-th level column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0381] As mentioned above, since the intermediate terminal NDmd[n] is set to the lowest negative voltage value L- (NDmd[n]=VSSQ=L-) as the voltage regulator transistor Tnmstb[n] is turned on, the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], and the voltage regulator terminal setting transistors Tf2[n] and Tf4[n] connected to the control terminal and the intermediate terminal NDmd[n] are all disconnected. Therefore, the column-by-column selection signal HC[k]=L- will not affect the voltage of the n-th column scanning state signal ST[n] through the state signal setting transistor Tss[n], nor will it affect the voltage of the n-th pixel gate signal G[n] through the gate signal setting transistor Tgs1[n]. In addition, the voltage regulator endpoint setting transistor Tf2[n] in the disconnected state can ensure that the voltage of the voltage regulator setting endpoint NDints[n] is only affected by the voltage regulator endpoint setting transistor Tf1[n]; the voltage regulator endpoint setting transistor Tf4[n] in the disconnected state can ensure that the voltage of the voltage regulator endpoint NDstb[n] is only affected by the voltage regulator endpoint setting transistor Tf3[n].

[0382] Table 12A is summarized in Fig.16A In the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0383] Table 12A

[0384]

[0385]

[0386] Please also see Fig.14 , 15 , 16B. Fig. 16B for, Fig.14The state of the nth gate drive circuit gtCKT[n] in the synchronization phase STG-a2 of the full gate synchronization period DURall-sync. When the nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a2, the (n-1)th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th gate drive circuit gtCKT[n-1], the (n+1)th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the positive voltage value H by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, and XON_S=H.

[0387] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the synchronization stage STG-a2. And how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the synchronization stage STG-a2 and the on / off state of the transistor.

[0388] Since the (n-1)th stage column scanning state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-), the intermediate terminal pull-up transistor Tnmu[n] is turned off. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0389] Since the (n+1)th stage column scanning state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0390] Since the voltage regulator terminal supply voltage LC is a positive voltage value H (LC=H), the voltage regulator terminal setting transistor Tf1[n] is turned on, and the voltage regulator terminal setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n]=LC=H. Since the voltage of the voltage regulator setting terminal NDints[n] is a positive voltage value H (NDints[n]=H), the voltage regulator terminal setting transistor Tf3[n] is maintained in a conductive state, and transmits the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC to the voltage regulator terminal NDstb[n]. That is, NDstb[n]=LC=H.

[0391] Since the voltage of the voltage regulating terminal NDstb[n] is a positive voltage value H (NDstb[n]=H), the gate signal setting transistor Tgs2[n], the voltage regulating transistor Tnmstb[n], and the Tsstb[n] connected to the control terminal and the voltage regulating terminal NDstb[n] are all in the on state. The gate signal setting transistor Tgs2[n] in the on state transmits the full gate synchronization enable signal XON_S to the n-th level pixel gate signal line G[n] (G[n]=XON_S). In addition, because the full gate synchronization enable signal XON_S is a positive voltage H (XON_S=H) in the synchronization stage STG-a2, the n-th level pixel gate signal G[n] in the synchronization stage STG-a2 is a positive voltage H. That is, G[n]=XON_S=H.

[0392] The voltage regulator transistor Tnmstb[n] in the on state transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-. The voltage regulator transistor Tsstb[n] in the on state transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the n-th stage column scanning state signal ST[n]. That is, ST[n]=VSSQ=L-.

[0393] As mentioned above, since the intermediate terminal NDmd[n] is set to the lowest negative voltage value L-(NDmd[n]=VSSQ=L-) as the voltage regulator transistor Tnmstb[n] is turned on, the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], and the voltage regulator terminal setting transistors Tf2[n] and Tf4[n] connected to the control terminal of the intermediate terminal NDmd[n] are all disconnected. Therefore, the lowest negative voltage value L-(HC[k]=L-) of the column-by-column selection signal HC[k] will not affect the voltage of the n-th column scanning state signal ST[n] through the state signal setting transistor Tss[n], nor will it affect the voltage of the n-th pixel gate signal G[n] through the gate signal setting transistor Tgs1[n]. In addition, the voltage regulator endpoint setting transistor Tf2[n] in the disconnected state can ensure that the voltage of the voltage regulator setting endpoint NDints[n] is only affected by the voltage regulator endpoint setting transistor Tf1[n]; the voltage regulator endpoint setting transistor Tf4[n] in the disconnected state can ensure that the voltage of the voltage regulator endpoint NDstb[n] is only affected by the voltage regulator endpoint setting transistor Tf3[n].

[0394] Table 12B is summarized in Fig. 16B In the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0395] Table 12B

[0396]

[0397]

[0398] Please also see Fig.14 , 15 , 16C. Fig. 16C for, Fig.14The state of the nth gate drive circuit gtCKT[n] in the synchronization phase STG-a3 of the full gate synchronization period DURall-sync. When the nth gate drive circuit gtCKT[n] is in the synchronization phase STG-a3, the (n-1)th column scan state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)th gate drive circuit gtCKT[n-1], the (n+1)th column scan state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=L-, and XON_S=L.

[0399] Depend on Fig.15 As can be seen from the waveform diagram, the levels of the input signals are the same in the synchronization phase STG-a1 and STG-a3. Therefore, the n-th gate drive circuit gtCKT[n] is Fig. 16C The state of the n-th gate drive circuit gtCKT[n] Fig.16A The status is the same as that of Fig. 16C , the states of circuit elements and signals of the nth-stage gate drive circuit gtCKT[n].

[0400] Table 12C is summarized in Fig. 16C In the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0401] Table 12C

[0402]

[0403]

[0404] See also Figures 17A to 17C, which is a schematic diagram of the states of the n-stage gate driver circuit gtCKT[n] according to the second embodiment of the present disclosure at different stages during the n-stage single-stage scan period DURscan[n]. The following does not specifically describe input signals with fixed voltage values ​​such as the voltage regulator terminal supply voltage LC, the intermediate terminal ground voltage VSSQ, and the gate supply voltage VGHD, but only describes the effects of the changes in the (n-1)-stage column scan state signal ST[n-1], the (n+1)-stage column scan state signal ST[n+1], the column-by-column selection signal HC[k], and the full gate synchronization enable signal XON_S on the n-stage gate driver circuit gtCKT[n].

[0405] Please also see Fig.14 , 15 、17A. Fig.17A for, Fig.14 The state of the n-th gate drive circuit gtCKT[n] in the scanning phase STG-s1[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning phase STG-s1[n], the (n-1)-th column scanning state signal ST[n-1] is set to a positive voltage value H by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1]=H, ST[n+1]=L-, HC[k]=L-, and XON_S=L.

[0406] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal in the synchronization phase STG-a1. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) of the n-th gate drive circuit gtCKT[n] are determined in response to the level of the input signal in the synchronization phase STG-a1 and the on / off state of the transistor.

[0407] Since the (n-1)th stage column scanning state signal ST[n-1] is a positive voltage value H (ST[n-1]=H), the intermediate terminal pull-up transistor Tnmu[n] is turned on. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the turned-on state transmits the positive voltage value H (VGHD=H) of the gate supply voltage VGHD to the intermediate terminal NDmd[n]. That is, NDmd[n]=VGHD=H.

[0408] Since the voltage of the intermediate terminal NDmd[n] is a positive voltage value H (NDmd[n]=H), the gate signal setting transistor Tgs1[n], the voltage regulating terminal setting transistors Tf2[n], and Tf4[n] are all turned on. As the gate signal setting transistor Tgs1[n] is turned on, the gate signal setting transistor Tgs1[n] transmits the lowest negative voltage value L- (HC[k]=L-) of the column-by-column selection signal HC[k] to the n-th level pixel gate signal line G[n]. That is, G[n]=HC[k]=L-. The voltage regulating terminal setting transistor Tf2[n] in the on state transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the voltage regulating setting terminal NDints[n]. That is, NDints[n]=VSSQ=L-. The voltage regulation terminal setting transistor Tf4[n] in the on state transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the voltage regulation terminal NDstb[n]. That is, NDstb[n]=VSSQ=L-.

[0409] Since the (n+1)th stage column scanning state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-), the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0410] exist Fig.17A In the embodiment, the voltage regulation terminal setting transistor Tf1[n] is in the on state because the control terminal continuously receives the positive voltage value H (LC=H) of the voltage regulation terminal supply voltage LC. Therefore, the voltage regulation terminal setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the supply voltage signal LC to the voltage regulation setting terminal NDints[n]. That is, NDints[n]=LC=H.

[0411] Since the voltage regulating endpoint setting transistors Tf2[n] and Tf1[n] are turned on respectively according to the intermediate endpoint NDmd[n] (NDmd[n]=VGHD=H) and the voltage regulating endpoint supply voltage LC (LC=H), the voltage regulating endpoint setting transistor Tf2[n] transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate endpoint ground voltage VSSQ to the voltage regulating endpoint NDints[n], and the voltage regulating endpoint setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the voltage regulating endpoint supply voltage LC to the voltage regulating endpoint NDints[n]. Accordingly, the voltage regulator setting transistors Tf1[n] and Tf2[n] connected between the voltage regulator supply voltage signal line LC and the intermediate terminal ground voltage signal line VSSQ form a voltage dividing effect, so that the voltage of the voltage regulator setting terminal NDints[n] is between the positive voltage H (LC=H) of the voltage regulator supply voltage LC conducted by the voltage regulator setting transistor Tf1[n] and the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ conducted by the voltage regulator setting transistor Tf2[n]. That is, L- <NDints[n]<H。

[0412] In actual application, the voltage value of the voltage setting terminal NDints[n] in the synchronization stage STG-a1 depends on the size relationship between the voltage setting terminal transistors Tf1[n] and Tf2[n]. For example, if the sizes of the voltage setting terminal transistors Tf1[n] and Tf2[n] are the same, the voltage value of the voltage setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n=(H+L-) / 2.

[0413] In the synchronization stage STG-a1, the voltage of the voltage setting terminal NDints[n] is between the lowest negative voltage value L- and the positive voltage value H, which is not enough to turn on the voltage setting terminal transistor Tf3[n]. Therefore, the voltage of the voltage setting terminal NDstb[n] is equal to the lowest negative voltage value L- of the intermediate terminal ground voltage VSSQ conducted by the voltage setting terminal transistor Tf4[n] (VSSQ=L-). That is, NDstb[n]=VSSQ=L-.

[0414] In conjunction, the gate signal setting transistor Tgs2[n], the voltage regulating transistors Tnmstb[n], and Tsstb[n] are all turned off because the voltage of the voltage regulating terminal NDstb[n] is equal to the second lowest negative voltage value L (NDstb[n]=L). Therefore, in the scanning stage STG-s1[n], the gate signal setting transistor Tgs2[n] is turned off, so the second lowest negative voltage value L (XON_S=L) of the gate synchronization enable signal XON_S does not affect the voltage of the n-th level pixel gate signal G[n]. In addition, in the scanning stage STG-s1[n], because the voltage regulating transistors Tnmstb[n] and Tsstb[n] are turned off, the voltage regulating transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; and the voltage regulating transistor Tsstb[n] does not affect the voltage of the n-th level column scanning state signal ST[n].

[0415] exist Fig.17A In the embodiment, the two ends of the capacitor C[n] are respectively set to a positive voltage value H (NDmd[n]=VGHD=H) by the intermediate terminal NDmd[n], and are set to a minimum negative voltage value L (G[n]=HC[k]=L-) by the n-th pixel gate signal G[n]. Therefore, the capacitor C[n] will be charged during the scanning stage STG-s1[n]. In this paper, the voltage difference between the two ends of the charged capacitor C[n] is expressed as the capacitor voltage difference ΔVc[n].

[0416] Table 13A is summarized in Fig.17A In the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0417] Table 13A

[0418]

[0419]

[0420] Please also see Fig.14 , 15 、17B. Fig. 17B for, Fig.14The state of the n-th gate drive circuit gtCKT[n] in the scanning phase STG-s2[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning phase STG-s2[n], the (n-1)-th column scanning state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the lowest negative voltage value L- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the positive voltage value H by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=L-, HC[k]=H, and XON_S=L.

[0421] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal during the scanning phase STG-s2[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) of the n-th gate drive circuit gtCKT[n] and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) are determined in response to the level of the input signal during the scanning phase STG-s2[n] and the on / off state of the transistor.

[0422] Since the (n-1)th column scanning state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-) in the scanning phase STG-s2[n], the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the disconnected state does not affect the voltage of the intermediate terminal NDmd[n].

[0423] Since the (n+1)th column scanning state signal ST[n+1] is the lowest negative voltage value L-(ST[n+1]=L-) in the scanning phase STG-s2[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned off. At this time, the intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-off state does not affect the voltage of the intermediate terminal NDmd[n].

[0424] As mentioned before, the capacitance C[n] will be Fig.17A During the scanning phase, STG-s1[n] charges and accumulates charge. Fig. 17BIn the embodiment, the gate signal setting transistor Tgs1[n] is turned on with the voltage difference between the control terminal and the source terminal (equivalent to the capacitor voltage difference ΔVc[n]). By turning on the gate signal setting transistor Tgs1[n], the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k] is transmitted to the n-th pixel gate signal line G[n].

[0425] As above, Fig.17A The intermediate terminal NDmd[n] will be charged to the positive voltage value H of the gate supply voltage VGHD (NDmd[n]=VGHD=H) due to the conduction of the intermediate terminal pull-up transistor Tnmu. In order to distinguish the voltage of the intermediate terminal NDmd[n] in different scanning stages STG-s1[n] and STG-s2[n], the voltage of the intermediate terminal NDmd[n] in the scanning stage STG-s1[n] can be further expressed as NDmd[n](@STG-s1[n]); and the voltage of the intermediate terminal NDmd[n] in the scanning stage STG-s1[n] can be expressed as NDmd[n](@STG-s2[n]).

[0426] exist Fig. 17B In the present embodiment, the intermediate terminal pull-up transistor Tnmu is disconnected, so that the intermediate terminal NDmd[n] is in a floating state during the scanning phase STG-s2[n]. At the moment when the intermediate terminal pull-up transistor Tnmu is just disconnected, the level of the intermediate terminal NDmd[n] in the floating state still maintains the positive voltage value H of the scanning phase STG-s1[n].

[0427] The gate signal sets transistor Tgs1[n] to remain conductive during the scanning phase STG-s1[n], STG-s2[n], so that the voltage of the n-th level pixel gate signal G[n] during the scanning phase STG-s1[n], STG-s2[n] is equal to the voltage of the column-by-column selection signal HC[k] during the scanning phase STG-s1[n], STG-s2[n]. Furthermore, because the column-by-column selection signal HC[k] turned on by the gate signal setting transistor Tgs1[n] switches from the lowest negative voltage value L-(HC[k](@STG-s1[n])=L-) in the scanning stage STG-s1[n] to the positive voltage value H(HC[k](@STG-s2[n])=H) in the scanning stage STG-s2[n], the n-th level pixel gate signal G[n] also rises from the lowest negative voltage value L-(G[n](@)STG-s1[n]=L-) in the scanning stage STG-s1[n] to the positive voltage value H(G[n](@)STG-s2[n]=H) in the scanning stage STG-s2[n].

[0428] Since the capacitor C is disposed between the intermediate terminal NDmd[n] in the floating state and the n-th pixel gate signal G[n], and since the intermediate terminal NDmd[n] in the floating state still temporarily maintains a positive voltage value H equal to the scanning stage STG-s1[n], and the capacitor C has a capacitance voltage difference ΔVc[n], coupling is formed between the intermediate terminal NDmd[n] and the n-th pixel gate signal G[n]. In conjunction, the voltage NDmd[n] (@STG-s2[n]) of the intermediate terminal NDmd[n] in the scanning stage STG-s2[n] will further increase from the positive voltage value H (NDmd[n](@STG-s1[n]) = VGHD = H) of the scanning stage STG-s1[n]. At this time, the voltage NDmd[n] (@STG-s2[n]) of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] will rise to the voltage sum (H+ΔVc[n]) of the positive voltage value H plus the capacitor voltage difference ΔVc[n].

[0429] According to the above description, it can be known that the voltage NDmd[n](@STG-s2[n]) of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] can be expressed as follows, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]=VGHD+ΔVc[n]=H+ΔVc[n].

[0430] Therefore, the voltage of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] (NDmd[n](@STG-s2[n])=H+ΔVc[n]) can keep the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] stably in the on state during the scanning phase STG-s2[n]. The conduction of the state signal setting transistor Tss[n] can keep the n-th level column scanning state signal ST[n] equal to the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k]. That is, ST[n]=HC[k]=H. And, the conduction of the gate signal setting transistor Tgs1[n] can keep the n-th level pixel gate signal G[n] stably equal to the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k]. That is, G[n]=HC[k]=H.

[0431] Because the n-th pixel gate signal G[n] is coupled with the capacitor C[n], the voltage NDmd[n] (@STG-s2[n]) of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] is equal to the sum of the positive voltage value H and the capacitor voltage difference ΔVc[n] (NDmd[n](@STG-s2[n])=H+ΔVc[n]), so that the gate signal setting transistor Tgs1[n], the voltage regulating terminal setting transistors Tf2[n] and Tf4[n] connected to the control terminal and the intermediate terminal NDmd[n] are all turned on. The gate signal setting transistor Tgs1[n] in the on state transmits the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k] to the n-th pixel gate signal line G[n]. That is, G[n]=HC[k]=H. The voltage regulation endpoint setting transistor Tf2[n] in the on state transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate endpoint ground voltage VSSQ to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=VSSQ=L-. The voltage regulation endpoint setting transistor Tf4[n] in the on state transmits the lowest negative voltage value L-(VSSQ=L-) of the intermediate endpoint ground voltage VSSQ to the voltage regulation endpoint NDstb[n]. That is, NDstb[n]=VSSQ=L-.

[0432] exist Fig. 17B In the embodiment, the control end of the voltage regulation endpoint setting transistor Tf1[n] continuously receives the positive voltage value H (LC=H) of the voltage regulation endpoint supply voltage LC and is in the on state. Therefore, the voltage regulation endpoint setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the voltage regulation endpoint supply voltage LC to the voltage regulation setting endpoint NDints[n]. That is, NDints[n]=LC=H.

[0433] Because the voltage regulator endpoint setting transistors Tf1[n] and Tf2[n] are both in the on state, the voltage regulator setting endpoint NDints[n] simultaneously receives the positive voltage value H (LC=H) of the voltage regulator endpoint supply voltage LC through the voltage regulator endpoint setting transistor Tf1[n], and receives the minimum negative voltage value L- (VSSQ=L-) of the intermediate endpoint ground voltage VSSQ through the voltage regulator endpoint setting transistor Tf2[n].

[0434] Accordingly, the voltage stabilizing terminal setting transistors Tf1[n] and Tf2[n] connected between the voltage supply signal line LC at the voltage stabilizing terminal and the ground voltage signal line VSSQ at the intermediate terminal form a voltage dividing effect between the positive voltage value H (LC = H) of the voltage supply LC at the voltage stabilizing terminal and the lowest negative voltage value L- (VSSQ = L-) of the ground voltage VSSQ at the intermediate terminal. Therefore, the voltage of the voltage stabilizing setting terminal NDints[n] is between the lowest negative voltage value L- and the positive voltage value H. That is, L- < NDints[n] < H.

[0435] In practical applications, the voltage value of the voltage stabilizing setting terminal NDints[n] during the synchronization stage STG-a2 will depend on the size relationship of the voltage stabilizing terminal setting transistors Tf1[n] and Tf2[n]. For example, when the sizes of the voltage stabilizing terminal setting transistors Tf1[n] and Tf2[n] are the same, the voltage value of the voltage stabilizing setting terminal NDints[n] is equivalent to the average of the lowest negative voltage value L- and the positive voltage value H. That is, NDints[n] = (H + L-) / 2.

[0436] During the synchronization stage STG-a2, the voltage of the voltage stabilizing setting terminal NDints[n] is between the lowest negative voltage value L- and the positive voltage value H (L- < NDints[n] < H), which is not sufficient to turn on the voltage stabilizing terminal setting transistor Tf3[n]. Therefore, at this time, the voltage of the voltage stabilizing terminal NDstb[n] is equal to the lowest negative voltage value L- (VSSQ = L-) of the ground voltage VSSQ conducted by the voltage stabilizing terminal setting transistor Tf4[n]. That is, NDstb[n] = VSSQ = L-.

[0437] Consequently, during the scanning stage STG-s2[n], the gate signal setting transistors Tgs2[n], the voltage stabilizing transistors Tnmstb[n] and Tsstb[n] are all turned off because the voltage of the voltage stabilizing terminal NDstb[n] is equal to the second lowest negative voltage value L (NDstb[n] = L). Due to the disconnection of the gate signal setting transistor Tgs2[n], the second lowest negative voltage value L (XON_S = L) of the full gate synchronization enable signal XON_S does not affect the voltage of the nth stage pixel gate signal G[n]. In addition, because the voltage stabilizing transistors Tnmstb[n] and Tsstb[n] are turned off, the voltage stabilizing transistor Tnmstb[n] does not affect the voltage of the intermediate terminal NDmd[n]; and, the voltage stabilizing transistor Tsstb[n] does not affect the voltage of the nth stage column scanning state signal ST[n].

[0438] Table 13B summarizes in Fig. 17BIn the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0439] Table 13B

[0440]

[0441] Please also see Fig.14 , 15 , 17C. Fig. 17C for, Fig.14 The state of the n-th gate drive circuit gtCKT[n] in the scanning stage STG-s3[n] during the n-th single-stage scanning period DURscan[n]. When the n-th gate drive circuit gtCKT[n] is in the scanning stage STG-s3[n], the (n-1)-th column scanning state signal ST[n-1] is set to the lowest negative voltage value L- by the (n-1)-th gate drive circuit gtCKT[n-1], the (n+1)-th column scanning state signal ST[n+1] is set to the positive voltage value H- by the (n+1)-th gate drive circuit gtCKT[n+1], the column-by-column selection signal HC[k] is set to the lowest negative voltage value L- by the timing controller, and the full gate synchronization enable signal XON_S is set to the second lowest negative voltage value L by the timing controller. That is, ST[n-1]=L-, ST[n+1]=H, HC[k]=L-, and XON_S=L.

[0442] Next, the following will explain how the on / off state of the transistor in the n-th gate drive circuit gtCKT[n] changes with the level of the input signal during the scanning phase STG-s3[n]. Also, how the voltage of the internal terminals (intermediate terminal NDmd[n], voltage regulation terminal NDints[n], voltage regulation terminal NDstb[n]) of the n-th gate drive circuit gtCKT[n] and the output signal (n-th pixel gate signal line G[n], n-th column scanning state signal ST[n]) are determined in response to the level of the input signal during the scanning phase STG-s3[n] and the on / off state of the transistor.

[0443] Since the (n-1)th column scanning state signal ST[n-1] is the lowest negative voltage value L-(ST[n-1]=L-) in the scanning phase STG-s3[n], the intermediate terminal pull-up transistor Tnmu[n] is disconnected. At this time, the intermediate terminal pull-up transistor Tnmu[n] in the disconnected state does not affect the voltage of the intermediate terminal NDmd[n].

[0444] Since the (n+1)th column scan state signal ST[n+1] is a positive voltage value H (ST[n+1]=H) in the scan phase STG-s3[n], the intermediate terminal pull-down transistor Tnmd_nxt[n] is turned on. The intermediate terminal pull-down transistor Tnmd_nxt[n] in the turned-on state transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. That is, NDmd[n]=VSSQ=L-.

[0445] Since the voltage of the intermediate terminal NDmd[n] is equal to the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ, the state signal setting transistor Tss[n], the gate signal setting transistor Tgs1[n], the voltage regulation terminal setting transistors Tf2[n] and Tf4[n] are all disconnected during the scanning phase STG-s3[n]. Since the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are disconnected, the lowest negative voltage value L-(HC[k]=L-) of the column-by-column selection signal HC[k] does not affect the n-th level column scanning state signal ST[n] and the n-th level pixel gate signal G[n]. In addition, Tf2[n] in the disconnected state does not affect the voltage of the voltage regulation setting terminal NDints[n]; and the voltage regulation terminal setting transistor Tf4[n] in the disconnected state does not affect the voltage of the voltage regulation terminal NDstb[n].

[0446] Since the voltage regulator terminal supply voltage LC is a positive voltage value H (LC=H), the voltage regulator terminal setting transistor Tf1[n] is turned on, and the voltage regulator terminal setting transistor Tf1[n] transmits the positive voltage value H (LC=H) of the voltage regulator terminal supply voltage LC to the voltage regulator setting terminal NDints[n]. That is, NDints[n]=LC=H.

[0447] Since the voltage of the voltage setting terminal NDints[n] is a positive voltage value H (NDints[n]=H), the voltage setting terminal transistor Tf3[n] is kept in the on state, thereby transmitting the positive voltage value H (LC=H) of the voltage supply voltage LC to the voltage stabilizing terminal NDstb[n]. That is, NDstb[n]=LC=H.

[0448] Since the voltage of the voltage stabilizing terminal NDstb[n] is a positive voltage value H (NDstb[n]=H), the gate signal setting transistor Tgs2[n], the voltage stabilizing transistor Tnmstb[n], and the Tsstb[n] connected to the voltage stabilizing terminal NDstb[n] are all in the on state during the scanning phase STG-s3[n]. The following is explained from right to left in the order of arrangement.

[0449] The gate signal setting transistor Tgs2[n] is turned on, so that the second lowest negative voltage value L (XON_S=L) of the full gate synchronous enable signal XON_S is transmitted to the n-th pixel gate signal line G[n]. That is, G[n]=XON_S=L.

[0450] The on-state voltage regulator transistor Tnmstb[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate node ground voltage VSSQ to the intermediate node NDmd[n], so that the voltage of the intermediate node NDmd[n] is equal to the lowest negative voltage value L- (VSSQ=L-) of the intermediate node ground voltage VSSQ. That is, NDmd[n]=VSSQ=L-.

[0451] The on-state voltage regulator transistor Tsstb[n] transmits the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the n-th stage column scanning state signal ST[n]. That is, ST[n]=VSSQ=L- Fig. 17C In the embodiment, the voltage regulator transistor Tnmstb[n] and the intermediate terminal pull-down transistor Tnmd_nxt[n] simultaneously transmit the lowest negative voltage value L- (VSSQ=L-) of the intermediate terminal ground voltage VSSQ to the intermediate terminal NDmd[n]. Therefore, the voltage of the intermediate terminal NDmd[n] can be stably maintained at the lowest negative voltage value L-. That is, NDmd[n]=VSSQ=L-.

[0452] Table 13C is summarized in Fig. 17C In the figure, the (n-1)th level column scanning state signal ST[n-1], the (n+1)th level column scanning state signal ST[n+1], and the input signals such as the voltage regulator terminal supply voltage LC=H affect the on / off state of the transistor, thereby setting the voltage of the internal terminal and the output signal.

[0453] Table 13C

[0454]

[0455]

[0456] Table 14 summarizes the states of the transistors shown in Figures 16 to 16C and 17A to 17C. In Table 14, "-" represents that the transistor is in the off state.

[0457]

[0458]

[0459] Please also see Fig.15 , 16A~16C, 17A~17C. Since each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to a gate signal setting transistor Tgs2[1]~Tgs2[N], and these gate signal setting transistors Tgs2[1]~Tgs2[N] are all controlled by the same full gate synchronization period signal XON_C, the behaviors of the gate signal setting transistors Tgs2[1]~Tgs2[N] are consistent.

[0460] In the second embodiment, unlike the first embodiment, the full gate synchronization period signal XON_C is not provided. In the second embodiment, the control terminal of the gate signal setting transistor Tgs2[n] is electrically connected to the voltage regulation terminal NDstb[n]. Fig.15 It can be seen from the waveform that the voltage regulation terminal NDstb[n] maintains a positive voltage value H during the full gate synchronization period DURall-sync. By analogy, the voltage regulation terminals NDstb[1]~NDstb[N] all maintain a positive voltage value H (NDstb[n]=H) during the full gate synchronization period DURall-sync, and the gate signal setting transistors Tgs2[1]~Tgs2[N] are turned on according to their corresponding voltage regulation terminals NDstb[1]~NDstb[N] during the full gate synchronization period DURall-sync.

[0461] When the gate signal setting transistors Tgs2[1]~Tgs2[N] maintain the on state during the full gate synchronization period DURall-sync along with the voltage of the voltage regulating terminals NDstb[1]~NDstb[N], the voltages of the N-level pixel gate signals G[1]~G[n] are all determined by the voltage of the full gate synchronization enable signal XON_S. Fig.15 It can be seen that the full gate synchronization enable signal XON_S is set to a positive voltage value H (XON_S=H) only in the synchronization stage STG-a2 of the full gate synchronization period DURall-sync, and is set to the second lowest negative voltage value L (XON_S=L) in the remaining stages. In this way, the timing controller can synchronize the N-level pixel gate signals G[1]~G[N] to the positive voltage value H (G[1]=…=G[N]=H) by making the full gate synchronization enable signal XON_S equal to the positive voltage value H (XON_S=H) in the synchronization stage STG-a2 of the full gate synchronization period DURall-sync. On the other hand, during the n-th single-level scanning period DURscan[n], the gate signal sets whether the transistor Tgs2[n] is turned on or off, which will change with the voltage change of the voltage regulating terminal NDstb[n].

[0462] Since the voltage regulation terminal NDstb[n] is at the lowest negative voltage value L- (NDstb[n]=L-) during the scanning phase STG-s1[n] and STG-s2[n], the gate signal sets the transistor Tgs2[n] to be disconnected during the scanning phase STG-s1[n] and STG-s2[n] (see Fig.17A , 17B ). At this time, the gate signal setting transistor Tgs2[n] does not affect the n-th pixel gate signal G[n].

[0463] Since the voltage stabilization terminal NDstb[n] is at a positive voltage value H (NDstb[n]=H) during the scanning phase STG-s3[n], the gate signal sets the transistor Tgs2[n] to be turned on during the scanning phase STG-s3[n] (see Fig. 17C ). At this time, the gate signal setting transistor Tgs2[n] transmits the second lowest negative voltage value L (XON_S=L) of the full gate synchronous enable signal XON_S to the n-th pixel gate signal line G[n]. That is, G[n]=XON_S=L.

[0464] As mentioned above, [n] is used herein to represent a signal that changes with n=1 to N, and [k] is used herein to represent one of the groups (HC[k], where k=1 to K) after the N columns are divided into K groups of column-by-column selection signals HC[1] to HC[K]. According to the concept of the present disclosure, the column-by-column selection signals HC[1] to HC[K] are input signals that sequentially generate pulses according to the differences of the N-stage gate drive circuits gtCKT[1] to gtCKT[N].

[0465] For example, when the timing controller sets the column-by-column selection signal HC[k-1] corresponding to the (n-1)th level gate drive circuit gtCKT[n-1] to the positive voltage value H (HC[k-1]=H) in the scanning stage STG-s2[n-1], the column-by-column selection signal HC[k] corresponding to the nth level gate drive circuit gtCKT[n] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)th level gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L-(HC[k]=HC[k+1]=L-). When the timing controller sets the column-by-column selection signal HC[k] corresponding to the n-th gate drive circuit gtCKT[n] to the positive voltage value H (HC[k]=H) in the scanning stage STG-s2[n], the column-by-column selection signal HC[k-1] corresponding to the (n-1)-th gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k+1] corresponding to the (n+1)-th gate drive circuit gtCKT[n+1] are set to the lowest negative voltage value L-(HC[k-1]=HC[k+1]=L-). When the timing controller sets the column-by-column selection signal HC[k+1] corresponding to the (n+1)-th gate drive circuit gtCKT[n+1] to the positive voltage value H (HC[k+1]=H) in the scanning stage STG-s2[n+1], the column-by-column selection signal HC[k-1] corresponding to the (n-1)-th gate drive circuit gtCKT[n-1] and the column-by-column selection signal HC[k] corresponding to the (n)-th gate drive circuit gtCKT[n] are set to the lowest negative voltage value L-(HC[k-1]=HC[k]=L-).

[0466] like Fig.15 As shown, the column-by-column selection signal HC[k] corresponding to the n-th gate drive circuit gtCKT[n] is set to a positive voltage value H in the scanning phase STG-s2[n] in the n-th single-stage scanning period DURscan[n]. Fig. 17B It can be seen that when the column-by-column selection signal HC[k] corresponding to the n-th stage gate driving circuit gtCKT[n] is set to a positive voltage value H (HC[k]=H) in the scanning stage STG-s2[n], the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] are turned on by the intermediate terminal NDmd[n]=H+ΔVc[n], and then the positive voltage value H (HC[k]=H) of the column-by-column selection signal HC[k] is transmitted to the n-th stage pixel gate signal line G[n] and the n-th stage column scanning state signal line ST[n]. That is, G[n]=ST[n]=H.

[0467] Since the column-by-column selection signal HC[k] corresponding to the n-th level gate driving circuit gtCKT[n] is generated at different time periods as the levels n=1 to N are different, in this way, the timing controller can enable the state signal setting transistor Tss[n] and the gate signal setting transistor Tgs1[n] in the n-th level gate driving circuit gtCKT[n] during the scanning phase STG-s2[n] corresponding to the n-th level gate driving circuit gtCKT[n], thereby generating the pulse of the n-th level pixel gate signal G[n] and the pulse of the n-th level column scanning state signal ST[n] corresponding only to the n-th level gate driving circuit gtCKT[n].

[0468] Please also note that the scanning stage STG-s2[n] corresponding to the n-th gate drive circuit gtCKT[n] overlaps with the scanning stage STG-s3[n-1] corresponding to the (n-1)-th gate drive circuit gtCKT[n-1]; and overlaps with the scanning stage STG-s1[n+1] corresponding to the (n+1)-th gate drive circuit gtCKT[n+1]. That is, STG-s3[n-1]=STG-s2[n]=STG-s1[n+1].

[0469] Therefore, during the period corresponding to the scanning stage STG-s3[n-1]=STG-s2[n]=STG-s1[n+1], the (n-1)th level pixel gate signal G[n-1] and the (n-1)th level column scanning state signal ST[n-1] corresponding to the (n-1)th level gate drive circuit gtCKT[n-1], and the (n+1)th level pixel gate signal G[n+1] and the (n+1)th level column scanning state signal ST[n-1] corresponding to the (n+1)th level gate drive circuit gtCKT[n+1] are The (n+1)th column scanning state signal ST[n+1] will not be set to the positive voltage value H because the column-by-column selection signal HC[k-1] corresponding to the (n-1)th gate driving circuit gtCKT[n-1] is the lowest negative voltage value L-(HC[k-1]=L-) and because the column-by-column selection signal HC[k+1] corresponding to the (n+1)th gate driving circuit gtCKT[n+1] is the lowest negative voltage value L-(HC[k+1]=L-).

[0470] As mentioned above, the round-robin scanning period DURall-scan includes N single-stage scanning periods DURscan[1]~DURscan[N]. In the second embodiment of the present disclosure, each gate drive circuit gtCKT[1]~gtCKT[N] corresponds to three scanning stages. Therefore, in the second embodiment of the present disclosure, the round-robin scanning period DURall-scan covers (N+2) scanning stages.

[0471] like Fig. 17B As explained, the voltage value of the intermediate terminal NDmd[n] during the scanning phase STG-s2[n] is equivalent to the sum of the voltage value of the intermediate terminal NDmd[n] during the scanning phase STG-s1[n] and the capacitor voltage difference ΔVc[n]. That is, NDmd[n](@STG-s2[n])=NDmd[n](@STG-s1[n])+ΔVc[n]. It can be seen that the intermediate terminal NDmd[n] is not actually turned on to a stable voltage value during the scanning phase STG-s2[n]. Therefore, the intermediate terminal NDmd[n] can be regarded as floating during the scanning phase STG-s2[n]. In order to avoid leakage current from the intermediate terminal pull-down transistor Tnmd_nxt[n] and the voltage regulator transistor Tnmstb[n] due to the floating of the intermediate terminal NDmd[n], or even incomplete opening of the gate signal setting transistor Tgs1[n], the present disclosure can further modify the design of the gate driving circuit gtCKT[n].

[0472] See also Fig.18 , which is a schematic diagram of a second embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, combined with a method of reducing leakage current phenomenon.

[0473] Fig.18 Two methods (methods A and B) for reducing leakage current are shown in the figure. Please also refer to Fig.14 , 18 .

[0474] The first method to reduce the leakage current phenomenon (method A) is as follows Fig.18 As shown by the line segment lkgCNT_2a. Fig.14 In the embodiment, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is electrically connected to the intermediate terminal ground voltage signal line VSSQ. Fig.18 In the embodiment, the source of the intermediate terminal pull-down transistor Tnmd_nxt[n] is changed to be electrically connected to the full gate synchronous enable signal line XON_S.

[0475] If the second embodiment does not adopt Fig.18In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th column scan state signal line ST[n-1] and the intermediate terminal ground voltage signal line VSSQ, respectively. When the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the disconnected state, its control terminal is the lowest negative voltage value L-(ST[n-1]=L-) of the (n-1)th column scan state signal line ST[n-1], and its source terminal is the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ. At this time, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] is close to 0V, which is more likely to generate leakage current.

[0476] On the other hand, if the second embodiment adopts Fig.18 In method A, the control terminal and source terminal of the intermediate terminal pull-down transistor Tnmd_nxt[n] are electrically connected to the (n-1)th level column scan state signal line ST[n-1] and the full gate synchronous enable signal line XON_S, respectively. If the intermediate terminal pull-down transistor Tnmd_nxt[n] is in the off state, its control terminal is the lowest negative voltage value L-(ST[n-1]=L-) of the (n-1)th level column scan state signal line ST[n-1], and its source terminal is the second lowest negative voltage value L (XON_S=L) of the full gate synchronous enable signal line XON_S. Therefore, the gate-source voltage difference (ΔVgs) of the intermediate terminal pull-down transistor Tnmd_nxt[n] presents a negative bias. Therefore, by this wiring method, the leakage current generated in the intermediate terminal pull-down transistor Tnmd_nxt[n] can be reduced.

[0477] The second method to reduce leakage current phenomenon (method B) is as follows Fig.18 As shown by the line segment lkgCNT_2b. Fig.14 In the embodiment, the source of the voltage regulator transistor Tnmstb[n] is originally electrically connected to the intermediate terminal ground voltage signal line VSSQ. Fig.18 In the embodiment, the source of the voltage regulator transistor Tnmstb[n] is changed to be electrically connected to the n-th stage column scanning state signal line ST[n].

[0478] Please also see Fig.14 , 15 、17B、18. Fig. 17B As shown, when the n-th gate drive circuit gtCKT[n] is in the scanning stage STG-s2[n], the voltage regulator transistor Tnmstb[n] is in the disconnected state.

[0479] according to Fig.14When the voltage stabilizing transistor Tnmstb[n] is disconnected, the voltage at the control end of the voltage stabilizing transistor Tnmstb[n] is equal to the lowest negative voltage value L-(NDstb[n]=VSSQ=L-) from the voltage stabilizing end NDstb[n], and the voltage at its source end is equal to the lowest negative voltage value L-(VSSQ=L-) from the intermediate end ground voltage VSSQ. Therefore, if the n-th stage gate drive circuit gtCKT[n] adopts Fig.14 , 17B In the connection mode, the voltage regulator transistor Tnmstb[n] in the off state will easily generate leakage current during the round-robin scanning period DURall-scan because the gate-source voltage difference (ΔVgs) is close to 0V.

[0480] On the other hand, according to Fig.18 In the connection mode, when the n-th gate drive circuit gtCKT[n] is in the disconnected state during the round-robin scanning period DURall-scan, the voltage at the control end of the voltage regulator transistor Tnmstb[n] is equal to the lowest negative voltage value L-(NDstb[n]=L-) from the voltage regulator end point NDstb[n], and the voltage at its source end is equal to the positive voltage value H (ST[n]=HC[k]=H) from the n-th column scan status signal ST[n].

[0481] Therefore, using Fig.18 When the connection method of method B is used, if the voltage stabilizing transistor Tnmstb[n] is in the off state, since the positive voltage value of the n-th column scanning state signal ST[n] (ST[n]=HC[k]=H) is higher than the lowest negative voltage value L-(VSSQ=L-) of the intermediate terminal ground voltage VSSQ, the gate-source voltage difference (ΔVgs) of the voltage stabilizing transistor Tnmstb[n] presents a negative bias voltage (ΔVgs<0). Therefore, when the connection method of method B is used, the chance of the voltage stabilizing transistor Tnmstb[n] generating leakage current can be reduced.

[0482] In actual application, the gate drive circuit gtCKT[n] can use only method A (line segment lkgCNT_2a), only method B (line segment lkgCNT_2b), or both methods A and B (line segments lkgCNT_2a, lkgCNT_2b) to reduce leakage current. Fig.15 , 16A 16C and 17A to 17C generate the n-th level pixel gate signal G[n] and the n-th level column scanning state signal ST[n].

[0483] In order to extend the circuit life (reduce TFT stress), the gate drive circuit gtCKT[n] can use two sets of voltage regulator circuits. Fig.19 , which is a second embodiment of the n-th stage gate driving circuit gtCKT[n] based on the concept of the present disclosure, with two sets of voltage stabilizing circuit schematics. Fig.19 The internal components and connection methods of the medium voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are the same as Fig.14 The voltage regulator module stbMDL[n] is similar.

[0484] Table 15 Comparison Figure 6 The voltage regulator module stbMDL[n], and Fig.19 Components inside the voltage regulator modules stbMDL-a[n] and stbMDL-b[n].

[0485] Table 15

[0486]

[0487]

[0488] and Fig.12 Compared with the voltage regulator module stbMDL[n], the voltage regulator module stbMDL-a[n] additionally includes: a voltage regulator module selection transistor Tsel-a; the voltage regulator module stbMDL-b[n] additionally includes: a voltage regulator module selection transistor Tsel-b. The drain terminals of the voltage regulator module selection transistor Tsel-a and the voltage regulator module selection transistor Tsel-b are both electrically connected to the control terminal of the gate signal setting transistor Tgs2[n], and the voltage regulator module selection transistor Tsel-a and the voltage regulator module selection transistor Tsel-b control the on / off state of the gate signal setting transistor Tgs2[n] in turn.

[0489] In the voltage regulator module stbMDL-a[n], the control end of the voltage regulator module selection transistor Tsel-a is controlled by the voltage regulator terminal supply voltage LC-a. When the voltage regulator module selection transistor Tsel-a is turned on with the voltage regulator terminal supply voltage LC-a, the control end of the gate signal setting transistor Tgs2[n] will be set to the voltage of the voltage regulator terminal NDstb[n]. In other words, when the timing controller enables the voltage regulator module stbMDL-a[n], it does not directly control the control end of the gate signal setting transistor Tgs2[n] with the voltage of the voltage regulator terminal NDstb-a[n]. Instead, after the voltage regulator module selection transistor Tsel-a[n] is turned on, the voltage of the voltage regulator terminal NDstb-a[n] is indirectly used to control the gate signal setting transistor Tgs2[n].

[0490] Similarly, in the voltage regulator module stbMDL-b[n], the control end of the voltage regulator module selection transistor Tsel-b is controlled by the voltage regulator terminal supply voltage LC-b. When the voltage regulator module selection transistor Tsel-b is turned on with the voltage regulator terminal supply voltage LC-b, the control end of the gate signal setting transistor Tgs2[n] will be set to the voltage of the voltage regulator terminal NDstb-b[n]. In other words, when the timing controller enables the voltage regulator module stbMDL-b[n], it does not directly control the gate signal setting transistor Tgs2[n] with the voltage of the voltage regulator terminal NDstb-b[n]. Instead, after the voltage regulator module selection transistor Tsel-b is turned on, the gate signal setting transistor Tgs2[n] is indirectly controlled by the voltage of the voltage regulator terminal NDstb-b[n].

[0491] When the timing controller sets the voltage regulator endpoint supply voltage LC-a to the positive voltage value H (LC-a=H), and sets the voltage regulator endpoint supply voltage LC-b to the lowest negative voltage value L- (LC-b=L-), the voltage regulator module selection transistor Tsel-a is turned on, and the voltage regulator module selection transistor Tsel-b is turned off. At this time, the voltage regulator module selection transistor Tsel-a transmits the voltage of the voltage regulator endpoint NDstb-a[n] to the control end of the gate signal setting transistor Tgs2[n]. Therefore, it can be regarded as the timing controller controlling the gate drive circuit gtCKT[n] to use the voltage regulator module stbMDL-a[n] and disable the voltage regulator module stbMDL-b[n].

[0492] When the timing controller sets the voltage regulator endpoint supply voltage LC-a to the lowest negative voltage value L- (LC-a = L-), and sets the voltage regulator endpoint supply voltage LC-b to the positive voltage value H (LC-b = H), the voltage regulator module selection transistor Tsel-a is turned off, and the voltage regulator module selection transistor Tsel-b is turned on. At this time, the voltage regulator module selection transistor Tsel-b transmits the voltage of the voltage regulator endpoint NDstb-b[n] to the control end of the gate signal setting transistor Tgs2[n]. Therefore, it can be regarded as the timing controller controlling the gate drive circuit gtCKT[n] to disable the voltage regulator module stbMDL-a[n] and use the voltage regulator module stbMDL-b[n].

[0493] According to the concept of the present disclosure, multiple voltage regulator modules stbMDL-a[n] and stbMDL-b[n] are provided in the gate drive circuit gtCKT[n] to extend the life of the transistor. The timing controller can control the gate drive circuit gtCKT[n] to alternately use the voltage regulator modules stbMDL-a[n] and stbMDL-b[n] during different frame periods Tframe.

[0494] See also Fig. 20, which is a schematic diagram summarizing the embodiments of two types of n-th stage gate driving circuits gtCKT[n] proposed in the present disclosure. Please also refer to Figure 5 , 13 , 20. Fig. 20 Aggregation Figure 5 , 13 The relationship between circuits, internal terminals and signals in.

[0495] The internal circuits, the composition of each internal circuit, the received signals, the connection relationship, etc. included in the n-th stage gate drive circuit gtCKT[n] have been explained in the above-mentioned embodiments and will not be described in detail here. Fig. 20 In the figure, the solid lines indicate the same connection relationships in both embodiments; and the dashed line segments L1a, L1b, L1c, L2a, and L2b indicate different connection relationships adopted in different embodiments.

[0496] The dashed line segments L1a, L1b, and L1c are only used in the first embodiment. The voltage regulator circuit stbCKT[n] is electrically connected to the n-th pixel gate signal line G[n] through the dashed line segment L1a, and is electrically connected to the pixel gate ground voltage signal line VSSG through the dashed line segment L1b. In addition, the full gate synchronization period signal XON_C is electrically connected to the voltage regulator endpoint setting circuit stbsCKT[n], the intermediate endpoint pull-down circuit nmdCKT[n], and the gate signal setting circuit gsCKT[n] through the dashed line segment L1c.

[0497] The dashed line segments L2a and L2b are only used in the second embodiment. The gate signal setting circuit gsCKT[n] is electrically connected to the voltage stabilization terminal NDstb[n] through the dashed line segment L2a, and the voltage stabilization circuit stbCKT[n] is electrically connected to the pixel gate ground voltage signal line VSSG through the dashed line segment L2b.

[0498] Table 16 summarizes the components and signals of the two embodiments. The components listed in Table 16 are designed as a set of voltage regulator modules ( Figure 6 , 14 ) for comparison.

[0499] Table 16

[0500]

[0501]

[0502]

[0503] According to the comparison of Table 16, it can be seen that the input signal and the number of transistors of the second embodiment are less than those of the first embodiment. In the second embodiment, the pixel gate ground voltage VSSG and the full gate synchronization period signal XON_C are not used. In conjunction, in the second embodiment, the voltage regulator transistor Tgstb[n] connected to the pixel gate ground voltage signal line VSSG, the voltage regulator terminal setting transistors Tf5[n], Tf6[n] connected to the full gate synchronization period signal XON_C in the first embodiment are also deleted.

[0504] In the second embodiment, because the full gate synchronization period signal XON_C is not used, the control end of the gate signal setting transistor Tgs2[n] is no longer connected to the full gate synchronization period signal XON_C as in the first embodiment, but is connected to the voltage regulation end NDstb[n]. Moreover, because the voltage regulation transistor Tgstb[n] is removed, in the second embodiment, the n-th level pixel gate signal line G[n] is only connected to the capacitor C[n] and the source ends of the gate signal setting transistors Tgs1[n] and Tgs2[n].

[0505] The above descriptions are all based on the example of the nth gate driver circuit gtCKT[n] among the N gate driver circuits gtCKT[1] to gtCKT[N]. n and N are positive integers, and n≤N. The nth gate driver circuit gtCKT[n] receives the (np)th column scan state signal ST[np] from the (np)th gate driver circuit gtCKT[np], and the (n+q)th column scan state signal ST[n+q] from the (n+q)th gate driver circuit gtCKT[n+q]. When (np)<1 or (n+q)>N, because the gate driver does not include the gate driver circuits gtCKT[np] and gtCKT[n+q], the gate driver needs to be used in conjunction with a timing controller to generate the column scan state signals ST[np] and ST[n+q] in an analog manner. This article does not elaborate on the application changes and design substitutions in this part.

[0506] It can be seen from the above two embodiments provided by the present disclosure that the gate driver of the present case can control the method and order of generating N-level pixel gate signals G[1]~G[N] based on the two types of requirements of synchronization and scanning. Therefore, the gate driver of the present case can improve the deficiency of the prior art that the gate driver cannot be realized using the GOA technology. As mentioned above, whether it is a cholesterol liquid crystal panel or a general liquid crystal panel, the gate driver will generate N-level pixel gate signals G[1]~G[N] in different periods for the two types of requirements of synchronous pulse generation and continuous pulse generation. Therefore, the present case can be applied to different types of display panels.

[0507] In summary, although the present invention has been disclosed as above by way of embodiments, it is not intended to limit the present invention. A person having ordinary knowledge in the technical field to which the present invention belongs may make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention shall be determined by the scope of the attached patent application.

Claims

1. A gate driver, characterized in that: The device is electrically connected to a timing controller and includes: N-stage gate driving circuits, wherein an n-th stage gate driving circuit of the N-stage gate driving circuits includes: An output signal setting module is electrically connected to the timing controller and an intermediate terminal, wherein During a full gate synchronization period, the N-stage gate driving circuit synchronously sets the N-stage pixel gate signals according to a full gate synchronization enabling signal transmitted by the timing controller, and, During an n-th single-stage scanning period in a round of continuous scanning, the output signal setting module selectively sets an n-th column scanning state signal and an n-th pixel gate signal among the N-stage pixel gate signals in response to a voltage of an intermediate terminal, wherein: The round-robin scanning period includes N single-stage scanning periods corresponding to each of the N-stage gate driving circuits, wherein n and N are positive integers, and n is less than or equal to N.

2. The gate driver according to claim 1, wherein: It also includes: an intermediate endpoint setting module, electrically connected to an (np)th level gate driving circuit and an (n+q)th level gate driving circuit in the N-level gate driving circuit, It selectively sets the voltage of the intermediate terminal to one of a first voltage value and a second voltage value in response to an (np)-level column scanning status signal transmitted by the (np)-level gate driving circuit and an (n+q)-level column scanning status signal transmitted by the (n+q)-level gate driving circuit, wherein p and q are positive integers, and the polarity of the first voltage value is opposite to that of the second voltage value.

3. The gate driver according to claim 2, wherein: The intermediary endpoint setting module includes: an intermediate terminal pull-up circuit electrically connected to the intermediate terminal and the (np)th stage gate driving circuit, and selectively transmitting the first voltage value to the intermediate terminal in response to the (np)th stage column scanning state signal received from the (np)th stage gate driving circuit; as well as An intermediate terminal pull-down circuit is electrically connected to the intermediate terminal and the (n+q)th stage gate driving circuit, and selectively transmits the second voltage value to the intermediate terminal in response to the (n+q)th stage column scanning state signal transmitted from the (n+q)th stage gate driving circuit.

4. The gate driver according to claim 2, wherein: The output signal setting module includes: a state signal setting circuit electrically connected to the timing controller and the intermediate terminal, and selectively transmitting a scan column selection signal transmitted by the timing controller to the n-th level column scan state signal according to the control of the intermediate terminal; and A gate signal setting circuit is electrically connected to the timing controller and the intermediate terminal, and selectively transmits the scanning column selection signal to the n-th pixel gate signal according to the control of the intermediate terminal.

5. The gate driver according to claim 1, wherein: The gate driver is electrically connected to a pixel array including M*N pixel transistors, and the n-th gate driving circuit is electrically connected to an (nq)-th gate driving circuit and an (n+p)-th gate driving circuit in the N-th gate driving circuit. The output signal setting module transmits the nth level column scanning state signal to the (nq)th level gate driving circuit and the (n+p)th level gate driving circuit, and The output signal setting module transmits the n-th level pixel gate signal to M pixel transistors located in an n-th column in the pixel array.

6. The gate driver according to claim 1, wherein: The full gate synchronization period includes: a first synchronization phase; a second synchronization phase; and, A third synchronization phase, in which The first synchronization phase is earlier than the second synchronization phase, and the second synchronization phase is earlier than the third synchronization phase, and, Each of the N-level single-level scanning periods includes: a first scanning stage; a second scanning phase; and A third scanning phase, in which The first scanning phase, the second scanning phase and the third scanning phase are of equal length, wherein The first scanning stage is earlier than the second scanning stage, and the second scanning stage is earlier than the third scanning stage.

7. The gate driver according to claim 6, wherein: in During the full gate synchronization, the output signal setting module sets the n-th level pixel gate signal according to the full gate synchronization enabling signal, wherein The timing controller sets the full gate synchronization enable signal to a first voltage value in the second synchronization phase, and The timing controller sets the full gate synchronous enabling signal to a second voltage value in the first synchronous phase and the third synchronous phase, wherein the polarity of the first voltage value is opposite to that of the second voltage value.

8. The gate driver according to claim 6, wherein: in During the first scanning phase and the second scanning phase of the n-th single-stage scanning period, The output signal setting module transmits a scanning column selection signal transmitted by the timing controller to the n-th column scanning state signal and the n-th pixel gate signal according to the control of the intermediate terminal, wherein The timing controller sets the scan column selection signal to a first voltage value in the second scan phase, and The timing controller sets the scanning column selection signal to a second voltage value during the full gate synchronization period, the second scanning stage and the third scanning stage, wherein the polarity of the first voltage value is opposite to that of the second voltage value.

9. The gate driver according to claim 6, wherein: The output signal setting module further comprises: A capacitor is electrically connected between the intermediate terminal and the n-th pixel gate signal, wherein In the first scanning stage, the capacitor is charged as the intermediate terminal is set to a first voltage value and the n-th pixel gate signal is set to a second voltage value, wherein the first voltage value is opposite to the second voltage value in polarity.

10. The gate driver according to claim 9, wherein: The capacitor has a capacitance voltage difference after being charged, and In the second scanning stage of the n-th single-stage scanning period, the voltage of the intermediate terminal is equal to a voltage sum formed by the first voltage value and the capacitor voltage difference.

11. The gate driver according to claim 6, wherein: in, In the first scanning phase during the n-th single-stage scanning period, the (np)-th stage gate driving circuit sets the (np)-th stage column scanning state signal to a first voltage value, the n-th stage gate driving circuit sets the n-th stage column scanning state signal to a second voltage value, and the (n+q)-th stage gate driving circuit sets the (n+q)-th stage column scanning state signal to the second voltage value; In the second scanning phase during the n-th single-stage scanning period, the (np)-th stage gate driving circuit sets the (np)-th stage column scanning state signal to the second voltage value, the n-th stage gate driving circuit sets the n-th stage column scanning state signal to the first voltage value, and the (n+q)-th stage gate driving circuit sets the (n+q)-th stage column scanning state signal to the second voltage value; as well as, In the third scanning stage during the n-th single-stage scanning period, the (np)-th stage gate driving circuit sets the (np)-th stage column scanning state signal to the second voltage value, the n-th stage gate driving circuit sets the n-th stage column scanning state signal to the second voltage value, and the (n+q)-th stage gate driving circuit sets the (n+q)-th stage column scanning state signal to the first voltage value, The polarity of the first voltage value is opposite to that of the second voltage value.

12. The gate driver according to claim 1, wherein: The n-th gate driving circuit further comprises: A voltage regulator module, comprising: A voltage stabilization terminal setting circuit is electrically connected to the intermediate terminal and a voltage stabilization terminal, continuously receives a first voltage value, and selectively transmits the first voltage value to the voltage stabilization terminal according to the voltage of the intermediate terminal; and a voltage stabilizing circuit electrically connected to the intermediate terminal, the voltage stabilizing terminal and the n-th column scanning state signal line, and selectively transmitting a second voltage value to the intermediate terminal and the n-th column scanning state signal line according to the voltage of the voltage stabilizing terminal, The polarity of the first voltage value is opposite to that of the second voltage value.

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