Apparatus and method for half-page mode of memory device

Abstract

Apparatuses, systems, and methods for half page mode for memory devices are disclosed. The memory device may operate in a full page mode in which all memory cells along a word line are used for data or a half page mode in which less than all memory cells are used for data. In some memory devices, each half of the memory cells may be individually activated by a different word line portion. In some half-page modes, data may be stored along selected portions of the memory cells and additional information, such as metadata or module parity, may be stored along unselected portions of the memory cells. The additional information may be provided along the additional data terminals so as not to increase the data burst length.

Description

Technical Field

[0001] The present disclosure relates generally to semiconductor devices, and more particularly to semiconductor memory devices. In particular, the present disclosure relates to volatile memory, such as dynamic random access memory (DRAM). Background Art

[0002] Information may be stored as physical signals (e.g., charge on a capacitive element) on individual memory cells of the memory. During an access operation, an access command may be received along with address information specifying which memory cells should be accessed. Memory devices may be packaged together into modules.

[0003] There is a growing interest in improving the efficiency of both memory devices and memory modules to reduce unnecessary power consumption during operation and to allow for the inclusion of additional information on the module. Certain memory modes may involve accessing less than the maximum number of bits that can be accessed at one time. Various improvements may be needed to improve efficiency in how those bits are accessed and / or how the unaccessed bits are used. Summary of the invention

[0004] One aspect of the present disclosure discloses an apparatus comprising: a first set of data terminals; a second set of data terminals; a memory array comprising word lines coupled to a plurality of memory cells, wherein the plurality of memory cells are configured to store data in a first mode or to store data and additional information in a second mode, wherein during a read operation in the first mode, the data is provided along the first set of data terminals, and wherein during a read operation in the second mode, the data is provided along one or more of the first set of data terminals and the additional information is provided along one or more of the second set of data terminals.

[0005] Another aspect of the present disclosure discloses an apparatus comprising: a memory array comprising a plurality of memory cells along a word line; a mode register configured to set the device to a first mode or a second mode; a plurality of data terminals; and an input / output circuit configured to receive a plurality of data bits from the plurality of memory cells as part of a read operation in the first mode and provide the plurality of data bits in a first burst length along one or more of the data terminals, and configured to receive a plurality of data bits and a plurality of additional information bits from the plurality of memory cells as part of a read operation in the second mode and provide the plurality of data bits in the first burst length along some of the plurality of data terminals and provide the plurality of additional information bits along other of the plurality of data terminals.

[0006] Another aspect of the present disclosure discloses a method comprising: receiving a row address as part of a read operation; reading multiple data bits from a memory array as part of a first mode; providing the data bits in a first burst length along a first set of data terminals as part of the first mode; reading multiple data bits from the memory array as part of a second mode; and providing the data bits in the first burst length along the first set of data terminals and providing additional information along at least one additional data terminal as part of the second mode. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 is a block diagram of a memory system according to some embodiments of the present disclosure.

[0008] Figure 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0009] Figure 3 is a block diagram of a memory device according to some embodiments of the present disclosure.

[0010] Figure 4 is a block diagram of a portion of a memory device according to some embodiments of the present disclosure.

[0011] Figure 5 is a block diagram of information storage in a memory array operating in a half-page mode without additional information according to some embodiments of the present disclosure.

[0012] Figure 6 is a flowchart of a method of writing data in half-page mode according to some embodiments of the present disclosure.

[0013] Figure 7 is a flow chart of a method of reading data and additional information from a memory device according to some embodiments of the present disclosure.

[0014] Figure 8 is a block diagram of information storage in a memory array operating in a half-page mode (eg, 8x2p3 high reliability mode) with block parity according to some embodiments of the present disclosure.

[0015] Fig. 9 is a block diagram of how data and block parity are transmitted along DQ terminals according to some embodiments of the present disclosure.

[0016] Fig.10 is a flow chart of a method of writing data and block parity to a memory device according to some embodiments of the present disclosure.

[0017] Fig.11is a block diagram of information storage in a memory array operating in a half-page mode with additional information (eg, 8x2p3 high reliability mode with metadata enabled) according to some embodiments of the present disclosure.

[0018] Fig.12 is a block diagram of how data, block parity, and metadata are transmitted along DQ terminals according to some embodiments of the present disclosure.

[0019] Fig.13 is a flow chart of a method of providing additional information along an additional data terminal when the additional information is enabled according to some embodiments of the present disclosure.

[0020] Fig.14 is a block diagram of how data and block parity are transmitted along DQ terminals according to some embodiments of the present disclosure.

[0021] Fig.15 A method of switching between module parity modes according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0022] The following description of certain embodiments is merely exemplary in nature and is in no way intended to limit the scope of the present disclosure or its application or use. In the following detailed description of the embodiments of the present system and method, reference is made to the accompanying drawings that form a part thereof and show in an illustrative manner how specific embodiments of the described system and method can be practiced therein. These embodiments are described in sufficient detail to enable those skilled in the art to practice the currently disclosed system and method, and it should be understood that other embodiments may be utilized and structural and logical changes may be made without departing from the spirit and scope of the present disclosure. In addition, for the purpose of clarity, when certain features will be apparent to those skilled in the art, the detailed description of the features will not be discussed to avoid blurring the description of the embodiments of the present disclosure. Therefore, the following detailed description should not be understood in a limiting sense, and the scope of the present disclosure is defined only by the appended claims.

[0023] A memory array may generally include a number of memory cells arranged at the intersection of word lines (rows) and bit lines / digit lines (columns). Columns may be grouped together into column planes, and column select (CS) signals may be used to select a set of columns within each of the active column planes to provide data. When an access command is received, the memory may pre-fetch a codeword (e.g., a number of data bits) along with one or more associated information bits from the memory array and either replace the pre-fetched data with new data (e.g., as part of a write operation) or provide the pre-fetched data from the memory device (e.g., as part of a read operation).

[0024] The memory device may store additional information associated with each codeword. For example, the additional information may include metadata including information about the data codeword (or a portion of information about a larger data set including the codeword), information related to error correction on the controller (e.g., module parity bits), or a combination thereof. The memory may also store parity bits used for error correction on the device.

[0025] Memory devices may be packaged together onto a memory module. A memory module may include several memory devices, each of which stores data. A controller may access one or more memory devices on the module. The controller may have its own error correction engine that may use module-level parity bits to correct information received from the module. The module includes several channels, each of which includes several data (DQ) terminals that couple data (and sometimes additional information) to / from the controller.

[0026] The memory device may operate in a mode in which less than all memory cells along a word line accessible at one time and less than all DQ terminals are used for data. For example, a full page mode may access data along all memory cells along a word line that the memory can access at one time (e.g., 128 data bits), while in a half page mode, data may be accessed in a half of the memory cells that can be accessed at one time (e.g., 64 data bits). It may be useful to utilize the architecture of the memory to optimize power consumption in such an operating mode, thereby utilizing unselected DQ terminals to more efficiently utilize module resources or additional information storage, or a combination thereof.

[0027] The present disclosure relates to devices, systems and methods for half-page mode. In at least one aspect, the present disclosure relates to a memory having a separately addressed word line driver (or row driver) per word line. Each word line can be divided into multiple parts, each of which is activated by an associated row driver. In some operating modes, the row driver can selectively activate one or more of the row drivers based on one or more row driver select bits in the row address. These row driver select bits can be the supplement of several bits in the row address used in full page mode. Since the row drivers can be activated individually, in modes such as half-page mode where less than all memory cells along a word line are accessed, only the portion intersecting the accessed memory cells needs to be activated, resulting in power savings.

[0028] In an example implementation, the memory may divide each word line into two parts, each driven by a respective row driver. In half-page mode, the row address includes an additional bit used as a row driver select bit, which determines which of the two row drivers is activated. In an example operation in half-page mode, the memory may receive a row address specifying the first or second half of a word line. The corresponding row driver is activated and the half of the word line that intersects the selected memory cell is activated, while the half of the word line that intersects the unselected memory cell may remain inactive. This may provide power savings because the word line that intersects the unaccessed column plane does not need to be excited and its sense amplifier does not need to be triggered.

[0029] The use of half-page mode can also be used to allow additional information to be stored on the memory device and to enable different operating modes based on the amount and type of additional information stored on the memory device. For example, if data is accessed along a half of the memory cells that can be accessed at one time, the additional information can be accessed in the other half of the memory cells. In some embodiments, a memory device that utilizes one or more row address bits to select a portion of a word line can be used (e.g., to take advantage of power savings). However, other architectures can also be used. For example, additional information can be stored in a memory device that uses bits of a column address to select a portion of memory cells along a word line.

[0030] In at least one aspect, the present disclosure relates to a memory module in which module parity bits are stored on a data memory device of the module in half-page mode. In a memory module operating in full-page mode, an additional memory device (or an error correction memory device) may be used to store module parity bits. However, this may be inefficient because the additional memory device requires power, etc. during operation. In the memory module of the present disclosure, a mode in which module parity is stored on the data memory device of the module instead may be enabled, and the error correction memory device may be omitted (or disabled). For example, each memory device may store a portion of data and a portion of module parity accessed by a controller (e.g., rather than some devices storing portions of data and some devices storing portions of module parity). In some embodiments, a memory module may have a selectable amount of module parity to achieve different levels of error correction.

[0031] In at least one aspect, the present disclosure relates to a memory module in which when additional information (e.g., module parity, metadata, or a combination thereof) is enabled, it is transmitted in parallel with data. During an access operation in which the additional information is enabled, data may be transmitted along a set of data terminals while the additional information is transmitted along at least one additional data terminal. Whether or not the additional information is enabled, the burst length or number of serial bits transmitted along each terminal may remain the same, which may save time. An example memory device may include 8 data (or DQ) terminals divided into two pseudo channels. During a 2p2 mode when the additional information is disabled, data may be transmitted along two of the DQ terminals in the pseudo channel using a burst length of 32 bits. When the additional information is enabled (e.g., 2p3 mode), then the two DQ terminals may still transmit data at a burst length of 32 bits, while the third DQ terminal along the pseudo channel provides additional information.

[0032] As used herein, the term data may represent any information bit that the controller wishes to store and / or retrieve from the memory. The term metadata may represent any information bit about the data written to the memory and / or received from the memory by the controller. For example, metadata may be information about the data generated by the controller, about how the data memory is stored in the memory or where it is stored in the memory, about how many errors are detected in the data, etc. The term module parity may represent any bit of error correction capability used for the memory device outside (e.g., on the module and / or controller). Data, metadata and / or module parity represent information written to the memory by the controller and then also read from the memory by the controller, wherein data, metadata and module parity are different in terms of content and how they are generated, because metadata is based on information about the data and module parity is generated based on data and metadata. The term parity may represent any bit generated by the error correction circuit of the memory based on data, metadata, module parity or a combination thereof. Although the terms 'parity' and 'module parity' are used, any error correction scheme may be used, and parity bits and module parity bits may represent error correction bits for any type of error correction scheme. Parity may generally be retained within memory, while module parity may be written to and read from memory. In some embodiments, the amount of data, metadata, and / or module parity retrieved as part of a single access operation may represent a group of bits that are a small portion of a larger piece of information. For example, metadata bits (e.g., 4 bits) retrieved as part of a single access operation may not have any meaning by themselves, but may be meaningful when combined with several groups of metadata bits retrieved as part of other access operations (e.g., to other memory arrays and / or the same array at different times).

[0033] Figure 11 is a block diagram of a memory system according to some embodiments of the present disclosure. The memory system 100 includes a memory module 102 and a controller 150 that operates the memory module 102. The module includes a number of memory devices 104, which may be referred to as data memory devices. The module may also include an optional error correction memory device 110. The data memory devices 104 may be used to store data, while (in embodiments where they are present / active) the error correction memory devices 110 may be used to store module parity bits (or module ECC bits) that are used by an error correction code (ECC) engine or ECC circuit 152 of the controller 150 to correct errors in data read from the data memory devices 104. In some embodiments, the error correction device 110 may be omitted and the module parity may be divided into portions, each of which is stored on the data device 104 along with the data.

[0034] Module logic 112 receives commands and addresses from controller 150 over a command / address C / A bus via C / A terminals 114, and distributes those commands and addresses to memory devices 104 (and 110, if present / active) over an internal command and address bus (not shown). Data and module parity bits are communicated between controller 150 and module 102 along a data bus coupled to data terminals (DQ) 124 of module 102. Data terminals 124 are organized into pseudo channels 122 and channels 120 and 121. Channel 120 is associated with data memory device 104, while channel 121 is associated with error correction memory device 110. Each channel 120 and 121 is a set of data terminals 124 associated with memory device 104 (although pseudo channels and DQ terminals are shown for only one example channel 120(0)).

[0035] The module logic 112 includes a module setting register 114 that stores one or more module-level information pieces. For example, the module setting register 114 may include information about the operating settings of the module 102 and / or the memory devices 104 and 110 thereon. The module setting register 114 may operate in conjunction with memory setting registers (e.g., mode registers, fuse arrays, or a combination thereof) on the individual memory devices 104 and 110. Some of the module setting registers 114 may be read-only, while other registers may be read / write. The controller 150 may perform a read operation on the module setting register 114 to collect information about the operation of the module 102 and / or about the current state of the module 102. The controller 150 may perform a write operation on the module setting register 114 to change various operations of the module. In some embodiments, one or more settings of the module setting register 114 may be set based on a non-volatile storage device (e.g., a fuse array), which may be set, for example, when the module 102 is assembled. In some embodiments, one or more settings of the module settings register 114 may be based on volatile storage devices (eg, latches, memory cells, etc.) and may be set when the device is powered on.

[0036] The example registers may specify the number of DQ terminals 124 per pseudo channel 122 used for data, as well as other details such as the burst length (e.g., the number of serial bits) along a given DQ terminal 124 during an access operation. In some embodiments, the module 102 may include more physical DQ terminals than are used in the selected operating mode. For example, each channel 120 may include eight physical DQ terminals divided into two pseudo channels 122 of four physical DQ terminals each. However, the module setting registers 114 may specify a 2p2 mode in which two DQ terminals per pseudo channel are used for data.

[0037] In some embodiments, the error correction memory device 110 may be an optional feature that is disabled in certain operating modes. For example, in some operating modes, the error correction memory device 110 may be active, and module parity bits may be sent and received along the error correction channel 121 and stored in the error correction memory device 110. In some embodiments, the error correction memory device 110 may be disabled. In some embodiments, the error correction memory device 110 may be omitted from the module.

[0038] Embodiments in which error correction device 110 is omitted (or disabled) may be referred to as operating in 8x2p3 mode. For example, in an 8x2p3 module 102, there may be a total of eight memory devices on module 102: data devices 104(0) through 104(7). As explained in more detail herein, in some modes, the module parity bits originally stored on error correction device 110 may instead be distributed and stored in data memory devices 104, and the module parity bits may be sent and received along channels 120 associated with data memory devices 104.

[0039] The module setting register 114 may include settings that determine how much module parity is stored on the memory device 104. For example, the module setting register 114 (together with individual settings of the memory device 104) may specify how many module parity bits are transmitted along with the data for each access operation on each memory. In an example embodiment, there may be two modes: a high reliability mode with a larger number of module parity bits and a high storage mode with a smaller number of module parity bits. The high reliability mode may allow the ECC circuit 152 of the controller 150 to correct a larger number of errors. The high storage mode may allow a smaller amount of error correction than the high reliability mode, but increases the space available for data storage on the data device 104. The high reliability mode may simulate the amount of error correction available in a memory module with 2 error correction devices (e.g., a 10x2p2 module). The high storage mode may simulate the amount of error correction available in a module with a single error correction device (e.g., a 9x2p2 module). The high reliability and high capacity modes may be user selectable features. For example, a user may change whether module 102 operates in high capacity mode or high reliability mode by changing one or more settings of module setting registers 114, settings of the controller, settings of individual data devices 104, or a combination thereof.

[0040] Figure 1 An example memory module 102 is shown that may be used to implement some embodiments of the present disclosure. Figure 1 The example modules shown in can be configured to operate in a variety of modes. For comparison, two optional error correction devices 110(0) and 110(1) are shown. If one or two error correction devices 110 are present, the device can operate in various 10x (two error correction devices) or 9x (one error correction device) modes, such as 10x2p4 mode, 10x2p2 mode, 9x2p4 mode, or 9x2p2 mode. Such modes can still utilize memory devices of the present disclosure that use separately addressable word line portions, especially in 2p2 modes, such as, for example Figures 2 to 7 Described in more detail in .

[0041] Since the 10x mode has two error correction devices instead of one in the 9x mode, more module parity bits in the 10x mode result in an increased amount of error correction capability. For example, in the 10x2p2 mode, the amount of module parity may allow the error correction circuit 152 to correct information along up to 4 DQ terminals 124 of one of the channels 120. This may allow for 'chipkilling' or repairing data from the entire data device 104, since in the 2p2 mode, there are a total of four DQ terminals for data. In the 9x2p2 mode, the amount of module parity may allow the error correction circuit 152 to correct information along up to 2 DQ terminals.

[0042] In some embodiments of the present disclosure, one or both of the optional error correction devices 110 may be omitted. For example, if two error correction devices are omitted, the device may operate in an 8x mode (e.g., an 8x2p2 or 8x2p3 mode). Some 8x modes (e.g., 8x2p3) may utilize a half-page mode in order to store both data and additional information on the data device 104. The additional information may include block parity, which may allow the error correction circuit 152 of the controller 150 to still perform corrections. In an 8x2p3 mode in which block parity is stored on the data device 104, the amount of block parity may be an optional feature. For example, a mode may be selected in which the amount of stored block parity allows up to 4 DQs of a channel to be repaired (e.g., an amount that simulates the amount in the 10x mode), or a mode may be selected in which the amount of stored block parity allows up to 2 DQs of a channel to be repaired (e.g., an amount that simulates the amount in the 9x mode). For purposes of discussion, an 8x mode that implements 4DQ repair (eg, similar to 10x mode) may be referred to as an 8x high reliability mode, while an 8x mode that implements up to 2DQ repair (eg, similar to 9x mode) may be referred to as an 8x high capacity mode.

[0043] Each channel 120 (0) to 120 (7) and 121 includes one or more pseudo channels 122 that can be operated independently of each other. In 2p2, 2p4 and 2p3 modes, each channel 120 includes two pseudo channels 122, each of which includes four physical data terminals. In 2p4 mode, each channel 120 includes two pseudo channels 122 that use four data terminals 124 for data. In 2p2 or 2p3 mode, each pseudo channel includes two data terminals for data. In 2p3 mode, additional DQ terminals are used for additional information in parallel with the two DQ terminals for data. 2p2 and 2p3 modes can represent half-page modes of individual memory devices 104, while 2p4 mode can represent full-page mode. The amount of data transferred per access operation can vary between half-page mode and full-page mode, as described in more detail herein.

[0044] Because memory devices and channels are generally similar to one another, only a single device 104(0) and its associated channel 120(0) are described in detail herein. To simplify the layout of the figure, an arrangement of two rows of four devices 104 each is shown, and their associated channels 120 are shown as stacked boxes. However, Figure 1 The representation does not necessarily represent the layout of the physical devices. For example, a single row of eight devices 104 may be used or four devices on the front side of the chip and four devices on the back side of the chip may be used. Similarly, for clarity in the drawings, various busses and signal lines have been simplified to single lines, however, multiple physical signal lines may be represented by a single line in the drawings.

[0045] During an example write operation, the controller 150 provides a write command and address (e.g., row, column, and / or bank address, as explained in more detail herein) to the module 102 via the C / A terminal 114. The module logic 112 distributes the command and address to the data memory devices 104(0)-104(7). The controller 150 also provides the data to be written along the various DQ channels 120(0)-120(7). The ECC circuit 152 generates parity based on the data to be written and also provides module parity to the module 102 along the DQ channels. The amount of module parity bits generated may be based on the mode of the module 102. For example, in a 10x mode or an 8x high reliability mode, a first number of module parity bits (e.g., 128 module parity bits) may be generated. In a 9x mode or a 9x high capacity mode, a second number of module parity bits (e.g., 64 module parity bits) less than the first number may be generated.

[0046] Since the pseudo channel 122 can operate independently, we will consider a single pseudo channel 122 and its DQ terminal 124. Each active data terminal receives a burst of serial bits as a burst length, which together represent the codeword of the data. For example, in a 2p2 mode or a 2p3 mode, two active data terminals each receive 32 data bits (32-bit burst length) serially, for this reason across eight data devices 104 of the module 102, each device has a total of 64 data bits and a total of 512 data bits per access operation. In a 2p4 mode, each of the four active terminals still receives 32 data bits serially. In a 2p4 mode, different numbers of data devices 104 can be used per access operation, for example, 5 data devices 104 can each provide 128 data bits, for this reason across a total of 640 data bits across the module 102.

[0047] In embodiments where error correction memory device 110 is present and active (e.g., 10x and 9x modes), block parity bits are written to error correction memory device 110 along lane 121. Lane 121 may operate in a manner similar to lane 120. For example, in 2p2 mode, each DQ terminal receives 32 block parity bits, for a total of 64 bits per error correction device 110, or a total of 128 block parity bits across modules 102 in 10x mode or a total of 64 block parity bits in 9x mode.

[0048] In a mode where the error correction memory device 110 is not used (e.g., 8x2p3 mode), the block parity may be provided along the channel 120 and stored in the data device 104. For example, the data may be provided along the active data terminals of a selected pseudo channel, and the block parity may be provided along one or more additional DQ terminals of the pseudo channel. For example, the data may be provided along DQ0 and DQ1, and the block parity may be provided along DQ2. In some embodiments, other additional information (e.g., metadata) may be provided along the additional DQ terminals. In some embodiments, the additional information may be a replacement or supplement to the block parity bits.

[0049] During an example read operation in 2p2 mode, the controller 150 provides read commands and addresses along the C / A terminals 114. The module logic 112 distributes these read commands and addresses to the memory devices 104 to 110 and reads out data from the locations specified by the addresses. Data may be read out from the data lanes 120. For example, each of the two active DQ terminals 124 in the selected pseudo lane provides 32 read data bits, for a total of 64 data bits per device 104. Depending on the mode of the memory array, the block parity is read out from the error correction memory device 110 along the lanes 121 (e.g., in 10x2p2 mode or 9x2p2 mode) or from the data memory device 104 along the additional DQ terminals (e.g., in 8x2p3 mode). The ECC engine 152 of the controller 150 uses the block parity bits to check for errors and / or correct errors in the read data (and metadata, if used). Similar to the block level parity bits, in a mode where metadata is used, the controller 150 may receive metadata along additional DQ terminals of the channel 120 .

[0050] In some embodiments, block parity bits may be stored in the error correction memory device 110, while metadata is stored in the data device 104 and accessed along the unselected pseudo channels. In some embodiments, both block parity bits and metadata are accessed along the unselected pseudo channels. In some embodiments, block level parity may be used and metadata may be disabled, or vice versa.

[0051] The access operation to the data storage device 104 may use a single access pass to access data, and if one or more access passes are enabled, module parity, metadata, internal parity bits (as described in more detail herein) or a combination thereof may be accessed. In an example embodiment, each memory device may use multiple row drivers, each of which individually activates different portions of a word line. For example, in a 2p2 architecture, a first row driver may activate a first half of a word line and a second row driver may activate a second half of a word line. Each word line may intersect with a corresponding half of a column plane. Each half of a column plane may be able to access up to 72 bits of information (e.g., 64 data bits and 8 internal parity bits). As part of the access operation, the controller provides a row driver select bit or a row portion select bit as part of the row address. The state of the row driver select bit indicates which row driver (and half of the column plane and pseudo channel) is selected. In an embodiment in which no additional information is stored on the memory device, unselected row drivers may remain inactive (e.g., this may save power). In embodiments where additional information (e.g., block parity and / or metadata bits) is stored on the memory device, it may be stored in memory cells along the unselected half of the word line. Thus, the additional information may be accessed in parallel with the data, which in turn may allow the additional information to be accessed without increasing the burst length of the data compared to a mode where the additional information is not enabled.

[0052] In some embodiments, each memory device 104 may also have its own separate error correction, such as an ECC circuit that can repair one or more error bits in the codeword of the memory. For example, each memory 104 may implement single error correction (SEC) and correct up to 1 error bit in the data (and block parity and metadata). The ECC circuit in each of the memory devices 104 may generate parity bits when writing data / metadata / block parity, and then may use those parity bits to detect and / or correct errors. Unlike block parity bits, the parity bits used by the on-device ECC circuit may typically remain within the device 104 and not be read out to the controller 150.

[0053] In some embodiments, the memory device 104 may have a separately addressable portion of the memory array. Certain modes of the memory module 102 may take advantage of this feature, and therefore, in those modes the controller 150 may generate an address that selects a portion. In an example embodiment, the memory device 104 may include a separate word line portion that is addressed based on a row address. In a mode in which a portion is selected, one or more additional row driver selection bits that are not present in a mode in which a portion is not selected may be utilized to generate a row address. For example, in a 2p4 mode, the controller may generate a row address having a first length (e.g., a first number of bits), and in a 2p2 or 2p3 mode, the controller 150 may generate a row address having a second length (e.g., a first number of bits + a number of row driver selection bits). The controller 150 may provide column addresses of the same length in a 2p2 / 2p3 mode or a 2p4 mode.

[0054] Controller 150 may have other operational changes between other modes of system 100. For example, if the device is in 10x mode or 8x high reliability mode, ECC circuit 152 may generate a first number of block parity bits, while if the device is in 9x mode or 8x high capacity mode, ECC circuit 152 may generate a second number of block parity bits.

[0055] The memory system 100 can operate in a number of different modes, some example modes and various settings associated with those modes are described below in Table 1. For example, by changing the settings of the controller 150, the module setting register 114, and / or the settings of the memory device 104 (e.g., the mode register), the memory system 100 may be able to be configured into some or all of the example modes of Table 1. In some embodiments, the memory system 100 may have more or fewer modes than those listed in Table 1. For example, if the memory module 102 lacks an error correction device, it may not be able to be set into a mode in which the error correction device is used.

[0056] Table 1. Example modes for memory systems

[0057]

[0058] Table 1 shows a variety of example modes along with some example details on how to implement them. For example, Table 1 discusses implementations in which row driver select bits can be used to select one or both halves of a word line in a data device. Other examples may use other methods to select portions of a memory array (e.g., using column plane select bits). The table shows columns for whether the various discussed modes are half-page modes (modes marked as non-half-page may be full-page modes). Table 1 also shows columns for whether row driver select bits are used. In the case where row driver select bits are used, the row address may be longer than when row driver select bits are not used. The activated row portion column shows whether only the portion of the column plane selected by the row driver select bits is activated or both portions are activated.

[0059] Table 1 also shows several columns related to module level error correction. The column 'Module Error Correction' shows examples of error correction levels that the error correction circuit 152 can perform. For example, in some modes, the error correction circuit 152 may be able to perform 'chip hunting', where data (and metadata) from the entire data device 104 may be corrected, while in some modes, the error correction circuit 152 may be able to partially correct data (and metadata) from one of the data devices 104. A column representing how many error correction devices 110 are used is shown. In some embodiments, the column may represent how many error correction devices are enabled, and in some embodiments, the column may represent how many error correction devices are physically present on the module 102.

[0060] The last column shows the information stored on the data device 104. The information shown includes data, metadata, and block parity. When metadata is shown as '(metadata)' in brackets, it indicates that metadata can be enabled or disabled as an optional feature in that mode. In half-page modes (such as 2p2 and 2p3 modes), additional information (such as block parity and / or metadata (if enabled)) can be accessed as part of a single access pass, such as by storing the additional information along an unselected portion of a word line. In full-page modes (such as 2p4 mode), metadata (if enabled) can be accessed as part of a two-pass architecture, such as by saving the additional information along a second word line.

[0061] Figure 2 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure. The semiconductor device 200 may be a semiconductor memory device, such as a DRAM device integrated on a single semiconductor chip. For example, the device 100 may implement Figure 2 2. In some embodiments, memory device 200 may be a stand-alone device that is not packaged as part of a memory module. Memory device 200 may operate in various modes, such as a half-page mode (e.g., a 2p2 or 2p3 mode) or a full-page mode (e.g., a 2p4 mode).

[0062] The semiconductor device 200 includes a memory array 218. The memory array 218 is shown as including a plurality of memory banks. Figure 2 In the embodiment of the present invention, the memory array 218 is shown as including eight memory banks BANK0 to BANK7. In other embodiments, the memory array 218 may include more or fewer memory banks.

[0063] Each memory bank includes a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC arranged at intersections of the plurality of word lines WL and the plurality of bit lines BL. The selection of the word line WL is performed by the row decoder 108 and the selection of the bit line BL is performed by the column decoder 210. Figure 2 In the embodiment of FIG. 5 , row decoder 208 includes a respective row decoder for each memory bank and column decoder 210 includes a respective column decoder for each memory bank.

[0064] The bit lines BL are coupled to corresponding sense amplifiers (SAMPs). During access operations, word lines are activated by word line or row drivers 219. When a word line is active, data from memory cells along the active word line are coupled to the bit line BL and amplified by sense amplifiers SAMPs. Selected bit lines (and memory cells at intersecting active word lines) are accessed by coupling to global input / output (GIO) lines through transfer gates (TG) via local input / output (LIO) and thereby to error correction code (ECC) circuits 220 and input / output circuits 222. The bit lines are selected based on a column select (CS) signal provided by column decoder 210 in response to a column address.

[0065] The semiconductor device 200 may employ a plurality of external terminals, such as pins or pads, including a command and address (C / A) terminal coupled to a command and address bus to receive commands and addresses, a clock terminal for receiving clocks CK and / CK, a data terminal DQ for coupling to a data bus to provide data, and a power supply terminal for receiving power supply potentials VDD, VSS, VDDQ, and VSSQ. The external terminals may be directly coupled to a controller (e.g., Figure 1 150) and / or various buses / connectors that may be coupled to the module (e.g., Figure 1 102).

[0066] The clock terminal is supplied with external clocks CK and / CK provided to the input circuit 212. The external clocks may be complementary. The input circuit 212 generates an internal clock ICLK based on the CK and / CK clocks. The ICLK clock is provided to the command decoder 206 and the internal clock generator 214. The internal clock generator 214 provides various internal clocks LCLK based on the ICLK clock. The LCLK clock can be used to time the operation of various internal circuits. The internal data clock LCLK is provided to the input / output circuit 222 to time the operation of the circuit included in the input / output circuit 222, for example, it is provided to the data receiver to time the reception of write data. The input / output circuit 222 may include several interface connections, each of which may be coupled to one of the DQ pads (e.g., pads that may serve as external connections to the device 200).

[0067] The C / A terminal may be supplied with a memory address. The memory address supplied to the C / A terminal is transmitted to the address decoder 204 via the command / address input circuit 202. The address decoder 204 receives the address and supplies the decoded row address XADD to the row decoder 208 and supplies the decoded column address YADD to the column decoder 210. The decoded row address XADD may be used to determine which row should be turned on (e.g., which word line should be activated), which may cause data along the bit line to be read out along the bit line. The column decoder 210 may provide a column select signal CS based on the decoded column address YADD, which may be used to determine which sense amplifiers are coupled to the LIO. The address decoder 204 may also supply a decoded memory bank address BADD, which may indicate the memory bank of the memory array 218 containing the decoded row address XADD and the column address YADD.

[0068] The C / A terminal may be supplied with commands. Examples of commands include timing commands for controlling the timing of various operations, access commands for accessing memory, such as a read command for performing a read operation and a write command for performing a write operation, and other commands and operations. The access command may be associated with one or more row addresses XADD, column addresses YADD, and bank addresses BADD to indicate the memory cell(s) to be accessed.

[0069] The command may be provided as an internal command signal to the command decoder 106 via the command / address input circuit 202. The command decoder 206 includes circuitry to decode the internal command signal to generate various internal signals and commands for performing operations. For example, the command decoder 206 may provide a signal indicating whether data is to be read, written, etc.

[0070] The device 200 may receive an access command as a write command. When the write command is received, and the bank address, row address, and column address are supplied in time with the write command, the write data and metadata supplied by the controller to the data terminal DQ are provided along the data bus and written to the memory cell corresponding to the row address and column address in the memory array 218. The write command is received by the command decoder 206, which provides an internal command so that the write data together with the metadata is received by the data receiver in the input / output circuit 222. The write data is supplied to the ECC circuit 220 (along with additional information, such as metadata and / or module ECC bits, if enabled) via the input / output circuit 222. The ECC circuit generates parity bits based on the received data (and additional information), and the ECC circuit 120 provides the data (and additional information) and parity to the memory array 218 to be written to the memory cell specified by the column address along the word line specified by the row address.

[0071] The device 200 may receive an access command as a read command. When the read command is received, and the bank address, row address, and column address are supplied in time with the read command, read data is read from the memory cell corresponding to the row address and column address in the memory array 218. The read command is received by the command decoder 206, which provides an internal command so that the read data (and additional information) from the memory array 218 is provided to the ECC circuit 220 together with the associated parity bits. The corrected read data (and additional bits) are provided along the data bus, and the data (and additional information) is output to the outside from the data terminal DQ via the input / output circuit 222.

[0072] When a word line is activated, all memory cells along the active word line are activated and the data is amplified by the sense amplifier along the bit line that intersects the memory cell and the active word line. The number of memory cells activated along the word line may be referred to as a 'page'. In an example embodiment, there may be 8,192 or '8k' memory cells in a page (e.g., a page size of 8k). In that full page, up to 128 bits (e.g., 8 bits for each of the 16 column planes) may be accessed simultaneously. In some embodiments, the page size may not take into account additional memory cells for parity bit storage. In some embodiments of the present disclosure, in certain operating modes, less than a full page may be accessed during an access operation. In other example embodiments, pages of other sizes may be used.

[0073] For example, each word line of array 218 may be divided into multiple portions, each of which may be selectively activated by a respective row driver 219. Figure 2In the example of , two portions WLa and WLb are shown, each of which has a corresponding driver 219a and 219b. Row decoder 208 can selectively activate one or both of the portions based on the mode of device 200 and one or more row driver select bits of row address XADD. In the example full page mode, both row drivers 219a and 219b are activated and two portions of the word line are activated (e.g., for a page size of 8k). In half page mode, only one of the two row drivers 219a or 219b is activated, and half of the memory cell is accessed (e.g., a page size of 4k). The number of DQ terminals used for data transmission may affect whether half page mode or full page mode is used. For example, in 2p4 or x8 mode, only full page access can be selected. In 2p2 or x4 mode, full page or half page access can be selected (e.g., based on the setting in mode register 230).

[0074] In an example full page mode, the two portions may be activated together and the row driver select bits may be omitted from the row address, and the row address may be used to determine which pair of row drivers 219a and 219b are activated. In an example half page mode, the two portions may be addressed separately, and the row address (without the row driver select bits) is used to determine which word line is activated, while the row driver select bits determine which portion of that word line is activated (e.g., 219a or 219b). Thus, depending on the operating mode, the length (e.g., number of bits) of the row address XADD may vary. The column address YADD may remain the same length between operating modes.

[0075] In some modes of operation, a 'half page' access may be performed with respect to the amount of data accessed, but additional information may still be retrieved from the unselected halves of the page. For example, in a mode such as the 8x2p3 mode, the row driver select bits of the row address may still be used to select one half or the other half of the word line. However, both halves may still be activated, with data accessed in the selected half (e.g., the half indicated by the row driver select bits), while additional information (e.g., block parity, metadata, or a combination thereof) is accessed in the unselected half (e.g., the half not indicated by the row driver select bits).

[0076] The device 200 includes refresh control circuits 216 each associated with a bank of a memory array 218. Each refresh control circuit 216 can determine when to perform a refresh operation on the associated bank. The refresh control circuit 216 provides a refresh address RXADD (along with one or more refresh signals, Figure 11. The row decoder 208 performs a refresh operation on one or more word lines associated with RXADD. The refresh control circuit 216 can perform multiple types of refresh operations, which can determine how to generate the address RXADD and other details, such as how many word lines are associated with the address RXADD.

[0077] The ECC circuit 220 may detect and / or correct errors in the accessed data. As part of a write operation, the ECC circuit 220 may receive bits from the IO circuit 222 and generate parity bits based on those received bits. The parity bits generated by the ECC circuit 220 may be separate from the module parity bits from the ECC circuit 152, but the parity bits may be generated based in part on the module parity bits. The received bits and parity bits are written to the memory array 218. During an example read operation, the ECC circuit 220 receives a set of bits and their associated parity bits from the array 218 and uses the set of bits and the associated parity bits to locate and / or correct errors. For example, in a single error correction (SEC) scheme, up to one error bit may be located and detected. In a single error correction double error detection (SECDED) scheme, up to one error bit may be corrected, but two errors may be detected (but the bits causing those errors are not individually located, so correction cannot be performed). ECC circuit 220 may correct the information and then provide the corrected information (and / or a signal indicative of a detected error) to IO circuit 222. Parity bits may not typically be provided to IO circuit 222.

[0078] The mode register 230 may include various settings and may be used to enable various optional modes of the device. For example, the mode register 230 may include settings that specify the number of DQ terminals and whether to perform a half-page access or a full-page access. Based on the number of DQ pads used, the memory 200 may be operated in various modes. In some embodiments, the mode register 230 may include settings that determine how many DQ pads are used, even if there are more DQ pads available. The mode may determine both how many DQ pads the controller expects to send / receive data along, and the format and / or number of bits that the controller expects as part of a single access command. For example, the memory may have 16 physical DQ pads. In 2p2 mode, four of those DQ pads are used, which are divided into two pseudo channels of two DQ pads each. In 2p4 mode, eight of those DQ pads are used, which are divided into two pseudo channels of four DQ pads each. The mode register 230 may also include settings that determine the burst length at each DQ terminal as part of an access operation. The burst length represents the number of serial bits at each DQ terminal during an access operation. In some embodiments, the burst length may not change between modes. For example, both the 2p2 mode and the 2p4 mode may use a burst length of sub-32 bits per DQ terminal.

[0079] The mode register 130 may include one or more registers that specify whether the device is in half-page mode or full-page mode. For example, when the device is in 2p2 mode, the register may specify whether one portion or multiple portions of the word line are activated. The device may also include registers that enable storing additional information (e.g., module parity bits and / or metadata) on the memory device 200. For example, the mode register may include one or more additional information registers, which may include settings such as whether to enable additional information, how many additional information bits are enabled, and / or how the additional information should be stored. For example, in half-page mode, register 230 may specify that data should be stored in memory cells along the portion of the word line specified by the row driver select bits, while the additional information should be stored in memory cells along the portion of the word line not selected by the row driver select bits. In half-page mode, when the additional information is enabled, both row drivers 219a and 219b may be activated together (e.g., similar to full-page mode), and the row driver select bit(s) of the row address determine which portion is selected to store data and which portion is used to store additional information, rather than determining which row driver is activated.

[0080] The power supply terminal is supplied with power supply potentials VDD and VSS. The power supply potentials VDD and VSS are supplied to the internal voltage generator circuit 224. The internal voltage generator circuit 224 generates various internal potentials VARY and the like based on the power supply potentials VDD and VSS supplied to the power supply terminal.

[0081] The power supply terminal is also supplied with power supply potentials VDDQ and VSSQ. The power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 222. In an embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be the same potential as the power supply potentials VDD and VSS supplied to the power supply terminal. In another embodiment of the present disclosure, the power supply potentials VDDQ and VSSQ supplied to the power supply terminal may be different potentials from the power supply potentials VDD and VSS supplied to the power supply terminal. The power supply potentials VDDQ and VSSQ supplied to the power supply terminal are used for the input / output circuit 122 so that the power supply noise generated by the input / output circuit 122 does not propagate to other circuit blocks.

[0082] Figure 3 is a block diagram of a memory array with individually addressed row drivers according to some embodiments of the present disclosure. Figure 3 A portion of a memory device 300 is shown, which in some embodiments may be included in, for example, Figure 1 104 and / or 110 and / or Figure 2of 200 memory devices. Figure 3 An example memory array 300 is shown in which each word line is divided into two parts, each of which can be activated separately by a respective row driver 304 in half-page mode or the two parts can be activated together in full-page mode. More parts and row drivers can be used in other example embodiments. Figure 3 The diagram shows various components useful for describing the operation and selection of individual word line portions. Certain other components (e.g., column decoders, address decoders, command decoders, etc.) are shown in FIG. Figure 3 The view is omitted.

[0083] Memory device 300 shows an example memory device that can be used in half-page or full-page modes (e.g., 2p4, 2p2, and / or 2p3 modes). There are four DQ terminals (e.g., in a pair such as DQ0 and DQ1) organized into two pairs (a first pair DQ2 and DQ3). Figure 1 122 of the pseudo channel). Other organizations of DQ terminals (e.g., DQ0 / DQ2 and DQ1 / DQ3) may be used in other example embodiments. In half-page modes such as 2p2 and 2p3, either the first pair or the second pair is used for data bits. In some embodiments, memory device 300 may also operate in a 2p4 operating mode, where all four DQ terminals are used for data.

[0084] The memory array 302 includes several word lines WL and bit lines BL, wherein the memory cells are disposed at the intersection of the word lines and the bit lines. The word lines and the bit lines may be formed by conductive elements. Each of the word lines is associated with a row address XADD and each of the bit lines is associated with a column address YADD. The memory array 302 is divided into two parts 302a and 302b. Each part includes several word line parts and bit lines and a corresponding number of memory cells. The word lines may be divided into two parts, wherein the first part of the word lines is in the first part 302a of the array and the second part of the word lines is in the second part 302b of the array. For example, the first part 302a includes word line parts WL0a to WLNa and bit lines BL0 to BLM-1, while the second part 302b includes word line parts WL0b to WLNb and bit lines BLM to BLK-1. In some embodiments, the number of bit lines (and therefore the number of memory cells) in the two parts 302a and 302b of the memory array may be equal.

[0085] The word line portion WLa in the first portion 302a of the memory array is coupled to a corresponding row driver 304a. The word line portion WLb in the second portion 302b of the memory array is coupled to a corresponding row driver 304b. The two portions may each be separate conductive elements that are not electrically coupled. The two word line portions may be activated independently of each other. For example, portion WL0a may be active while portion WL0b remains inactive. The row decoder 310 (e.g., Figure 2 208) receives the row address XADD and selects which word line and which portion of the word line to activate based on the row address and mode. In some modes such as full page mode (e.g., as determined by, for example, Figure 2 In the mode register setting of 230), the two parts can be activated together in response to the row address.

[0086] In some modes (e.g., half-page mode), one portion of a word line may be activated and used to store data, while another portion may remain inactive (or activated and used for additional information, as described in more detail herein). In half-page mode, row decoder 310 receives a row address XADD including a row driver select bit. Figure 3 In the example of , the row driver select bit is the last bit of the row address, however other positions of the row driver select bits in the row address may be used in other example embodiments. Based on the state of the row driver select bits, the row decoder 310 provides the decoded row address signal to the first group of row drivers 304a or the second group of row drivers 304b. The remaining portion of the row address is used to determine which row driver is activated within the group. For example, if the row address is a J+1 bit address (e.g., XADD<0:J>), then one of those bits acts as a row driver select bit and the remaining J bits (e.g., XADD<0:J-1>) are used to determine which row driver and word line are activated. Therefore, the row address can be J bits long (e.g., XADD<0:J-1>) in full page mode and can be J+1 bits long (e.g., XADD<0:J>) in half page mode.

[0087] The column decoder may provide a column select signal CS that may select which bit lines are accessed, common to both memory array portions 302a and 302b. Similarly, the portion of the decoder that does not include the row driver select bits for the row address may be shared between the two portions. In some embodiments, the column select signals may be provided separately to each half to allow different bit lines to be accessed if both halves are accessed (e.g., during a half page mode in which additional information is stored in the unselected half). In general, the row driver select bits determine which portion of the word line is active, while the remainder of the row and column addresses determine which memory cells are accessed in that portion.

[0088] Each memory array portion 302a and 302b is coupled to a respective error correction code (ECC) circuit 312 and 313 (eg, Figure 2 220) and coupled to I / O circuit 314 (e.g., Figure 2 222) and DQ terminals. ECC circuit 312 can use the parity bits stored in memory array portion 302a to locate and correct errors in data stored in memory cells of portion 302a. Similarly, ECC circuit 313 can use the parity bits stored in memory array portion 302b to locate and correct errors in data stored in memory cells of portion 302b. In this way, data (and additional information) can have on-die error correction even in half-page mode.

[0089] In some embodiments, in a half-page mode where additional information is enabled, data may be stored in a selected portion, while additional information associated with that data (e.g., block parity and / or metadata bits) is stored in an unselected portion. The state of the row driver select bit may determine which portion is selected and which portion is unselected. For example, if the row driver select bit is in a first state, data may be stored in a first portion 302a along a first portion WLa of a selected word line, while additional information is stored in a second (unselected) portion 302b along a second portion WLb of the word line. Similarly, if the row driver select bit is in a second state, data may be stored in portion 302b, while additional information is stored in 302a.

[0090] When data is associated with additional information stored in an unselected portion of the array, the ECC circuit associated with the selected portion can be used for both the data and the additional information. For example, during a write operation, if the row driver select bit indicates the first portion 302a, the I / O circuit 314 provides the data and the additional data to the first ECC circuit 312, which generates parity based on the data and the additional information. The data and parity are written to the memory cells in the selected first portion 302a, while the additional information is written to the memory cells in the unselected portion 302b.

[0091] Figure 4 is a block diagram of a portion of a memory device according to some embodiments of the present disclosure. In some embodiments, the memory device 400 may represent Figure 1 The memory device 104 and / or 110, Figure 2 The memory device 200 and / or Figure 3 Part of one of the 300. Figure 4 A view showing a portion of a memory array that may be implemented in some embodiments Figure 3One of parts 302a or 302b. Figure 4 The view shows a word line portion WLx (which may be Figure 3 An example organization of half of a memory array is shown in FIG. 1 and FIG. 2 and FIG. 3 and FIG. 4 and FIG. 5 and FIG. 6 and FIG. 7 and FIG. 8 and FIG. 9 and FIG. 10 and FIG. 11 and FIG. 12 and FIG. 13 and FIG. 14 and FIG. 15 and FIG. 16 and FIG. 17 and FIG. 18 and FIG. 19 and FIG. 20 and FIG. 2 Figure 4 components.

[0092] The memory device 400 is organized into several column planes 410 to 414. Each of the column planes represents a portion of a memory bank. Each column plane 410 to 414 includes several memory cells at the intersection of a word line portion WL and a bit line. The bit lines can be grouped together into groups activated by the value of a column select (CS) signal. For clarity, only a single vertical line is used to represent the bit lines of each column selection group, however, there may be multiple columns accessed by that value of CS. For example, each line may represent 8 bit lines that are all accessed together by the value of CS. As used herein, the 'value' of CS may refer to a decoded signal provided to several groups of bit lines. Therefore, a first value may represent a first value of a multi-bit CS signal, or be active after decoding a signal line associated with that value. The word line portion WLx may extend across multiple of the column planes 410 to 414.

[0093] The memory 400 includes a set of data column planes 410 and an additional column plane 412. The additional column plane 412 may be used to store additional information, such as parity bits used by the ECC circuit 442.

[0094] In some embodiments, memory 400 may also include an optional global column redundancy (GCR) column plane 414. In some embodiments, GCR plane 414 may have fewer memory cells (e.g., fewer column select groups) than data column plane 410. GCR CP 414 includes a number of redundant columns that may be used as part of a repair operation. If the value of the CS signal is identified as including a defective memory cell in one of the data column planes 410, the memory may be remapped so that the data that was originally stored in that column plane for that value of CS is instead stored in GCR CP 414.

[0095] In an example embodiment, the memory 400 may include 8 data column planes 410(0) to 410(7). Each of those data column planes 410 includes 64 sets of column selects activated by the value of the column select signal, and each set of column selects includes 8 bit lines. Thus, when the word line is turned on in response to the row address, and the column select signal is provided to each of the 8 column planes, then 8 bits are accessed from each of the 8 column planes, for a total of 64 bits are accessed from this memory array portion. If two word line portions are active, then 128 bits are accessed. The column select signal is also provided to the additional column plane 412, but for the additional 8 bits (e.g., 8 parity bits), the column select signal may be a different value than that provided to the data column plane 410. If a repair has been performed, the GCR CP 414 may also be accessed and the value on the GCR LIO may be used, while ignoring the LIO of the column plane it replaced.

[0096] In an instance write operation, the controller (for example, Figure 1 150) provides data and additional information (if enabled) written as part of a single access pass to the memory device. If the memory array portion 400 represents a selected portion, the controller provides the data bits along the DQ terminals. In an example embodiment of a 2p2 architecture, the data may be provided as a 32-bit long burst length along two DQ terminals. The data is provided to the ECC circuit 432, which generates a set of parity bits based on the data bits. For example, 8 parity bits may be generated based on 64 data bits. Based on the column address, the value of the CS signal is provided to the column plane 410 and the data is written to the data column plane. The column select signal (which may be the same or different) is provided to the additional column plane 412 and the parity is written to the selected half of the column plane and the second value of the CS signal is provided to the unselected half of the column plane.

[0097] In a mode where additional information is enabled, then as part of the write operation described above, while the DQ terminals associated with the selected portion (e.g., the portion selected by the row driver select bit) receive data, one or more additional DQ terminals may then receive additional information. The additional information may be received in parallel with the data received along the selected DQ terminals. For example, if data is received along both the first and second DQ terminals in a burst length of 32 bits, the additional information may be received along the third and / or fourth DQ terminals. In some embodiments, there may be fewer additional information bits than data bits. In some embodiments, there may be fewer additional information bits (e.g., less than 32 bits) than the burst length of the data. In some embodiments, by adding 'junk' bits that are not latched (or otherwise ignored / discarded) by the I / O circuit to the additional information, the burst length along the additional DQ terminals may match the burst length used by the data. For example, the first two DQ terminals may each receive 32 data bits, while the third DQ terminal receives 16 additional information bits and 16 junk bits.

[0098] The extra bits are provided to the same ECC circuit (e.g., 432) as the data bits, and the parity bits are generated based on both the data bits and the extra bits. For example, if the extra information includes 16 module parity bits (e.g., in 8x high reliability mode), the ECC circuit 432 receives 80 bits, 64 data bits, and 16 module parity bits, and generates 8 parity bits based on those 80 bits. The data is written to the column plane 410 and the parity is written to the extra column plane 412 of the selected portion. The extra information is written to the memory cells of the unselected portion. The two parts of the word line portion are activated, and in the unselected portion of the value of the row driver selection bit, the extra information is written to one or more column planes specified by the value of the CS generated based on the column address. The value of the CS used in the unselected column plane may be different from the value used for the selected portion. The value for the unselected portion may be based on an internal mapping and may use the CS value reserved for storing the extra information, and therefore may not be directly addressed by the controller.

[0099] In an example read operation, the controller provides row and column addresses together with a read command. Based on the row driver selection bits of the row address, a portion 400 is selected. The remainder of the row address is used to select which word line portion is activated and the value of CS is provided based on the column address. Data is read from the data column plane 410 and parity is read from the extra column plane 412 to the ECC circuit 432 through sense amplifiers 420 and 422. The ECC circuit 432 performs error correction on the data based on parity. Depending on the embodiment and implementation, the ECC circuit may perform different levels of error detection / correction, such as single error correction (SEC), SEC double error detection (SECDED) or other forms of error correction. The ECC circuit provides the corrected data to the I / O circuit 434, which provides the data to the DQ terminals. For example, a burst of 32 data bits across 2 DQ terminals is provided.

[0100] In an embodiment where the additional information is enabled, the additional information is then retrieved from the unselected portion as part of the same example read operation. In a manner similar to a write operation, the second (unselected) portion of the word line is also accessed based on the row address and a CS signal (which may be different in value from the CS signal used in the selected portion) is provided. The additional information is read out from the selected column plane of the unselected portion to the ECC circuit 432 of the selected portion. The data and parity read out from the selected portion are combined with the additional information, and the ECC circuit detects / corrects errors in the combined data and additional information based on the parity. For example, the ECC circuit 432 may receive 88 bits, 64 data bits, 16 additional information bits (e.g., module parity in 8x high reliability mode) and 8 parity bits. The ECC circuit 432 may then correct / detect errors in the data and additional information based on the parity. The corrected data is provided to the DQ terminal associated with the selected portion by the I / O circuit 434, and the corrected additional information is provided to the DQ terminal associated with the unselected portion by the I / O circuit 434. Data is provided in bursts along selected DQ terminals, while additional information is provided in bursts in parallel along one or more of the unselected DQ terminals. If necessary, the I / O circuitry can provide one or more junk data bits to match the burst length.

[0101] Different amounts of additional information may be stored in different example modes. For example, in 8x high reliability mode, 16 module parity bits may be stored on the device. In 8x high capacity mode, 8 module parity bits may be stored on the device. If metadata is enabled, 2, 4, 8, or 16 metadata bits may also be stored. More or fewer module parity and / or metadata bits may be used in other example embodiments.

[0102] Figure 5is a block diagram of information storage in a memory array operating in half-page mode according to some embodiments of the present disclosure. Figure 5 Memory array 500 shows how data and its associated parity can be stored in a memory array in which word line portions are individually addressable (e.g., Figure 2 The memory array 218 and / or Figure 3 302). Specifically, Figure 5 An embodiment is shown in which no additional information is stored. For example, the mode register (e.g., Figure 2 230) and / or module setting registers (e.g., Figure 1 In some embodiments, Figure 5 The example of may represent the operation of a memory device on a module operating in 10x2p2 or 9x2p2 mode.

[0103] Figure 5 5. The memory array 500 is shown as being divided into two portions 502a and 502b (eg, Figure 3 302a and 302b), each of the two portions includes a number of data column planes (e.g., Figure 4 410) and corresponding additional row planes 506a and 506b (e.g., Figure 4 Each section has individually addressed row drivers 504a and 504b. Figure 5 In an implementation of , each portion 502a and 502b includes 8 data column planes, each of which provides 8 bits when accessed, and an additional column plane 506a and 506b, respectively, for storing parity.

[0104] During the example write operation, the memory receives a row address including a row driver select bit RAx. In this example, the RAx bit has a value of 0. The memory also receives data along the DQ terminals (not shown). Since this is a 2p2 mode, the data is received in two bursts along the two DQ terminals. For example, each DQ terminal can receive a burst length of 32 bits (e.g., 64 bits in total). The ECC circuit 510 receives the data bits (e.g., 64 bits) and generates parity based on those data bits. For example, 8 parity bits can be generated. Because the value of RAx is 0, the first portion 502a is selected, and the row driver 504a activates the half of the word line extending into the first portion 502a (specified by the remaining bits of the row address). The data bits are written to the memory cells at the intersection of the active portion of the word line selected by the column select signal based on the row address and the bit line. Parity bits are written to an additional column plane 506a in the selected portion at the intersection of memory cells along the active portion of the word line and the bit line selected by a column select signal (which may be the same or different than the column select signal provided to the rest of the portion).

[0105] During an example read operation, the memory receives a row address including RAx. Based on the value of RAx, one of the portions is selected, and the portion selected by RAx of the word line selected by the remaining portion of the row address is activated by row driver 504a. Data is read from memory cells associated with the value of CS along the active word line based on the column address, and parity bits are read from additional column plane 506a. ECC circuit 510 can detect and / or correct errors in the data based on parity and provide the corrected data to the DQ terminals. In 2p2 mode, 64 corrected data bits are provided along two DQ terminals in two burst lengths of 32 bits.

[0106] Figure 6 is a flow chart of a method of writing data in half-page mode according to some embodiments of the present disclosure. The method 600 may be performed by one or more of the devices or systems described herein. For example, in some embodiments, the method 600 may be performed by Figure 1 The memory device 104 and / or 110, Figure 2 200 Figure 3 300 Figure 4 400 and / or Figure 5 The method 600 is described with respect to 2p2 half-page mode, however the half-page mode may be used with other DQ terminal settings.

[0107] Method 600 represents operation of a memory device in a half-page mode without additional information. In some embodiments, method 600 may include setting the device into half-page mode. For example, method 600 may include writing to a module setup register (e.g., 114) and / or a mode register (e.g., Figure 2 230) to set the memory device to half-page mode. In some embodiments, the controller (e.g., 150) can write to the register.

[0108] The method 600 may begin at block 610, which describes receiving a plurality of data bits and a row address as part of a write operation. The method 600 may also include receiving a column address and a write command as part of the write operation. The method 600 may include receiving the data bits along a pair of DQ terminals and receiving a row address, a column address, and a write command along one or more command / address terminals.

[0109] Block 610 may be followed by block 620, which describes selecting a first portion or a second portion of a word line based on a row driver select bit of a row address. The selection may be based on a state of the row driver select bit. Method 600 may include selecting one of a plurality of word lines based on a remaining portion of the row address (e.g., a portion of the row address other than the row driver select bit) and selecting a portion of the selected word line based on the row driver select bit.

[0110] Block 620 is followed by block 630, which depicts activating the selected first portion or second portion of the word line. For example, method 600 may include activating a row driver associated with the first portion or the second portion.

[0111] In an example implementation where there are two portions of a word line, method 610 may include activating a row driver select bit associated with the first portion (eg, Figure 2 WLa and / or Figure 3 302a) associated with a first row driver (eg, Figure 2 219a and / or Figure 3 304a), or in response to the row driver select bit having a second value, activating the second portion (e.g., Figure 2 WLb and / or Figure 3 302b) associated with a second row driver (eg, Figure 2 219b and / or Figure 3 In some embodiments, method 600 may include activating a first half of memory cells along a word line instead of a second half of memory cells along the word line when the row driver select bit is in a first state, or activating a second half of memory cells along a word line instead of a first half of memory cells along the word line when the row driver select bit is in a second state.

[0112] The method 600 may include generating, with the controller, a row address having a row driver select bit as an additional bit when the device is in half-page mode. The method 600 may also include generating, with the controller, a row address without a row driver select bit when the device is not in half-page mode. For example, the method 600 may include generating, with the controller, a row address having a first number of bits when the device is in half-page mode, and generating, with the controller, a row address having a second number of bits when the device is not in half-page mode. The first number of bits may be greater than the second number of bits. The method 600 may include generating a column address having the same number of bits in half-page mode and in non-half-page mode.

[0113] Block 630 may be followed by block 640, which describes writing a plurality of data bits to the activated selected first portion or second portion of the word line. The method 600 may include writing the data to memory cells along the first portion but not the second portion if the first portion is selected, or writing the data to memory cells along the second portion but not the first portion if the second portion is selected. The method 600 may include utilizing a column decoder (e.g., Figure 2 210) generates a column select signal based on the column address and provides the column select signal to the first and second portions. The method 600 may include generating a column select signal based on the column address and providing the column select signal to the first and second portions. Figure 4 A set of bit lines is selected in each of 410) and data is written to memory cells that intersect activated portions of a set of selected bit lines and word lines in each of the column planes.

[0114] In some embodiments, method 600 may include utilizing an ECC circuit (e.g., Figure 2 220 Figure 3 312 / 313 and / or Figure 4 432) generates a set of parity bits based on the data. The method 600 may include writing the parity bits to the additional column planes along the activated portion in the first portion or the second portion.

[0115] An example read operation may be substantially similar to the example write operation of method 600. For example, the read operation may include receiving a row address including a row driver select bit, selecting a first portion or a second portion of a word line based on the row select bit, activating the selected portion, receiving a read command and a column address, and reading a plurality of data bits from memory cells along the activated portion of the word line. The read operation may also include reading parity from memory cells along the selected portion in an additional column plane and detecting / correcting errors in the read data based on the parity using an ECC circuit.

[0116] Figure 7700 is a flow chart of a method of reading data and additional information from a memory device according to some embodiments of the present disclosure. The method 700 may be performed by one or more of the apparatuses or systems described herein. For example, in some embodiments, the method 700 may be performed by Figure 1 The memory device 104 and / or 110, Figure 2 200 Figure 3 300 Figure 4 400 and / or Figure 5 In some embodiments, method 700 may be implemented on the same device as method 600, however, method 700 represents a method in which storage of additional information has been enabled (e.g., in Figure 2 The mode register 230 and / or for example Figure 1 The example operates in mode 114 of the module setting register). Figure 7

[0076] The description will generally be made with respect to a half-page mode (eg, 8x2p3 mode) that enables additional information, however in other examples, the method 700 may be implemented with other modes.

[0117] Figure 7 The method 700 may begin at block 710, which describes receiving a row address as part of a read operation. The row address may include a row driver select bit. The row driver select bit may be a supplement to a number of bits of the row address used in a mode in which additional information is disabled. The method 700 may also include receiving a read command and a column address as part of the read operation. For example, the method 700 may include receiving a read command from a controller (e.g., Figure 1 150) receives a row address, a column address, and a read command. The row address, the column address, and / or the read command may be received at different times during the overall read operation.

[0118] Block 710 may be followed by block 720, which describes selecting a first portion or a second portion of a word line based on a row driver select bit of a row address. The selection may be based on a state of the row driver select bit. Method 700 may include selecting one of a plurality of word lines based on a remaining portion of the row address (e.g., a portion of the row address other than the row driver select bit) and selecting a portion of the selected word line based on the row driver select bit.

[0119] In an example implementation where there are two portions of a word line, method 720 may include selecting a row driver select bit associated with the first portion (eg, Figure 2 WLa and / or Figure 3 302a) associated with a first row driver (eg, Figure 2 219a and / or Figure 3 304a), or in response to the row driver select bit having a second value, selects the second portion (e.g., Figure 2WLb and / or Figure 3 302b) associated with a second row driver (eg, Figure 2 219b and / or Figure 3 In some embodiments, method 700 may include activating two portions of a word line: a selected portion and an unselected portion.

[0120] Block 720 is followed by blocks 730 and 740. Block 730 describes reading a plurality of data bits from memory cells along selected ones in the first portion or the second portion of the word line. Block 740 describes reading a plurality of additional information bits (e.g., block parity bits and / or metadata bits) from memory cells along unselected ones in the first portion or the second portion of the word line. In some embodiments, blocks 730 and 740 may occur more or less simultaneously as part of the same access operation. In embodiments where the word line is divided into two portions, then the method may include reading data bits from memory cells along one portion and reading additional bits from memory cells along the other portion. For example, if the row driver select bit selects the first portion, then the additional bits are read from the second portion.

[0121] The method 700 may include providing a first column select signal (eg, from, for example, Figure 2 210) to provide a plurality of column planes along a selected one of the first portion or the second portion (e.g., Figure 4 410) and provides a second column select signal (e.g., from a column decoder) to one or more column planes along an unselected one of the first portion or the second portion. In some embodiments, the two column select signals may have different values ​​from each other. The value of the first column select signal may be based on the column address, and the value of the second column select signal may be based on an internal mapping that associates the second value with the first value (and the row address).

[0122] Blocks 730 and 740 may generally be followed by block 750, which describes providing a plurality of data bits along the first set of data terminals and providing a plurality of additional information bits along at least one additional data terminal. For example, the plurality of data bits may be provided along the first data terminal and the second data terminal. The additional information bits may be provided along the third data terminal. The data may be provided in a burst length along the first set of data terminals. The burst length may match the burst length used when the additional information is not enabled. In some embodiments, method 700 may include providing the additional information in a burst length that matches the burst length along the first set of data terminals. For example, the method may include providing the additional information and junk bits along the third data terminal.

[0123] In some embodiments, the method may include removing from an additional column plane (eg, Figure 4412) reads the parity bits. For example, the method may include providing a third column select signal from a column decoder to the additional column plane and reading the parity bits from the additional column plane. The third column select signal may have the same or different value as the first column select signal. The method 700 may include correcting errors in the data and the additional information based on the data, the additional information, and the parity. The method 700 may include providing the corrected data and the additional information along the first set of data terminals and the at least one additional data terminal, respectively.

[0124] Figures 8 to 15 Various example embodiments in which additional information is enabled are discussed in more detail. For example, Figures 8 to 10 14-15 discuss example embodiments in which the additional information includes a module parity bit, and Figures 11 to 13 Example embodiments are discussed in which the additional information includes both module parity bits and metadata. In particular, Figures 8 to 10 Discuss the 8x2p3 high reliability mode, and Figures 14 to 15 Discuss the 8x2p3 high capacity mode. Figures 11 to 13 Description is made with respect to an example embodiment in which metadata is enabled in 8x high reliability mode. Figures 8 to 15 Each of the examples of may be described with respect to a particular number of module parity, data, metadata bits, etc. However, other example embodiments may use other numbers of bits.

[0125] In some embodiments, Figures 8 to 13 An example embodiment of can be provided by, for example Figure 1 In some embodiments, Figures 8 to 15 An example of Figures 2 to 7 In some embodiments, the memory device discussed above may be implemented in which different portions of the word lines may be activated individually (e.g., by row driver select bits of a row address). Figures 8 to 15 Examples of may be implemented in other ways. For example, an entire word line may be activated by a row address, and a column address may include a column plane select bit that determines which portion of the column plane is selected.

[0126] Figure 8 is a block diagram of information storage in a memory array operating in a half-page mode (eg, 8x2p3 high reliability mode) with block parity according to some embodiments of the present disclosure. Figure 8 Memory array 800 of FIG. 8 shows an example in which data, its associated parity, and additional information may be stored in a memory array. In some embodiments, memory array 800 may be a memory array in which word line portions are individually addressable (e.g., Figure 2 The memory array 218 and / or Figure 3 part 302).

[0127] Figure 8 and Figure 5 Generally similar, except that Figure 8 Shows a half-page mode in which additional information is enabled (e.g., by Figure 1 The module setting register 114 and / or for example Figure 2 Specifically, Figure 8 An embodiment is shown in which the module parity is distributed among the data storage devices (e.g., 8x2p3 mode). For the sake of brevity, Figure 5 Some of the details described will no longer be relevant Figure 8 repeat.

[0128] Figure 8 The diagram shows a circuit having two parts 802a and 802b (e.g., Figure 3 302a and 302b), each of the two portions includes a first set of row drivers 804a or a second set of row drivers 804b (eg, Figure 2 219a or 219b and / or Figure 3 Each of the two portions 802a and 802b includes a plurality of corresponding row planes (e.g., Figure 4 410) and additional row planes (e.g., Figure 4 412).

[0129] Figure 8 The description is made with respect to an example embodiment in which each access operation reads or writes 64 data bits from or to the memory array 800 along with 16 block parity bits and the memory array includes an ECC circuit 810 that uses 8 parity bits for on-die error correction. Other embodiments may use other numbers of data, block parity, and / or parity bits per access operation. The use of 16 block parity bits may represent an example implementation of an 8x high reliability mode.

[0130] During an instance write operation, the controller (for example, Figure 1 The controller also provides 64 data bits along the third DQ terminal from the controller ECC circuit (e.g., Figure 1The three DQ terminals may be part of the same pseudo channel. The module parity may be received as part of a 32-bit burst length, where 16 bits are module parity and 16 bits are garbage bits (e.g., bits that are not latched or discarded by the I / O circuitry). The module parity may represent a portion of the total number of module parity bits generated by the controller's ECC circuitry. The controller ECC circuitry may generate a set of module parity associated with all data bits divided across the module, and then divide the data and module parity into portions, where each portion is stored in one of the data devices (e.g., Figure 1 In this example, the data is divided into 8 parts of 64 bits each and the module parity is also divided into 8 parts of 16 bits each.

[0131] During a write operation, either the first portion 802a or the second portion 802a is selected to store data. For example, the portion may be selected based on the row driver selection bit RAx. In this example, RAx has a value of 0, and the first portion 802a is selected to store data. Since an extra bit is stored, both the first portion 802a and the second portion 802b are activated by their corresponding row drivers 804a and 804b. Which row driver and word line is activated in the two portions is determined by the remainder of the row address. The ECC circuit 810 generates a set of parity bits based on the data bits and the module parity bits. In this example, 8 parity bits are generated based on 80 received bits (64 data bits and 16 module parity bits). Data is written to the selected portion 802a and parity is written to the extra column plane 806a in the selected portion. The module parity bits are written to one or more column planes in the unselected portion 802b. Since there are 16 block parity bits, the block parity can be written to both column planes. In some embodiments, a first column select signal is provided to the selected portion 802a, and a second column select signal is provided to the unselected portion 802b.

[0132] The example read operation may be substantially similar to the example write operation. The first or second portion is selected based on the row driver select bit, but both portions are activated. Data is read from the selected portion 802a and parity is read from the additional column plane 806a in the selected portion. Module parity bits are read from the unselected portion 802b. The ECC circuit 810 receives the data, module parity, and parity bits, and then detects and corrects the data and module parity based on the parity bits. The corrected data and module parity are then provided to the DQ terminals by the I / O circuit (not shown). The data is provided as two bursts of 32 bits each along two DQ terminals, and the module parity bits are provided along the third DQ terminal. The module parity can be provided in a 32-bit burst length to match the burst length with the data, wherein 16 module parity bits are provided together with 16 garbage bits.

[0133] Fig. 9 900 is a block diagram of how data and module parity are transmitted along DQ terminals according to some embodiments of the present disclosure. Figure 1 A set of memory devices 902 (e.g., Figure 1 A set of DQ terminals on 104). Fig. 9 represents an example embodiment in which there are 8 memory devices and each memory device includes 8 DQ terminals and the devices operate in 2p3 mode (in which additional information is enabled). Specifically, Fig. 9 An 8x2p3 high reliability mode may be represented, where each device sends / receives 64 data bits and 16 block parity bits per access operation.

[0134] Each memory device 902 shows two example pseudo channels labeled PC0 and PC1. Each pseudo channel includes four physical DQ terminals, but since this is a 2p3 mode, two physical DQ terminals are used for data. One of the additional two DQ terminals is used for additional information, which in this example is module parity. The columns represent physical DQ terminals, and the filled boxes represent the burst length of information transmitted along the DQ terminals. The shading represents the type of information, data, or additional information. Diagram 900 shows data and additional information along the two pseudo channels of each device PC0 and PC1, however each pseudo channel can operate independently of each other.

[0135] In an example access operation, data and additional information are transmitted along the DQ terminals of the pseudo channel. Data is transmitted along the first DQ terminal and the second DQ terminal with a burst length of 32 bits each, for a total of 64 data bits. Additional information is transmitted along the third DQ terminal of the pseudo channel, in which case the additional information is module parity. In this example embodiment, 16 module parity bits are transmitted along the third DQ terminal. In order to match the length of the burst length along the first two DQ terminals, additional garbage bits (e.g., 16 module parity bits and 16 garbage bits) may be provided.

[0136] During a given access operation, data and block parity may be written to or read from one of the pseudo channels across eight data storage devices. During a write operation, the controller's ECC circuitry (e.g., Figure 1 The ECC circuit 152 of the embodiment of the present invention generates 128 block parity bits based on the 512 data bits. The number of bits generated may be based on the setting of the module (for example, in Figure 1 module setting register 114), device setting (e.g., in Figure 2 The data and module parity are divided into portions of 64 data bits and 16 module parity bits, and each portion is written to one of the data memory devices. Similarly, during a read operation, portions of data and module parity are read from the 8 data devices and provided to the ECC circuit on the controller, which performs error correction based on the data and module parity.

[0137] Block-level error correction circuits (e.g. Figure 1 152) can receive data and block parity from memory device 902. In this example embodiment (8x2p3 high reliability mode), the controller receives 512 data bits (e.g., 64 bits for each of the 8 devices) and 128 block parity bits (e.g., 16 bits for each of the 8 devices). The block error correction circuitry can be capable of repairing up to an entire device's worth of data based on the block parity (e.g., chip hunting). For example, data for an entire device 902 can be repaired.

[0138] Fig.10 1000 is a flowchart of a method for writing data and module parity to a memory device according to some embodiments of the present disclosure. The method 1000 may be performed by one or more of the apparatuses and systems described herein. For example, the method 1000 may be performed by, for example Figure 1 104, Figure 2 200 Figure 3 300 and / or Figure 4 In some embodiments, the memory device of 400 is used to execute. Figure 8 and9 Similar to the operations described, method 1000 may represent a method of performing access operations in 2p2 mode with block parity enabled as additional information.

[0139] Method 1000 generally begins at block 1010, which describes receiving a plurality of data bits along a first set of data terminals and receiving a plurality of block parity bits along at least one additional data terminal as part of a write operation. Method 1000 may also include receiving row and column addresses and a write command along a command address bus. Method 1000 may include utilizing a controller (e.g., Figure 1 150) on the ECC circuit (for example, Figure 1 152) generates a set of module parity bits based on a set of data bits and divides the set of module parity bits and the set of data bits into a plurality of parts. A plurality of data bits may be one of the parts of the set of data bits and a plurality of module parity bits may be one of the parts of the set of module parity bits.

[0140] In an example embodiment, the first set of data terminals may include two data terminals (e.g., DQ0 and DQ1). Each data terminal may receive a portion of a plurality of data bits at a burst length. For example, the method may include receiving 32 data bits along a first data terminal and receiving 32 data bits along a second terminal and receiving 16 module parity bits along a third DQ terminal (e.g., DQ2).

[0141] Block 1010 may be followed by block 1020, which describes selecting a first portion or a second portion of memory cells along a word line. In some embodiments, method 1000 may include selecting a first portion or a second portion of a word line. The first or second portion may be selected based on a row driver select bit of a row address. For example, method 1000 may be performed in a memory device having individually addressable row drivers (e.g., Figure 2 200 and / or Figure 3 In some embodiments, method 1000 may use other methods of selecting the first or second portion, such as selecting the first group of column planes or the second group of column planes based on column plane selection bits of a column address.

[0142] Block 1020 is followed by blocks 1030 and 1040. Block 1030 describes writing a plurality of data bits to selected ones of the first portion or the second portion of memory cells. Block 1040 describes writing a plurality of block parity bits to unselected ones of the first portion or the second portion of memory cells. For example, if data is written to memory cells in the first portion (e.g., because the row driver select bit is in a first state), then block parity is written to memory cells in the second portion and vice versa. Method 1000 may include writing data from a column decoder (e.g., Figure 2A first column select signal of 210 is provided to a column plane (eg, Figure 4 410) and write data along the bit line selected by the first column select signal, and provide a second column select signal from the column decoder to one or more column planes including the second portion of the memory cell. In some embodiments, the first portion of the memory cell may be organized into a first plurality of column planes and the second portion of the memory cell may be organized into a second plurality of column planes. Method 1000 may include writing data to the first plurality of column planes and selecting one or more column planes to which a plurality of module parity bits are written from the second plurality of column planes. The first column select signal may be based on a column address, and the second column select signal may be related to the first column select signal based on an internal mapping according to the first column select signal. The first and second column select signals may have different values ​​from each other. Similarly, which of the second plurality of column planes is selected may also be determined based on an internal mapping. For example, the first plurality and the second plurality of column planes may each include 8 column planes. 64 data bits may be written to each of the 8 column planes in the first plurality of column planes. 16 module parity bits may be written to two of the 8 column planes in the second plurality of column planes.

[0143] In some embodiments, method 1000 may include utilizing an ECC circuit (e.g., Figure 2 220 Figure 3 312 / 313, Figure 4 432 and / or Figure 8 810) generates a set of parity bits based on a plurality of data bits and a plurality of block parity bits. The method 100 may include writing the set of parity bits to an additional column plane (e.g., Figure 4 412 and / or Figure 8 806a / 806b of FIG. 1000). The method 1000 may include generating a third column select signal and writing parity to the bit lines of the additional column plane. The third column select signal may have the same or different value as the first and second column select signals.

[0144] An example read operation may be substantially similar to method 1000, except that the read operation includes reading a plurality of data bits from a selected one of the first or second portions and reading a plurality of block parity bits from an unselected one of the first or second portions, and providing the data bits along a first set of data terminals and providing the block parity bits along at least one additional data terminal. As part of the read operation, method 1000 may include reading parity bits from an additional column plane and correcting or detecting errors in the data and block parity based on the parity.

[0145] In some embodiments, method 1000 may include both module parity and metadata. For example, block 1010 may include receiving a plurality of module parity bits and a plurality of metadata bits along at least one additional data terminal as part of a write operation. Block 1040 may include writing the plurality of module parity bits and metadata bits to an unselected one of the first or second portion of memory cells.

[0146] In some embodiments, method 1000 may include selecting a certain amount of block parity bits. For example, a user of a device may change a setup register of a module, a device, or a combination thereof to select a first mode having a first amount of block parity (e.g., 8x2p3 high reliability mode) or a second mode having a second amount of block parity (e.g., 8x2p3 high capacity mode). As part of a write operation, the method may include selecting a certain amount of block parity bits in a block level error correction circuit (e.g., Figure 1 The method 1000 may include receiving a plurality of data bits at 152 of the present invention and generating a first or second amount of block parity. As part of the read operation, the method 1000 may include reading the first or second amount of block parity and the amount of data to a block level correction circuit and performing a first level or a second level of error correction. For example, the first level may be chip hunting (e.g., correcting data for the entire device) while the second level may be less than chip hunting (e.g., correcting a portion of the data from the device). Fig.15 An example method of selecting module-level error correction is discussed in more detail.

[0147] Fig.11 is a block diagram of information storage in a memory array operating in a half-page mode with additional information (eg, 8x2p3 high reliability mode with metadata enabled) according to some embodiments of the present disclosure. Fig.11 Memory array 1100 of FIG. 1 shows an example of how data, its associated parity, and additional information may be stored in a memory array, such as as part of an 8x2p3 pattern. In some embodiments, memory array 1100 may be a memory array in which word line portions are individually addressable (e.g., Figure 2 The memory array 218 and / or Figure 3 part 302).

[0148] Specifically, Fig.11 An example embodiment is shown in which the additional information includes both module parity bits and metadata. Fig.11 Can be used with Figure 5 and Figure 8 Generally similar, except that Fig.11 Shows an example mode of operation where extra information is enabled and also includes metadata. Figure 5 and / or Figure 8 The details described will no longer be relevant Fig.11Repeat. In some embodiments, Fig.11 The operation can be performed by Figure 5 and / or Figure 8 The operations are performed by the same hardware, but with different amounts of extra information enabled.

[0149] Fig.11 Described with respect to example embodiments, where each access operation reads or writes 64 data bits along with 16 block parity bits and 4 metadata bits from or to the memory array 1100 and reads 8 parity bits from the ECC circuit 1110 for on-die error correction. Other embodiments may use other numbers of data, block parity, metadata, and / or parity. Fig.11 The discussion is generally about 8x2p3 high reliability mode and a corresponding amount of block parity (eg, 16 bits stored per access operation). However, metadata may also be enabled in 8x2p3 high capacity mode (eg, 8 bits of block parity per access operation).

[0150] In an instance write operation, the controller (for example, Figure 1 The controller also provides 64 data bits as two 32-bit burst lengths along two DQ terminals. The controller also provides ECC circuits from the controller (e.g., Figure 1 The 16 block parity bits of 152) of the 152) and 4 metadata bits are provided along the third DQ terminal. The three DQ terminals can be part of the same pseudo channel. The block parity and metadata can be received as part of a 32-bit burst, of which 20 bits are block parity and metadata and 12 bits are garbage bits. As in the previous example, the data, block parity, and metadata can each represent a burst generated by the controller and separated and stored in separate memory devices (e.g., Figure 1 104), a whole set of data, a set of module parity, and a set of metadata.

[0151] During a write operation, either the first portion 1102a or the second portion 1102b is selected. For example, the portion may be selected based on the row driver select bit RAx. Fig.11 In the example shown in FIG. 1 , RAx has a value of 0, and therefore the first portion 1102a is selected. Because the extra bits are stored, the two portions 1102a and 1102b of the word line are activated by their respective row drivers 1104a and 1104b. The ECC circuit 1110 generates a set of 8 parity bits based on the 84 bits (64 data bits, 16 module parity bits, and 4 metadata bits) from the controller. The 64 data bits are written to the data column plane (e.g., Figure 4410), and 8 parity bits are written to an additional column plane 1106a along the selected portion 1102a. 16 module parity bits and 4 metadata bits are written to one or more column planes of the unselected portion 1102b. For example, module parity may be written to 2 column planes and metadata may be written to a single column plane. In some embodiments, a first column select signal is provided to the selected portion 1102a, and a second column select signal is provided to the unselected portion 1102b.

[0152] The example read operation is substantially similar to the example write operation. 88 bits (64 data bits, 16 module parity bits, 4 metadata bits, and 8 parity bits) are read out to the ECC circuit 1110, which detects / corrects errors in the 80 data bits, module parity bits, and metadata bits. The corrected 80 bits are provided to the I / O circuit, which provides these bits along the DQ terminals. The 64 data bits are provided as two 32-bit bursts along the first and second DQ terminals. 16 module parity bits and 4 metadata bits are provided along the third DQ terminal.

[0153] Fig.12 1200 is a block diagram of how data, module parity, and metadata are transmitted along DQ terminals according to some embodiments of the present disclosure. Figure 1 A set of memory devices 1202 (e.g., Figure 1 A set of DQ terminals on 104). Fig.12 An example embodiment is represented in which there are 8 memory devices, each of which includes 8 DQ terminals organized into two pseudo channels, where two DQ terminals are used for data and one or more of the other two DQ terminals can be used for additional information (e.g., 8x2p3 mode) within a pseudo channel.

[0154] Figure 1200 can be used with Fig. 9 900 is substantially similar to FIG. Fig.12 In , metadata and module parity are also enabled, so the amount of additional information increases. For the sake of brevity, Fig. 9 The features and operations described will no longer be relevant to Fig.12 repeat. Fig.12 The description is about module parity based on 8x2p3 high reliability mode with metadata enabled, however metadata can also be enabled for 8x2p3 high capacity mode.

[0155] In the operation represented by diagram 1200, each pseudo channel transmits a total of 64 data bits divided into two burst lengths along the first and second DQ terminals and 20 additional information bits (16 block parity bits and 4 metadata bits) along the third DQ terminal. In some embodiments, to match the amount along the first two DQ terminals, an additional 12 garbage bits may be transmitted along the third DQ terminal. More or fewer metadata bits may be used in other example embodiments.

[0156] Fig.13 1300 is a flow chart of a method for providing additional information along an additional data terminal when additional information is enabled according to some embodiments of the present disclosure. In some embodiments, method 1300 may be performed by one or more of the devices and / or systems described herein. For example, method 1300 may be performed by, for example, Figure 1 104, Figure 2 200 Figure 3 300 Figure 4 400 and / or Fig.11 The memory device of 1100 is executed.

[0157] Method 1300 describes two modes of operation of a memory device. The first mode is a mode in which the additional information is not enabled (e.g., 8x2p2 mode). The second mode is a mode in which the additional information is enabled (e.g., 8x2p3 mode). Which mode the device is in can be a device-level setting register (e.g., Figure 2 mode register 230) and / or module level setting registers (e.g., Figure 1 For comparison, method 1300 describes example read operations with respect to the two modes.

[0158] Method 1300 as a whole may begin at block 1310, which describes receiving a row address as part of a read operation. The row address is received along a command / address terminal. Block 1310 may also include receiving a column address and a read command. The steps of block 1310 may generally be the same in the first mode and the second mode.

[0159] Block 1310 is followed by block 1320, which describes determining whether the device is in the first mode or the second mode. Method 1300 may include checking the state of one or more registers, such as a mode register of the device. If the device is in the first mode, method 1300 includes blocks 1310, 1330, and 1340. If the device is in the second mode, method 1300 includes blocks 1310, 1350, and 1360.

[0160] If the device is in the first mode, block 1310 may be followed by block 1330, which describes reading a plurality of data bits from the memory array. The method 1300 may include selecting a first portion or a second portion of the plurality of memory cells. For example, the method 1300 may involve selecting a first portion or a second portion of a word line based on a row driver select bit of a row address (e.g., similar to Figure 6 The method 1300 may include reading a plurality of data bits from a selected one of the first portion or the second portion.

[0161] Block 1330 may generally be followed by block 1340, which depicts providing data bits in a first burst length along a first set of data terminals.For example, method 1300 may include providing 64 data bits in a burst length of 32 bits along two DQ terminals.

[0162] If the device is in the second mode, block 1310 may generally be followed by block 1350, which describes reading a plurality of data bits and a plurality of additional information bits from the memory array. Figures 11 to 12 Similar to the embodiment of , the additional information may include block parity and metadata. In some embodiments, the number of data bits read in the second mode may be the same as the number of bits read in the first mode.

[0163] In some embodiments, block 1350 may include selecting a first portion or a second portion of memory cells along the word line (e.g., similar to the selection described with respect to block 1330 of the first mode). Block 1350 may include reading a plurality of data bits from selected ones of the first or second portions and reading additional information from unselected ones of the first or second portions.

[0164] Block 1350 may generally be followed by block 1360, which describes providing data bits at a first burst length along a first set of data terminals and providing additional information along at least one additional data terminal. The first burst length used in the second mode may match the first burst length used in the first mode. In other words, method 1300 may include maintaining the same burst length of data and changing the number of DQ terminals along which information (e.g., data and additional information) is provided. For example, method 1300 may include providing data at a burst length of 32 bits along two data terminals and providing additional information along a third DQ terminal. The amount of additional information provided may be based on the settings of the device and / or module. For example, in an 8x2p3 high reliability mode with metadata enabled, method 1300 may include providing 20 additional information bits, 16 module parity bits, and 4 metadata bits. In an 8x2p3 high capacity mode with metadata enabled, method 1300 may include providing 12 additional information bits, 8 module parity bits, and 4 metadata bits. More or fewer block parity bits and / or metadata may be used in other examples.

[0165] In some embodiments, method 1300 may include reading parity bits from the memory array and using the parity bits to detect / correct errors in the read data or the data and additional information. For example, method 1300 may include reading parity from an additional column plane (which may be associated with a selected one of the first portion or the second portion of memory cells) in either the first or second mode.

[0166] The write operation may be performed in a manner generally similar to method 1300. For example, the write operation may include receiving a row address together with a write command, data, and if the device is in the second mode, receiving additional information. In the first mode, data may be received along a first set of data terminals with a first burst length. In the second mode, data bits are received along the first set of data terminals with a first burst length and additional information is received along at least one additional data terminal. For example, in the first or second mode, 64 data bits are received along DQ0 and DQ1 with a 32-bit burst length, and in the second mode, additional information is received along DQ2. In some embodiments, the data (and additional information) may be provided to an ECC circuit that generates parity based on the data (and additional information). The data, additional information (in the second mode), and parity (in some embodiments) are then written to the memory array. The data (and parity) may be written to a selected portion of the memory array (e.g., selected by a row driver select bit) in the first or second mode. In the second mode, additional information may be written to an unselected portion.

[0167] Fig.14 1400 is a block diagram of how data and module parity are transmitted along DQ terminals according to some embodiments of the present disclosure. Figure 1 A set of memory devices 1402 (e.g., Figure 1 A set of DQ terminals on 104). Fig.14 represents an example embodiment in which there are 8 memory devices and each memory device includes 8 DQ terminals and the devices operate in 2p3 mode with additional information enabled. Specifically, Fig.13 An 8x2p3 high capacity mode may be represented where each device sends / receives 64 data bits and 8 block parity bits. Fig.14 Can be used with Fig. 9 Generally similar, except that Fig. 9 indicates 8x2p3 high reliability mode, while Fig.14 Indicates 8x2p3 high capacity mode. For the sake of brevity, Fig. 9 Certain details and operations described may not be relevant to Fig.14 repeat.

[0168] Each memory device 1402 shows two example pseudo channels labeled PC0 and PC1. Each pseudo channel includes four physical DQ terminals, but since this is a 2p3 mode, two physical DQ terminals are used for data. One of the additional two DQ terminals is used for additional information, which in this example is module parity. The columns represent physical DQ terminals, and the filled boxes represent the burst length of information transmitted along the DQ terminals. The shading represents the type of information, data or module parity. Figure 1400 shows data and additional information along the two pseudo channels of each device PC0 and PC1, however each pseudo channel can operate independently of each other.

[0169] In an example access operation, data and additional information are transmitted along the DQ terminals of the pseudo channel. Data is transmitted along the first DQ terminal and the second DQ terminal with a burst length of 32 bits each, for a total of 64 data bits. Additional information is transmitted along the third DQ terminal of the pseudo channel, in which case the additional information is module parity. In this example embodiment, 8 module parity bits are transmitted along the third DQ terminal. In order to match the length of the burst length along the first two DQ terminals, additional garbage bits (e.g., 8 module parity bits and 24 garbage bits) may be provided.

[0170] During a given access operation, data and block parity may be written to or read from one of the pseudo channels across eight data storage devices. During a write operation, the controller's ECC circuitry (e.g., Figure 1 The ECC circuit 152 of the embodiment of the present invention generates 64 block parity bits based on the 512 data bits. The number of bits generated may be based on the configuration of the module (e.g., Figure 1 module setting register 114), device setting (e.g., in Figure 2 The data and module parity are divided into portions of 64 data bits and 8 module parity bits, and each portion is written to one of the data memory devices. Similarly, during a read operation, portions of the data and module parity are read out of the 8 data devices and provided to the ECC circuit on the controller, which performs error correction based on the data and module parity.

[0171] Block-level error correction circuits (e.g. Figure 1152) may receive data and block parity from memory device 1402. In this example embodiment (8x2p3 high capacity mode), the controller receives 512 data bits (e.g., 64 bits for each of the 8 devices) and 64 block parity bits (e.g., 8 bits for each of the 8 devices). Block error correction circuitry may be able to repair a portion of the data from one of the devices 1402. For example, block error correction circuitry may be able to repair information along one of the two DQ terminals of each pseudo channel in a single device.

[0172] In some embodiments, Fig.14 The 8x2p3 high capacity mode can be represented by Figure 8 800. For example, 64 data bits may be stored in the selected portion 802a, while 8 block parity bits may be stored in the unselected portion 802b. Since fewer block parity bits are stored on each device, more devices are available for storing information, which is why an embodiment with 8 block parity bits may be referred to as a high capacity mode relative to an embodiment with 16 block parity bits.

[0173] In some embodiments, the memory module can be configured to operate in either 8x2p3 high reliability mode or 8x2p3 high capacity mode. For example, settings on the controller, module, and / or memory device can specify how many module parity bits are used. The user can select which mode to operate in by programming such settings. This is different from the case where the amount of module parity is determined by how many physical error correction devices are placed on the module (e.g., Figure 1 Metadata may also be enabled in high reliability or high capacity mode.

[0174] Fig.15 A method of switching between module parity modes according to some embodiments of the present disclosure. Fig.15 The method 1500 may be implemented by one or more of the devices or systems described herein. For example, the method 1500 may be implemented by, for example, Figure 1 For example, a portion of 100 memory systems Figure 1 In some embodiments, the memory module may include several devices, such as Figure 2 The device 200, Figure 3 300 and / or Figure 4 of 400.

[0175] Method 1500 begins at block 1510, which describes selecting a first mode or a second mode for a memory module. The selection may include writing to one or more setup registers of a module, a controller, a memory device of the module, or a combination thereof. For example, method 1500 may include writing to a mode register on a memory device of the module (e.g., Figure 2 230) and / or write to the module setting register (e.g., Figure 1 114). In some embodiments, method 1500 may include changing the operation of the memory system from a first mode to a second mode. The change may be made after the device is manufactured (eg, by a user of the memory system).

[0176] Block 1510 is followed by block 1520, which describes determining whether the system is in the first mode or the second mode. Which mode the system is in may be based on one or more settings, which may be set as part of the steps of block 1510. If the system is in the first mode, then the method proceeds to block 1530. If the system is in the second mode, then the method 1500 proceeds to block 1540.

[0177] Block 1530 describes storing respective portions of a plurality of data bits and respective portions of a first number of module parity bits on each memory device of the memory module in a first mode. Block 1540 describes storing respective portions of a plurality of data bits and respective portions of a second number of module parity bits on each memory device of the memory module in a second mode. The first number may be greater than the second number. For example, the first mode may be an 8x2p3 high reliability mode and the second mode may be an 8x2p3 high capacity mode. The number of data bits may be the same between the first mode and the second mode.

[0178] As part of an example write operation, the method may include utilizing a block level error correction circuit (eg, Figure 1 152), generating a first number of module parity bits based on the data bits in a first mode or generating a second number of module parity bits based on the data bits in a second mode. An example write operation may include dividing a plurality of data bits and module parity bits into a number of portions. The number of portions may match the number of memory devices on the module. For example, the data and module parity may be divided into 8 portions. The write operation may include providing a corresponding portion of the data bits and a corresponding portion of the module parity bits to each memory device. For example, the write operation may include providing a portion of the data bits along a first set of data terminals associated with the device and providing a portion of the module parity along at least one additional data terminal. In some embodiments, the write operation may include Fig.10 The method 1000 has steps.

[0179] As part of an example read operation, the method may include reading data and a corresponding portion of module parity from each of the devices of the module. For example, method 1500 may include Figure 7 The read operation may include a block-level error correction circuit (e.g., Figure 1 The data and block parity are received at 152 of the device. The read operation may include combining the data and the corresponding portions of the parity bits from each of the devices into a plurality of data bits and a plurality of block parity bits (e.g., a first or second number based on the mode). The read operation may include performing a first level of error correction in the first mode or performing a second level of error correction in the second mode. The first level of error correction may include correcting the data along a maximum of a first number of data terminals associated with the device, while the second level of error correction may include correcting the data along a maximum of a second number of data terminals associated with the device. For example, the first level may include correcting the data along a maximum of four DQ terminals, two DQ terminals of two pseudo channels of one device (e.g., chip hunting), while the second level may include correcting the data along a maximum of two DQ terminals, one of the DQ terminals of the two pseudo channels. The first level of error correction may include correcting a maximum of an entire portion of the data read from a single memory device in the memory devices, while the second level of error correction may include correcting less than an entire portion of the data read from a single memory device in the memory devices.

[0180] In some embodiments, method 1500 may include enabling metadata in a first or second mode. Method 1500 may include storing respective portions of a plurality of metadata bits on each of the memory devices in either the first or second mode. Method 1500 may include generating module parity bits based on the data and metadata as part of a write operation and correcting the data and metadata as part of a read operation.

[0181] In some embodiments, method 1500 may include addressing a first amount of space on a memory device for data storage in a first mode or addressing a second amount of space on a memory device for data storage in a second mode. Since the first mode may need to make room for a larger amount of module parity, in the first mode, the method may include reserving a first number of memory cells on each device for storing module parity, and in the second mode, the method may include reserving a second number of memory cells on each device for storing module parity. The first number of memory cells may be greater than the second number of memory cells. In other words, in the first mode, the data device may have a first amount of capacity for data storage, and in the second mode, the data device may have a second amount of capacity for data storage that is greater than the first amount.

[0182] Of course, it should be understood that any of the examples, embodiments, or processes described herein may be combined with one or more other examples, embodiments, and / or processes according to the present systems, devices, and methods, or separated and / or executed in a separate device or device portion.

[0183] Finally, the above discussion is intended only to illustrate the present system and should not be construed as limiting the appended claims to any particular embodiment or group of embodiments. Therefore, although the present system has been described in particular detail with reference to exemplary embodiments, it should also be understood that one of ordinary skill in the art may devise numerous modifications and alternative embodiments without departing from the broader and intended spirit and scope of the present system as set forth in the appended claims. Therefore, the specification and drawings should be viewed in an illustrative manner and are not intended to limit the scope of the appended claims.

Claims

1. A device comprising: The first set of data terminals; The second set of data terminals; A memory array comprising word lines coupled to a plurality of memory cells, wherein the plurality of memory cells are configured to store data in a first mode or to store data and additional information in a second mode, wherein during a read operation in the first mode, the data is provided along the first set of data terminals, and Wherein during a read operation in the second mode, the data is provided along one or more of the first set of data terminals and the additional information is provided along one or more of the second set of data terminals.

2. The apparatus of claim 1 , wherein the word line comprises a first portion coupled to a first portion of the plurality of memory cells and a second portion coupled to a second portion of the plurality of memory cells, and Wherein in the second mode the data is read from the first portion of the plurality of memory cells and the additional information is read from the second portion of the plurality of memory cells.

3. The apparatus of claim 2, further comprising selecting the first portion based on a row address.

4. The apparatus of claim 1, wherein during the first mode and the second mode, the data is provided in the same burst length along the first set of data terminals.

5. The apparatus of claim 1 , further comprising an error correction circuit configured to receive parity bits from the plurality of memory cells in the first mode or the second mode, and configured to correct the data based on the parity bits in the first mode and configured to correct the data and the additional information based on the parity bits in the second mode. The apparatus of claim 1 , wherein the first mode is a 2p2 mode and the second mode is a 2p3 mode.

7. The apparatus of claim 1, wherein the additional information comprises module parity, metadata, or a combination thereof.

8. A device comprising: a memory array comprising a plurality of memory cells along word lines; a mode register configured to set the device to a first mode or a second mode; Multiple data terminals; and an input / output circuit configured to receive a plurality of data bits from the plurality of memory cells as part of a read operation in the first mode and to provide the plurality of data bits in a first burst length along one or more of the data terminals, and configured to receive a plurality of data bits and a plurality of additional information bits from the plurality of memory cells as part of a read operation in the second mode and to provide the plurality of data bits at the first burst length along some of the plurality of data terminals and to provide the plurality of additional information bits along others of the plurality of data terminals.

9. The apparatus of claim 8, wherein the word line comprises a first portion coupled to a first portion of the plurality of memory cells and a second portion coupled to a second portion of the plurality of memory cells.

10. The apparatus of claim 9, further comprising a row decoder configured to select the first portion or the second portion based on a row driver select bit of a row address, wherein the data is read from the selected one of the first portion or the second portion in the first or second mode, and the plurality of additional information bits are read from an unselected one of the first portion or the second portion in the second mode.

11. The apparatus of claim 8, further comprising error correction circuitry configured to detect errors in the plurality of data bits in the first mode or to detect errors in the plurality of data bits and the plurality of additional information bits in the second mode.

12. The apparatus of claim 8, wherein the plurality of additional information bits comprises block parity, metadata, or a combination thereof.

13. The apparatus of claim 8, wherein the input / output circuit is configured to provide the plurality of data bits along first and second data terminals and is configured to provide the plurality of additional information bits along a third data terminal.

14. The apparatus of claim 13, wherein the first mode is a 2p2 mode and the second mode is a 2p3 mode.

15. A method comprising: receiving a row address as part of a read operation; reading a plurality of data bits from a memory array as part of a first pattern; providing the data bits in a first burst length along a first set of data terminals as part of the first pattern; reading a plurality of data bits from the memory array as part of a second mode; and The data bits are provided at the first burst length along the first set of data terminals and additional information is provided along at least one additional data terminal as part of the second pattern.

16. The method according to claim 15, further comprising: selecting a first portion or a second portion of a word line; reading the plurality of data bits from the selected one of the first portion or the second portion in the first mode and the second mode; and The additional information is read from unselected one of the first portion or the second portion in the second mode.

17. The method according to claim 15, further comprising: changing the number of data terminals used between the first mode and the second mode; and The first burst length is kept the same between the first mode and the second mode.

18. The method of claim 15, further comprising: providing the data bits at the first burst length along first and second data terminals in both the first and second modes; and The additional information is provided along a third data terminal in the second mode.

19. The method of claim 15, further comprising: reading a plurality of parity bits from the memory array as part of the first pattern or the second pattern; correcting errors in the data based on the parity bits in the first mode; and Errors in the data and the additional information are corrected in the second mode.

20. The method of claim 15, wherein the additional information comprises module parity, metadata, or a combination thereof.

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