Read-only memory array with high speed and high write times

Abstract

The invention provides a high-speed read-only memory array with high write-in times, which belongs to the field of memory arrays and comprises a plurality of word lines, a plurality of selection lines, a plurality of bit lines and a plurality of sub-memory arrays. The word lines comprise a first word line, the selection lines comprise a first selection line and a second selection line, and the bit lines comprise a first bit line, a second bit line, a third bit line and a fourth bit line. Each sub-memory array comprises a first memory unit cell, a second memory unit cell, a third memory unit cell and a fourth memory unit cell. The first memory unit cell is coupled to the first word line, the first bit line and the first selection line, the second memory unit cell is coupled to the first word line, the second bit line and the first selection line, the third memory unit cell is coupled to the first word line, the third bit line and the second selection line, and the fourth memory unit cell is coupled to the first word line, the fourth bit line and the second selection line. According to the invention, the purposes of high-speed writing and high writing times can be achieved by using lower voltage.

Description

Technical Field

[0001] The invention belongs to the field of memory arrays, and in particular relates to a high-speed and high-write-time read-only memory array. Background Art

[0002] Complementary Metal Oxide Semiconductor (CMOS) process technology has become a common manufacturing method for application specific integrated circuits (ASIC). In today's advanced computer information products, Electrically Erasable Programmable Read Only Memory (EEPROM) is widely used in electronic products because it has the function of electrically writing and erasing data in a non-volatile memory, and the data will not disappear after the power is turned off.

[0003] Non-volatile memory is programmable. It is used to store charge to change the gate voltage of the memory's transistor, or not store charge to leave the gate voltage of the original memory's transistor. The erase operation removes all the charge stored in the non-volatile memory, so that all non-volatile memories return to the gate voltage of the original memory's transistor. When the non-volatile memory is burned, its internal switch elements will be disconnected or turned on. In order to program the non-volatile memory array, a certain voltage and current need to be applied so that the corresponding switch elements can be turned on or off. The reading, writing and erasing operations of non-volatile memory are all operated from the drain. When writing and erasing, the drain will operate with high voltage, which makes it easy for electrons to enter the gate, causing the critical voltage to change and reducing the number of writes. In addition, the voltage applied by the Fowler-Neumann effect is large and the speed is slow. Generally, the writing and erasing time is greater than 1 millisecond (ms).

[0004] Therefore, the present invention aims at the above-mentioned problems and proposes a high-speed and high-write-endurance read-only memory array to solve the problems arising from the prior art. Summary of the invention

[0005] The invention provides a high-speed and high-write-time read-only memory array, which can use a lower voltage to achieve the purpose of high-speed writing and high writing times.

[0006] In one embodiment of the present invention, a high-speed high-write-time read-only memory array is provided, which includes a plurality of parallel word lines, a plurality of parallel selection lines, a plurality of parallel bit lines, and a plurality of sub-memory arrays. The word line includes a first word line, the selection line and the word line are perpendicular to each other, wherein the selection line includes a first selection line and a second selection line. The bit line and the selection line are parallel to each other, and the bit line includes a first bit line, a second bit line, a third bit line, and a fourth bit line. The first selection line is located between the first bit line and the second bit line, and the second selection line is located between the third bit line and the fourth bit line. Each sub-memory array is coupled to a word line, two selection lines, and four bit lines, wherein each sub-memory array includes a first memory cell, a second memory cell, a third memory cell, and a fourth memory cell. The first memory cell is coupled to the first word line, the first bit line and the first selection line, the second memory cell is coupled to the first word line, the second bit line and the first selection line, the third memory cell is coupled to the first word line, the third bit line and the second selection line, and the fourth memory cell is coupled to the first word line, the fourth bit line and the second selection line.

[0007] Based on the above, the high-speed high-write-endurance read-only memory array reads the current of the memory cell from the source to identify the current storage state, rather than reading the current from the drain that undergoes high-voltage operation, to reduce the impact of electrons entering the gate to change the threshold voltage. Compared to Fowler-Nordheim tunneling, the high-speed high-write-endurance read-only memory array can use a lower voltage to achieve the purpose of high-speed writing and high write endurance. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative labor.

[0009] Figure 1 FIG. 1 is a schematic diagram of a circuit layout of a high-speed and high-write-endurance read-only memory array according to an embodiment of the present invention.

[0010] Figure 2 FIG. 4 is a schematic diagram of a circuit layout of a sub-memory array according to an embodiment of the present invention.

[0011] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a high-speed and high-write-endurance read-only memory array according to an embodiment of the present invention.

[0012] Figure 4 FIG. 4 is a structural cross-sectional view of an embodiment of a first memory cell of the present invention.

[0013] Figure 5 FIG. 4 is a structural cross-sectional view of an embodiment of a second memory cell of the present invention.

[0014] Figure 6 FIG. 4 is a structural cross-sectional view of an embodiment of a third memory cell of the present invention.

[0015] Figure 7 FIG. 4 is a structural cross-sectional view of an embodiment of a fourth memory cell of the present invention.

[0016] Figure 8 FIG. 1 is a schematic diagram of an equivalent circuit of another embodiment of a high-speed and high-write-endurance read-only memory array of the present invention.

[0017] Fig. 9 FIG. 4 is a structural cross-sectional view of another embodiment of the first memory cell of the present invention.

[0018] Fig.10 FIG. 4 is a structural cross-sectional view of another embodiment of the second memory cell of the present invention.

[0019] Fig.11 FIG. 4 is a structural cross-sectional view of another embodiment of the third memory cell of the present invention.

[0020] Fig.12 FIG. 4 is a structural cross-sectional view of another embodiment of the fourth memory cell of the present invention.

[0021] Explanation of symbols:

[0022] 1: high-speed high-write-endurance read-only memory array; 10: sub-memory array;

[0023] 100: first memory cell; 1000: first gate dielectric block; 1001: first conductive gate; 1002: first heavily doped region; 1003: first well region; 1004: first dielectric block; 1005: first electrode block; 1006: heavily doped region;

[0024] 101: second memory cell; 1010: second gate dielectric block; 1011: second conductive gate; 1012: second heavily doped region; 1013: second well region; 1014: second dielectric block; 1015: second electrode block; 1016: heavily doped region;

[0025] 102: third memory cell; 1020: third gate dielectric block; 1021: third conductive gate; 1022: third heavily doped region; 1023: third well region; 1024: third dielectric block; 1025: third electrode block; 1026: heavily doped region;

[0026] 103: fourth memory cell; 1030: fourth gate dielectric block; 1031: fourth conductive gate; 1032: fourth heavily doped region; 1033: fourth well region; 1034: fourth dielectric block; 1035: fourth electrode block; 1036: heavily doped region;

[0027] 104: semiconductor region; 2: semiconductor substrate;

[0028] WL: word line; WL1: first word line; SL: select line; SL1: first select line; SL2: second select line; BL: bit line; BL1: first bit line; BL2: second bit line; BL3: third bit line; BL4: fourth bit line;

[0029] T1: first field effect transistor; T2: second field effect transistor; T3: third field effect transistor; T4: fourth field effect transistor; C1: first capacitor structure; C2: second capacitor structure; C3: third capacitor structure; C4: fourth capacitor structure;

[0030] O1: first insulating structure; O2: second insulating structure; O3: third insulating structure; O4: fourth insulating structure;

[0031] L: dielectric layer; E: electrode layer; W: common well area;

[0032] BK1: first conductive block; BK2: second conductive block; BK3: third conductive block; BK4: fourth conductive block; BK5: fifth conductive block; BK6: sixth conductive block;

[0033] H: conductive through hole; H1: first conductive through hole; H2: second conductive through hole; H3: third conductive through hole; H4: fourth conductive through hole; H5: fifth conductive through hole; H6: sixth conductive through hole; H7: seventh conductive through hole; H8: eighth conductive through hole; H9: ninth conductive through hole; H10: tenth conductive through hole; H11: eleventh conductive through hole; H12: twelfth conductive through hole. DETAILED DESCRIPTION

[0034] In the following description, a read-only memory array is provided, which reads the current of the memory cell from the source to identify the current storage state, rather than reading the current from the drain which is subjected to high voltage operation, so as to reduce the effect caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the read-only memory array can use a lower voltage to achieve high-speed writing and high writing times.

[0035] Figure 1 FIG. 1 is a schematic diagram of a circuit layout of an embodiment of a high-speed and high-write-endurance read-only memory array of the present invention. Figure 2 FIG. 1 is a schematic diagram of a circuit layout of an embodiment of a sub-memory array of the present invention. Figure 1 and Figure 2 , the high-speed high-write-time read-only memory array 1 of the present invention is introduced below. The high-speed high-write-time read-only memory array 1 includes a plurality of parallel word lines WL, a plurality of parallel selection lines SL, a plurality of parallel bit lines BL and a plurality of sub-memory arrays 10. All word lines WL include a first word line WL1, all selection lines SL are perpendicular to all word lines WL, and all selection lines SL include a first selection line SL1 and a second selection line SL2. All bit lines BL are parallel to all selection lines SL, and all bit lines BL include a first bit line BL1, a second bit line BL2, a third bit line BL3 and a fourth bit line BL4, the first selection line SL1 is located between the first bit line BL1 and the second bit line BL2, and the second selection line SL2 is located between the third bit line BL3 and the fourth bit line BL4. Each sub-memory array 10 is coupled to a word line WL, two selection lines SL and four bit lines BL. Each sub-memory array 10 includes a first memory cell 100, a second memory cell 101, a third memory cell 102, and a fourth memory cell 103. The first memory cell 100 is coupled to the first word line WL1, the first bit line BL1, and the first selection line SL1, the second memory cell 101 is coupled to the first word line WL1, the second bit line BL2, and the first selection line SL1, the third memory cell 102 is coupled to the first word line WL1, the third bit line BL3, and the second selection line SL2, and the fourth memory cell 103 is coupled to the first word line WL1, the fourth bit line BL4, and the second selection line SL2. In some embodiments of the present invention, the first memory cell 100 and the second memory cell 101 are symmetrically arranged, the first memory cell 100 and the third memory cell 102 are symmetrically arranged, the fourth memory cell 103 and the second memory cell 101 are symmetrically arranged, and the fourth memory cell 103 and the third memory cell 102 are symmetrically arranged.

[0036] Figure 3 FIG. 1 is a schematic diagram of an equivalent circuit of a high-speed and high-write-endurance read-only memory array according to an embodiment of the present invention. Figure 4 FIG. 1 is a cross-sectional view of a first memory cell according to an embodiment of the present invention. Figure 2 , Figure 3 and Figure 4, the first memory cell 100, the second memory cell 101, the third memory cell 102 and the fourth memory cell 103 are arranged in a semiconductor region 104 having a first conductivity type. The semiconductor region 104 is taken as a semiconductor substrate. The first memory cell 100 may include a first field effect transistor T1 and a first capacitor structure C1. The first field effect transistor T1, the first capacitor structure C1 and a first insulating structure O1 are arranged in the semiconductor region 104, and the first insulating structure O1 is located between the first field effect transistor T1 and the first capacitor structure C1 to isolate the first field effect transistor T1 from the first capacitor structure C1. The first field effect transistor T1 includes a first gate dielectric block 1000, a first conductive gate 1001 and two first heavily doped regions 1002. The first gate dielectric block 1000 is a part of the dielectric layer L, the first conductive gate 1001 is a part of the electrode layer E, and the first heavily doped region 1002 has a second conductivity type opposite to the first conductivity type. In this embodiment, the first conductivity type is P type, and the second conductivity type is N type. The first gate dielectric block 1000 is disposed on the semiconductor region 104, and the first conductive gate 1001 is disposed on the first gate dielectric block 1000. The first heavily doped region 1002 is disposed in the semiconductor region 104, and is respectively located on different sides of the semiconductor region 104 directly below the first conductive gate 1001, and is respectively coupled to the first bit line BL1 and the first selection line SL1. The first heavily doped region 1002 coupled to the first bit line BL1 serves as a drain, and the first heavily doped region 1002 coupled to the first selection line SL1 serves as a source. The first capacitor structure C1 includes a first well region 1003, a first dielectric block 1004, and a first electrode block 1005. The first well region 1003 is a part of the common well region W, the first dielectric block 1004 is a part of the dielectric layer L, and the first electrode block 1005 is a part of the electrode layer E. The common well region W and the first well region 1003 are both of the second conductivity type. The first well region 1003 is disposed in the semiconductor region 104 and is coupled to the first word line WL1. The first dielectric block 1004 is disposed on the surface of the first well region 1003, and the first electrode block 1005 is stacked on the first dielectric block 1004 and is coupled to the first conductive gate 1001. In some embodiments, in order to form an ohmic contact, the first capacitor structure C1 may further include a heavily doped region 1006, which has the second conductivity type, is located in the first well region 1003, and is coupled to the first word line WL1. Figure 1 The word line WL, the first conductive block BK1 and the second conductive block BK2 are all part of the first conductive metal layer. Figure 1The bit line BL and the selection line SL in the circuit are both part of the second conductive metal layer. The electrode layer E, the first conductive metal layer and the second conductive metal layer are arranged in sequence from bottom to top. The first conductive block BK1 overlaps the first conductive through hole H1 and the second conductive through hole H2. One end of the first conductive through hole H1 is coupled to an external voltage, and the other end passes through the dielectric layer L, and is sequentially coupled to the first conductive block BK1, the second conductive through hole H2 and the first bit line BL1. In other words, the first conductive through hole H1, the first conductive block BK1, the second conductive through hole H2 and the first bit line BL1 are arranged in sequence from bottom to top. The second conductive block BK2 overlaps the third conductive through hole H3 and the fourth conductive through hole H4. One end of the third conductive through hole H3 is coupled to an external voltage, and the other end passes through the dielectric layer L, and is sequentially coupled to the second conductive block BK2, the fourth conductive through hole H4 and the first selection line SL1. That is, the third conductive via H3, the second conductive block BK2, the fourth conductive via H4 and the first selection line SL1 are arranged in sequence from bottom to top. The first word line WL1, the conductive via H, the common well area W and the dielectric layer L overlap each other. One end of the conductive via H is coupled to the first word line WL1, and the other end is coupled to an external voltage, and the conductive via H passes through the common well area W and the dielectric layer L.

[0037] The following describes the operation process of the first memory cell 100, which includes programming, erasing and reading operations. The select line or word line is coupled to a low voltage or a ground voltage according to process characteristics.

[0038] When the first memory cell 100 is selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the first bit line BL1 and the first word line WL1 are coupled to a high voltage, and the first selection line SL1 is coupled to a low voltage or a ground voltage. When the first memory cell 100 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the first bit line BL1 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the first selection line SL1 is coupled to a medium voltage. When the first memory cell 100 is selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the first bit line BL1 is coupled to a high voltage, the first word line WL1 is coupled to a ground voltage or a low voltage, and the first selection line SL1 is coupled to a ground voltage. When the first memory cell 100 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the first bit line BL1 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the first selection line SL1 is coupled to a medium voltage. When the first memory cell 100 is selected to perform a read operation, the semiconductor region 104 is coupled to the first bit line BL1 with a ground voltage, and the first word line WL1 is coupled to the first selection line SL1 with a low voltage. When the first memory cell 100 is not selected to perform a read operation, the semiconductor region 104 is coupled to the first word line WL1 with a ground voltage, the first bit line BL1 is coupled with a low voltage, and the first selection line SL1 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the drain of the first field effect transistor T1 to the source of the first field effect transistor T1, that is, the high voltage is equal to the breakdown voltage of the drain of the first field effect transistor T1 to the source of the first field effect transistor T1 minus the critical voltage of the first field effect transistor T1. The medium voltage is equal to the breakdown voltage of the drain of the first field effect transistor T1 to the source of the first field effect transistor T1 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the drain of the first field effect transistor T1 to the source of the first field effect transistor T1 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the first memory cell 100 reads the current from the source of the first field effect transistor T1 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0039] Figure 5 FIG. 1 is a cross-sectional view of a second memory cell according to an embodiment of the present invention. Figure 2 , Figure 3 and Figure 5. The second memory cell 101 may include a second field effect transistor T2 and a second capacitor structure C2. The second field effect transistor T2, the second capacitor structure C2 and a second insulating structure O2 are disposed in the semiconductor region 104, and the second insulating structure O2 is located between the second field effect transistor T2 and the second capacitor structure C2 to isolate the second field effect transistor T2 from the second capacitor structure C2. The second field effect transistor T2 includes a second gate dielectric block 1010, a second conductive gate 1011 and two second heavily doped regions 1012. The second gate dielectric block 1010 is a part of the dielectric layer L, the second conductive gate 1011 is a part of the electrode layer E, and the second heavily doped region 1012 has a second conductivity type. The second gate dielectric block 1010 is disposed on the semiconductor region 104, and the second conductive gate 1011 is disposed on the second gate dielectric block 1010. The second heavily doped region 1012 is disposed in the semiconductor region 104 and is located at different sides of the semiconductor region 104 directly below the second conductive gate 1011, and is respectively coupled to the second bit line BL2 and the first selection line SL1. The second heavily doped region 1012 coupled to the second bit line BL2 serves as a drain, and the second heavily doped region 1012 coupled to the first selection line SL1 serves as a source. The second capacitor structure C2 includes a second well region 1013, a second dielectric block 1014, and a second electrode block 1015. The second well region 1013 is a part of the common well region W, the second dielectric block 1014 is a part of the dielectric layer L, and the second electrode block 1015 is a part of the electrode layer E. The second well region 1013 is of the second conductivity type. The second well region 1013 is disposed in the semiconductor region 104 and is coupled to the first word line WL1. The second dielectric block 1014 is disposed on the surface of the second well region 1013, and the second electrode block 1015 is stacked on the second dielectric block 1014 and coupled to the second conductive gate 1011. In some embodiments, in order to form an ohmic contact, the second capacitor structure C2 may further include a heavily doped region 1016, which has a second conductivity type and is located in the second well region 1013 and is coupled to the first word line WL1. The third conductive block BK3 is a part of the first conductive metal layer. The third conductive block BK3 overlaps the fifth conductive through hole H5 and the sixth conductive through hole H6. One end of the fifth conductive through hole H5 is coupled to an external voltage, and the other end passes through the dielectric layer L, and is sequentially coupled to the third conductive block BK3, the sixth conductive through hole H6 and the second bit line BL2. In other words, the fifth conductive through hole H5, the third conductive block BK3, the sixth conductive through hole H6 and the second bit line BL2 are sequentially arranged from bottom to top.

[0040] The following describes the operation process of the second memory cell 101, which includes programming, erasing and reading operations. The select line or word line is coupled to a low voltage or a ground voltage according to process characteristics.

[0041] When the second memory cell 101 is selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the second bit line BL2 and the first word line WL1 are coupled to a high voltage, and the first selection line SL1 is coupled to a low voltage or a ground voltage. When the second memory cell 101 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the second bit line BL2 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the first selection line SL1 is coupled to a medium voltage. When the second memory cell 101 is selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the second bit line BL2 is coupled to a high voltage, the first word line WL1 is coupled to a ground voltage or a low voltage, and the first selection line SL1 is coupled to a ground voltage. When the second memory cell 101 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the second bit line BL2 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the first selection line SL1 is coupled to a medium voltage. When the second memory cell 101 is selected to perform a read operation, the semiconductor region 104 is coupled to the ground voltage with the second bit line BL2, and the first word line WL1 is coupled to the first selection line SL1 with a low voltage. When the second memory cell 101 is not selected to perform a read operation, the semiconductor region 104 is coupled to the ground voltage with the first word line WL1, the second bit line BL2 is coupled to a low voltage, and the first selection line SL1 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the drain of the second field effect transistor T2 to the source of the second field effect transistor T2, that is, the high voltage is equal to the breakdown voltage of the drain of the second field effect transistor T2 to the source of the second field effect transistor T2 minus the critical voltage of the second field effect transistor T2. The medium voltage is equal to the breakdown voltage of the drain of the second field effect transistor T2 to the source of the second field effect transistor T2 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the drain of the second field effect transistor T2 to the source of the second field effect transistor T2 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the second memory cell 101 reads the current from the source of the second field effect transistor T2 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0042] Figure 6 FIG. 1 is a cross-sectional view of a structure of an embodiment of a third memory cell of the present invention. Figure 2 , Figure 3 and Figure 6The third memory cell 102 may include a third field effect transistor T3 and a third capacitor structure C3. The third field effect transistor T3, the third capacitor structure C3 and a third insulating structure O3 are disposed in the semiconductor region 104, and the third insulating structure O3 is located between the third field effect transistor T3 and the third capacitor structure C3 to isolate the third field effect transistor T3 from the third capacitor structure C3. The third field effect transistor T3 includes a third gate dielectric block 1020, a third conductive gate 1021 and two third heavily doped regions 1022. The third gate dielectric block 1020 is a part of the dielectric layer L, the third conductive gate 1021 is a part of the electrode layer E, and the third heavily doped region 1022 has a second conductivity type. The third gate dielectric block 1020 is disposed on the semiconductor region 104, and the third conductive gate 1021 is disposed on the third gate dielectric block 1020. The third heavily doped region 1022 is disposed in the semiconductor region 104 and is located at different sides of the semiconductor region 104 directly below the third conductive gate 1021, and is respectively coupled to the third bit line BL3 and the second selection line SL2. The third heavily doped region 1022 coupled to the third bit line BL3 serves as a drain, and the third heavily doped region 1022 coupled to the second selection line SL2 serves as a source. The third capacitor structure C3 includes a third well region 1023, a third dielectric block 1024, and a third electrode block 1025. The third well region 1023 is a part of the common well region W, the third dielectric block 1024 is a part of the dielectric layer L, and the third electrode block 1025 is a part of the electrode layer E. The common well region W and the third well region 1023 are both of the second conductivity type. The third well region 1023 is disposed in the semiconductor region 104 and is coupled to the first word line WL1. The third dielectric block 1024 is disposed on the surface of the third well region 1023, and the third electrode block 1025 is stacked on the third dielectric block 1024 and coupled to the third conductive gate 1021. In some embodiments, in order to form an ohmic contact, the third capacitor structure C3 may further include a heavily doped region 1026, which has a second conductivity type, is located in the third well region 1023, and is coupled to the first word line WL1. The fourth conductive block BK4 and the fifth conductive block BK5 are both part of the first conductive metal layer. The fourth conductive block BK4 overlaps the seventh conductive through hole H7 and the eighth conductive through hole H8. One end of the seventh conductive through hole H7 is coupled to an external voltage, and the other end passes through the dielectric layer L, and is sequentially coupled to the fourth conductive block BK4, the eighth conductive through hole H8, and the third bit line BL3. In other words, the seventh conductive through hole H7, the fourth conductive block BK4, the eighth conductive through hole H8, and the third bit line BL3 are sequentially arranged from bottom to top. The fifth conductive block BK5 overlaps the ninth conductive via H9 and the tenth conductive via H10. One end of the ninth conductive via H9 is coupled to an external voltage, and the other end passes through the dielectric layer L and is sequentially coupled to the fifth conductive block BK5, the tenth conductive via H10 and the second selection line SL2.That is to say, the ninth conductive via H9, the fifth conductive block BK5, the tenth conductive via H10 and the second selection line SL2 are sequentially arranged from bottom to top.

[0043] The following describes the operation process of the third memory cell 102, which includes programming, erasing and reading operations. The select line or word line is coupled to a low voltage or a ground voltage according to process characteristics.

[0044] When the third memory cell 102 is selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the third bit line BL3 and the first word line WL1 are coupled to a high voltage, and the second selection line SL2 is coupled to a low voltage or a ground voltage. When the third memory cell 102 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the third bit line BL3 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the second selection line SL2 is coupled to a medium voltage. When the third memory cell 102 is selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the third bit line BL3 is coupled to a high voltage, the first word line WL1 is coupled to a ground voltage or a low voltage, and the second selection line SL2 is coupled to a ground voltage. When the third memory cell 102 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the third bit line BL3 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the second selection line SL2 is coupled to a medium voltage. When the third memory cell 102 is selected to perform a read operation, the semiconductor region 104 is coupled to the third bit line BL3 with a ground voltage, and the first word line WL1 is coupled to the second selection line SL2 with a low voltage. When the third memory cell 102 is not selected to perform a read operation, the semiconductor region 104 is coupled to the first word line WL1 with a ground voltage, the third bit line BL3 is coupled with a low voltage, and the second selection line SL2 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the drain of the third field effect transistor T3 to the source of the third field effect transistor T3, that is, the high voltage is equal to the breakdown voltage of the drain of the third field effect transistor T3 to the source of the third field effect transistor T3 minus the critical voltage of the third field effect transistor T3. The medium voltage is equal to the breakdown voltage of the drain of the third field effect transistor T3 to the source of the third field effect transistor T3 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the drain of the third field effect transistor T3 to the source of the third field effect transistor T3 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the third memory cell 102 reads the current from the source of the third field effect transistor T3 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0045] Figure 7 FIG. 1 is a cross-sectional view of a structure of an embodiment of a fourth memory cell of the present invention. Figure 2 , Figure 3 and Figure 7. The fourth memory cell 103 may include a fourth field effect transistor T4 and a fourth capacitor structure C4. The fourth field effect transistor T4, the fourth capacitor structure C4 and a fourth insulating structure O4 are disposed in the semiconductor region 104, and the fourth insulating structure O4 is located between the fourth field effect transistor T4 and the fourth capacitor structure C4 to isolate the fourth field effect transistor T4 from the fourth capacitor structure C4. The fourth field effect transistor T4 includes a fourth gate dielectric block 1030, a fourth conductive gate 1031 and two fourth heavily doped regions 1032. The fourth gate dielectric block 1030 is a part of the dielectric layer L, the fourth conductive gate 1031 is a part of the electrode layer E, and the fourth heavily doped region 1032 has a second conductivity type. The fourth gate dielectric block 1030 is disposed on the semiconductor region 104, and the fourth conductive gate 1031 is disposed on the fourth gate dielectric block 1030. The fourth heavily doped region 1032 is disposed in the semiconductor region 104 and is located at different sides of the semiconductor region 104 directly below the fourth conductive gate 1031, and is respectively coupled to the fourth bit line BL4 and the second selection line SL2. The fourth heavily doped region 1032 coupled to the fourth bit line BL4 serves as a drain, and the fourth heavily doped region 1032 coupled to the second selection line SL2 serves as a source. The fourth capacitor structure C4 includes a fourth well region 1033, a fourth dielectric block 1034, and a fourth electrode block 1035. The fourth well region 1033 is a part of the common well region W, the fourth dielectric block 1034 is a part of the dielectric layer L, and the fourth electrode block 1035 is a part of the electrode layer E. The fourth well region 1033 is of the second conductivity type. The fourth well region 1033 is disposed in the semiconductor region 104 and is coupled to the first word line WL1. The fourth dielectric block 1034 is disposed on the surface of the fourth well region 1033, and the fourth electrode block 1035 is stacked on the fourth dielectric block 1034 and coupled to the fourth conductive gate 1031. In some embodiments, in order to form an ohmic contact, the fourth capacitor structure C4 may further include a heavily doped region 1036, which has the second conductivity type and is located in the fourth well region 1033 and is coupled to the first word line WL1. The sixth conductive block BK6 is a part of the first conductive metal layer. The sixth conductive block BK6 overlaps the eleventh conductive via H11 and the twelfth conductive via H12. One end of the eleventh conductive via H11 is coupled to an external voltage, and the other end penetrates the dielectric layer L, and is sequentially coupled to the sixth conductive block BK6, the twelfth conductive via H12 and the fourth bit line BL4. That is, the eleventh conductive via H11, the sixth conductive block BK6, the twelfth conductive via H12 and the fourth bit line BL4 are sequentially arranged from bottom to top.

[0046] The operation process of the fourth memory cell 103 is described below, which includes programming, erasing and reading operations. The select line or word line is coupled to a low voltage or a ground voltage according to process characteristics.

[0047] When the fourth memory cell 103 is selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the fourth bit line BL4 and the first word line WL1 are coupled to a high voltage, and the second selection line SL2 is coupled to a low voltage or a ground voltage. When the fourth memory cell 103 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a ground voltage, the fourth bit line BL4 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the second selection line SL2 is coupled to a medium voltage. When the fourth memory cell 103 is selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the fourth bit line BL4 is coupled to a high voltage, the first word line WL1 is coupled to a ground voltage or a low voltage, and the second selection line SL2 is coupled to a ground voltage. When the fourth memory cell 103 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a ground voltage, the fourth bit line BL4 is electrically floating, the first word line WL1 is coupled to a low voltage or a ground voltage, and the second selection line SL2 is coupled to a medium voltage. When the fourth memory cell 103 is selected to perform a read operation, the semiconductor region 104 is coupled to the fourth bit line BL4 with a ground voltage, and the first word line WL1 is coupled to the second selection line SL2 with a low voltage. When the fourth memory cell 103 is not selected to perform a read operation, the semiconductor region 104 is coupled to the first word line WL1 with a ground voltage, the fourth bit line BL4 is coupled with a low voltage, and the second selection line SL2 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the drain of the fourth field effect transistor T4 to the source of the fourth field effect transistor T4, that is, the high voltage is equal to the breakdown voltage of the drain of the fourth field effect transistor T4 to the source of the fourth field effect transistor T4 minus the critical voltage of the fourth field effect transistor T4. The medium voltage is equal to the breakdown voltage of the drain of the fourth field effect transistor T4 to the source of the fourth field effect transistor T4 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the drain of the fourth field effect transistor T4 to the source of the fourth field effect transistor T4 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the fourth memory cell 103 reads the current from the source of the fourth field effect transistor T4 to identify the current storage state, rather than reading the current from the drain that will experience high-voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0048] Figure 8 FIG. 1 is a schematic diagram of an equivalent circuit of another embodiment of a high-speed and high-write-endurance read-only memory array of the present invention. Figure 2 , Figure 4 and Figure 8 In this embodiment, the first conductivity type is N type and the second conductivity type is P type. The operation process of the first memory cell 100 is described below, which includes programming, erasing and reading. The select line or word line is coupled to a medium voltage or a high voltage according to the process characteristics.

[0049] When the first memory cell 100 is selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the first bit line BL1 and the first word line WL1 are coupled to a ground voltage, and the first selection line SL1 is coupled to a medium voltage or a high voltage. When the first memory cell 100 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the first bit line BL1 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a low voltage. When the first memory cell 100 is selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the first bit line BL1 is coupled to a ground voltage, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a high voltage. When the first memory cell 100 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the first bit line BL1 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a low voltage. When the first memory cell 100 is selected for a read operation, the semiconductor region 104 is coupled to the first bit line BL1 with a medium voltage, and the first word line WL1 is coupled to the first selection line SL1 with a low voltage. When the first memory cell 100 is not selected for a read operation, the semiconductor region 104 is coupled to the first word line WL1 with a medium voltage, the first bit line BL1 is coupled with a low voltage, and the first selection line SL1 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the source of the first field effect transistor T1 to the drain of the first field effect transistor T1, that is, the high voltage is equal to the breakdown voltage of the source of the first field effect transistor T1 to the drain of the first field effect transistor T1 plus the critical voltage of the first field effect transistor T1. The medium voltage is equal to the breakdown voltage of the source of the first field effect transistor T1 to the drain of the first field effect transistor T1 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the source of the first field effect transistor T1 to the drain of the first field effect transistor T1 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the first memory cell 100 reads the current from the source of the first field effect transistor T1 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0050] See also Figure 2 , Figure 5 and Figure 8In this embodiment, the first conductivity type is N type and the second conductivity type is P type. The operation process of the second memory cell 101 is described below, which includes programming, erasing and reading. The select line or word line is coupled to a medium voltage or a high voltage according to the process characteristics.

[0051] When the second memory cell 101 is selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the second bit line BL2 and the first word line WL1 are coupled to a ground voltage, and the first selection line SL1 is coupled to a medium voltage or a high voltage. When the second memory cell 101 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the second bit line BL2 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a low voltage. When the second memory cell 101 is selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the second bit line BL2 is coupled to a ground voltage, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a high voltage. When the second memory cell 101 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the second bit line BL2 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the first selection line SL1 is coupled to a low voltage. When the second memory cell 101 is selected to perform a read operation, the semiconductor region 104 is coupled to the second bit line BL2 with a medium voltage, and the first word line WL1 is coupled to the first selection line SL1 with a low voltage. When the second memory cell 101 is not selected to perform a read operation, the semiconductor region 104 is coupled to the first word line WL1 with a medium voltage, the second bit line BL2 is coupled to a low voltage, and the first selection line SL1 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the source of the second field effect transistor T2 to the drain of the second field effect transistor T2, that is, the high voltage is equal to the breakdown voltage of the source of the second field effect transistor T2 to the drain of the second field effect transistor T2 plus the critical voltage of the second field effect transistor T2. The medium voltage is equal to the breakdown voltage of the source of the second field effect transistor T2 to the drain of the second field effect transistor T2 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the source of the second field effect transistor T2 to the drain of the second field effect transistor T2 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the second memory cell 101 reads the current from the source of the second field effect transistor T2 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0052] See also Figure 2 , Figure 6 and Figure 8In this embodiment, the first conductivity type is N type and the second conductivity type is P type. The operation process of the third memory cell 102 is described below, which includes programming, erasing and reading. The select line or word line is coupled to a medium voltage or a high voltage according to process characteristics.

[0053] When the third memory cell 102 is selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the third bit line BL3 and the first word line WL1 are coupled to a ground voltage, and the second selection line SL2 is coupled to a medium voltage or a high voltage. When the third memory cell 102 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the third bit line BL3 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a low voltage. When the third memory cell 102 is selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the third bit line BL3 is coupled to a ground voltage, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a high voltage. When the third memory cell 102 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the third bit line BL3 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a low voltage. When the third memory cell 102 is selected for reading, the semiconductor region 104 is coupled to the third bit line BL3 with a medium voltage, and the first word line WL1 is coupled to the second selection line SL2 with a low voltage. When the third memory cell 102 is not selected for reading, the semiconductor region 104 is coupled to the first word line WL1 with a medium voltage, the third bit line BL3 is coupled with a low voltage, and the second selection line SL2 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the source of the third field effect transistor T3 to the drain of the third field effect transistor T3, that is, the high voltage is equal to the breakdown voltage of the source of the third field effect transistor T3 to the drain of the third field effect transistor T3 plus the critical voltage of the third field effect transistor T3. The medium voltage is equal to the breakdown voltage of the source of the third field effect transistor T3 to the drain of the third field effect transistor T3 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the source of the third field effect transistor T3 to the drain of the third field effect transistor T3 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the third memory cell 102 reads the current from the source of the third field effect transistor T3 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0054] See also Figure 2 , Figure 7 and Figure 8In this embodiment, the first conductivity type is N type and the second conductivity type is P type. The operation process of the fourth memory cell 103 is described below, which includes programming, erasing and reading. The select line or word line is coupled to a medium voltage or a high voltage according to process characteristics.

[0055] When the fourth memory cell 103 is selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the fourth bit line BL4 and the first word line WL1 are coupled to a ground voltage, and the second selection line SL2 is coupled to a medium voltage or a high voltage. When the fourth memory cell 103 is not selected to perform a programming operation, the semiconductor region 104 is coupled to a high voltage, the fourth bit line BL4 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a low voltage. When the fourth memory cell 103 is selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the fourth bit line BL4 is coupled to a ground voltage, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a high voltage. When the fourth memory cell 103 is not selected to perform an erase operation, the semiconductor region 104 is coupled to a high voltage, the fourth bit line BL4 is electrically floating, the first word line WL1 is coupled to a medium voltage or a high voltage, and the second selection line SL2 is coupled to a low voltage. When the fourth memory cell 103 is selected for reading, the semiconductor region 104 is coupled to the fourth bit line BL4 with a medium voltage, and the first word line WL1 is coupled to the second selection line SL2 with a low voltage. When the fourth memory cell 103 is not selected for reading, the semiconductor region 104 is coupled to the first word line WL1 with a medium voltage, the fourth bit line BL4 is coupled with a low voltage, and the second selection line SL2 is electrically floating. In the above operation, the high voltage is greater than the medium voltage, the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage. Specifically, the high voltage is slightly lower than the breakdown voltage of the source of the fourth field effect transistor T4 to the drain of the fourth field effect transistor T4, that is, the high voltage is equal to the breakdown voltage of the source of the fourth field effect transistor T4 to the drain of the fourth field effect transistor T4 plus the critical voltage of the fourth field effect transistor T4. The medium voltage is equal to the breakdown voltage of the source of the fourth field effect transistor T4 to the drain of the fourth field effect transistor T4 multiplied by 0.5. The low voltage is equal to the breakdown voltage of the source of the fourth field effect transistor T4 to the drain of the fourth field effect transistor T4 multiplied by 0.25. The ground voltage is zero voltage. Based on the above operation, the fourth memory cell 103 reads the current from the source of the fourth field effect transistor T4 to identify the current storage state, rather than reading the current from the drain that will experience high voltage operation, so as to reduce the impact caused by electrons entering the gate to change the threshold voltage. Compared with Fowler-Nordheim tunneling, the high-speed high-write-number read-only memory array 1 can use a lower voltage to achieve the purpose of high-speed writing and high write-number.

[0056] Fig. 9 is a structural cross-sectional view of another embodiment of the first memory cell of the present invention, Fig.10 is a structural cross-sectional view of another embodiment of the second memory cell of the present invention, Fig.11is a structural cross-sectional view of another embodiment of the third memory cell of the present invention, Fig.12 FIG. 4 is a cross-sectional view of another embodiment of the fourth memory cell of the present invention. Fig. 9 , Fig.10 , Fig.11 and Fig.12 The first memory cell 100, the second memory cell 101, the third memory cell 102 and the fourth memory cell 103 can be arranged in a semiconductor region 104 implemented by a semiconductor epitaxial layer, and the semiconductor region 104 is arranged on a semiconductor substrate 2. The remaining structures have been described above and will not be repeated here.

[0057] According to the above embodiments, the high-speed and high-write-endurance read-only memory array can use a lower voltage to achieve the purpose of high-speed writing and high write-endurance.

[0058] The above is only a preferred embodiment of the present invention and is not intended to limit the scope of the present invention. Therefore, all equivalent changes and modifications to the shape, structure, characteristics and spirit described in the claims of the present invention should be included in the scope of the claims of the present invention.

Claims

1. A high-speed, high-write-endurance read-only memory array, characterized in that: The high-speed high-write-time read-only memory array comprises: a plurality of parallel word lines, including a first word line; A plurality of parallel selection lines, which are perpendicular to the plurality of parallel word lines, wherein the plurality of parallel selection lines include a first selection line and a second selection line; a plurality of parallel bit lines, parallel to the plurality of parallel selection lines, the plurality of parallel bit lines comprising a first bit line, a second bit line, a third bit line and a fourth bit line, the first selection line being located between the first bit line and the second bit line, and the second selection line being located between the third bit line and the fourth bit line; and A plurality of sub-memory arrays, each sub-memory array is coupled to a word line, two selection lines and four bit lines, wherein each sub-memory array comprises: a first memory cell coupled to the first word line, the first bit line and the first selection line; a second memory cell coupled to the first word line, the second bit line and the first selection line; a third memory cell coupled to the first word line, the third bit line and the second selection line; and A fourth memory cell is coupled to the first word line, the fourth bit line and the second selection line.

2. The high-speed high-write-endurance read-only memory array according to claim 1, characterized in that: The first memory unit cell is symmetrically arranged with the second memory unit cell, the first memory unit cell is symmetrically arranged with the third memory unit cell, the fourth memory unit cell is symmetrically arranged with the second memory unit cell, and the fourth memory unit cell is symmetrically arranged with the third memory unit cell.

3. The high-speed high-write-endurance read-only memory array according to claim 2, characterized in that: The first memory cell, the second memory cell, the third memory cell and the fourth memory cell are disposed in a semiconductor region having a first conductivity type, and the first memory cell comprises: a first field effect transistor disposed in the semiconductor region; and a first capacitor structure, disposed in the semiconductor region and isolated from the first field effect transistor; Wherein, the first field effect transistor comprises: a first gate dielectric block disposed on the semiconductor region; a first conductive gate disposed on the first gate dielectric block; and Two first heavily doped regions are disposed in the semiconductor region and are respectively located on different sides of the semiconductor region directly below the first conductive gate and are respectively coupled to the first bit line and the first selection line, wherein the two first heavily doped regions have a second conductivity type opposite to the first conductivity type; The first capacitor structure comprises: a first well region, disposed in the semiconductor region and coupled to the first word line, wherein the first well region has the second conductivity type; a first dielectric block disposed on the surface of the first well region; and A first electrode block is stacked on the first dielectric block and coupled to the first conductive gate.

4. The high-speed high-write-endurance read-only memory array according to claim 3, characterized in that: The second memory cell comprises: a second field effect transistor disposed in the semiconductor region; and a second capacitor structure, disposed in the semiconductor region and isolated from the second field effect transistor; Wherein, the second field effect transistor comprises: a second gate dielectric block disposed on the semiconductor region; a second conductive gate disposed on the second gate dielectric block; and Two second heavily doped regions are disposed in the semiconductor region and are respectively located on different sides of the semiconductor region directly below the second conductive gate and are respectively coupled to the second bit line and the first selection line, wherein the two second heavily doped regions have the second conductivity type; The second capacitor structure comprises: a second well region, disposed in the semiconductor region and coupled to the first word line, wherein the second well region has the second conductivity type; a second dielectric block disposed on the surface of the second well region; and A second electrode block is stacked on the second dielectric block and coupled to the second conductive gate.

5. The high-speed high-write-endurance read-only memory array according to claim 4, characterized in that: The third memory cell comprises: a third field effect transistor, disposed in the semiconductor region; and a third capacitor structure, disposed in the semiconductor region and isolated from the third field effect transistor; Wherein, the third field effect transistor comprises: a third gate dielectric block disposed on the semiconductor region; a third conductive gate disposed on the third gate dielectric block; and Two third heavily doped regions are disposed in the semiconductor region and are respectively located on different sides of the semiconductor region directly below the third conductive gate and are respectively coupled to the third bit line and the second selection line, wherein the two third heavily doped regions have the second conductivity type; The third capacitor structure comprises: a third well region, disposed in the semiconductor region and coupled to the first word line, wherein the third well region has the second conductivity type; a third dielectric block disposed on the surface of the third well region; and A third electrode block is stacked on the third dielectric block and coupled to the third conductive gate.

6. The high-speed high-write-endurance read-only memory array according to claim 5, characterized in that: The fourth memory cell comprises: a fourth field effect transistor, disposed in the semiconductor region; and a fourth capacitor structure, disposed in the semiconductor region and isolated from the fourth field effect transistor; Wherein, the fourth field effect transistor comprises: a fourth gate dielectric block disposed on the semiconductor region; a fourth conductive gate disposed on the fourth gate dielectric block; and Two fourth heavily doped regions are disposed in the semiconductor region and are respectively located on different sides of the semiconductor region directly below the fourth conductive gate and are respectively coupled to the fourth bit line and the second selection line, wherein the two fourth heavily doped regions have the second conductivity type; The fourth capacitor structure comprises: a fourth well region, disposed in the semiconductor region and coupled to the first word line, wherein the fourth well region has the second conductivity type; a fourth dielectric block disposed on the surface of the fourth well region; and A fourth electrode block is stacked on the fourth dielectric block and coupled to the fourth conductive gate.

7. The high-speed high-write-endurance read-only memory array according to claim 6, characterized in that: The first conductivity type is P type, and the second conductivity type is N type.

8. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is selected for programming, the semiconductor region is coupled to a ground voltage, the first bit line and the first word line are coupled to a high voltage, and the first selection line is coupled to a low voltage or the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

9. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is not selected for programming, the semiconductor region is coupled to a ground voltage, the first bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the first selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

10. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is selected for programming, the semiconductor region is coupled to a ground voltage, the second bit line and the first word line are coupled to a high voltage, and the first selection line is coupled to a low voltage or the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

11. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is not selected for programming, the semiconductor region is coupled to a ground voltage, the second bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the first selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

12. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is selected for programming, the semiconductor region is coupled to a ground voltage, the third bit line and the first word line are coupled to a high voltage, and the second selection line is coupled to a low voltage or a ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

13. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is not selected for programming, the semiconductor region is coupled to a ground voltage, the third bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the second selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

14. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is selected for programming, the semiconductor region is coupled to a ground voltage, the fourth bit line and the first word line are coupled to a high voltage, and the second selection line is coupled to a low voltage or the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

15. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is not selected for programming, the semiconductor region is coupled to a ground voltage, the fourth bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the second selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

16. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is selected for erasing, the semiconductor region is coupled to a ground voltage, the first bit line is coupled to a high voltage, the first word line is coupled to a ground voltage or a low voltage, and the first selection line is coupled to the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

17. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is not selected for erasing, the semiconductor region is coupled to a ground voltage, the first bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the first selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

18. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is selected for erasing, the semiconductor region is coupled to a ground voltage, the second bit line is coupled to a high voltage, the first word line is coupled to a ground voltage or a low voltage, and the first selection line is coupled to the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

19. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is not selected for erasing, the semiconductor region is coupled to a ground voltage, the second bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the first selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

20. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is selected for erasing, the semiconductor region is coupled to a ground voltage, the third bit line is coupled to a high voltage, the first word line is coupled to a ground voltage or a low voltage, and the second selection line is coupled to the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

21. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is not selected for erasing, the semiconductor region is coupled to a ground voltage, the third bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the second selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

22. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is selected for erasing, the semiconductor region is coupled to a ground voltage, the fourth bit line is coupled to a high voltage, the first word line is coupled to a ground voltage or a low voltage, and the second selection line is coupled to the ground voltage, wherein the high voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

23. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is not selected for erasing, the semiconductor region is coupled to a ground voltage, the fourth bit line is electrically floating, the first word line is coupled to a low voltage or the ground voltage, and the second selection line is coupled to a medium voltage, wherein the medium voltage is greater than the low voltage, and the low voltage is greater than the ground voltage.

24. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is selected for a read operation, the semiconductor region and the first bit line are coupled to a ground voltage, and the first word line and the first selection line are coupled to a low voltage, wherein the low voltage is greater than the ground voltage.

25. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the first memory cell is not selected for reading, the semiconductor region and the first word line are coupled to a ground voltage, the first bit line is coupled to a low voltage, and the first selection line is electrically floating, wherein the low voltage is greater than the ground voltage.

26. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is selected for a read operation, the semiconductor region and the second bit line are coupled to a ground voltage, and the first word line and the first selection line are coupled to a low voltage, wherein the low voltage is greater than the ground voltage.

27. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the second memory cell is not selected for reading, the semiconductor region and the first word line are coupled to a ground voltage, the second bit line is coupled to a low voltage, and the first selection line is electrically floating, wherein the low voltage is greater than the ground voltage.

28. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is selected for a read operation, the semiconductor region and the third bit line are coupled to a ground voltage, and the first word line and the second selection line are coupled to a low voltage, wherein the low voltage is greater than the ground voltage.

29. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the third memory cell is not selected for reading, the semiconductor region and the first word line are coupled to a ground voltage, the third bit line is coupled to a low voltage, and the second selection line is electrically floating, wherein the low voltage is greater than the ground voltage.

30. The high-speed high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is selected for a read operation, the semiconductor region and the fourth bit line are coupled to a ground voltage, and the first word line and the second selection line are coupled to a low voltage, wherein the low voltage is greater than the ground voltage.

31. The high-speed and high-write-endurance read-only memory array according to claim 7, characterized in that: When the fourth memory cell is not selected for reading, the semiconductor region and the first word line are coupled to a ground voltage, the fourth bit line is coupled to a low voltage, and the second selection line is electrically floating, wherein the low voltage is greater than the ground voltage.

32. The high-speed high-write-endurance read-only memory array according to claim 6, characterized in that: The first conductivity type is N type, and the second conductivity type is P type.

33. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is selected for programming, the semiconductor region is coupled with a high voltage, the first bit line and the first word line are coupled with a ground voltage, and the first selection line is coupled with a medium voltage or the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

34. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is not selected for programming, the semiconductor region is coupled with a high voltage, the first bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the first selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

35. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is selected for programming, the semiconductor region is coupled with a high voltage, the second bit line and the first word line are coupled with a ground voltage, and the first selection line is coupled with a medium voltage or the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

36. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is not selected for programming, the semiconductor region is coupled with a high voltage, the second bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the first selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

37. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is selected for programming, the semiconductor region is coupled with a high voltage, the third bit line and the first word line are coupled with a ground voltage, and the second selection line is coupled with a medium voltage or the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

38. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is not selected for programming, the semiconductor region is coupled with a high voltage, the third bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

39. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is selected for programming, the semiconductor region is coupled with a high voltage, the fourth bit line and the first word line are coupled with a ground voltage, and the second selection line is coupled with a medium voltage or the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

40. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is not selected for programming, the semiconductor region is coupled with a high voltage, the fourth bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

41. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is selected to perform an erase operation, the semiconductor region is coupled to a high voltage, the first bit line is coupled to a ground voltage, the first word line is coupled to a medium voltage or the high voltage, and the first selection line is coupled to the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

42. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is not selected for erasing, the semiconductor region is coupled with a high voltage, the first bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the first selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

43. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is selected for erasing, the semiconductor region is coupled with a high voltage, the second bit line is coupled with a ground voltage, the first word line is coupled with a medium voltage or the high voltage, and the first selection line is coupled with the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

44. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is not selected for erasing, the semiconductor region is coupled with a high voltage, the second bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the first selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

45. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is selected for erasing, the semiconductor region is coupled with a high voltage, the third bit line is coupled with a ground voltage, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

46. ​​The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is not selected for erasing, the semiconductor region is coupled with a high voltage, the third bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

47. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is selected for erasing, the semiconductor region is coupled with a high voltage, the fourth bit line is coupled with a ground voltage, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with the high voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the ground voltage.

48. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is not selected for erasing, the semiconductor region is coupled with a high voltage, the fourth bit line is electrically floating, the first word line is coupled with a medium voltage or the high voltage, and the second selection line is coupled with a low voltage, wherein the high voltage is greater than the medium voltage, and the medium voltage is greater than the low voltage.

49. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is selected for a read operation, the semiconductor region and the first bit line are coupled to a medium voltage, and the first word line and the first selection line are coupled to a low voltage, wherein the medium voltage is greater than the low voltage.

50. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the first memory cell is not selected for reading, the semiconductor region and the first word line are coupled with a medium voltage, the first bit line is coupled with a low voltage, and the first selection line is electrically floating, wherein the medium voltage is greater than the low voltage.

51. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is selected for a read operation, the semiconductor region and the second bit line are coupled to a medium voltage, and the first word line and the first selection line are coupled to a low voltage, wherein the medium voltage is greater than the low voltage.

52. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the second memory cell is not selected for reading, the semiconductor region and the first word line are coupled with a medium voltage, the second bit line is coupled with a low voltage, and the first selection line is electrically floating, wherein the medium voltage is greater than the low voltage.

53. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is selected for a read operation, the semiconductor region and the third bit line are coupled to a medium voltage, and the first word line and the second selection line are coupled to a low voltage, wherein the medium voltage is greater than the low voltage.

54. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the third memory cell is not selected for reading, the semiconductor region and the first word line are coupled with a medium voltage, the third bit line is coupled with a low voltage, and the second selection line is electrically floating, wherein the medium voltage is greater than the low voltage.

55. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is selected for a read operation, the semiconductor region and the fourth bit line are coupled to a medium voltage, and the first word line and the second selection line are coupled to a low voltage, wherein the medium voltage is greater than the low voltage.

56. The high-speed high-write-endurance read-only memory array according to claim 32, characterized in that: When the fourth memory cell is not selected for reading, the semiconductor region and the first word line are coupled with a medium voltage, the fourth bit line is coupled with a low voltage, and the second selection line is electrically floating, wherein the medium voltage is greater than the low voltage.

57. The high-speed high-write-endurance read-only memory array according to claim 3, characterized in that: The semiconductor region is a semiconductor substrate or a semiconductor epitaxial layer arranged on the semiconductor substrate.

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