Package and method of forming same

Abstract

The method includes forming a first conductive element on a first composite layer extending through the first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, where the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on the second polymer layer extending through the second polymer layer, where the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming a second conductive element extending through the second composite layer. The embodiment of the invention also relates to a package and a method of forming the same.

Description

Technical Field

[0001] Embodiments of the present application relate to packages and methods of forming the same. Background Art

[0002] The semiconductor industry has experienced rapid growth due to the continuous improvement in the integration density of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.). In most cases, the improvement in integration density comes from the iterative reduction of the minimum component size, which allows more components to be integrated into a given area. As the demand for shrinking electronic devices grows, there is a demand for smaller and more creative semiconductor chip packaging technologies. Summary of the invention

[0003] Some embodiments of the present application provide a method for forming a package, comprising: forming a plurality of first conductive elements on a first composite layer extending through the first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer above the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on the second polymer layer extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming a plurality of second conductive elements extending through the second composite layer.

[0004] Other embodiments of the present application provide a method for forming a package, comprising: forming a first interconnect layer on a first carrier substrate, wherein the first interconnect layer includes a first composite material; forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure includes: depositing a first dielectric layer; patterning the first dielectric layer using a photolithography mask; and depositing a first conductive material on the first dielectric layer; forming a second redistribution structure on the first redistribution structure, wherein forming the second redistribution structure includes: depositing a second dielectric layer; patterning the second dielectric layer using a photolithography mask; and depositing a second conductive material on the second dielectric layer; and attaching an integrated circuit die to the second redistribution structure.

[0005] Still other embodiments of the present application provide a package, comprising: a first composite layer; a second composite layer located on the first composite layer; a plurality of conductive elements located within the first composite layer and the second composite layer; a first redistribution structure located on the second composite layer, wherein the first redistribution structure comprises a plurality of first polymer layers and a plurality of first conductive wires; a second redistribution structure located on the first redistribution structure, wherein the second redistribution structure comprises a plurality of second polymer layers and a plurality of second conductive wires, wherein the second polymer layers are thinner than the first polymer layers, and wherein the second conductive wires are thinner than the first conductive wires; and a semiconductor device attached to the second redistribution structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0006] When read in conjunction with the accompanying drawings, various aspects of the disclosed embodiments can be best understood from the following detailed description. It should be noted that, in accordance with standard practice in the industry, the various components are not drawn to scale. In fact, for clarity of discussion, the size of the various components may be arbitrarily increased or reduced.

[0007] Figure 1 , Figure 2 , Figure 3 and Figure 4 Cross-sectional views of intermediate steps during a process for forming an integrated circuit package are shown in accordance with some embodiments.

[0008] Figure 5 , Figure 6 , Figure 7 , Figure 8 , Fig. 9 and Fig.10 Cross-sectional views are shown of intermediate steps during a process for forming a redistribution structure for an integrated circuit package, in accordance with some embodiments.

[0009] Fig.11 , Fig.12 , Fig.13 , Fig.14 and Fig.15 Cross-sectional views are shown of intermediate steps during a process for forming a redistribution structure for an integrated circuit package, in accordance with some embodiments.

[0010] Fig.16 , Fig.17 , Fig.18 , Fig.19 , Fig. 20 , Fig.21 , Fig. 22 , Fig.23 , Fig.24 , Fig.25 and Fig.26 Cross-sectional views of intermediate steps during a process for forming an integrated circuit package are shown in accordance with some embodiments.

[0011] Fig. 27 A cross-sectional view of a singulation process for forming an integrated circuit package is shown in accordance with some embodiments.

[0012] Fig.28 A cross-sectional view of an integrated circuit package is shown in accordance with some embodiments.

[0013] Fig.29 A cross-sectional view of an integrated circuit package is shown in accordance with some embodiments. DETAILED DESCRIPTION

[0014] The following disclosure provides many different embodiments or examples for realizing different features of the disclosed embodiments. Specific examples of components and arrangements are described below to simplify the disclosed embodiments. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the disclosed embodiments may repeat reference numerals and / or characters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and / or configurations discussed.

[0015] Additionally, for ease of description, spatially relative terms such as "below," "beneath," "lower," "above," "upper," etc. may be used herein to describe the relationship of one element or component to another (or additional) elements or components as illustrated in the figures. The spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein should likewise be interpreted accordingly.

[0016] The embodiments will be described with respect to embodiments in a specific context, namely, an integrated circuit package and a method for forming the same. In various embodiments presented herein, the package includes a wiring structure formed by a plurality of redistribution structures, which may be formed, for example, by a polymer layer. The wiring structure is formed above a composite interconnect structure formed by a plurality of composite layers, which may be formed, for example, by a prepreg layer. Each redistribution structure of the wiring structure has conductive components of different thicknesses and different sizes. The redistribution structures are formed using photolithography techniques, which may improve the yield and throughput of manufacturing the package. The use of multiple composite layers may allow for improved structural stability and thermal performance of the package.

[0017] Figures 1 to 28An integrated circuit package 100 (see FIG. 1 ) is shown in accordance with some embodiments. Fig.28 ) is a cross-sectional view of an intermediate step. Figure 1 In the embodiment, a carrier substrate 102 is provided or formed. In some embodiments, the carrier substrate 102 includes a semiconductor material (such as silicon), a dielectric material (such as glass, ceramic material, quartz, plastic, etc.), a combination thereof, etc. The carrier substrate 102 may be a wafer, so that a plurality of package components may be formed on the carrier substrate 102 at the same time. Figures 1 to 18 FIG. 1 shows an intermediate step of forming a single package component in a structure region 101A of a carrier substrate 102 surrounded by an edge region 101B. In some embodiments, the edge region 101B may be trimmed. Fig.18 It should be understood that multiple package components may be formed in the structure area 101A and subsequently processed to form multiple integrated circuit packages 100. The multiple integrated circuit packages 100 may be singulated to form individual integrated circuit packages 100, as described in more detail below.

[0018] In addition, Figure 1 In some embodiments, a seed layer 104 is formed over a carrier substrate 102. The seed layer 104 may include a metal layer, which may be a single layer or a composite layer including multiple sub-layers formed of different materials. In a specific embodiment, the seed layer 104 includes a titanium layer and a copper layer over the titanium layer. The seed layer 104 may be formed using, for example, physical vapor deposition (PVD), sputtering, etc. Other materials or deposition techniques are also possible.

[0019] exist Figure 2In some embodiments, a first composite layer 106 is formed over the seed layer 104. The first composite layer 106 is an insulating layer formed of one or more composite layers. In some embodiments, the first composite layer 106 may be formed of a pre-impregnated composite fiber ("prepreg") material, etc., but other materials are also possible. For example, the first composite layer 106 may be formed of a pre-impregnated material including glass fibers pre-impregnated with a resin, such as an epoxy resin-impregnated glass cloth laminate, a polyimide-impregnated glass cloth laminate, etc. The first composite layer 106 may include glass cloth having any suitable weight, thickness, weave, density, resin content, coefficient of thermal expansion (CTE), etc. In some instances, the material of the first composite layer 106 may be selected so that the first composite layer 106 has a CTE similar to the CTE of other components of the package (such as an integrated circuit die, a support ring, other composite layers, etc.). The first composite layer 106 may include a single prepreg material or a stack of prepreg materials. In some embodiments, the first composite layer 106 can be formed on the seed layer 104 using a suitable process such as a lamination process. In some embodiments, the first composite layer 106 can have a thickness TP1 in the range of about 100 μm to about 300 μm, but other thicknesses are possible. In some examples, forming the insulating layer from a composite material such as a prepreg can allow the package to be formed with improved structural strength and a smaller overall thickness.

[0020] exist Figure 3 In some embodiments, openings 107 are formed in the first composite layer 106. The openings 107 may extend through the first composite layer 106 to expose a portion of the seed layer 104. The openings 107 may be formed using a mechanical drilling process, a laser drilling process, a photolithography masking and etching process, or another suitable process. In some embodiments, each opening 107 may have a width in a range of about 100 μm to about 300 μm, but other widths are possible.

[0021] exist Figure 4 In some embodiments, a conductive material is deposited to form a metallization pattern 108. The metallization pattern 108 includes a conductive via portion that extends through the first composite layer 106 and physically and electrically contacts the underlying seed layer 104. Figure 4 As shown in , the metallization pattern 108 may also include conductive element portions, such as conductive lines, conductive pads, etc., extending along the top surface of the first composite layer 106. In some embodiments, the conductive element portion of the metallization pattern 108 located on the top surface of the first composite layer 106 may have a thickness in the range of about 20 μm to about 40 μm, but other thicknesses are also possible. In some examples, the metallization pattern 108 and the first composite layer 106 together may be considered an "interconnect layer".

[0022] The metallization pattern 108 may include a conductive material such as copper, tungsten, aluminum, silver, gold, ruthenium, cobalt, combinations thereof, or the like. The conductive material may be deposited using a suitable technique, such as plating (e.g., electroplating or chemical plating), chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or another technique. Other materials or deposition techniques are also possible. In some embodiments, the metallization pattern 108 may include an optional barrier layer, a liner layer, or the like (not shown) covered by a conductive material.

[0023] In some embodiments, the metallization pattern 108 can be formed by: depositing a blanket layer of conductive material that fills the opening 107 and covers the top surface of the first composite layer 106; and then patterning the blanket layer. The conductive material can be patterned using suitable photolithographic masking and etching techniques. For example, a photoresist (not shown) can be formed and patterned on the conductive material. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The patterned photoresist can cover the portion of the conductive material corresponding to the metallization pattern 108 while exposing other portions of the conductive material. An etching process can then be implemented to remove the exposed portion of the conductive material, wherein the metallization pattern 108 is formed by the remaining portion of the conductive material. The etching process can include a wet etching process and / or a dry etching process. The photoresist can then be removed using a suitable process (such as ashing or stripping process).

[0024] In some embodiments, the metallization pattern 108 can be formed by first forming a patterned photoresist on the first composite layer 106. For example, the photoresist (not shown) can be formed by spin coating, etc., and can be exposed to light for patterning. The patterned photoresist can expose a portion of the first composite layer 106 corresponding to the metallization pattern 108, such as exposing the opening 107. Then, a conductive material can be deposited using a suitable technique. The upper portion of the photoresist and the conductive material can be removed using a suitable technique, wherein the remaining portion of the conductive material forms the metallization pattern 108.

[0025] In some embodiments, the metallization pattern 108 can be formed by first forming a seed layer (not shown) above the first composite layer 106 and in the opening 107. Then a photoresist is formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 108. Patterning forms an opening through the photoresist to expose the seed layer. Then a conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The photoresist and the portion of the seed layer on which the conductive material is not formed are removed. Once the photoresist is removed, the exposed portion of the seed layer is removed, such as by using an acceptable etching process, such as a wet etching process and / or a dry etching process. The remaining conductive material and the lower portion of the seed layer form the metallization pattern 108. These are examples, and other formation techniques are also possible.

[0026] Figures 5 to 10 The formation of the first redistribution structure 114 according to some embodiments is shown (see Fig.10 ). The first redistribution structure 114 includes a plurality of metallization patterns 112A-112D formed in a plurality of dielectric layers 110A-110D. The metallization patterns 112A-112D may include conductive lines, conductive vias, conductive pads, or other conductive components, and in some instances may be considered redistribution layers or interconnects. The first redistribution structure 114 described herein is an example, and in other embodiments there may be a different number, arrangement, or configuration of dielectric layers or metallization patterns. For example, if fewer dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below may be repeated.

[0027] exist Figure 5 In some embodiments, a dielectric layer 110A is deposited over the first composite layer 106 and the metallization pattern 108. In some embodiments, the dielectric layer 110A is formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as polybenzoxazole (PBO), polyimide, benzocyclobutene (BCB), etc. In other embodiments, the dielectric layer 110A is formed of: a nitride, such as silicon nitride; an oxide, such as silicon oxide, phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), etc.; etc. The dielectric layer 110A may be formed by any acceptable deposition process, such as spin coating, CVD, lamination, etc., or a combination thereof. In some embodiments, the dielectric layer 110A may be formed to have a thickness T1 in a range of about 10 μm to about 60 μm over the first composite layer 106, but other thicknesses are also possible.

[0028] exist Figure 6 In the embodiment of the present invention, the dielectric layer 110A is patterned to form an opening 111 that exposes a portion of the metallization pattern 108. The dielectric layer 110A can be patterned using an acceptable photolithography process. For example, in an embodiment where the dielectric layer 110A is a photosensitive material, the dielectric layer 110A can be exposed to light using a photolithography mask. The dielectric layer 110A can then be developed after exposure to form the opening 111. In other embodiments, a photoresist can be formed and patterned over the dielectric layer 110A, and the patterned photoresist can then be used as an etching mask to etch the dielectric layer 110A. In some embodiments, the opening 111 can have a width in the range of about 10 μm to about 60 μm, but other widths are also possible.

[0029] exist Figure 7 In the embodiment of the present invention, a metallization pattern 112A is formed on the dielectric layer 110A. The metallization pattern 112A includes a conductive wire extending along the top surface of the dielectric layer 110A and a conductive via extending through the opening 111 in the dielectric layer 110A to physically and electrically contact the metallization pattern 108. As an example of forming the metallization pattern 112A, a seed layer is first formed above the dielectric layer 110A and in the opening 111. In some embodiments, the seed layer is similar to the seed layer 104 or other seed layers described herein. For example, the seed layer may include a metal layer, and the metal layer may be a single layer or a composite layer including multiple sublayers formed by different materials. In some embodiments, the seed layer includes a copper layer above a titanium layer and a titanium layer. The seed layer can be formed using, for example, PVD, etc. A photoresist (not shown) is then formed and patterned on the seed layer. The photoresist can be formed by spin coating, etc., and can be exposed to light for patterning. The pattern of the photoresist corresponds to the metallization pattern 112A. Patterning forms an opening through the photoresist to expose the seed layer. Conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material can include metals, such as copper, titanium, tungsten, aluminum, etc. Then, remove the photoresist and the portion of the seed layer on which the conductive material is not formed. For example, the photoresist can be removed using a suitable ashing or stripping process. Once the photoresist is removed, the exposed portion of the seed layer is removed using, for example, an acceptable wet etching process or dry etching process. The remaining portion of the seed layer and the conductive material forms a metallization pattern 112A. In some embodiments, the wire portion of the metallization pattern 112A has a thickness in the range of about 5 μm to about 30 μm above the top surface of the dielectric layer 110A, but other thicknesses are also possible.

[0030] In some embodiments, another metallization pattern 112B may be formed over the metallization pattern 112A. Figure 8In the embodiment of the present invention, a dielectric layer 110B may be deposited over the dielectric layer 110A and the metallization pattern 112A. The dielectric layer 110B may be a material similar to the material of the dielectric layer 110A and may be formed using similar techniques. In some embodiments, the dielectric layer 110B may also be formed to have a thickness similar to that of the dielectric layer 110A (e.g., thickness T1). However, in other embodiments, the dielectric layer 110B may be formed of a different material than the dielectric layer 110A and / or may have a different thickness than the dielectric layer 110A.

[0031] exist Fig. 9 In the embodiment of the present invention, the metallization pattern 112B can be formed above the dielectric layer 110B using techniques similar to those described for the metallization pattern 112A. For example, an opening can be patterned in the dielectric layer 110B, the opening exposing a portion of the metallization pattern 112A. A seed layer can be formed above the dielectric layer 110B and in the opening, and a patterned photoresist can then be formed above the seed layer. A conductive material can be deposited on the exposed portion of the seed layer. The conductive material can be similar to those previously described for the metallization pattern 112A. The photoresist and the seed layer below can then be removed using a suitable process, wherein the remaining portion of the seed layer and the conductive material forms the metallization pattern 112B. In this way, the metallization pattern 112B includes a conductive line extending along the top surface of the dielectric layer 110B and a conductive via extending through the dielectric layer 110B to physically and electrically contact the metallization pattern 112A. The conductive line portion of the metallization pattern 112B may have a thickness similar to that of the metallization pattern 112A, but in some embodiments the metallization patterns 112A and 112B may have different thicknesses.

[0032] According to some embodiments, a method similar to Figures 5 to 9 Additional metallization patterns may be formed using techniques such as those described in , to form the first redistribution structure 114 . Fig.10 The first redistribution structure 114 is shown as having four dielectric layers 110A-110D and four metallization patterns 112A-112D, but the first redistribution structure 114 may have any suitable number of dielectric layers and metallization patterns. The dielectric layers of the first redistribution structure 114 may have thicknesses similar to the thickness T1 described for the dielectric layer 110A, or the dielectric layers may have different thicknesses. The metallization patterns of the first redistribution structure 114 may have thicknesses similar to the thicknesses described for the metallization patterns 112A, or the metallization patterns may have different thicknesses.

[0033] If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above may be repeated. The metallization pattern may include one or more conductive elements. The conductive elements may be formed during the formation of the metallization pattern by forming a seed layer and conductive material of the metallization pattern above the surface of the underlying dielectric layer and in the openings of the underlying dielectric layer, thereby interconnecting and electrically coupling the various conductors.

[0034] Figures 11 to 16 1 shows that a second redistribution structure 120 is formed over the first redistribution structure 114 according to some embodiments (see Fig.16 ). The second redistribution structure 120 includes a plurality of metallization patterns 118A-118C formed in a plurality of dielectric layers 116A-116C. The metallization patterns 118A-118C may include conductive lines, conductive vias, conductive pads, or other conductive components, and in some instances may be considered redistribution layers or interconnects. The second redistribution structure 120 described herein is an example, and in other embodiments may have a different number, arrangement, or configuration of dielectric layers or metallization patterns. For example, if fewer dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below may be omitted. If more dielectric layers and metallization patterns are to be formed, some of the steps and processes discussed below may be repeated.

[0035] The dielectric layers 116A-116C of the second redistribution structure 120 may be formed of materials similar to those described for the dielectric layers 110A-110D of the first redistribution structure 114. For example, in some embodiments, the dielectric layers 116A-116C are formed of a polymer, which may be a photosensitive material that can be patterned using a photolithography mask, such as PBO, polyimide, BCB, etc. In other embodiments, the dielectric layers 116A-116C may be formed of a different material than the dielectric layers 110A-110C of the first redistribution structure 114. The dielectric layers 116A-116C may be formed by any acceptable deposition process, such as spin coating, CVD, lamination, etc., or a combination thereof. In some embodiments, each dielectric layer 116A-116C may be formed to have a thickness T2 in the range of about 5 μm to about 10 μm, but other thicknesses are also possible. The dielectric layers 116A-116C may have similar thicknesses or different thicknesses. In some embodiments, each dielectric layer of the second redistribution structure 120 has a thickness (eg, thickness T2 ) less than a thickness (eg, thickness T1 ) of each dielectric layer of the first redistribution structure 114 .

[0036] exist Fig.11 In some embodiments, a dielectric layer 116A is deposited over the first redistribution structure 114. For example, Fig.11The dielectric layer 116A in is deposited over the dielectric layer 110D and the metallization pattern 112D, which are the topmost dielectric layer and the topmost metallization layer of the first redistribution structure 114. As previously described, the dielectric layer 116A may have a thickness T2 that is less than the thickness of the underlying dielectric layer 110D.

[0037] exist Fig.12 , patterning dielectric layer 116A to form openings 117 that expose portions of metallization pattern 112D. Dielectric layer 116A may be patterned using an acceptable photolithography process. For example, in an embodiment where dielectric layer 116A is a photosensitive material, dielectric layer 116A may be exposed to light using a photolithography mask. Dielectric layer 116A may then be developed after exposure to form openings 117. In other embodiments, a photoresist may be formed and patterned over dielectric layer 116A, and dielectric layer 116A may then be etched using the patterned photoresist as an etching mask. In some embodiments, opening 117 may have a width in a range of about 5 μm to about 10 μm, but other widths are possible. In some embodiments, opening 117 has a smaller width than opening 111 and / or a smaller pitch than opening 111 (see FIG. 2 ). Figure 6 ).

[0038] exist Fig.13 In the embodiment of the present invention, a metallization pattern 118A is formed on the dielectric layer 116A. The metallization pattern 118A includes a conductive wire extending along the top surface of the dielectric layer 116A and an opening 117 extending through the dielectric layer 116A to physically and electrically contact the conductive via of the metallization pattern 112D. The metallization pattern 118A can be formed using techniques similar to those previously described for forming the metallization pattern 112A. For example, a seed layer can first be formed above the dielectric layer 116A and in the opening 117. In some embodiments, the seed layer is similar to the seed layer 104 or other seed layers described herein. For example, the seed layer can include a metal layer formed using PVD, etc. Then a photoresist (not shown) is formed and patterned on the seed layer, wherein the pattern of the photoresist corresponds to the metallization pattern 118A. The patterning forms an opening through the photoresist to expose the seed layer. A conductive material is formed in the opening of the photoresist and on the exposed portion of the seed layer. The conductive material can be formed by plating, such as electroplating or chemical plating. The conductive material may include metals such as copper, titanium, tungsten, aluminum, etc. Then, the photoresist and the portion of the seed layer on which the conductive material is not formed are removed using, for example, an ashing process. Once the photoresist is removed, the exposed portion of the seed layer is removed using, for example, an acceptable wet etching process or a dry etching process. The remaining portion of the seed layer and the conductive material forms the metallization pattern 118A.

[0039] In some embodiments, the conductive line portion of the metallization pattern 118A has a thickness in the range of about 1 μm to about 10 μm above the dielectric layer 116A, but other thicknesses are possible. The other metallization patterns 118B-118C of the second redistribution structure 120 can have conductive line thicknesses similar to or different from the conductive line thickness of the metallization pattern 118A. In some embodiments, each metallization pattern of the second redistribution structure 120 has a thickness less than the thickness of each metallization pattern of the first redistribution structure 114. In some embodiments, each metallization pattern of the second redistribution structure 120 has a pitch less than the pitch of each metallization pattern of the first redistribution structure 114.

[0040] If more dielectric layers and metallization patterns are to be formed, the steps and processes discussed above can be repeated. Figure 14 to Figure 15 , additional metallization patterns 118B-118C may be formed using techniques similar to those used for metallization pattern 118A. Fig.14 , a dielectric layer 116B is formed over the dielectric layer 116A and the metallization pattern 118A. The metallization pattern 118B is formed to include a conductive line portion on the dielectric layer 116B and a conductive via portion extending through the dielectric layer 116B to physically and electrically contact the metallization pattern 118A. For example, the metallization pattern 118B may be formed by forming a seed layer and a conductive material of the metallization pattern 118B above the surface of the underlying dielectric layer 116B and in the opening of the underlying dielectric layer 116B, thereby interconnecting and electrically coupling the various conductive lines. In some embodiments, the thickness and material of the dielectric layer 116B and the metallization pattern 118B may be similar to those described for the dielectric layer 116A and the metallization pattern 118A.

[0041] exist Fig.15 In the embodiment of the present invention, a dielectric layer 116C is formed over the dielectric layer 116B and the metallization pattern 118B. The metallization pattern 118C is formed to include a conductive via portion extending through the dielectric layer 116C to physically and electrically contact the metallization pattern 118B. In some embodiments, the metallization pattern 118C is also formed to include a wire portion on the dielectric layer 116C. The metallization pattern 118C can be formed by forming a seed layer and a conductive material of the metallization pattern 118C in an opening of the dielectric layer 116B below, thereby interconnecting and electrically coupling the various wires. In some embodiments, the thickness and material of the dielectric layer 116C and the metallization pattern 118C can be similar to those described for the dielectric layer 116A and the metallization pattern 118A.

[0042] As described above, in some embodiments, the dielectric layer of the first redistribution structure 114 is thicker than the dielectric layer of the second redistribution structure 120. In addition, the metallization pattern of the first redistribution structure 114 has conductive features (e.g., conductive lines and conductive vias) that are larger than (e.g., thicker or wider than) the conductive features of the metallization pattern of the second redistribution structure 120. In some embodiments, the total thickness T3 of the first redistribution structure 114 may be greater than the total thickness T4 of the second redistribution structure 120. In other embodiments, the first redistribution structure 114 may have a total thickness T3 that is less than or about the same as the total thickness T4 of the second redistribution structure 120. In some embodiments, the total thickness T3 of the first redistribution structure 114 is in a range from about 100 μm to about 350 μm, and the total thickness T4 of the second redistribution structure 120 is in a range from about 15 μm to about 70 μm, but other thicknesses are possible. As described herein, forming a "thin" second redistribution structure 120 electrically coupled to the "thick" first redistribution structure 114 over the "thick" first redistribution structure 114 can allow for efficient fan-out routing within the package. In some examples, the first redistribution structure 114 and the second redistribution structure 120 together can be considered a "redistribution substrate" or "wiring structure" formed on the first composite layer 106.

[0043] Forming the redistribution structure 114 / 120 on the first composite layer 106 as described herein can allow for improved yields, improved process throughput, and / or thinner packages. For example, using photolithography techniques to form the redistribution structure 114 / 120 to pattern a dielectric layer formed from a polymer can produce better yields and faster processing than using other techniques (such as using laser drilling on layers of Ajinomoto accumulation film (ABF), organic cores, etc.). In addition, in some instances, the redistribution structure 114 / 120 using a polymer layer can be formed to have fewer and / or thinner layers than a redistribution structure formed from layers of ABF or other composite materials. In this way, the overall thickness of the package can be reduced. In addition, by forming the redistribution structure 114 / 120 on the first composite layer 106, the package can have improved structural stability, improved thermal properties, and improved operation.

[0044] exist Fig.16 In some embodiments, a conductive connector 122 is formed over the second redistribution structure 120. The conductive connector 122 may be physically and electrically connected to a topmost metallization pattern of the second redistribution structure 120, such as Fig.16. The metallization pattern 118C of the second redistribution structure 120 shown in . The conductive connector 122 may include a ball grid array (BGA) connector, a solder ball, a metal column, a conductive pad, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by chemical nickel plating-chemical palladium plating-immersion gold technology (ENEPIG), an under-bump metal (UBM), etc. The conductive connector 122 may include a conductive material, such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, etc. or a combination thereof. In some embodiments, the conductive connector 122 is formed by initially forming a solder layer by evaporation, electroplating, printing, solder transfer, ball placement, etc. Once the solder layer has been formed on the structure, reflow can be implemented to shape the material into a desired bump shape. In another embodiment, the conductive connector 122 includes a metal column (such as a copper column) formed by sputtering, printing, electroplating, chemical plating, CVD, etc. The metal column can be solder-free and have a substantially vertical sidewall. In some embodiments, a metal capping layer is formed on top of the metal pillar. The metal capping layer may include nickel, tin, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc. or a combination thereof, and may be formed by a plating process.

[0045] exist Fig.17 In some embodiments, one or more integrated circuit dies 126 are attached to the second redistribution structure 120. The integrated circuit dies 126 may include logic dies (e.g., central processing unit (CPU), graphics processing unit (GPU), system on chip (SoC), application processor (AP), microcontroller, application specific integrated circuit (ASIC) die, etc.), memory dies (e.g., dynamic random access memory (DRAM) die, static random access memory (SRAM) die, hybrid memory cube (HMC) module, high bandwidth memory (HBM) module, etc.), power management dies (e.g., power management integrated circuit (PMIC) die), radio frequency (RF) die, sensor die, microelectromechanical system (MEMS) die, signal processing die (e.g., digital signal processing (DSP) die), front-end die (e.g., analog front end (AFE) die), etc. or a combination thereof. The plurality of integrated circuit dies 126 may include dies of similar types and / or dies of different types. The integrated circuit dies 126 may have different sizes (eg, different heights and / or surface areas), or may have the same sizes (eg, the same height and / or surface areas).

[0046] In some embodiments, the integrated circuit die 126 is attached to the second redistribution structure 120 using solder regions, which can be formed on the conductive connectors 122 and / or on the conductive connectors of the integrated circuit die 126. The integrated circuit die 126 can be placed on the second redistribution structure 120 using, for example, a pick and place tool. After the integrated circuit die 126 is placed on the second redistribution structure 120, the solder regions are in physical contact with the corresponding conductive connectors 122 of the second redistribution structure 120 and the corresponding conductive connectors of the integrated circuit die 126. After the integrated circuit die 126 is placed on the second redistribution structure 120, a reflow process is performed on the solder regions to melt the solder regions and merge them into the solder joints 124. The solder joints 124 electrically and mechanically couple the integrated circuit die 126 to the second redistribution structure 120. In some embodiments, an optional bottom filler (not shown) can be formed between the integrated circuit die 126 and the second redistribution structure 120. As shown in FIG. Fig.17 As shown in , in some embodiments, the integrated circuit die 126 can be directly attached to the second redistribution structure 120 without an interposer or the like. In this way, in some instances, the redistribution structure 114 / 120 can replace the interposer. In other embodiments, the interposer is disposed between the integrated circuit die 126 and the second redistribution structure 120.

[0047] Still reference Fig.17 , according to some embodiments, a support ring 128 is attached to the second redistribution structure 120. For example, the support ring 128 may be attached to provide mechanical support to the package and reduce warpage. In some embodiments, the support ring 128 may surround the integrated circuit die 126. The support ring 128 may be formed of a rigid material, such as a metal, a semiconductor, a ceramic, or another material. In some embodiments, the support ring 128 may be attached to the topmost dielectric layer (e.g., dielectric layer 116C) of the second redistribution structure 120 using an adhesive film or the like (not shown). In some embodiments, the support ring 128 may have a thickness TR in the range of about 500 μm to about 700 μm, but other thicknesses are also possible. The thickness TR of the support ring 128 may be greater than the thickness of the integrated circuit die 126, about the same as the thickness of the integrated circuit die 126, or less than the thickness of the integrated circuit die 126.

[0048] exist Fig.18In some embodiments, an encapsulant 130 is formed over the structure and the edge region 101B is optionally trimmed. The encapsulant 130 can be formed over and around the integrated circuit die 126 and the support ring 128, and in some instances can be formed under the integrated circuit die 126. In this way, after formation, the encapsulant 130 seals the integrated circuit die 126 and the support ring 128. The encapsulant 130 can be a molding compound, an epoxy resin, or the like. The encapsulant 130 can be applied by compression molding, transfer molding, or the like, and can be formed over the carrier substrate 102, burying or covering the integrated circuit die 126 and the support ring 128. The encapsulant 130 can be applied in a liquid or semi-liquid form and then subsequently cured.

[0049] In some embodiments, a planarization process may be performed after forming the encapsulant 130. The planarization process may include a chemical mechanical polishing (CMP) process, a grinding process, etc. The planarization process may remove the encapsulant 130 from above the integrated circuit die 126 and the support ring 128. In some embodiments, the planarization process may expose one or more of the support ring 128 and / or the integrated circuit die 126. In other embodiments, the support ring 128 and / or the integrated circuit die 126 may remain covered by the encapsulant 130, such as Fig.18 After the planarization process is performed, the top surfaces of one or more of the encapsulant 130 , the support ring 128 , and / or the integrated circuit die 126 may be flush.

[0050] In addition, Fig.18 In some embodiments, the edge region 101B may be optionally trimmed. The trimming process may partially or completely remove the material within the edge region 101B. The trimming process may include a mechanical sawing process, a laser sawing process, an etching process, etc., or a combination thereof. In some embodiments, after the trimming process is performed, the sidewall surfaces of the encapsulant 130, the first redistribution structure 114, the second redistribution structure 120, and / or the first composite layer 106 may be coplanar or coterminal.

[0051] exist Fig.19 In some embodiments, Fig.18 The package assembly is peeled from carrier substrate 102, turned upside down, and bonded to another carrier substrate 132. In some examples, carrier substrate 132 can be similar to carrier substrate 102. The package assembly can be attached to carrier substrate 132 using an adhesive, a release layer, etc. (not shown).

[0052] exist Fig. 20In some embodiments, a metal layer 105 is formed on the seed layer 104. The metal layer 105 can be formed, for example, using a plating process (e.g., electroplating, chemical plating, etc.) to deposit a metal material on the seed layer 104. The deposited metal material and the seed layer 104 together form a metal layer 105, which physically contacts the first composite layer 106 and the conductive via portion of the metallization pattern 108. The metal layer 105 may include one or more metals, such as copper, titanium, tungsten, aluminum, etc. In some embodiments, the metal layer 105 has a thickness in the range of about 20 μm to about 40 μm, but other thicknesses are also possible. In some embodiments, the thickness of the metal layer 105 is greater than the thickness of the conductive line portion (e.g., metallization layer) of the first redistribution structure 114 and / or the second redistribution structure 120.

[0053] exist Fig.21 In some embodiments, the metal layer 105 is patterned to form a conductive element 134 on the composite layer 106. The conductive element 134 may include, for example, a conductive wire, a conductive pad, etc. The conductive element 134 may be physically and electrically in contact with the conductive via portion of the metallization pattern 108. In some embodiments, the conductive element 134 is thicker than the conductive wire portion of the first redistribution structure 114 and / or the second redistribution structure 120. Forming a relatively thick conductive element 134 in this manner may allow for efficient fan-out routing within the package. In some instances, the conductive element 134 may be considered a metallization pattern.

[0054] exist Fig. 22 In some embodiments, a second composite layer 136 is formed over the conductive element 134 and the first composite layer 106. The second composite layer 136 may be formed of one or more composite material layers, which may be similar to those previously described for the first composite layer 106. For example, the second composite layer 136 may be formed of a prepreg or the like. In some embodiments, the second composite layer 136 may be a different material from the first composite layer 106, such as a prepreg having different properties. Other materials or combinations of materials are also possible. In some instances, forming an insulating layer from a composite material such as a prepreg may allow the package to be formed with improved structural strength and a smaller overall thickness. In some embodiments, the material of the second composite layer 136 may be selected to have a CTE similar to the CTE of other components in the package (such as the integrated circuit die 126, the first composite layer 106, the support ring 128, etc.). In some instances, the materials of the first composite layer 106 and the second composite layer 136 may be selected to have a combined CTE that is appropriately matched to the CTE of the support ring 128. In this way, the package may have improved thermal performance. In some examples, first composite layer 106 and second composite layer 136 together may be considered a “composite layer stack” or a “composite interconnect structure”.

[0055] In some embodiments, the second composite layer 136 may have a thickness TP2 in the range of about 100 μm to about 300 μm, but other thicknesses are possible. The second composite layer 136 may have a thickness TP2 that is greater than the thickness TP1 of the first composite layer 106, about the same as the thickness TP1 of the first composite layer 106, or less than the thickness TP1 of the first composite layer 106. In some embodiments, the first composite layer 106 and the second composite layer 136 may have a combined thickness TP in the range of about 500 μm to about 700 μm. In some embodiments, the total thickness TP of the composite layer 106 / 136 may be greater than the thickness T4 of the second redistribution structure 120. In some embodiments, the total thickness TP of the composite layer 106 / 136 may be about the same as the thickness TR of the support ring 128. In this way, the structural and thermal performance of the package may be improved. Other thicknesses TP1, TP2, or TP or their relative thicknesses are also possible.

[0056] exist Fig.23 In some embodiments, an opening 135 is formed in the second composite layer 136. The opening 135 may extend through the second composite layer 136 to expose a portion of the conductive element 134. The opening 135 may be formed using a similar method to that used for the opening 107 (see Figure 3 ) are formed by techniques such as those described in the prior art. For example, the openings 135 can be formed using a mechanical drilling process, a laser drilling process, a photolithography masking and etching process, or another suitable process. In some embodiments, each opening 135 can have a width in the range of about 100 μm to about 300 μm, but other widths are also possible.

[0057] exist Fig.24 In some embodiments, a conductive material is deposited to form a metallization pattern 138. The metallization pattern 138 includes conductive via portions extending through the second composite layer 136 and physically and electrically contacting the underlying conductive element 134. Fig.24 As shown in , the metallization pattern 138 may also include a conductive element portion extending along the top surface of the second composite layer 136, such as a conductive line, a conductive pad, etc. In some embodiments, the conductive element portion of the metallization pattern 138 located on the top surface of the second composite layer 136 may have a thickness in the range of about 100 μm to about 300 μm, but other thicknesses are also possible. In some examples, the conductive element 134, the metallization pattern 138, and the second composite layer 136 may be considered an "interconnect layer" together.

[0058] The metallization pattern 138 can be formed using techniques similar to those described for the metallization pattern 108. For example, a seed layer can be formed over the second composite layer 136 and in the opening 135, and then a patterned photoresist can be formed over the seed layer. A conductive material can be deposited on the exposed portion of the seed layer. The conductive material can be similar to those previously described for the metallization pattern 108. The photoresist and the underlying seed layer can then be removed using a suitable process, with the remaining portions of the seed layer and the conductive material forming the metallization pattern 138. Other formation techniques are also possible.

[0059] exist Fig.25 In some embodiments, a solder resist layer 140 is formed over the second composite layer 136 and the metallization pattern 138. The solder resist layer 140 may include a suitable insulating material, such as a dielectric material, a polymer material, etc., and may be formed using any suitable deposition technique. In some embodiments, the solder resist layer 140 is patterned to form one or more openings in the solder resist layer 140 that expose portions of the metallization pattern 138. The patterning process may include suitable photolithography and etching techniques. The etching technique may include a dry etching process or a wet etching process, and may be anisotropic.

[0060] exist Fig.26 In some embodiments, a conductive connector 142 is formed. The conductive connector 142 extends through the opening in the solder resist layer 140 to physically and electrically contact the exposed portion of the metallization pattern 138. The conductive connector 142 can be a ball grid array (BGA) connector, a solder ball, a metal pillar, a controlled collapse chip connection (C4) bump, a microbump, a bump formed by electroless nickel-electroless palladium-immersion gold technology (ENEPIG), etc. In some examples, the conductive connector 142 can be formed using the same method as described above. Fig.17 The conductive connector 122 is formed using similar materials and methods as described above.

[0061] exist Fig. 27 In some embodiments, a singulation process is performed to separate the structure into individual integrated circuit packages 100. The singulation process may include mechanical sawing, laser sawing, etching, cutting, combinations thereof, and the like. In some instances, the techniques described herein allow the integrated circuit packages 100 to be formed using only one singulation process. In other words, all sidewall layers of the integrated circuit package 100 are sawed through in the same process, thereby avoiding the need to perform multiple sawing processes during the formation of the integrated circuit package 100. In this way, the package can be formed using fewer processing steps, which can reduce costs and improve production throughput.

[0062] Fig.28FIG. 2 shows a singulated integrated circuit package 100 according to some embodiments. Due to the singulation process as described above, the integrated circuit package 100 has flat sidewalls. Fig.28 As shown in , sidewall surfaces of the encapsulant 130 , the first composite layer 106 , the second composite layer 136 , the first redistribution structure 114 , the second redistribution structure 120 , and / or the solder resist layer 140 may be coplanar (eg, coterminal).

[0063] In other embodiments, the composite interconnect structure of the integrated circuit package 100 may include another number of composite layers and associated metallization patterns. As an example, Fig.29 Shows something like Fig.28 The integrated circuit package 100 of the integrated circuit package 100 is different in that a third composite layer 146 is formed on the second composite layer 136. In addition, a metallization pattern 148 is formed on the third composite layer 146. The metallization pattern 148 may include a conductive via portion extending through the third composite layer 146 and physically and electrically contacting the underlying metallization layer 138. Fig.29 As shown in , the metallization pattern 148 may also include conductive element portions extending along the top surface of the third composite layer 146, such as wires, conductive pads, etc. The third composite layer 146 can be formed using materials and techniques similar to those previously described for the first composite layer 106 and / or the second composite layer 136. The composite layers 106 / 136 / 146 can be formed of similar materials or different materials. The metallization pattern 148 can be formed using materials and techniques similar to those previously described for the metallization pattern 108 and / or the metallization pattern 138. In some examples, the metallization pattern 148 and the third composite layer 146 can be considered as an "interconnect layer" together. The process steps described for the composite layers 136 / 146 and the metallization patterns 138 / 148 can be repeated to form any desired number of composite layers and metallization patterns in the integrated circuit package 100. The conductive connector 142 can be formed on the metallization layer 148. In some examples, forming additional composite layers and metallization patterns can provide improved structural stability, improved thermal performance, and additional electrical wiring.

[0064] Other components and processes may also be included. For example, a test structure may be included to help perform verification testing on a 3D package or 3DIC device. The test structure may include, for example, a test pad formed in a redistribution layer or on a substrate, which allows testing of the 3D package or 3DIC, using probes and / or probe cards, etc. Verification testing may be performed on intermediate structures as well as final structures. In addition, the structures and methods disclosed herein may be used in conjunction with a test method that incorporates intermediate verification of known good dies to increase yield and reduce costs.

[0065] Embodiments can achieve advantages. Using a polymer layer instead of, for example, an ABF layer to form wiring above a composite layer can improve yield, increase throughput, increase wiring density, and reduce package thickness. For example, using photolithography instead of laser drilling can avoid drilling particles that reduce yield, and multiple openings can be formed simultaneously rather than sequentially, which can increase process throughput. In addition, using a polymer layer instead of an ABF layer, etc. can reduce the overall number of layers used for wiring, which can reduce thickness, processing time, and cost. Forming a second redistribution structure having a thinner dielectric layer and a smaller line width above a first redistribution structure having a thicker dielectric layer and a larger line width can provide effective fan-out wiring for the package. The technology described herein also allows for the implementation of a single sawing or segmentation process, which can reduce processing time and cost, and improve throughput. In addition, forming multiple composite layers can improve package strength and allow better CTE matching, which can improve the thermal performance of the package.

[0066] According to an embodiment of the present disclosure, a method includes: forming a first conductive element extending through the first composite layer on a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer above the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern extending through the second polymer layer on the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming the second composite layer on the first composite layer; and forming a second conductive element extending through the second composite layer. In an embodiment, forming the first metallization pattern includes: patterning the first polymer layer using a photolithography mask to expose the first conductive element; and depositing a conductive material on the first polymer layer and on the exposed first conductive element. In an embodiment, the method includes connecting an integrated circuit die to the second metallization pattern. In an embodiment, the first composite layer includes a prepreg material layer. In an embodiment, the first polymer layer physically contacts the first composite layer. In an embodiment, the method includes: forming a third conductive element on the first composite layer and on the first conductive element before forming the second composite layer. In an embodiment, the thickness of the third conductive element is greater than the thickness of the first metallization pattern. In an embodiment, the first polymer layer and the second polymer layer are different polymers.

[0067] According to an embodiment of the present disclosure, a method includes: forming a first interconnect layer on a first carrier substrate, wherein the first interconnect layer includes a first composite material; forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure includes: depositing a first dielectric layer; patterning the first dielectric layer using a photolithography mask; and depositing a first conductive material on the first dielectric layer; forming a second redistribution structure on the first redistribution structure, wherein forming the second redistribution structure includes: depositing a second dielectric layer; patterning the second dielectric layer using a photolithography mask; and depositing a second conductive material on the second dielectric layer; and attaching an integrated circuit die to the second redistribution structure. In an embodiment, the first conductive material is deposited to a first thickness, and the second conductive material is deposited to a second thickness less than the first thickness. In an embodiment, the first dielectric layer includes at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). In an embodiment, the method includes: attaching a support ring to the second redistribution structure. In an embodiment, the method includes: forming a second interconnect layer on the first interconnect layer, wherein the second interconnect layer includes a second composite material, wherein the second interconnect layer is electrically connected to the first interconnect layer. In an embodiment, the method includes: performing a sawing process, wherein after performing the sawing process, sidewall surfaces of the first interconnect layer, the first redistribution structure, and the second redistribution structure are coplanar. In an embodiment, the method includes: before forming the first interconnect layer, depositing a seed layer on the first carrier substrate.

[0068] According to an embodiment of the present disclosure, a package includes: a first composite layer; a second composite layer located on the first composite layer; a conductive element located in the first composite layer and the second composite layer; a first redistribution structure located on the second composite layer, wherein the first redistribution structure includes a first polymer layer and a first wire; a second redistribution structure located on the first redistribution structure, wherein the second redistribution structure includes a second polymer layer and a second wire, wherein the second polymer layer is thinner than the first polymer layer, wherein the second wire is thinner than the first wire; and a semiconductor device attached to the second redistribution structure. In an embodiment, the package includes: an encapsulant located above the semiconductor device, wherein the encapsulant and the second redistribution structure have coplanar sidewalls. In an embodiment, the first composite layer, the second composite layer, the first redistribution structure, and the second redistribution structure have coplanar sidewalls. In an embodiment, the thickness of the first redistribution structure is greater than the thickness of the second redistribution structure. In an embodiment, the combined thickness of the first composite layer and the second composite layer is greater than the thickness of the second redistribution structure.

[0069] Some embodiments of the present application provide a method for forming a package, comprising: forming a plurality of first conductive elements extending through the first composite layer on a first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer above the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern extending through the second polymer layer on the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and forming a plurality of second conductive elements extending through the second composite layer. In some embodiments, forming the first metallization pattern comprises: patterning the first polymer layer using a photolithography mask to expose the first conductive elements; and depositing a conductive material on the first polymer layer and on the exposed first conductive elements. In some embodiments, the method further comprises: connecting a plurality of integrated circuit dies to the second metallization pattern. In some embodiments, the first composite layer comprises a prepreg material layer. In some embodiments, the first polymer layer physically contacts the first composite layer. In some embodiments, the method further comprises: forming a plurality of third conductive elements on the first composite layer and on the plurality of first conductive elements before forming the second composite layer. In some embodiments, the thickness of the plurality of third conductive elements is greater than the thickness of the first metallization pattern. In some embodiments, the first polymer layer and the second polymer layer include different polymers.

[0070] Some other embodiments of the present application provide a method of forming a package, comprising: forming a first interconnect layer on a first carrier substrate, wherein the first interconnect layer comprises a first composite material; forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure comprises: depositing a first dielectric layer; patterning the first dielectric layer using a photolithography mask; and depositing a first conductive material on the first dielectric layer; forming a second redistribution structure on the first redistribution structure, wherein forming the second redistribution structure comprises: depositing a second dielectric layer; patterning the second dielectric layer using a photolithography mask; and depositing a second conductive material on the second dielectric layer; and attaching an integrated circuit die to the second redistribution structure. In some embodiments, the first conductive material is deposited to a first thickness, and the second conductive material is deposited to a second thickness less than the first thickness. In some embodiments, the first dielectric layer comprises at least one of polybenzoxazole (PBO), polyimide, or benzocyclobutene (BCB). In some embodiments, the method further comprises: attaching a support ring to the second redistribution structure. In some embodiments, the method further comprises: forming a second interconnect layer on the first interconnect layer, wherein the second interconnect layer comprises a second composite material, wherein the second interconnect layer is electrically connected to the first interconnect layer. In some embodiments, the method further comprises: performing a sawing process, wherein after performing the sawing process, the sidewall surfaces of the first interconnect layer, the first redistribution structure, and the second redistribution structure are coplanar. In some embodiments, the method further comprises: depositing a seed layer on the first carrier substrate before forming the first interconnect layer.

[0071] Some other embodiments of the present application provide a package, comprising: a first composite layer; a second composite layer located on the first composite layer; a plurality of conductive elements located in the first composite layer and the second composite layer; a first redistribution structure located on the second composite layer, wherein the first redistribution structure comprises a plurality of first polymer layers and a plurality of first wires; a second redistribution structure located on the first redistribution structure, wherein the second redistribution structure comprises a plurality of second polymer layers and a plurality of second wires, wherein the second polymer layer is thinner than the first polymer layer, wherein the second wire is thinner than the first wire; and a semiconductor device attached to the second redistribution structure. In some embodiments, the package further comprises: an encapsulant located above the semiconductor device, wherein the encapsulant and the second redistribution structure have coplanar sidewalls. In some embodiments, the first composite layer, the second composite layer, the first redistribution structure, and the second redistribution structure have coplanar sidewalls. In some embodiments, the thickness of the first redistribution structure is greater than the thickness of the second redistribution structure. In some embodiments, the combined thickness of the first composite layer and the second composite layer is greater than the thickness of the second redistribution structure.

[0072] The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the embodiments of the present disclosure. Those skilled in the art should understand that they can easily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purpose and / or achieving the same advantages as the embodiments introduced herein. Those skilled in the art should also appreciate that such equivalent constructions do not deviate from the spirit and scope of the embodiments of the present disclosure, and that they can make various changes, substitutions and modifications herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of forming a package, comprising: forming a plurality of first conductive elements on a first composite layer extending through the first composite layer; forming a first polymer layer on the first composite layer; forming a first metallization pattern extending through the first polymer layer; forming a second polymer layer over the first polymer layer, wherein the second polymer layer is thinner than the first polymer layer; forming a second metallization pattern on the second polymer layer extending through the second polymer layer, wherein the second metallization pattern is thinner than the first metallization pattern; forming a second composite layer on the first composite layer; and A plurality of second conductive elements are formed extending through the second composite layer.

2. The method according to claim 1, wherein: Forming the first metallization pattern includes: patterning the first polymer layer using a photolithographic mask to expose first conductive elements; and A conductive material is deposited over the first polymer layer and over the exposed first conductive elements.

3. The method according to claim 1, further comprising: A plurality of integrated circuit dies are coupled to the second metallization pattern.

4. The method according to claim 1, wherein: The first composite layer includes a prepreg material layer.

5. The method according to claim 1, wherein: The first polymer layer physically contacts the first composite layer.

6. The method according to claim 1, further comprising: Before forming the second composite layer, a plurality of third conductive elements are formed on the first composite layer and on the plurality of first conductive elements.

7. The method according to claim 6, wherein: The thickness of the third conductive elements is greater than the thickness of the first metallization pattern.

8. The method according to claim 1, wherein: The first polymer layer and the second polymer layer include different polymers.

9. A method of forming a package, comprising: forming a first interconnect layer on a first carrier substrate, wherein the first interconnect layer comprises a first composite material; forming a first redistribution structure on the first interconnect layer, wherein forming the first redistribution structure comprises: depositing a first dielectric layer; patterning the first dielectric layer using a photolithography mask; and depositing a first conductive material on the first dielectric layer; forming a second redistribution structure on the first redistribution structure, wherein forming the second redistribution structure comprises: depositing a second dielectric layer; patterning the second dielectric layer using a photolithography mask; and depositing a second conductive material on the second dielectric layer; and An integrated circuit die is attached to the second redistribution structure.

10. A package comprising: first composite layer; a second composite layer, located on the first composite layer; a plurality of conductive elements disposed within the first composite layer and the second composite layer; A first redistribution structure is located on the second composite layer, wherein the first redistribution structure includes a plurality of first polymer layers and a plurality of first conductive lines; a second redistribution structure located on the first redistribution structure, wherein the second redistribution structure comprises a plurality of second polymer layers and a plurality of second conductive lines, wherein the second polymer layers are thinner than the first polymer layers, and wherein the second conductive lines are thinner than the first conductive lines; and A semiconductor device is attached to the second redistribution structure.

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