A performance evaluation method and device for a field effect transistor containing black phosphorus

Abstract

The present invention discloses a method and device for evaluating the performance of a field-effect transistor containing black phosphorus. The method specifically includes the following steps: preparing a field-effect transistor containing black phosphorus; giving a transmission model of the field-effect transistor through electrical characteristic measurement under a first controllable environmental variable; obtaining bias temperature instability data and analyzing the failure behavior; combining the characterization of channel defects and surface potential to optimize the transmission model of the field-effect transistor and the analysis of the failure behavior; and realizing the performance evaluation of the field-effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior. The present invention combines electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential, and gives an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of the field-effect transistor device structure, and the optimization of the manufacturing process in the field-effect transistor containing black phosphorus.

Description

Technical Field

[0001] The present invention belongs to the technical field of field effect transistors, and particularly relates to a method and device for evaluating the performance of a field effect transistor containing black phosphorus. Background Art

[0002] With the continuous miniaturization of electronic devices, since graphene was first exfoliated, two-dimensional materials have attracted extensive research and applications due to their atomic-scale ultra-thin sheet-like nanostructures. Although graphene has extremely high mobility, its characteristic of having no bandgap makes graphene unsuitable for the switching of transistors. Transition-Metal Dichalcogenides (TMDs) in two-dimensional materials, especially MoS2, are research hotspots for channel materials of field-effect transistors (FETs). The ultra-thin FETs composed of them effectively prevent the short-channel effect. However, the carrier mobilities of most reported TMDs transistors are much lower than those of graphene and traditional semiconductors.

[0003] Existing research has shown that black phosphorus has high mobility (close to 1000 cm 2 / Vs), a high current on-off ratio, and an adjustable bandgap width. Black Phosphorus (BP), as a new type of two-dimensional material, is formed by stacking two-dimensional atomic layers through van der Waals (vdW) interactions. Using black phosphorus as the channel material of a field effect transistor meets the requirements of low-power integrated complementary metal oxide semiconductor (CMOS) and thin film transistor (TFT), and has broad prospects in the application of p-type field effect transistors (p-FETs).

[0004] However, black phosphorus lacks stability in an air environment. When exfoliated black phosphorus is exposed to air and water, it will be oxidized, resulting in a rapid degradation of its electrical and optical properties. On the one hand, it is very challenging to fabricate black phosphorus-containing field effect transistors that simultaneously have environmental stability and high performance (such as the most important performance parameters: high mobility and high current on-off ratio, etc.).

[0005] For example, Patent CN107644906A discloses a black phosphorus field effect transistor and a manufacturing method thereof, including: providing a semiconductor substrate; forming a mask layer on the semiconductor substrate, the mask layer having an opening pattern; forming a black phosphorus thin sheet in the opening; performing a heat treatment to convert the black phosphorus thin sheet into a red phosphorus layer covering the bottom of the opening; converting the red phosphorus layer into a black phosphorus layer covering the bottom of the opening; and removing the mask layer. According to the manufacturing method of the black phosphorus field effect transistor proposed by this solution, the performance of the black phosphorus field effect transistor can be improved.

[0006] On the other hand, the characterization of the basic device characteristics of black phosphorus field effect transistors is equally crucial. However, the current device characterization only targets one or a few parameters and lacks research on the overall reliability of the device.

[0007] The reliability of black phosphorus field effect transistors is of great significance for device design, optimization of process manufacturing, and evaluation of actual service performance. Studying the reliability of black phosphorus field effect transistors is a requirement for the development of ultra-thin two-dimensional material FET technology and has important scientific significance.

[0008] Therefore, in the research field of black phosphorus field effect transistors, there is an urgent need to carry out the design of a scheme for evaluating the device reliability to achieve guidance for the selection of heterojunction materials in field effect transistors containing black phosphorus, the design of the device structure of field effect transistors, and the optimization of the manufacturing process. Summary of the Invention

[0009] Aiming at the defects existing in the above-mentioned prior art, the present invention provides a performance evaluation method and device for a field effect transistor containing black phosphorus. The method specifically includes the following steps: preparing a field effect transistor containing black phosphorus; giving a transmission model of the field effect transistor through electrical characteristic measurement under a first controllable environmental variable; obtaining bias temperature instability data and analyzing the failure behavior; combining the characterization of channel defects and surface potential to optimize the transmission model of the field effect transistor and the analysis of the failure behavior; and realizing the performance evaluation of the field effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior. The present invention combines electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential to give an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials in field effect transistors containing black phosphorus, the design of the device structure of field effect transistors, and the optimization of the manufacturing process.

[0010] In a first aspect, the present invention provides a performance evaluation method for a field effect transistor containing black phosphorus, specifically including the following steps:

[0011] Preparing a field effect transistor containing black phosphorus;

[0012] By measuring the electrical characteristics in the first controllable environmental variable, a transfer model of the field effect transistor is given;

[0013] Obtain bias temperature instability data and analyze failure behavior;

[0014] Combined with the characterization of channel defects and surface potential, optimization of field-effect transistor transfer models and analysis of failure behavior;

[0015] Combining the optimized transfer model with the analysis of failure behavior, the performance evaluation of field-effect transistors containing black phosphorus is achieved.

[0016] Furthermore, the field effect transistor containing black phosphorus uses a material containing black phosphorus as a channel of the field effect transistor, and the material containing black phosphorus includes pure black phosphorus and a two-dimensional material-black phosphorus in a stacked heterojunction form;

[0017] The preparation of a field effect transistor containing black phosphorus specifically includes the following steps:

[0018] Growing a 10-300nm SiO2 dielectric layer on a P-type silicon wafer substrate;

[0019] Transferring the prepared black phosphorus layer or the two-dimensional material-black phosphorus stacked heterojunction layer to the surface of the SiO2 dielectric layer to obtain an intermediate component, wherein the black phosphorus layer has a thickness of 0.5-5 nm, the two-dimensional material-black phosphorus stacked heterojunction layer has a thickness of 0.5-5 nm, and the two-dimensional material is one of graphene, BN and InSe;

[0020] Annealing the intermediate component, wherein the annealing is performed in an inert gas at a temperature of 250-300° C., an annealing time of 30-60 min, and a heating and cooling rate of 5-10° C. / min;

[0021] Use a mask to process the middle to obtain a channel with a length of 5-50μm and a width of 5-50μm;

[0022] By magnetron sputtering or evaporation, electrodes are deposited at both ends of the channel as source and drain to prepare a field-effect transistor containing black phosphorus.

[0023] Furthermore, by measuring the electrical characteristics of the first controllable environmental variable, a transmission model of the field effect transistor is provided, which specifically includes the following steps:

[0024] Determining parameters and parameter value ranges of a first controllable environmental variable;

[0025] Through transfer characteristics and output characteristics tests, electrical characteristics data under different controllable environmental variables are given;

[0026] Give the transfer model of the field effect transistor.

[0027] Further, the parameters of the first controllable environmental variable include the first environmental atmosphere, the voltage between the source and the drain, the gate voltage, and the test time. The first environmental atmosphere includes humidity, oxygen concentration, and temperature;

[0028] The electrical characteristic data includes the average mobility of the field effect transistor.

[0029] Further, the transmission model of the field effect transistor is specifically expressed as:

[0030]

[0031] where μ lin is the average mobility in the linear state, μ sat is the average mobility in the saturation state, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in the saturation state.

[0032] Further, to obtain the bias temperature instability data and analyze the failure behavior, the specific steps are as follows:

[0033] Determine the parameters and the numerical range of the parameters of the second controllable environmental variable;

[0034] Conduct the bias temperature instability test, and give the bias temperature instability data under different controllable environmental variables, and analyze the failure behavior of the field effect transistor. Among them, the bias temperature instability test includes the positive bias temperature instability test and the negative bias temperature instability test.

[0035] Further, the parameters of the second controllable environmental variable include: the second environmental atmosphere, the source-drain voltage, and the bottom gate bias voltage. The bottom gate bias voltage includes the bottom gate positive bias voltage and the bottom gate negative bias voltage. The second environmental atmosphere includes the aging temperature and the aging time;

[0036] The bias temperature instability data includes the threshold voltage and the subthreshold swing.

[0037] Further, to conduct the bias temperature instability test, the specific steps are as follows:

[0038] Set the aging temperature, the relaxation time, and the aging time. The relaxation time is the interval time between the aging times of applying adjacent bottom gate bias voltages. The ratio of the aging time to the relaxation time is 1:(0.1 - 10);

[0039] Apply a preset equal bottom gate bias. After multiple aging times, the threshold voltage and subthreshold swing under the bias are given.

[0040] Apply a preset equal increment bias or equal decrement bias. After multiple aging times, the threshold voltage and subthreshold swing under the bias are given.

[0041] Furthermore, combining the characterization of channel defects and surface potential, optimize the transmission model of the field effect transistor, which specifically includes the following steps:

[0042] Use a scanning probe microscope to test the transfer characteristics and output characteristics of the field effect transistor, and give the channel defects and channel surface potential.

[0043] Based on the channel defects, give the equivalent channel size and ideal channel size of the field effect transistor, and analyze the current at the channel center by combining the distribution of the channel surface potential respectively, which is specifically expressed as:

[0044]

[0045] Among them, I D，C，0 is the current at the channel center under the ideal channel size, W0 is the width of the ideal channel, n C，0 is the carrier density under the ideal channel size, μ C，0 is the mobility at the channel center position under the ideal channel size, q is the electric charge of an electron, F D，0，x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the ideal channel size, I D，C is the current at the channel center under the equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under the equivalent channel size, μ C is the mobility at the channel center position under the equivalent channel size, F D，x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the equivalent channel size;

[0046] Based on the analysis and comparison of the current at the channel center, give the transmission adjustment coefficient and optimize the transmission model of the field effect transistor, which is specifically expressed as:

[0047]

[0048] Among them, η is the transmission adjustment coefficient, μ lin′ is the average mobility in the optimized linear state, μ sat ′ is the average mobility in the optimized saturation state, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C iis the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in the saturation state.

[0049] In a second aspect, the present invention also provides a performance evaluation device for a field effect transistor containing black phosphorus, which adopts the performance evaluation method for a field effect transistor containing black phosphorus as described above, and specifically includes:

[0050] A data acquisition module, configured to acquire electrical characteristic data, bias temperature instability data, and characterization data of channel defects and surface potential for electrical characteristic measurement under a first controllable environmental variable;

[0051] An analysis module, configured to construct a transmission model of the field effect transistor according to the acquired electrical characteristic data, analyze the failure behavior according to the acquired bias temperature instability data, and optimize the transmission model and failure behavior of the field effect transistor in combination with the characterization data of channel defects and surface potential;

[0052] An evaluation module, configured to evaluate the performance of the field effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior.

[0053] The performance evaluation method and device for a field effect transistor containing black phosphorus provided by the present invention have at least the following beneficial effects:

[0054] (1) The present invention integrates electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential, and gives an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of the field effect transistor device structure, and the optimization of the manufacturing process in the field effect transistor containing black phosphorus.

[0055] (2) Through the analysis of channel defects and surface potential, it is used to correct the mobility of the field effect transistor containing black phosphorus and optimize the transmission model of the field effect transistor. Characterize the defects on the channel surface, compare with the defects in the initial state of the field effect transistor device, explore the influence of the failure mechanism on the defects, reveal the law of channel surface charge trapping under the influence of the failure mechanism, as well as the electrostatic accumulation and potential change trend during the device failure process, which can verify the analyzed BTI failure behavior to a certain extent, thereby further improving the failure behavior mechanism. Description of the Drawings

[0056] Figure 1Schematic structural diagrams of a pure black phosphorus field-effect transistor and a stacked heterojunction transistor of a two-dimensional material - black phosphorus provided by the present invention. (a) is a pure black phosphorus field-effect transistor, and (b) is a stacked heterojunction transistor of a two-dimensional material - black phosphorus;

[0057] Figure 2 Schematic flow diagram of a performance evaluation method for a field-effect transistor containing black phosphorus provided by the present invention;

[0058] Figure 3 Schematic diagrams of the equivalent channel and ideal channel of a field-effect transistor containing black phosphorus provided by the present invention;

[0059] Figure 4 Schematic structural diagram of a certain embodiment provided by the present invention for characterizing channel defects and surface potential using CAFM technology;

[0060] Figure 5 Schematic structural diagram of a certain embodiment provided by the present invention for characterizing channel defects and surface potential using KPFM technology;

[0061] Figure 6 Schematic diagram of a preset bottom gate bias of a certain embodiment provided by the present invention. (a) is a schematic diagram of aging time and relaxation time, and (b) is a schematic diagram of equal value bias, arithmetic increasing bias, and arithmetic decreasing bias.

[0062] Description of reference numerals:

[0063] 11 - P-type silicon wafer substrate; 12 - SiO2 dielectric layer; 13 - black phosphorus layer; 14 - two-dimensional material layer. Detailed implementation manners

[0064] In order to better understand the above technical solutions, the above technical solutions will be described in detail below in conjunction with the accompanying drawings of the specification and specific implementation manners. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those of ordinary skill in the art without making creative efforts shall fall within the protection scope of the present invention.

[0065] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms of "a", "the", and "said" used in the embodiments of the present invention and the appended claims are also intended to include the plural forms unless the context clearly indicates otherwise. "Plural" generally includes at least two.

[0066] It should also be noted that the term "including", "comprising" or any other variant thereof is intended to cover non-exclusive inclusion, such that a commodity or device comprising a series of elements not only includes those elements but also includes other elements not expressly listed, or elements inherent to such commodity or device. Without further limitation, an element defined by the statement "comprising one..." does not exclude the presence of additional identical elements in the commodity or device comprising said element.

[0067] Regarding the evolution of the preparation process of black phosphorus-based field-effect transistors, it is mainly from the perspective of improving the stability and mobility of field-effect transistors. First, the surface of black phosphorus is modified by molecules and ions to passivate the lone pair electrons of phosphorus atoms in black phosphorus, thereby improving the stability of black phosphorus flakes. However, this strategy changes the intrinsic properties of the black phosphorus layer, the controllability of device modification is poor, and there are problems such as thermal stability and time degradation in interface modification; second, the covering method, that is, using two-dimensional materials such as oxide films or boron nitride to cover the black phosphorus layer to improve its stability, so as to improve stability without significantly affecting the device mobility. The structure of the two-dimensional material (such as boron nitride)-black phosphorus heterojunction is the current optimal technical strategy for improving the comprehensive performance of black phosphorus-based field-effect transistors.

[0068] However, a large amount of research is still needed on the basic data in the structure of the two-dimensional material-black phosphorus heterojunction, such as charge transfer and bandgap change. At the same time, stacking a heterojunction on the structure of the original field-effect transistor as the channel of the field-effect transistor will cause a huge redistribution of electrostatic potential on the contact surface, greatly affecting the movement of carriers.

[0069] Therefore, relevant research on the carrier transport properties and reliability evaluation in field-effect transistors with stacked two-dimensional material-black phosphorus heterojunctions is very necessary. Regarding the performance evaluation of black phosphorus-based field-effect transistors, it is necessary not only to start from the characterization of basic device characteristics (such as current on-off ratio, mobility, etc.), but also to consider the overall reliability of the device for reliability evaluation. In reliability evaluation, bias temperature instability (BTI, due to the charge trapping effect of the device, the transistor characteristics shift), is one of the most important failure mechanisms in field-effect transistors, and it has also been confirmed to have an important impact on the characteristics of two-dimensional material field-effect transistors and is an important direction for reliability research.

[0070] The present invention uses conductive atomic force microscopy and Kelvin probe force microscopy techniques to achieve in-situ research on the failure mechanism of two-dimensional material-black phosphorus heterojunctions, constructs the physical mechanism of the degradation of field-effect transistor devices containing black phosphorus, and combines a variety of other electronics research means to construct a comprehensive and perfect reliability evaluation scheme for the electrical characteristics, defects, and bias temperature instability of two-dimensional material-black phosphorus heterojunction FETs.

[0071] As Figure 1 shown, the field-effect transistor containing black phosphorus uses the material containing black phosphorus as the channel of the field-effect transistor. The material containing black phosphorus includes pure black phosphorus and two-dimensional material-black phosphorus in the form of a stacked heterojunction.

[0072] The pure black phosphorus field-effect transistor is a field-effect transistor that uses only black phosphorus as the channel layer material; the stacked heterojunction transistor of two-dimensional material-black phosphorus is a field-effect transistor formed by attaching black phosphorus to a two-dimensional material to form a stacked heterojunction and using the stacked heterojunction as the channel layer material. The two-dimensional material in the stacked heterojunction transistor of two-dimensional material-black phosphorus can be graphene, can also be boron nitride (BN), or can also be indium selenide (InSe).

[0073] The field-effect transistor containing black phosphorus can be prepared by existing methods or by the following transfer process. The device structure adopts the structure of a bottom gate electrode and top source-drain electrodes. Such an open-channel structure brings great convenience to the characterization of device characteristics (such as channel defects and surface potential) using a scanning probe microscope (SPM). The following solutions respectively use the typical conductive atomic force microscopy (CAFM) and Kelvin probe force microscopy (KPFM) in SPM to perform characterization tests on channel defects and surface potential.

[0074] Specifically, the preparation of the field-effect transistor containing black phosphorus specifically includes the following steps:

[0075] Grow a SiO2 dielectric layer with a thickness of 10-300 nm on a P-type silicon wafer substrate;

[0076] Transfer the prepared black phosphorus layer or two-dimensional material-black phosphorus stacked heterojunction layer to the surface of the SiO2 dielectric layer to obtain an intermediate. Among them, the thickness of the black phosphorus layer is 0.5-5 nm, the thickness of the two-dimensional material-black phosphorus stacked heterojunction layer is 0.5-5 nm, and the two-dimensional material is one of graphene, BN, and InSe; the preparation of the black phosphorus layer and the two-dimensional material-black phosphorus stacked heterojunction layer can be carried out in an existing manner, and no further limitation is made here.

[0077] Anneal the intermediate layer. The annealing is carried out in an inert gas, with the annealing temperature being 250 - 300 °C, the annealing time being 30 - 60 min, and the heating and cooling rate of annealing being 5 - 10 °C / min. Annealing the intermediate layer can reduce the surface oxidation of black phosphorus and the generation of impurities. The inert gas can be nitrogen or argon, avoiding black phosphorus being exposed to the air environment.

[0078] Use a mask plate to process the intermediate layer to obtain a channel with a length of 5 - 50 μm and a width of 5 - 50 μm.

[0079] Deposit electrodes at both ends of the channel as the source and drain through magnetron sputtering or evaporation to fabricate a field - effect transistor containing black phosphorus. The size of the source and drain is from 50×50 μm to 200×200 μm.

[0080] As Figure 2 , the present invention provides a method for evaluating the performance of a field - effect transistor containing black phosphorus, which specifically includes the following steps:

[0081] Fabricate a field - effect transistor containing black phosphorus;

[0082] Give the transmission model of the field - effect transistor by measuring the electrical characteristics under the first controllable environmental variable;

[0083] Obtain the bias - temperature instability data and analyze the failure behavior;

[0084] Combine the characterization of channel defects and surface potential to optimize the transmission model of the field - effect transistor and the analysis of the failure behavior;

[0085] Combine the optimized transmission model and the analysis of the failure behavior to achieve the performance evaluation of the field - effect transistor containing black phosphorus.

[0086] Through a set of research methods such as electrical characteristic measurement, characterization of channel defects and surface potential, and failure behavior analysis of bias - temperature instability, study the physical mechanism (transmission model) of different types of field - effect transistors containing black phosphorus, evaluate charge exchange, give the electrostatic shielding effect and its causes, achieve the performance evaluation of reliability, and guide the optimization of the design of field - effect transistors containing black phosphorus.

[0087] Give the transmission model of the field - effect transistor by measuring the electrical characteristics under the first controllable environmental variable, which specifically includes the following steps:

[0088] Determine the parameters and parameter value ranges of the first controllable environmental variable;

[0089] Give the electrical characteristic data under different controllable environmental variables through transfer characteristic and output characteristic tests;

[0090] Give the transfer model of the field-effect transistor.

[0091] The parameters of the first controllable environmental variable include the first environmental atmosphere, the voltage between the source and drain, the gate voltage, and the test time. The first environmental atmosphere includes humidity, oxygen concentration, and temperature.

[0092] The electrical property data includes the average mobility of the field-effect transistor.

[0093] The above measurement of the electrical properties of the field-effect transistor containing black phosphorus can be carried out by a semiconductor analyzer, an accessory device for auxiliary control of environmental variables. The first environmental atmosphere can be a vacuum, nitrogen, and atmospheric environment, and the parameters such as humidity, oxygen concentration, and temperature in these three environments are given.

[0094] For the parameter value ranges of the first controllable environmental variable, they can be set as follows: the voltage between the source and drain (0 - 40V), the gate voltage (0 - 80V), humidity (10 - 60%), oxygen concentration (0 - 90%), and temperature (25 - 180°C). The span of the test time can be extended to 1 year, and the test time points for the electrical property data can be set at the 1st, 2nd, 3rd, 7th, 14th, 30th, 60th, 90th, 180th, and 360th days. By calculating the average mobility of the field-effect transistors with different black phosphorus types at different time points, evaluating the performance and degradation time characteristics of the field-effect transistors, a transfer model of the field-effect transistor can be constructed, and the laws of device performance and stability can be given.

[0095] Specifically, the transfer model of the field-effect transistor is specifically expressed as:

[0096]

[0097] Among them, μ lin is the average mobility in the linear state, μ sat is the average mobility in the saturation state, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in the saturation state.

[0098] The average mobility of the field-effect transistor needs to be analyzed separately in two sections: the linear state and the saturation state. The linear state (i.e., the linear region) and the saturation state (i.e., the saturation region) can be clearly identified from the output characteristic curve of the field-effect transistor. Generally, the material containing black phosphorus presents an irregular shape, and the width and length of the channel are equivalent size values.

[0099] However, among the core performance indicators of field-effect transistors, the average mobility is often overestimated. Possible reasons include errors introduced by contact resistance, channel bypass effect, edge field effect, etc. Among them, the edge field effect has a particularly important impact on mobility in field-effect transistors based on materials such as metal oxides, polymers, and two-dimensional materials.

[0100] As Figure 3 shown, the actual area (equivalent size) of the channel layer material is significantly larger than the area of the apparent channel (the ideal rectangular area between the source and drain electrodes), resulting in a significant edge current when the field-effect transistor device operates. This is reflected in the transfer, output, and other characteristics of the device, ultimately leading to an overestimation of mobility. Through the above analysis of channel defects and surface potential, the mobility of field-effect transistors containing black phosphorus is corrected.

[0101] For the optimization of the transport model, specifically, through the characterization of channel defects and surface potential, the transport model is optimized, which specifically includes the following steps:

[0102] Use a scanning probe microscope to test the transfer characteristics and output characteristics of the field-effect transistor, and give the channel defects and channel surface potential;

[0103] Based on the channel defects, give the equivalent channel size and ideal channel size of the field-effect transistor, and analyze the current at the channel center by combining the distribution of the channel surface potential respectively, which is specifically expressed as:

[0104]

[0105] Among them, I D，C，0 is the current at the channel center under the ideal channel size, W0 is the width of the ideal channel, n C，0 is the carrier density under the ideal channel size, μ C，0 is the mobility at the channel center position under the ideal channel size, q is the charge of an electron, F D，0，x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the ideal channel size, I D，C is the current at the channel center under the equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under the equivalent channel size, μ C is the mobility at the channel center position under the equivalent channel size, F D，x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the equivalent channel size;

[0106] Based on the analysis and comparison of the current at the channel center, give the transport adjustment coefficient to optimize the transport model of the field-effect transistor, which is specifically expressed as:

[0107]

[0108] where η is the transmission adjustment coefficient, μ lin ′ is the average mobility in the optimized linear state, μ sat ′ is the average mobility in the optimized saturation state, I D，lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D，sat is the source-drain current in the saturation state.

[0109] Combined with a scanning probe microscope to determine channel defects and the equivalent channel size, and then obtain the carrier density, mobility, and surface potential at the channel center under the equivalent channel size and the ideal channel size respectively. Among them, the surface potential obtained by the scanning probe microscope will vary due to the size difference between the equivalent channel size and the ideal channel size, and the potential data formats given by different types of scanning probe microscopes are also different. Here, the specific data and presentation forms of the surface potential are not limited.

[0110] Determine the current at the channel center from the carrier density, mobility, and surface potential, compare the current conditions in the two cases, and the transmission adjustment coefficient can be obtained. Thus, the transmission model of the field-effect transistor can be optimized.

[0111] To study the reliability of various types of black phosphorus-containing field-effect transistors, bias temperature instability data can be obtained and the failure behavior can be analyzed, which specifically includes the following steps:

[0112] Determine the parameters and parameter value ranges of the second controllable environmental variable;

[0113] Conduct a bias temperature instability test, give the bias temperature instability data under different controllable environmental variables, and analyze the failure behavior of the field-effect transistor. Among them, the bias temperature instability test includes a positive bias temperature instability test and a negative bias temperature instability test.

[0114] The parameters of the second controllable environmental variable include: the second environmental atmosphere, source-drain voltage, bottom gate bias voltage. The bottom gate bias voltage includes a bottom gate positive bias voltage and a bottom gate negative bias voltage. The second environmental atmosphere includes the aging temperature and aging time;

[0115] The bias temperature instability data includes the threshold voltage and subthreshold swing.

[0116] Bias Temperature Instability (BTI) refers to the phenomenon of performance degradation in field-effect transistors under bias voltage and high-temperature conditions. The degradation is manifested as a decrease in parameters such as operating voltage and transconductance, an increase in parameters such as leakage current, and most critically, a shift in the threshold voltage. Therefore, for failure behavior, the threshold voltage and subthreshold swing are used as the core indicators for quantitative analysis.

[0117] Bias Temperature Instability is divided into Positive Bias Temperature Instability (PBTI) and Negative Bias Temperature Instability (NBTI).

[0118] The above BTI tests can be combined with CAFM and KPFM technologies, semiconductor analyzers, and accessory devices for auxiliary control of environmental variables. Among them, the parameter values of the second controllable environmental variable can be set as follows:

[0119] Apply a bottom gate bias (PBTI: in the range of 0 to 80 V; NBTI: in the range of 0 to -80 V), source-drain voltage (0–40 V); heat to the aging temperature (50–180 °C), aging time (0 - 3600 s).

[0120] Conduct a bias temperature instability test, which specifically includes the following steps:

[0121] Set the aging temperature, relaxation time, and aging time. The relaxation time is the interval time between the aging times of applying adjacent bottom gate biases, and the ratio of aging time to relaxation time is 1:(0.1 - 10);

[0122] Apply a preset equal-value bottom gate bias. After multiple aging times, give the threshold voltage and subthreshold swing under bias voltage;

[0123] Apply a preset arithmetic increasing bias or arithmetic decreasing bias. After multiple aging times, give the threshold voltage and subthreshold swing under bias voltage.

[0124] Through multiple measurement data, plot the curves of threshold voltage and subthreshold swing versus aging time, temperature, and bottom gate bias. Use physical models (such as power law models, exponential models, etc.) to fit the experimental data, analyze the mechanism of the BTI effect, and thereby determine the parameters of the physical model (such as acceleration factor, activation energy, etc.) to predict the long-term stability of the device under actual working conditions.

[0125] Such as Figure 6As shown, during multiple aging and measurement cycles in the BTI test, specific BTI aging time and relaxation time t(base) are configured, and the bias temperature instability data of the device are measured at the time point when aging ends and relaxation begins. Three different bias voltage (VG) loading methods are set, namely equal-value bias voltage: the bias voltage is the same for each aging; arithmetic progressive bias voltage: the aging bias voltage gradually increases; arithmetic decreasing bias voltage: the aging bias voltage gradually decreases. By adjusting the BTI aging time, relaxation time, and maximum bias voltage (VG,max), the degree to which the field-effect transistor device slows down or accelerates failure is evaluated, and its main mechanism is analyzed in combination with the failure mechanism model, so as to guide the optimization of the field-effect transistor containing black phosphorus.

[0126] For the failure behavior of the above field-effect transistor, it can also be optimized by in-situ characterization of channel defects and surface potential.

[0127] As Figure 4 shown, CAFM is used for channel defect analysis. Various types of field-effect transistor devices containing black phosphorus are placed on the atomic force microscope sample stage. The probe scans the transistor channel in contact mode or tapping mode and applies a DC voltage simultaneously, so as to obtain the current signal at the contact point position, which is collected by the CAFM system after amplification processing; while the probe is scanning, the field-effect transistor can be in the working or non-working state. The working state means applying a voltage between the source and drain.

[0128] For the analysis of channel defects, the following technical solutions can be adopted: First, perform CAFM scanning on the region of the field-effect transistor device containing black phosphorus between the source and drain electrodes, covering the region inside the channel and the regions near the source and drain of the channel, to obtain the conductivity and current map, and surface potential of the region, showing information such as the density and distribution of defects.

[0129] The probe used is made of platinum Pt or iridium Ir, in contact mode, the scanned area is in the range of 2×2 to 20×20μm 2 range, the scanning speed is in the range of 0.1–10 s / line, the voltage applied between the source and drain is in the range of 0–10 V, the bottom gate voltage is in the range of 0–10 V, and the voltage applied by the CAFM probe is in the range of 0–10 V. Subsequently, the output characteristic curve and transfer characteristic curve of the field-effect transistor device are tested, including measuring the electrical characteristics of the device under the introduction of controllable environmental variables of humidity (in the range of 10–60%), oxygen concentration (in the range of 0–90%), and temperature (in the range of 25–180 °C), as a simulation of the actual working conditions of the field-effect transistor.

[0130] Subsequently, the area between the source and drain electrodes after testing for each case was scanned by CAFM and compared with the scanning results in the as-prepared state to obtain the changes in defects after the device was simulated under working conditions. Thus, the influence of the changes in charged impurities generated by different stacked heterojunctions on the channel defects of the field-effect transistor was studied, and the defect stability of the device under different working conditions could be reflected. In addition, the channel defect state of the field-effect transistor device during the aging process was characterized: without introducing other external factors, the transistors were placed in nitrogen and atmospheric environments for a long time, with a time span of about 1 year. The area between the source and drain electrodes of the black phosphorus-containing field-effect transistor was scanned by CAFM on the 1st, 2nd, 3rd, 7th, 14th, 30th, 60th, 90th, 180th, and 360th days, respectively. By comparing with the scanning results in the as-prepared state, the changes in defects during the degradation process of the field-effect transistor were analyzed and studied. Given the large time span of the experiment, the same batch of prepared field-effect transistor devices could be used and carried out synchronously with the electrical property measurement experiment of the above black phosphorus-containing field-effect transistor.

[0131] In addition, as Figure 5 shown, KPFM was used to analyze the surface potential of the channel. The device was placed on the atomic force microscope sample stage, and a conductive probe made of platinum (Pt) or iridium (Ir) was used to scan the transistor channel in a constant-distance mode, non-contact mode. The scanning area was in the range of 2×2 to 20×20 μm 2 range, and the scanning speed was in the range of 0.1–10 s / line. The output characteristic curve and transfer characteristic curve of the black phosphorus-containing field-effect transistor device were tested, including measuring the electrical properties of the device under the introduction of controllable environmental variables of humidity (in the range of 10–60%), oxygen concentration (in the range of 0–90%), and temperature (in the range of 25–180 °C); the voltage between the source and drain was controlled at 0–40 V, and the gate voltage was controlled at 0–80 V; during the test, the channel area was scanned by KPFM simultaneously.

[0132] In addition, the changes in defects during the degradation process of the field-effect transistor could also be carried out synchronously with the electrical property measurement experiment of the black phosphorus-containing field-effect transistor.

[0133] In addition, after several groups of experiments with specific bias voltages and temperatures, CAFM was used to characterize the defects on the channel surface, compare with the defects in the initial state of the device, explore the influence of the failure mechanism on the defects, reveal the law of charge trapping on the channel surface under the influence of the failure mechanism, as well as the electrostatic accumulation and potential change trend during the device failure process, which could verify the BTI failure behavior analyzed to a certain extent, and thus further improve the failure behavior mechanism. On the basis of the above failure behavior analysis, by adjusting the bias voltage, aging time in the BTI test, and the interval time in the cyclic test, the possibility of slowing down and accelerating the device failure was explored, and the effectiveness of the failure behavior mechanism was verified with this.

[0134] In addition, the present invention also provides a performance evaluation device for a field effect transistor containing black phosphorus. Using the performance evaluation method for a field effect transistor containing black phosphorus as described above, it specifically includes:

[0135] A collection module for collecting electrical characteristic data, bias temperature instability data, and characterization data of channel defects and surface potential in electrical characteristic measurements under a first controllable environmental variable;

[0136] An analysis module for constructing a transmission model of the field effect transistor based on the collected electrical characteristic data, analyzing the failure behavior based on the collected bias temperature instability data, and optimizing the transmission model and failure behavior of the field effect transistor in combination with the characterization data of channel defects and surface potential;

[0137] An evaluation module for realizing the performance evaluation of the field effect transistor containing black phosphorus by combining the optimized transmission model and the analysis of the failure behavior.

[0138] The performance evaluation method and device for a field effect transistor containing black phosphorus provided by the present invention have at least the following beneficial effects:

[0139] (1) The present invention combines electrical characteristic measurement, failure analysis of bias temperature instability data, and characterization of defects and surface potential, and gives an optimized transmission model and failure behavior analysis, which can more effectively guide the selection of heterojunction materials, the design of the field effect transistor device structure, and the optimization of the manufacturing process in the field effect transistor containing black phosphorus.

[0140] (2) Through the analysis of channel defects and surface potential, it is used to correct the mobility of the field effect transistor containing black phosphorus and optimize the transmission model of the field effect transistor. Characterize the defects on the channel surface, compare with the defects in the initial state of the field effect transistor device, explore the influence of the failure mechanism on the defects, reveal the law of charge trapping on the channel surface under the influence of the failure mechanism, and the electrostatic accumulation and potential change trend during the device failure process, which can verify the analyzed BTI failure behavior to a certain extent, thereby further improving the failure behavior mechanism.

[0141] Although the preferred embodiments of the present invention have been described, those skilled in the art can make additional changes and modifications once they know the basic creative concepts. Therefore, the appended claims are intended to be construed as including the preferred embodiments and all changes and modifications falling within the scope of the present invention. Obviously, those skilled in the art can make various changes and variations to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalent technologies, the present invention is also intended to include these modifications and variations.

Claims

1. A method for evaluating the performance of a field effect transistor containing black phosphorus, characterized in that Specifically, it includes the following steps: Fabricate a field-effect transistor containing black phosphorus; Through the electrical property measurement of the first controllable environmental variable, give the transmission model of the field-effect transistor; Obtain bias temperature instability data and analyze the failure behavior; Combined with the characterization of channel defects and surface potential, optimize the transmission model of the field-effect transistor and the analysis of the failure behavior; Combined with the optimized transmission model and the analysis of the failure behavior, realize the performance evaluation of the field-effect transistor containing black phosphorus; Among them, combined with the characterization of channel defects and surface potential, optimizing the transmission model of the field-effect transistor specifically includes the following steps: Use a scanning probe microscope to test the transfer characteristics and output characteristics of the field-effect transistor, and give the channel defects and channel surface potential; Based on the channel defects, give the equivalent channel size and ideal channel size of the field-effect transistor, and analyze the current at the channel center respectively in combination with the distribution of the channel surface potential, specifically expressed as: Among them, ID ,C,0 is the current at the center of the channel under the ideal channel size, W0 is the width of the ideal channel, n C,0 is the carrier density under the ideal channel size, μ C,0 is the mobility at the center position of the channel under the ideal channel size, q is the electric charge of an electron, F D，0,x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the ideal channel size, ID ，C is the current at the center of the channel under the equivalent channel size, W sc is the width of the equivalent channel, n C is the carrier density under the equivalent channel size, μ C is the mobility at the center position of the channel under the equivalent channel size, F D,x＝0 (y)dy is the longitudinal line surface potential when the channel width is zero under the equivalent channel size; Based on the analysis and comparison of the current at the channel center, give the transmission adjustment coefficient and optimize the transmission model of the field-effect transistor, specifically expressed as: Among them, η is the transmission adjustment coefficient, μ lin ' is the average mobility in the optimized linear state, μ sat ' is the average mobility in the optimized saturation state, I D,lin is the source-drain current in the linear state, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D,sat is the source-drain current in the saturation state.

2. The performance evaluation method for a field effect transistor containing black phosphorus as described in claim 1, wherein The field-effect transistor containing black phosphorus uses a material containing black phosphorus as the channel of the field-effect transistor. The material containing black phosphorus includes pure black phosphorus and two-dimensional material-black phosphorus in the form of a stacked heterojunction; Fabricate a field-effect transistor containing black phosphorus, specifically including the following steps: Grow a SiO2 dielectric layer with a thickness of 10 - 300 nm on a P-type silicon wafer substrate; Stack the prepared black phosphorus layer or two-dimensional material-black phosphorus stacked heterojunction layer and transfer it to the surface of the SiO2 dielectric layer to obtain an intermediate. Among them, the thickness of the black phosphorus layer is 0.5 - 5 nm, the thickness of the two-dimensional material-black phosphorus stacked heterojunction layer is 0.5 - 5 nm, and the two-dimensional material is one of graphene, BN, and InSe; Anneal the intermediate. Among them, the annealing is carried out in an inert gas, the annealing temperature is 250 - 300 °C, the annealing time is 30 - 60 min, and the heating and cooling rate of the annealing is 5 - 10 °C / min; Use a mask to process the intermediate to obtain a channel with a length of 5 - 50 μm and a width of 5 - 50 μm; Deposit electrodes at both ends of the channel as the source and drain by magnetron sputtering or evaporation to fabricate a field-effect transistor containing black phosphorus.

3. The performance evaluation method for the field effect transistor containing black phosphorus according to claim 2, characterized in that, Through the electrical property measurement of the first controllable environmental variable, give the transmission model of the field-effect transistor, specifically including the following steps: Determine the parameters and parameter value ranges of the first controllable environmental variable; Through transfer characteristic and output characteristic tests, give the electrical property data under different controllable environmental variables; Give the transmission model of the field-effect transistor.

4. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 3, wherein The parameters of the first controllable environmental variable include the first environmental atmosphere, the voltage between the source and drain, the gate voltage, and the test time. The first environmental atmosphere includes humidity, oxygen concentration, and temperature; The electrical property data includes the average mobility of the field-effect transistor.

5. The performance evaluation method for the field effect transistor containing black phosphorus according to claim 4, characterized in that The transmission model of the field-effect transistor is specifically expressed as: where μ lin is the average mobility in the linear regime, μ sat is the average mobility in the saturation regime, I D，lin is the source-drain current in the linear regime, W is the width of the channel, L is the length of the channel, C i is the capacitance per unit area of the SiO2 dielectric layer, V GS is the gate measurement voltage, V TH is the gate threshold voltage, V D is the source-drain voltage, I D,sat is the source-drain current in the saturation regime.

6. The performance evaluation method for a field effect transistor containing black phosphorus according to claim 1, characterized in that Obtain bias temperature instability data and analyze the failure behavior, specifically including the following steps: Determine the parameters and parameter value ranges of the second controllable environmental variable; Perform the bias temperature instability test, give the bias temperature instability data under different controllable environmental variables, and analyze the failure behavior of the field-effect transistor. Among them, the bias temperature instability test includes the positive bias temperature instability test and the negative bias temperature instability test.

7. The performance evaluation method for the field effect transistor containing black phosphorus according to claim 6, characterized in that The parameters of the second controllable environmental variable include: the second environmental atmosphere, the source-drain voltage, and the bottom-gate bias. The bottom-gate bias includes the bottom-gate positive bias and the bottom-gate negative bias. The second environmental atmosphere includes the aging temperature and the aging time; The bias temperature instability data includes the threshold voltage and the subthreshold swing.

8. The performance evaluation method for the field effect transistor containing black phosphorus according to claim 7, characterized in that, Perform the bias temperature instability test, which specifically includes the following steps: Set the aging temperature, relaxation time, and aging time. The relaxation time is the interval time between the aging times of applying adjacent bottom-gate biases. The ratio of the aging time to the relaxation time is 1:(0.1 - 10); Apply a preset equal-value bottom-gate bias. After multiple aging times, give the threshold voltage and the subthreshold swing under the bias. Apply a preset arithmetic increment bias or arithmetic decrement bias. After multiple aging times, give the threshold voltage and the subthreshold swing under the bias.

9. A performance evaluation device for a field effect transistor containing black phosphorus, characterized in that, Use the performance evaluation method for the field-effect transistor containing black phosphorus as described in any one of claims 1-8, which specifically includes: A collection module for collecting the electrical characteristic data of the electrical characteristic measurement, the bias temperature instability data, and the characterization data of the channel defect and the surface potential under the first controllable environmental variable; An analysis module for constructing a transmission model of the field-effect transistor according to the collected electrical characteristic data, analyzing the failure behavior according to the collected bias temperature instability data, and optimizing the transmission model and the failure behavior of the field-effect transistor in combination with the characterization data of the channel defect and the surface potential; An evaluation module for realizing the performance evaluation of the field-effect transistor containing black phosphorus in combination with the optimized transmission model and the analysis of the failure behavior.

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