Wafer-level integrated structure and manufacturing method thereof

Abstract

The invention discloses a wafer-level integrated structure and a manufacturing method thereof. The wafer-level integrated structure comprises a silicon adapter plate, a chip unit layer, a conductive bulge layer and a device module layer. The silicon adapter plate comprises a first surface and a second surface which are oppositely arranged; the chip unit layer is positioned on the first surface side of the silicon adapter plate and is electrically connected with the first surface of the silicon adapter plate; the chip unit layer comprises a plurality of semiconductor chips; the conductive bulge layer is positioned on the second surface side of the silicon adapter plate and is electrically connected with the second surface of the silicon adapter plate; and the device module layer is positioned on one side, far away from the silicon adapter plate, of the conductive bulge layer, and is electrically connected with the conductive bulge layer. The invention provides a wafer-level integrated structure and a manufacturing method thereof, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a wafer-level integrated structure and a manufacturing method thereof. Background Art

[0002] Wafer Level Package (WLP) refers to the process of packaging and testing most or all chips directly on the wafer, and then cutting them into individual components. WLP packaging has the advantages of smaller package size and better electrical performance.

[0003] The existing wafer-level packaging structure has the following problems: the number of wafer-level multi-chip connections is limited, the number of interconnection lines between wafer-level chips is limited, the bandwidth between wafer-level chips is limited, and communication between wafer-level chips requires the use of multiple channels such as substrates and PCB boards, resulting in long communication links and large delays. Summary of the invention

[0004] The present invention provides a wafer-level integrated structure and a manufacturing method thereof, which can improve the bandwidth of the wafer-level integrated structure and reduce communication paths.

[0005] According to another aspect of the present invention, there is provided a wafer-level integrated structure, the wafer-level integrated structure comprising:

[0006] A silicon adapter plate, the silicon adapter plate comprising a first surface and a second surface arranged opposite to each other;

[0007] A chip unit layer is located on the first surface side of the silicon adapter board and is electrically connected to the first surface of the silicon adapter board; the chip unit layer includes a plurality of semiconductor chips;

[0008] A conductive protrusion layer, located on the second surface side of the silicon adapter plate and electrically connected to the second surface of the silicon adapter plate;

[0009] The device module layer is located on a side of the conductive protruding layer away from the silicon adapter plate and is electrically connected to the conductive protruding layer.

[0010] Optionally, the plurality of semiconductor chips include a plurality of computing chips and a plurality of storage chips;

[0011] The computing chip and the storage chip are connected and communicated via the silicon adapter board;

[0012] The computing chips are connected and communicated with each other through the silicon adapter board.

[0013] Optionally, the device module layer includes a plurality of power modules;

[0014] The power supply module is used to supply power to the chip unit layer, and the power supply direction of the power supply module to the chip unit layer is the thickness direction of the silicon adapter board.

[0015] Optionally, the device module layer further includes a plurality of passive devices, a plurality of low-speed connectors and a plurality of high-speed connectors;

[0016] The low-speed connector is adjacent to the power module;

[0017] A vertical projection of the high-speed connector on the silicon adapter board is located at an edge region of the silicon adapter board.

[0018] Optionally, the silicon adapter plate includes a first redistribution layer, a silicon wafer body, and a second redistribution layer which are stacked in sequence;

[0019] The silicon wafer body includes a plurality of through silicon vias;

[0020] The chip unit layer is electrically connected to the first redistribution layer; the conductive protrusion layer is electrically connected to the second redistribution layer; the first redistribution layer and the second redistribution layer are electrically connected via silicon through vias in the silicon wafer body.

[0021] Optionally, the silicon wafer body further includes a groove and a micro-device;

[0022] The micro device is located in the groove and is electrically connected to the first redistribution layer.

[0023] Optionally, the silicon wafer body further includes a multi-layer conductive pattern layer and a multi-layer silicon support layer;

[0024] The conductive pattern layer and the silicon support layer are arranged in an alternating and stacked manner;

[0025] The silicon support layer includes a plurality of through silicon vias;

[0026] Two adjacent conductive pattern layers are electrically connected via the through silicon via.

[0027] Optionally, the wafer-level integrated structure provided in this embodiment further includes a metal bump layer;

[0028] The metal bump layer is located between the chip unit layer and the silicon adapter plate;

[0029] The chip unit layer is electrically connected to the first surface of the silicon adapter plate through the metal bump layer.

[0030] Optionally, the wafer-level integrated structure provided in this embodiment further includes a first heat dissipation layer and a second heat dissipation layer;

[0031] The first heat dissipation layer is located on a side of the chip unit layer away from the silicon adapter plate;

[0032] The second heat dissipation layer is located on a side of the device module layer away from the conductive protrusion layer.

[0033] According to another aspect of the present invention, a method for manufacturing a wafer-level integrated structure is provided, the method comprising:

[0034] Forming a silicon adapter plate; wherein the silicon adapter plate includes a first surface and a second surface disposed opposite to each other;

[0035] Forming a chip unit layer electrically connected to the first surface of the silicon interposer on the first surface side of the silicon interposer, wherein the chip unit layer includes a plurality of semiconductor chips;

[0036] forming a conductive protrusion layer electrically connected to the second surface of the silicon adapter plate on the second surface side of the silicon adapter plate;

[0037] A device module layer electrically connected to the conductive protrusion layer is formed on a side of the conductive protrusion layer away from the silicon adapter plate.

[0038] An embodiment of the present invention provides a wafer-level integrated structure, which includes a silicon adapter board, a chip unit layer located on the first surface side of the silicon adapter board, a conductive protrusion layer located on the second surface side of the silicon adapter board, and a device module layer located on the side of the conductive protrusion layer away from the silicon adapter board. The chip unit layer includes a plurality of semiconductor chips, and the device module layer includes a plurality of devices and modules. The plurality of semiconductor chips in the chip unit layer are electrically connected to the silicon adapter board, and the plurality of semiconductor chips can communicate with each other through the silicon adapter board, and the chip unit layer and the device module layer can also communicate with each other through the silicon adapter board, and the devices in the device module layer can also communicate with each other through the silicon adapter board. In this embodiment, the device module layer is set on the second surface side of the silicon adapter board, so that more semiconductor chips can be set on the first surface side of the silicon adapter board, thereby improving the bandwidth of the wafer-level integrated structure, and each semiconductor chip communicates with each other through the silicon adapter board, which can reduce the communication path. In summary, the wafer-level integrated structure provided in this embodiment can improve the bandwidth of the wafer-level integrated structure and reduce the communication path.

[0039] It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0041] Figure 1 is a schematic diagram of the front structure of a wafer-level integrated structure provided in an embodiment of the present invention;

[0042] Figure 2 is a schematic diagram of the back side structure of a wafer-level integrated structure provided according to an embodiment of the present invention;

[0043] Figure 3 is a schematic cross-sectional structural diagram of a wafer-level integrated structure provided according to an embodiment of the present invention;

[0044] Figure 4 is a schematic structural diagram of a silicon adapter board provided according to an embodiment of the present invention;

[0045] Figure 5 is a schematic structural diagram of another silicon adapter board provided according to an embodiment of the present invention;

[0046] Figure 6 is a structural schematic diagram of another wafer-level integrated structure provided according to an embodiment of the present invention;

[0047] Figure 7 It is a flow chart of a method for manufacturing a wafer-level chip integrated structure provided according to an embodiment of the present invention. DETAILED DESCRIPTION

[0048] In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

[0049] It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

[0050] Figure 1 is a schematic diagram of the front structure of a wafer-level integrated structure provided according to an embodiment of the present invention, Figure 2 is a schematic diagram of the back side structure of a wafer-level integrated structure provided according to an embodiment of the present invention, Figure 3 is a schematic cross-sectional view of a wafer-level integrated structure provided according to an embodiment of the present invention, with reference to Figure 1-Figure 3 The wafer-level integrated structure provided in this embodiment includes: a silicon adapter board 110, a chip unit layer 120, a conductive protrusion layer 130 and a device module layer 140; the silicon adapter board 110 includes a first surface S1 and a second surface S2 arranged opposite to each other; the chip unit layer 120 is located on the first surface S1 side of the silicon adapter board 110 and is electrically connected to the first surface S1 of the silicon adapter board 110, and the chip unit layer 120 includes a plurality of semiconductor chips 121; the conductive protrusion layer 130 is located on the second surface S2 side of the silicon adapter board 110 and is electrically connected to the second surface S2 of the silicon adapter board 110; the device module layer 140 is located on the side of the conductive protrusion layer 130 away from the silicon adapter board 110, and is electrically connected to the conductive protrusion layer 130.

[0051] Specifically, the silicon adapter board 110 is a wafer-level substrate with silicon as a carrier, and its size is a wafer-level size. The thickness of the silicon adapter board 110 can be less than 0.8 mm. The semiconductor chip 121 in the chip unit layer 120 can be a bare chip that has been cut and tested but has not yet been packaged. The chip unit layer 120 may include a plurality of semiconductor chips 121 with different functions. The device module layer 140 may include a plurality of devices and modules with different functions. Exemplarily, the device module layer 140 includes a plurality of passive devices such as resistors, capacitors and inductors, as well as power modules, low-speed connectors and high-speed connectors. The conductive protrusion layer 130 includes a plurality of conductive protrusions 131, each of which is electrically connected to the second surface S2 of the silicon adapter board 110, and the shape of the conductive protrusion 131 may be spherical.

[0052] Each semiconductor chip 121 is electrically connected to the silicon adapter board 110. Each semiconductor chip 121 can communicate with each other through the silicon adapter board 110. The device module layer 140 and the chip unit layer 120 can also communicate with each other through the silicon adapter board 110. The devices and modules in the device module layer 140 can also communicate with each other through the silicon adapter board 110. It can be seen that the silicon adapter board 110 in this embodiment can replace the existing PCB board to realize the communication between different semiconductor chips 121, reduce the communication path between different semiconductor chips 121, and also connect the semiconductor chip 121 with external devices through the device module layer 140. In this embodiment, the device module layer 140 is set on the second surface S2 side of the silicon adapter board 110 without occupying the space of the first surface S1 of the silicon adapter board 110, so that more semiconductor chips 121 can be set on the first surface S1 of the silicon adapter board 110, thereby improving the bandwidth of the wafer-level integrated structure.

[0053] The present embodiment provides a wafer-level integrated structure, which includes a silicon adapter board, a chip unit layer located on the first surface side of the silicon adapter board, a conductive protrusion layer located on the second surface side of the silicon adapter board, and a device module layer located on the side of the conductive protrusion layer away from the silicon adapter board. The chip unit layer includes a plurality of semiconductor chips, and the device module layer includes a plurality of devices and modules. The plurality of semiconductor chips in the chip unit layer are electrically connected to the silicon adapter board, and the plurality of semiconductor chips can communicate with each other through the silicon adapter board, and the chip unit layer and the device module layer can also communicate with each other through the silicon adapter board, and the devices in the device module layer can also communicate with each other through the silicon adapter board. In this embodiment, the device module layer is set on the second surface side of the silicon adapter board, so that more semiconductor chips can be set on the first surface side of the silicon adapter board, thereby improving the bandwidth of the wafer-level integrated structure, and each semiconductor chip communicates with each other through the silicon adapter board, which can reduce the communication path. In summary, the wafer-level integrated structure provided in this embodiment can improve the bandwidth of the wafer-level integrated structure and reduce the communication path.

[0054] Optional, continue to refer to Figure 1 and Figure 3 The plurality of semiconductor chips 121 include a plurality of computing chips 122 and a plurality of storage chips 123 ; the computing chips 122 are connected and communicated with each other via a silicon adapter board 110 ; and the computing chips 122 are connected and communicated with each other via a silicon adapter board 110 .

[0055] Specifically, the computing chip 122 may be a SOC chip, and the memory chip 123 may be an HBM chip or a DDR chip. The computing chip 122 may be arranged in an array, and the memory chip 123 may also be arranged in an array. The computing chip 122 may be adjacent to the memory chip 123.

[0056] The computing chip 122 and the storage chip 123 are connected and communicated through the silicon adapter board 110, which can reduce the length of the signal link and the number of connectors. The computing chip 122 and the computing chip 122 are connected and communicated through the silicon adapter board 110, which can reduce the length of the signal link and the number of connectors.

[0057] Optional, continue to refer to Figure 2 and Figure 3 The device module layer 140 includes a plurality of power modules 141 ; the power modules 141 are used to supply power to the chip unit layer 120 , and the power supply direction of the power modules 141 to the chip unit layer 120 is the thickness direction of the silicon adapter board 110 .

[0058] Specifically, each power module 141 is electrically connected to the conductive protruding layer 130, and each power module 141 can be arranged in an array. The vertical projection of a power module 141 on the silicon adapter board 110 overlaps with the vertical projection of at least one semiconductor chip 121 on the silicon adapter board 110. The power module 141 can supply power to the computing chip 122, or to the storage chip 123. A power module 141 can supply power to one semiconductor chip 121, or to multiple semiconductor chips 121 at the same time. The power supply direction of the power module 141 to each semiconductor chip 121 is the thickness direction of the silicon adapter board 110.

[0059] The power supply direction of the power module 141 refers to the current transmission direction when the power module 141 supplies power to the chip unit layer 120. The power supply direction of the power module 141 is the thickness direction of the silicon adapter board 110, indicating that the power module 141 supplies power vertically to the semiconductor chip 121 in the chip unit layer 120. Using vertical power supply can reduce the wiring length of the power path, thereby reducing voltage drop and improving power supply efficiency.

[0060] Optional, continue to refer to Figure 2 and Figure 3 The device module layer 140 also includes multiple passive devices 142, multiple low-speed connectors 143 and multiple high-speed connectors 144; the low-speed connector 143 is adjacent to the power module 141; the vertical projection of the high-speed connector 144 on the silicon adapter board 110 is located at the edge area of ​​the silicon adapter board 110.

[0061] Specifically, the passive device 142 can be a resistor, capacitor, inductor or other device. By arranging the passive device 142 on the side of the silicon adapter board 110 away from the chip unit layer 120, more semiconductor chips 121 can be arranged on the first surface of the silicon adapter board 110, further improving the bandwidth of the wafer-level integrated structure. The low-speed connector 143 can be electrically connected to the power module 141, and can also be electrically connected to the high-speed connector 144. The semiconductor chip 121 can be connected to the high-speed connector 144 through the silicon adapter board 110 and the low-speed connector 143, and connected to external devices through the high-speed connector 144. Arranging the high-speed connector 144 in the edge area of ​​the silicon adapter board 110 can facilitate the connection of the high-speed connector 144 with external devices, and the high-speed connector 144 can surround the power module 141. The transmission path of the high-speed connector 144 is separated from the power supply path of the power module 141, which can further improve the interconnection between systems.

[0062] Optional, Figure 4 is a schematic diagram of the structure of a silicon adapter board provided according to an embodiment of the present invention, with reference to Figure 4 The silicon adapter board 110 includes a first redistribution layer 112, a silicon wafer body 113 and a second redistribution layer 114 which are stacked in sequence; the silicon wafer body 113 includes a plurality of through silicon vias 111; the chip unit layer is electrically connected to the first redistribution layer 112; the conductive protrusion layer is electrically connected to the second redistribution layer 114; the first redistribution layer 112 and the second redistribution layer 114 are electrically connected via the through silicon vias 111 in the silicon wafer body 113.

[0063] Specifically, the first redistribution layer 112 is located on one side of the silicon wafer body 113, and the second redistribution layer 114 is located on the side of the silicon wafer body 113 away from the first redistribution layer 112. The first redistribution layer 112 includes a first passivation layer 101 located on one side of the silicon wafer body 113 and a first conductive line 102 located in the first passivation layer 101, and the second redistribution layer 114 includes a second passivation layer 103 located on one side of the silicon wafer body 113 and a second conductive line 104 located in the second passivation layer 103. The through silicon via 111 is electrically connected to the first conductive line 102 and the second conductive line 104, and the material of the through silicon via 111 can be metal. The semiconductor chips in the chip unit layer are electrically connected through the first conductive line 102, which reduces the length of the signal link and the number of connectors connecting the semiconductor chips. The devices and modules in the device module layer can be electrically connected through the second conductive line 104, which reduces the length of the signal link and the number of connectors.

[0064] In terms of wafer-level manufacturing process, the first conductive circuit 102 and the second conductive circuit 104 can be manufactured by global exposure, or by stepper process and multi-mask splicing.

[0065] Optionally, the silicon wafer body further includes a groove and a micro-device; the micro-device is located in the groove and is electrically connected to the first redistribution layer.

[0066] Specifically, by placing the micro-device inside the silicon wafer body instead of on the surface of the silicon wafer body, the area of ​​the first surface and the second surface of the silicon adapter can be reduced, so that more semiconductor chips can be placed on the first surface and more passive devices and power modules can be placed on the second surface. The micro-device can be a deep trench capacitor.

[0067] Optional, Figure 5 is a schematic diagram of the structure of another silicon adapter board provided according to an embodiment of the present invention, Figure 5 The silicon wafer body 113 also includes a plurality of conductive pattern layers 105 and a plurality of silicon support layers 106 , wherein the conductive pattern layers 105 and the silicon support layers 106 are alternately stacked; the silicon support layer 106 includes a plurality of through silicon vias 111 , and two adjacent conductive pattern layers 105 are electrically connected via the through silicon vias 111 .

[0068] Specifically, the number of layers of the conductive pattern layer 105 is equal to the number of layers of the silicon support layer 106. The semiconductor chips in the chip unit layer can be electrically connected through the multi-layer conductive pattern layer 105. The multi-layer conductive pattern layer 105 is arranged in the silicon wafer body 113, which can reduce the number of wiring layers of the first redistribution layer 112 and the number of wiring layers of the second redistribution layer 114. At least one through silicon via 111 in each silicon support layer 106 is connected integrally.

[0069] Optional, Figure 6 is a schematic diagram of another wafer-level integrated structure provided according to an embodiment of the present invention, with reference to Figure 6 The wafer-level integrated structure provided in this embodiment further includes a metal bump layer 170 ; the metal bump layer 170 is located between the chip unit layer 120 and the silicon adapter board 110 ; the chip unit layer 120 is electrically connected to the first surface of the silicon adapter board 110 through the metal bump layer 170 .

[0070] Specifically, the metal bump layer 170 includes a plurality of metal bumps 171 , and each semiconductor chip 121 is electrically connected to the first surface of the silicon interposer 110 via the metal bumps 171 .

[0071] Optional, continue to refer to Figure 6 The wafer-level integrated structure provided in this embodiment also includes a first heat dissipation layer 150 and a second heat dissipation layer 160; the first heat dissipation layer 150 is located on the side of the chip unit layer 120 away from the silicon adapter board 110; the second heat dissipation layer 160 is located on the side of the device module layer 140 away from the conductive protrusion layer 130.

[0072] Specifically, the first heat dissipation layer 150 includes a first heat conducting layer 151 and a first heat dissipation module 152, the first heat conducting layer 151 is located on one side of the chip unit layer 120, and the first heat dissipation module 152 is located on the side of the first heat conducting layer 151 away from the chip unit layer 120. The second heat dissipation layer 160 includes a second heat conducting layer 161 and a second heat dissipation module 162, the second heat conducting layer 161 is located on one side of the device module layer 140, and the second heat dissipation module 162 is located on the side of the second heat conducting layer 161 away from the device module layer 140. Both the first heat conducting layer 151 and the second heat conducting layer 161 can be heat conducting interface materials. The first heat dissipation module 152 and the second heat dissipation module 162 can be heat dissipation structures such as metal heat sinks or microchannels. The first heat dissipation layer 150 can quickly dissipate the heat generated by multiple semiconductor chips 121 to improve the working performance of the semiconductor chips 121, and the second heat dissipation layer 160 can quickly dissipate the heat generated by the devices and modules in the device module layer 140 to improve the working performance of the devices and modules. The first heat dissipation layer 150 and the second heat dissipation layer 160 can improve the heat dissipation performance of the wafer-level integrated structure. The inventors have found that the wafer-level integrated structure provided by this embodiment can still effectively dissipate heat when the power consumption exceeds kilowatts during operation, ensuring that the wafer-level integrated structure can work normally.

[0073] Figure 7 is a flow chart of a method for manufacturing a wafer-level chip integrated structure according to an embodiment of the present invention, with reference to Figure 7 The method for manufacturing the wafer-level chip integrated structure provided in this embodiment includes the following steps:

[0074] S110, forming a silicon adapter plate; wherein the silicon adapter plate includes a first surface and a second surface that are oppositely disposed.

[0075] S120, forming a chip unit layer electrically connected to the first surface of the silicon interposer on the first surface side of the silicon interposer, wherein the chip unit layer includes a plurality of semiconductor chips.

[0076] S130, forming a conductive protrusion layer electrically connected to the second surface of the silicon adapter board on the second surface side of the silicon adapter board.

[0077] S140, forming a device module layer electrically connected to the conductive protrusion layer on a side of the conductive protrusion layer away from the silicon adapter plate.

[0078] The manufacturing method of a wafer-level chip integrated structure provided in this embodiment has corresponding beneficial effects as the wafer-level chip integrated structure provided in any embodiment of the present invention. For technical details not elaborated in this embodiment, please refer to the wafer-level chip integrated structure provided in any embodiment of the present invention.

[0079] It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

[0080] The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A wafer-level integrated structure, characterized in that: include: A silicon adapter plate, the silicon adapter plate comprising a first surface and a second surface arranged opposite to each other; A chip unit layer is located on the first surface side of the silicon adapter board and is electrically connected to the first surface of the silicon adapter board; the chip unit layer includes a plurality of semiconductor chips; A conductive protrusion layer, located on the second surface side of the silicon adapter plate and electrically connected to the second surface of the silicon adapter plate; The device module layer is located on a side of the conductive protruding layer away from the silicon adapter plate and is electrically connected to the conductive protruding layer.

2. The wafer-level integrated structure according to claim 1, characterized in that: The plurality of semiconductor chips include a plurality of computing chips and a plurality of storage chips; The computing chip and the storage chip are connected and communicated via the silicon adapter board; The computing chips are connected and communicated with each other via the silicon adapter board.

3. The wafer-level integrated structure according to claim 1, characterized in that: The device module layer includes a plurality of power modules; The power supply module is used to supply power to the chip unit layer, and the power supply direction of the power supply module to the chip unit layer is the thickness direction of the silicon adapter board.

4. The wafer-level integrated structure according to claim 3, characterized in that: The device module layer also includes a plurality of passive devices, a plurality of low-speed connectors and a plurality of high-speed connectors; The low-speed connector is adjacent to the power module; The vertical projection of the high-speed connector on the silicon adapter board is located at an edge area of ​​the silicon adapter board.

5. The wafer-level integrated structure according to claim 1, characterized in that: The silicon adapter plate comprises a first redistribution layer, a silicon wafer body and a second redistribution layer which are stacked in sequence; The silicon wafer body includes a plurality of through silicon vias; The chip unit layer is electrically connected to the first redistribution layer; the conductive protrusion layer is electrically connected to the second redistribution layer; the first redistribution layer and the second redistribution layer are electrically connected via silicon through vias in the silicon wafer body.

6. The wafer-level integrated structure according to claim 5, characterized in that: The silicon wafer body also includes grooves and micro devices; The micro device is located in the groove and is electrically connected to the first redistribution layer.

7. The wafer-level integrated structure according to claim 5, characterized in that: The silicon wafer body also includes a multi-layer conductive pattern layer and a multi-layer silicon support layer; The conductive pattern layer and the silicon support layer are arranged in an alternating and stacked manner; The silicon support layer includes a plurality of through silicon vias; Two adjacent conductive pattern layers are electrically connected via the through silicon via.

8. The wafer-level integrated structure according to claim 1, characterized in that: Also includes a metal bump layer; The metal bump layer is located between the chip unit layer and the silicon adapter plate; The chip unit layer is electrically connected to the first surface of the silicon adapter plate through the metal bump layer.

9. The wafer-level integrated structure according to any one of claims 1 to 8, characterized in that: Also includes a first heat dissipation layer and a second heat dissipation layer; The first heat dissipation layer is located on a side of the chip unit layer away from the silicon adapter plate; The second heat dissipation layer is located on a side of the device module layer away from the conductive protrusion layer.

10. A method for manufacturing a wafer-level integrated structure, characterized in that: include: Forming a silicon adapter plate; wherein the silicon adapter plate includes a first surface and a second surface disposed opposite to each other; Forming a chip unit layer electrically connected to the first surface of the silicon interposer on the first surface side of the silicon interposer, wherein the chip unit layer includes a plurality of semiconductor chips; forming a conductive protrusion layer electrically connected to the second surface of the silicon adapter plate on the second surface side of the silicon adapter plate; A device module layer electrically connected to the conductive protrusion layer is formed on a side of the conductive protrusion layer away from the silicon adapter plate.

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