A Low Noise Programmable Amplifier

Abstract

The present invention relates to the technical field of integrated circuit design, and specifically discloses a low-noise programmable amplifier, comprising: a first fully differential amplifier, comprising two pairs of differential input terminals; a second fully differential amplifier, comprising a pair of differential input terminals, electrically connected to the first fully differential amplifier through an interstage chopper switch; a pair of input chopper switches, the input terminal of each input chopper switch is electrically connected to a differential input signal; a pair of output chopper switches, the output terminal of each output chopper switch is electrically connected to the output terminal of the second fully differential amplifier; an input capacitor network, located between a pair of input chopper switches and the two pairs of differential input terminals; a feedback capacitor network, located between a pair of output chopper switches and the two pairs of differential input terminals; and a plurality of zeroing switches, located between the input and output of the first fully differential amplifier. The two transconductance amplifiers inside the first fully differential amplifier of the present invention share the same current, and the overall transconductance is doubled compared to a single pair of differential inputs, thereby reducing the noise of the amplifier.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuit design, and in particular to a low-noise programmable amplifier. Background Art

[0002] Programmable amplifiers are mainly used in signal chains, in front of analog-to-digital converters (ADCs), to amplify signals. A typical capacitive gain amplifier chops the input signal by alternating between two chopping (CHP) amplification stages, where the second CHP stage has an amplified signal with reversed polarity compared to the first CHP stage. The output of the capacitive gain amplifier circuit can be input to an analog-to-digital converter (ADC) circuit for analog-to-digital conversion. The conversion accuracy is improved when the final voltage from the output of the capacitive gain amplifier circuit is well stabilized to the correct final value before the ADC circuit acquires the sample for conversion. Therefore, for high-frequency periodic sampling of the signal, it is expected that the capacitive gain amplifier circuit will quickly stabilize its output voltage to the accurate final value. The maximum sampling rate or frequency of the capacitive gain amplifier circuit is limited by the speed at which the amplified sample value stabilizes to the accurate final value. Current capacitive gain amplifiers have too many switches and complex timing control. The design is difficult, and the signal path is prone to nonlinear errors. When the chop cycle switches, a pseudo AZ phase is introduced, which is not conducive to the rapid establishment of the signal, while driving the output voltage signal of this phase.

[0003] Patent application CN114844479 is a working cycle of the amplifier (such as Figure 2 As shown in FIG. 1 ), the AZ phase, CHP1 phase and CHP2 phase are set, and the common mode signal of the amplifier is established by using the AZ phase. The signal is programmed to be amplified by periodically alternating the CHP1 phase and the CHP2 phase in conjunction with the selection of capacitors in the input capacitor network and the feedback capacitor network, thereby solving the problem of long signal establishment time and easy introduction of nonlinear errors in the signal path. In the patent application, Figure 1 As shown in the figure, in the two-stage amplification structure, the common-mode voltage of the capacitor amplifier is set by the first stage Gm1, and the noise is also mainly determined by Gm1. However, Gm1 has only one pair of differential input terminals, its gain improvement is limited, and the current utilization efficiency is not high, which makes it difficult to further reduce the noise level of the capacitor amplifier, affecting the detection accuracy of the signal.

[0004] Based on this technical background, the present invention studies a low-noise programmable amplifier. Summary of the invention

[0005] In view of the shortcomings of the prior art, the present invention proposes a low-noise programmable amplifier. The first fully differential amplifier includes two pairs of differential input terminals. Correspondingly, the corresponding two input pairs inside share the same current. Compared with a single pair of differential input terminals, the overall transconductance is approximately doubled, which effectively reduces the overall noise of the amplifier and improves the current utilization efficiency and signal detection accuracy.

[0006] In order to achieve the above object, the present invention provides a low-noise programmable amplifier, a first fully differential amplifier, comprising two pairs of differential input terminals;

[0007] A second fully differential amplifier, comprising a pair of differential input terminals, the pair of differential input terminals being electrically connected to the differential output terminals of the first fully differential amplifier via an inter-stage chopper switch;

[0008] a pair of input chopping switches, wherein a pair of input terminals of each input chopping switch is electrically connected to a pair of differential input signals;

[0009] a pair of output chopping switches, wherein a pair of output terminals of each output chopping switch is electrically connected to the differential output terminals of the second fully differential amplifier;

[0010] an input capacitor network located between the output terminals of the pair of input chopping switches and the two pairs of differential input terminals;

[0011] a feedback capacitor network located between the input terminals of the pair of output chopping switches and the two pairs of differential input terminals;

[0012] A plurality of zero adjustment switches are located between the input and output of the first fully differential amplifier and between the input / output end of the feedback capacitor network and the common mode voltage.

[0013] The beneficial effects of the present invention include:

[0014] (1) The low-noise programmable amplifier proposed in the present invention comprises a first fully differential amplifier including two pairs of differential input terminals, and correspondingly, two corresponding transconductance amplifiers inside the amplifier share the same current. Compared with a single pair of differential input terminals, the overall transconductance is approximately doubled, which effectively reduces the overall noise of the amplifier, improves the current utilization efficiency and the detection accuracy of the signal.

[0015] (2) In the low-noise programmable amplifier proposed in the present invention, the same current flows through a pair of PMOS input tubes and a pair of NMOS input tubes inside the first fully differential amplifier at the same time, and the overall transconductance of the amplifier is equivalently increased. Compared with an amplifier with a single pair of input tubes, the noise is reduced by about 3dB.

[0016] Other features and advantages of the present invention will be described in detail in the following detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The above and other objects, features and advantages of the present invention will become more apparent through a more detailed description of exemplary embodiments of the present invention in conjunction with the accompanying drawings, wherein like reference numerals generally represent like components throughout the exemplary embodiments of the present invention.

[0018] Figure 1 The schematic diagram is a structural diagram of a circuit of an existing programmable amplifier.

[0019] Figure 2 The figure is a schematic diagram of the phase relationship of an existing programmable amplifier in one working cycle.

[0020] Figure 3 This is a schematic diagram of the circuit structure of the low-noise programmable amplifier proposed by the present invention.

[0021] Figure 4 This is a schematic diagram of the input stage circuit structure of a first fully differential amplifier in a specific implementation of the low-noise programmable amplifier proposed by the present invention.

[0022] Figure 5 This is a schematic diagram of the input stage circuit structure of a first fully differential amplifier in another specific implementation manner of the low-noise programmable amplifier proposed by the present invention.

[0023] Description of reference numerals:

[0024] Gm1-first fully differential amplifier, Gm2-second fully differential amplifier, CPI1-first input chopping switch, CPI2-second input chopping switch, CPO1-first output chopping switch, CPO2-second output chopping switch, CPM-interstage chopping switch, C IP1 / 2, C IP2 / 2, C IN1 / 2, C IN2 / 2-Adjustable capacitor in the input capacitor network, C FP1 / 2, C FP2 / 2, C FN1 / 2, C FN2 / 2-adjustable capacitor in the feedback capacitor network, Ccp, Ccn-compensation capacitor, PAZ-zero adjustment switch, VAIN1, VAIP1-first pair of differential input terminals, VAIN2, VAIP2-second pair of differential input terminals, V CM1 -First common mode voltage, V CM2 - a second common mode voltage;

[0025] VIN, VIP - a pair of differential input signals, VOUTN, VOUTP - a pair of differential output signals, PCI1, PCI2, PCH1, PCH2 - chopping signals;

[0026] M0-first NMOS input tube, M1-second NMOS input tube, M2-first NMOS load tube, M3-second NMOS load tube, M4-first PMOS load tube, M5-second PMOS load tube, M6-first PMOS input tube, M7-second PMOS input tube;

[0027] VDD-power supply, GND-ground, Vbp-first bias voltage, Vbn-second bias voltage, Vout1, Vout2-differential output terminals of the input stage of the first fully differential amplifier, CMFB-common mode feedback voltage, I1-first current source, I2-second current source. DETAILED DESCRIPTION

[0028] The preferred embodiments of the present invention will be described in more detail below. Although the preferred embodiments of the present invention are described below, it should be understood that the present invention can be implemented in various forms and should not be limited to the embodiments set forth herein.

[0029] In the present invention, unless otherwise specified, the directional words used, such as "upper and lower", generally refer to the upper and lower parts of the device in normal use, and "inside and outside" refer to the outline of the device. In addition, the terms "first, second, third" are used for descriptive purposes only and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first, second, third" may explicitly or implicitly include one or more of the features. In the description of the present invention, "multiple" means two or more, unless otherwise clearly and specifically defined.

[0030] The present invention provides a low noise programmable amplifier, such as Figure 3 As shown, including:

[0031] A first fully differential amplifier Gm1 includes two pairs of differential input terminals;

[0032] The second fully differential amplifier Gm2 comprises a pair of differential input terminals, the pair of differential input terminals being electrically connected to the differential output terminals of the first fully differential amplifier Gm1 via the inter-stage chopper switch CPM;

[0033] A pair of input chopping switches, wherein a pair of input terminals of each input chopping switch is electrically connected to a pair of differential input signals VIN and VIP;

[0034] a pair of output chopping switches, wherein a pair of output terminals of each output chopping switch is electrically connected to the differential output terminals of the second fully differential amplifier Gm2;

[0035] an input capacitor network located between the output terminals of a pair of input chopping switches and the two pairs of differential input terminals;

[0036] a feedback capacitor network located between the input terminals of a pair of output chopping switches and the two pairs of differential input terminals;

[0037] A plurality of zero adjustment switches PAZ are located between the input and output of the first fully differential amplifier Gm1 and between the input / output terminal of the feedback capacitor network and the common mode voltage.

[0038] In the present invention, the first fully differential amplifier includes two pairs of differential input terminals, and the corresponding two transconductance amplifiers inside it share the same current. Compared with a single pair of differential input terminals, the overall transconductance is approximately doubled, which effectively reduces the overall noise of the amplifier and improves the current utilization efficiency and signal detection accuracy.

[0039] According to the present invention, Figure 4 As shown, the input stage of the first fully differential amplifier Gm1 includes:

[0040] A first current source I1, an input end of which is electrically connected to a power source VDD;

[0041] A pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source I1, and the gates serve as the second pair of differential input terminals VAIN2 and VAIP2 of the two pairs of differential input terminals;

[0042] A pair of PMOS load tubes, wherein the gates of the two PMOS load tubes are electrically connected to each other, and the voltage applied to the gates is a first bias voltage Vbp, the source of the first PMOS load tube M4 is electrically connected to the drain of the first PMOS input tube M6 of the pair of PMOS input tubes, and the source of the second PMOS load tube M5 is electrically connected to the drain of the second PMOS input tube M7 of the pair of PMOS input tubes;

[0043] A pair of NMOS load tubes, wherein the gates of the two NMOS load tubes are electrically connected to each other, and the voltage applied to the gates is the second bias voltage Vbn, the drain of the first NMOS load tube M2 is electrically connected to the drain of the first PMOS load tube M4, and the drain of the second NMOS load tube M3 is electrically connected to the drain of the second PMOS load tube M5;

[0044] A pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as the first pair of differential input terminals VAIN1 and VAIP1 of the two pairs of differential input terminals, the drain of the first NMOS input tube M0 is electrically connected to the source of the first NMOS load tube M2, and the drain of the second NMOS input tube M1 is electrically connected to the source of the second NMOS load tube M3;

[0045] A second current source I2, an input end of which is electrically connected to the sources of the two NMOS input tubes, and an output end of which is electrically connected to the ground GND;

[0046] The drain of the first NMOS load tube M2 and the drain of the second NMOS load tube M3 are electrically connected to the differential input terminal of the main amplifier stage of the first fully differential amplifier Gm1 as the differential output terminal of the input stage.

[0047] or,

[0048] The input stage of the first fully differential amplifier Gm1 comprises:

[0049] A first current source I1, an input end of which is electrically connected to a power source VDD;

[0050] A pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source I1, and the gates serve as the second pair of differential input terminals VAIN2 and VAIP2 of the two pairs of differential input terminals;

[0051] A pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as the first pair of differential input terminals VAIN1 and VAIP1 of the two pairs of differential input terminals, the drain of the first NMOS input tube M0 is electrically connected to the drain of the first PMOS input tube M6 of the two PMOS input tubes, and the drain of the second NMOS input tube M1 is electrically connected to the drain of the second PMOS input tube M7 of the two PMOS input tubes;

[0052] A second current source I2, an input end of which is electrically connected to the sources of the two NMOS input tubes, and an output end of which is electrically connected to the ground GND;

[0053] The drain of the first NMOS input tube M0 and the drain of the second NMOS input tube M1 are electrically connected to the differential input terminal of the main amplification stage of the first fully differential amplifier Gm1 as the differential output terminal of the input stage.

[0054] In the present invention, the gates of the two PMOS input tubes in a pair of PMOS input tubes can also be used as the first pair of differential input terminals VAIN1 and VAIP1 in the two pairs of differential input terminals, and the gates of the two NMOS input tubes in a pair of NMOS input tubes can be used as the second pair of differential input terminals VAIN2 and VAIP2 in the two pairs of differential input terminals; that is, the gate input signals of the two PMOS input tubes in a pair of PMOS input tubes and the gate input signals of the two NMOS input tubes in a pair of NMOS input tubes can be connected interchangeably.

[0055] According to the present invention, the first PMOS input tube M6, the first PMOS load tube M4, the first NMOS load tube M2 and the first NMOS input tube M0 are sequentially connected to form a current path;

[0056] The second PMOS input tube M7, the second PMOS load tube M5, the second NMOS load tube M3 and the second NMOS input tube M1 are sequentially connected to form a current path.

[0057] or,

[0058] The first PMOS input tube M6 and the first NMOS input tube M0 are sequentially connected to form a current path;

[0059] The second PMOS input tube M7 and the second NMOS input tube M1 are connected in sequence to form a current path.

[0060] In the present invention, the main amplifier stage of the first fully differential amplifier Gm1 may adopt a folded cascode structure or other existing amplifier structures.

[0061] In the present invention, the same current flows through a pair of PMOS input tubes and a pair of NMOS input tubes in the first fully differential amplifier at the same time, and the overall transconductance of the amplifier is equivalently increased. Compared with an amplifier with a single pair of input tubes, the noise is reduced by about 3dB.

[0062] According to the present invention, the working phase of each chopping switch in a pair of input chopping switches, a pair of output chopping switches and the inter-stage chopping switch CPM includes a CHP1 phase and a CHP2 phase;

[0063] The working phase of each switch in the plurality of zero adjustment switches PAZ is the AZ phase;

[0064] Each chopping switch in a pair of input chopping switches and interstage chopping switches CPM has two input terminals and two output terminals;

[0065] Each chopper switch in a pair of output chopper switches has an input terminal and two output terminals.

[0066] According to the present invention, one working cycle of the amplifier includes an AZ phase, a CHP1 phase and a CHP2 phase;

[0067] The AZ phase is used to establish the common-mode signal of the amplifier;

[0068] When the amplifier operates in the AZ phase, each of the multiple zeroing switches is closed;

[0069] When the amplifier operates in the CHP1 phase and the CHP2 phase, each of the multiple zeroing switches is disconnected;

[0070] The CHP1 phase is the in-phase chopping phase, and the CHP2 phase is the anti-phase chopping phase;

[0071] The amplifier completes programmed amplification of the signal by periodically alternating the CHP1 phase and the CHP2 phase in conjunction with the selection of capacitors in the input capacitor network and the feedback capacitor network.

[0072] In the present invention, the relationship between the chopping signals PCI1, PCI2, PCH1, PCH2 and the AZ phase, CHP1 phase and CHP2 phase is as follows: Figure 2 As shown, the timing decomposition of the relevant circuit and the working process of the circuit can be found in the embodiment of patent application CN114844479, which will not be repeated here.

[0073] According to the present invention, the two pairs of differential input terminals include two in-phase input terminals and two inverting input terminals;

[0074] Each output terminal of a first input chopping switch CPI1 in a pair of input chopping switches is electrically connected to two in-phase input terminals via a variable capacitor;

[0075] The two variable capacitors electrically connected to each non-inverting input terminal are equal in value;

[0076] Each output terminal of the second input chopping switch CPI2 of the pair of input chopping switches is electrically connected to the two inverting input terminals via a variable capacitor;

[0077] The two variable capacitors electrically connected to each inverting input terminal are equal in value;

[0078] All variable capacitors located between the output terminals of a pair of input chopping switches and the two pairs of differential input terminals form an input capacitor network;

[0079] Each variable capacitor in the input capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal.

[0080] Preferably, the input terminal of the first output chopper switch CPO1 in the pair of output chopper switches is electrically connected to the two in-phase input terminals via a variable capacitor respectively;

[0081] The input terminal of the second output chopper switch CPO2 in the pair of output chopper switches is electrically connected to the two inverting input terminals via a variable capacitor respectively;

[0082] The values ​​of two variable capacitors electrically connected to two input terminals of each pair of differential input terminals are equal;

[0083] All variable capacitors located between the input terminals of a pair of output chopping switches and the two pairs of differential input terminals form a feedback capacitor network;

[0084] Each variable capacitor in the feedback capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal.

[0085] According to the present invention, a plurality of zeroing switches PAZ comprises:

[0086] a switch located between an inverting output terminal and a first non-inverting input terminal of the first fully differential amplifier Gm1;

[0087] a switch located between a non-inverting output terminal and a first inverting input terminal of the first fully differential amplifier Gm1;

[0088] At the first common mode voltage V CM1 A switch between an input terminal of a first input chopping switch CPI1;

[0089] At the first common mode voltage V CM1 A switch between an input terminal of a second input chopping switch CPI2;

[0090] At the second common mode voltage V CM2 a switch between the second of the two non-inverting input terminals;

[0091] At the second common mode voltage V CM2 A switch between the second of the two inverting inputs.

[0092] According to the present invention, two output terminals of each output chopping switch in a pair of output chopping switches are electrically connected to two differential output terminals of the second fully differential amplifier Gm2, respectively.

[0093] According to the present invention, compensation capacitors Ccp and Ccn are provided between the non-inverting input terminal and the inverting output terminal, and between the inverting input terminal and the non-inverting output terminal of the second fully differential amplifier Gm2.

[0094] The present invention will be described in more detail below through specific embodiments. Example

[0095] like Figure 3 As shown, this embodiment provides a low-noise programmable amplifier, a first fully differential amplifier Gm1, comprising two pairs of differential input terminals;

[0096] The second fully differential amplifier Gm2 comprises a pair of differential input terminals, the pair of differential input terminals being electrically connected to the differential output terminals of the first fully differential amplifier Gm1 via the inter-stage chopper switch CPM;

[0097] A pair of input chopping switches, wherein a pair of input terminals of each input chopping switch is electrically connected to a pair of differential input signals VIN and VIP;

[0098] a pair of output chopping switches, wherein a pair of output terminals of each output chopping switch is electrically connected to the differential output terminals of the second fully differential amplifier Gm2;

[0099] an input capacitor network located between the output terminals of a pair of input chopping switches and the two pairs of differential input terminals;

[0100] a feedback capacitor network located between the input terminals of a pair of output chopping switches and the two pairs of differential input terminals;

[0101] A plurality of zero adjustment switches PAZ, located between the input and output of the first fully differential amplifier Gm1, and between the input / output end of the feedback capacitor network and the common mode voltage;

[0102] In this embodiment, Figure 4 As shown, the input stage of the first fully differential amplifier Gm1 includes:

[0103] A first current source I1, an input end of which is electrically connected to a power source VDD;

[0104] A pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source I1, and the gates serve as the second pair of differential input terminals VAIN2 and VAIP2 of the two pairs of differential input terminals;

[0105] A pair of PMOS load tubes, wherein the gates of the two PMOS load tubes are electrically connected to each other, and the voltage applied to the gates is a first bias voltage Vbp, the source of the first PMOS load tube M4 is electrically connected to the drain of the first PMOS input tube M6 of the pair of PMOS input tubes, and the source of the second PMOS load tube M5 is electrically connected to the drain of the second PMOS input tube M7 of the pair of PMOS input tubes;

[0106] A pair of NMOS load tubes, wherein the gates of the two NMOS load tubes are electrically connected to each other, and the voltage applied to the gates is the second bias voltage Vbn, the drain of the first NMOS load tube M2 is electrically connected to the drain of the first PMOS load tube M4, and the drain of the second NMOS load tube M3 is electrically connected to the drain of the second PMOS load tube M5;

[0107] A pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as the first pair of differential input terminals VAIN1 and VAIP1 of the two pairs of differential input terminals, the drain of the first NMOS input tube M0 is electrically connected to the source of the first NMOS load tube M2, and the drain of the second NMOS input tube M1 is electrically connected to the source of the second NMOS load tube M3;

[0108] A second current source I2, an input end of which is electrically connected to the sources of the two NMOS input tubes, and an output end of which is electrically connected to the ground GND;

[0109] The drain of the first NMOS load tube M2 and the drain of the second NMOS load tube M3 are electrically connected to the differential input terminal of the main amplifier stage of the first fully differential amplifier Gm1 as the differential output terminal of the input stage;

[0110] In this embodiment, the first PMOS input tube M6, the first PMOS load tube M4, the first NMOS load tube M2 and the first NMOS input tube M0 are sequentially connected to form a current path;

[0111] The second PMOS input tube M7, the second PMOS load tube M5, the second NMOS load tube M3 and the second NMOS input tube M1 are sequentially connected to form a current path;

[0112] In this embodiment, the main amplifier stage of the first fully differential amplifier Gm1 adopts an existing folded cascode structure (not shown);

[0113] In this embodiment, the working phase of each chopper switch in the pair of input chopper switches, the pair of output chopper switches and the inter-stage chopper switch CPM includes a CHP1 phase and a CHP2 phase;

[0114] The working phase of each switch in the plurality of zero adjustment switches PAZ is the AZ phase;

[0115] Each chopping switch in a pair of input chopping switches and interstage chopping switches CPM has two input terminals and two output terminals;

[0116] Each chopper switch in a pair of output chopper switches has an input terminal and two output terminals;

[0117] In this embodiment, one working cycle of the amplifier includes an AZ phase, a CHP1 phase and a CHP2 phase;

[0118] The AZ phase is used to establish the common-mode signal of the amplifier;

[0119] When the amplifier operates in the AZ phase, each of the multiple zeroing switches is closed;

[0120] When the amplifier operates in the CHP1 phase and the CHP2 phase, each of the multiple zeroing switches is disconnected;

[0121] The CHP1 phase is the in-phase chopping phase, and the CHP2 phase is the anti-phase chopping phase;

[0122] The amplifier completes the programmed amplification of the signal through the periodic alternation of CHP1 phase and CHP2 phase and the selection of capacitors in the input capacitor network and the feedback capacitor network;

[0123] In this embodiment, the relationship between the chopping signals PCI1, PCI2, PCH1, PCH2 and the AZ phase, CHP1 phase and CHP2 phase is as follows: Figure 2 As shown, the timing decomposition of the circuit and the working process of the circuit refer to the embodiment of patent application CN114844479, which will not be repeated here;

[0124] In this embodiment, the two pairs of differential input terminals include two in-phase input terminals and two inverting input terminals;

[0125] Each output terminal of a first input chopping switch CPI1 in a pair of input chopping switches is electrically connected to two in-phase input terminals via a variable capacitor;

[0126] The two variable capacitors electrically connected to each non-inverting input terminal are equal in value;

[0127] Each output terminal of the second input chopping switch CPI2 of the pair of input chopping switches is electrically connected to the two inverting input terminals via a variable capacitor;

[0128] The two variable capacitors electrically connected to each inverting input terminal are equal in value;

[0129] All variable capacitors located between the output terminals of a pair of input chopping switches and the two pairs of differential input terminals form an input capacitor network;

[0130] Each variable capacitor in the input capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal;

[0131] In this embodiment, the input terminal of the first output chopper switch CPO1 in the pair of output chopper switches is electrically connected to the two in-phase input terminals via a variable capacitor respectively;

[0132] The input terminal of the second output chopper switch CPO2 in the pair of output chopper switches is electrically connected to the two inverting input terminals via a variable capacitor respectively;

[0133] The values ​​of two variable capacitors electrically connected to two input terminals of each pair of differential input terminals are equal;

[0134] All variable capacitors located between the input terminals of a pair of output chopping switches and the two pairs of differential input terminals form a feedback capacitor network;

[0135] Each variable capacitor in the feedback capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal;

[0136] In this embodiment, the plurality of zero adjustment switches PAZ include:

[0137] a switch located between an inverting output terminal and a first non-inverting input terminal of the first fully differential amplifier Gm1;

[0138] a switch located between a non-inverting output terminal and a first inverting input terminal of the first fully differential amplifier Gm1;

[0139] At the first common mode voltage V CM1 A switch between an input terminal of a first input chopping switch CPI1;

[0140] At the first common mode voltage V CM1 A switch between an input terminal of a second input chopping switch CPI2;

[0141] At the second common mode voltage V CM2 a switch between the second of the two non-inverting input terminals;

[0142] At the second common mode voltage V CM2 a switch between the second inverting input terminal and the two inverting input terminals;

[0143] In this embodiment, the two output terminals of each output chopper switch in a pair of output chopper switches are electrically connected to the two differential output terminals of the second fully differential amplifier Gm2 respectively;

[0144] In this embodiment, compensation capacitors Ccp and Ccn are provided between the non-inverting input terminal and the inverting output terminal, and between the inverting input terminal and the non-inverting output terminal of the second fully differential amplifier Gm2;

[0145] In this embodiment, Figure 4 As shown, the first NMOS input tube M0 and the second NMOS input tube M1 form Gm1A, the first PMOS input tube M6 and the second PMOS input tube M7 form Gm1B, and the same current flows through the N input pair and the P input pair at the same time. The transconductance of the amplifier is equivalently increased, which is equivalent to Gm x 2, and the noise is reduced by about 3dB.

[0146] Since Gm1A and Gm1B are implemented by two input pairs (PMOS input pair and NMOS input pair), different operating voltages need to be set, and the gain capacitor is split in half, C IP1 , C IN1 , C FP1 , C FN1 For the first group of capacitors, corresponding to Gm1A; C IP2 , C IN2 , C FP2 , C FN2The second group of capacitors is connected to Gm1B; the first group of capacitors is combined with Gm1A for auto-zero, and the second group of capacitors is combined with Gm1B for reset. At the same time, the first common-mode voltage V of the two groups of capacitors at the Gm1 input stage is set. CM1 and the second common mode voltage V CM2 . Example

[0147] The rest of this embodiment is the same as that of embodiment 1, except that Figure 5 As shown, the input stage of the first fully differential amplifier Gm1 includes:

[0148] A first current source I1, an input end of which is electrically connected to a power source VDD;

[0149] A pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source I1, and the gates serve as the second pair of differential input terminals VAIN2 and VAIP2 of the two pairs of differential input terminals;

[0150] A pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as the first pair of differential input terminals VAIN1 and VAIP1 of the two pairs of differential input terminals, the drain of the first NMOS input tube M0 is electrically connected to the drain of the first PMOS input tube M6 of the two PMOS input tubes, and the drain of the second NMOS input tube M1 is electrically connected to the drain of the second PMOS input tube M7 of the two PMOS input tubes;

[0151] A second current source I2, an input end of which is electrically connected to the sources of the two NMOS input tubes, and an output end of which is electrically connected to the ground GND;

[0152] The drain of the first NMOS input tube M0 and the drain of the second NMOS input tube M1 are electrically connected to the differential input terminal of the main amplifier stage of the first fully differential amplifier Gm1 as the differential output terminal of the input stage;

[0153] The first PMOS input tube M6 and the first NMOS input tube M0 are sequentially connected to form a current path;

[0154] The second PMOS input tube M7 and the second NMOS input tube M1 are connected in sequence to form a current path.

[0155] The low-noise programmable amplifier proposed in an embodiment of the present invention, the first fully differential amplifier includes two pairs of differential input terminals, and the corresponding two transconductance amplifiers inside it share the same current. Compared with a single pair of differential input terminals, the overall transconductance is approximately doubled, which effectively reduces the overall noise of the amplifier and improves the current utilization efficiency and signal detection accuracy.

[0156] The embodiments of the present invention have been described above, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many modifications and changes will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments.

Claims

1. A low noise programmable amplifier, characterized in that: include: A first fully differential amplifier includes two pairs of differential input terminals; A second fully differential amplifier, comprising a pair of differential input terminals, the pair of differential input terminals being electrically connected to the differential output terminals of the first fully differential amplifier via an inter-stage chopper switch; a pair of input chopping switches, wherein a pair of input terminals of each input chopping switch is electrically connected to a pair of differential input signals; a pair of output chopping switches, wherein a pair of output terminals of each output chopping switch is electrically connected to the differential output terminals of the second fully differential amplifier; an input capacitor network located between the output terminals of the pair of input chopping switches and the two pairs of differential input terminals; a feedback capacitor network located between the input terminals of the pair of output chopping switches and the two pairs of differential input terminals; a plurality of zeroing switches, located between the input and output of the first fully differential amplifier and between the input / output end of the feedback capacitor network and the common mode voltage; The input stage of the first fully differential amplifier comprises: A first current source, an input end of which is electrically connected to a power supply; a pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source, and the gates serve as the second pair of differential input ends of the two pairs of differential input ends; A pair of PMOS load tubes, wherein the gates of the two PMOS load tubes are electrically connected to each other, and the voltage applied to the gates is a first bias voltage, the source of the first PMOS load tube is electrically connected to the drain of the first PMOS input tube of the pair of PMOS input tubes, and the source of the second PMOS load tube is electrically connected to the drain of the second PMOS input tube of the pair of PMOS input tubes; A pair of NMOS load tubes, wherein the gates of the two NMOS load tubes are electrically connected to each other, and the voltage applied to the gates is a second bias voltage, the drain of the first NMOS load tube is electrically connected to the drain of the first PMOS load tube, and the drain of the second NMOS load tube is electrically connected to the drain of the second PMOS load tube; A pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as a first pair of differential input terminals of the two pairs of differential input terminals, the drain of the first NMOS input tube is electrically connected to the source of the first NMOS load tube, and the drain of the second NMOS input tube is electrically connected to the source of the second NMOS load tube; A second current source, the input end of which is electrically connected to the sources of the two NMOS input tubes, and the output end of which is electrically connected to the ground; The drain of the first NMOS load tube and the drain of the second NMOS load tube are electrically connected to the differential input terminal of the main amplifier stage of the first fully differential amplifier as the differential output terminal of the input stage. or, The input stage of the first fully differential amplifier comprises: A first current source, an input end of which is electrically connected to a power supply; a pair of PMOS input tubes, wherein the sources of the two PMOS input tubes are electrically connected to the output end of the first current source, and the gates serve as the second pair of differential input ends of the two pairs of differential input ends; a pair of NMOS input tubes, wherein the gates of the two NMOS input tubes serve as a first pair of differential input terminals of the two pairs of differential input terminals, the drain of the first NMOS input tube is electrically connected to the drain of the first PMOS input tube of the two PMOS input tubes, and the drain of the second NMOS input tube is electrically connected to the drain of the second PMOS input tube of the two PMOS input tubes; A second current source, the input end of which is electrically connected to the sources of the two NMOS input tubes, and the output end of which is electrically connected to the ground; The drain of the first NMOS input tube and the drain of the second NMOS input tube are electrically connected to the differential input end of the main amplification stage of the first fully differential amplifier as the differential output end of the input stage.

2. The amplifier according to claim 1, characterized in that The first PMOS input tube, the first PMOS load tube, the first NMOS load tube and the first NMOS input tube are sequentially connected to form a current path; The second PMOS input tube, the second PMOS load tube, the second NMOS load tube and the second NMOS input tube are sequentially connected to form a current path, or, The first PMOS input tube and the first NMOS input tube are sequentially connected to form a current path; The second PMOS input tube and the second NMOS input tube are connected in sequence to form a current path.

3. The amplifier according to claim 1, characterized in that The working phase of each chopper switch in the pair of input chopper switches, the pair of output chopper switches and the inter-stage chopper switch includes a CHP1 phase and a CHP2 phase; The working phase of each switch in the plurality of zero adjustment switches is an AZ phase; Each chopper switch in the pair of input chopper switches and interstage chopper switches has two input terminals and two output terminals; Each chopper switch of the pair of output chopper switches has one input terminal and two output terminals.

4. The amplifier according to claim 3, characterized in that One working cycle of the amplifier includes an AZ phase, a CHP1 phase and a CHP2 phase; The AZ phase is used to establish a common mode signal of the amplifier; When the amplifier operates in the AZ phase, each of the plurality of zeroing switches is closed; When the amplifier operates in the CHP1 phase and the CHP2 phase, each of the plurality of zeroing switches is disconnected; The CHP1 phase is an in-phase chopping phase, and the CHP2 phase is an anti-phase chopping phase; The amplifier completes programmed amplification of the signal by periodically alternating the CHP1 phase and the CHP2 phase in coordination with the selection of capacitors in the input capacitor network and the feedback capacitor network.

5. The amplifier according to claim 3, characterized in that The two pairs of differential input terminals include two in-phase input terminals and two inverting input terminals; Each output terminal of the first input chopping switch of the pair of input chopping switches is electrically connected to two in-phase input terminals via a variable capacitor; The two variable capacitors electrically connected to each non-inverting input terminal are equal in value; Each output terminal of the second input chopping switch of the pair of input chopping switches is electrically connected to the two inverting input terminals via a variable capacitor; The two variable capacitors electrically connected to each inverting input terminal are equal in value; All variable capacitors located between the output terminals of the pair of input chopping switches and the two pairs of differential input terminals form the input capacitor network; Each variable capacitor in the input capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal.

6. The amplifier according to claim 5, characterized in that The input end of the first output chopper switch of the pair of output chopper switches is electrically connected to the two in-phase input ends via a variable capacitor respectively; The input end of the second output chopper switch of the pair of output chopper switches is electrically connected to the two inverting input ends via a variable capacitor respectively; The values ​​of two variable capacitors electrically connected to two input terminals of each pair of differential input terminals are equal; All variable capacitors located between the input terminals of the pair of output chopping switches and the two pairs of differential input terminals form the feedback capacitor network; Each variable capacitor in the feedback capacitor network is composed of a weighted capacitor array, and the value of each variable capacitor is obtained by selecting a corresponding weighted capacitor through a digital signal.

7. The amplifier according to claim 6, characterized in that The plurality of zeroing switches include: a switch located between the inverting output terminal of the first fully differential amplifier and the first of the two non-inverting input terminals; a switch located between the non-inverting output terminal of the first fully differential amplifier and the first inverting input terminal of the two inverting input terminals; a switch between a first common mode voltage and an input terminal of said first input chopping switch; a switch between the first common mode voltage and the input of the second input chopping switch; a switch located between the second common mode voltage and a second one of the two non-inverting input terminals; A switch is located between the second common mode voltage and a second one of the two inverting input terminals.

8. The amplifier according to claim 2, characterized in that Two output terminals of each output chopping switch in the pair of output chopping switches are electrically connected to two differential output terminals of the second fully differential amplifier, respectively.

9. The amplifier according to claim 1, characterized in that Compensation capacitors are provided between the non-inverting input terminal and the inverting output terminal, and between the inverting input terminal and the non-inverting output terminal of the second fully differential amplifier.

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