PWM wave adjusting circuit and electronic equipment
By designing the adjustment circuit of PWM waves, using the first adjustment unit to flip the original PWM signal, and adjusting the voltage through the peak and trough adjustment module of the second adjustment unit, the problem of the inability to adjust the peak and trough voltage of the PWM signal in the prior art is solved, and the input and output requirements for different electronic devices are met.
Patent Information
- Application Number
- CN202411647925.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-11-18
- Publication Date
- 2025-03-07
AI Technical Summary
The prior art cannot adjust the peak voltage and trough voltage of the PWM signal, resulting in the inability to meet the requirements of different electronic devices for signal input and output.
A PWM wave adjustment circuit is designed, including a first adjustment unit and a second adjustment unit. The first adjustment unit flips the input original PWM signal to obtain the first PWM signal. The second adjustment unit includes a peak adjustment module and a trough adjustment module through which the voltages of the trough and the peak signal of the first PWM signal are adjusted under different conditions.
The independent adjustment of the peak and trough voltage of the PWM signal is achieved, which meets the requirements of different electronic devices for signal input and output, and solves the problem that the peak and trough voltage of the PWM signal cannot be adjusted in the prior art.
Smart Images
Figure CN119582818A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the technical field of PWM wave regulation, and in particular to a PWM wave regulation circuit and electronic equipment. Background Art
[0002] With the continuous development of electronic technology, various types of semiconductor devices are gradually increasing. In order to meet the requirements of different electronic devices for signal input and output and the needs in application scenarios, various conversions and transformations of circuit signals are required.
[0003] PWM technology is a digital electronic switching circuit signal technology. The signal is generally generated by an electronic switching device. Its waveform characteristics are divided into peaks and troughs. The peak is the high-level logic of PWM, and the trough is the low-level logic of PWM. Different circuit interfaces or electronic components have different level logic voltages for PWM input and output. This requires an intermediate conversion circuit to meet the input and output of different components to achieve voltage level conversion of peaks and troughs. Traditionally, this special signal conversion circuit is only a single peak or trough conversion, usually a small part of an integrated circuit or a unit circuit, and is integrated into various finished chips. There are almost no separate PWM peak and trough conversion chips on the market.
[0004] Therefore, there is an urgent need for a circuit that ensures that the voltages of the PWM peaks and valleys are adjustable. Summary of the invention
[0005] The main purpose of the present application is to provide a PWM wave adjustment circuit and electronic device to at least solve the problem in the prior art that both the peak voltage and the valley voltage of the PWM signal cannot be adjusted.
[0006] In order to achieve the above-mentioned purpose, according to one aspect of the present application, a PWM wave adjustment circuit is provided, the adjustment circuit comprising a first adjustment unit and a second adjustment unit; the first adjustment unit comprises an input end and an output end, wherein the input end of the first adjustment unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first adjustment unit, and the waveform of the first PWM signal is opposite to that of the input PWM signal; the second adjustment unit is electrically connected to the output end of the first adjustment unit, the second adjustment unit comprises a peak adjustment module and a valley adjustment module, the input end of the peak adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs the valley signal to obtain the peak signal of the second PWM signal, the input end of the valley adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the peak signal of the first PWM signal when the first adjustment unit outputs the peak signal to obtain the valley signal of the second PWM signal, and the output end of the valley adjustment module is electrically connected to the output end of the peak adjustment module and serves as the output end of the second adjustment unit.
[0007] Optionally, the first regulating unit includes a flip module and a first resistor module; the flip module includes a first NMOS tube, the gate of the first NMOS tube is used to input the original PWM signal, and the source of the first NMOS tube is grounded; the first end of the first resistor module is used to input the power supply voltage, and the second end of the first resistor module is electrically connected to the drain of the first NMOS tube.
[0008] Optionally, the flip module further includes a first parasitic diode, an anode of the first parasitic diode is electrically connected to the source of the first NMOS tube, and a cathode of the first parasitic diode is electrically connected to the drain of the first NMOS tube.
[0009] Optionally, the first regulating unit further includes a second resistance module, a first end of the second resistance module is electrically connected to the gate of the flip module, and a second end of the second resistance module is grounded.
[0010] Optionally, the first regulating unit further includes a third resistance module, and the third resistance module is connected to a connecting branch between the gate of the flip module and the first end of the second resistance module.
[0011] Optionally, the peak adjustment module includes a fourth resistor module, a first PMOS tube, a fifth resistor module, a second PMOS tube and a first potentiometer; the first end of the fourth resistor module is electrically connected to the output end of the first adjustment unit; the gate of the first PMOS tube is electrically connected to the second end of the fourth resistor module; the first end of the fifth resistor module is electrically connected to the output end of the first adjustment unit; the gate of the second PMOS tube is electrically connected to the second end of the fifth resistor module, the drain of the second PMOS tube is electrically connected to the drain of the first PMOS tube, and the source of the second PMOS tube is the output end of the peak adjustment module; the first end of the first potentiometer is used to input the power supply voltage, the second end of the first potentiometer is grounded, and the adjustable end of the potentiometer is electrically connected to the source of the first PMOS tube.
[0012] Optionally, the peak adjustment module further includes a first capacitor module and a sixth resistor module; the first end of the first capacitor module is used to input the power supply voltage, and the second end of the first capacitor module is grounded; the first end of the sixth resistor module is electrically connected to the second end of the first potentiometer, and the second end of the sixth resistor module is grounded.
[0013] Optionally, the valley adjustment module includes a seventh resistor module, a second NMOS tube and a second potentiometer; the first end of the seventh resistor module is electrically connected to the output end of the first adjustment unit; the gate of the second NMOS tube is electrically connected to the second end of the seventh resistor module, and the drain of the second NMOS tube is the output end of the valley adjustment module; the first end of the second potentiometer is used to input the power supply voltage, the second end of the second potentiometer is grounded, and the adjustable end of the second potentiometer is electrically connected to the source of the second NMOS tube.
[0014] Optionally, the above-mentioned valley adjustment module also includes a second capacitor module and an eighth resistor module; the first end of the above-mentioned second capacitor module is used to input the above-mentioned power supply voltage, and the second end of the above-mentioned second capacitor module is grounded; the first end of the above-mentioned eighth resistor module is used to input the power supply voltage, and the second end of the above-mentioned eighth resistor module is electrically connected to the first end of the above-mentioned second potentiometer.
[0015] Optionally, the PWM wave adjustment circuit also includes a voltage following unit, which includes a ninth resistor module, an operational amplifier, a third capacitor module and a fourth capacitor module; the first end of the ninth resistor module is connected to the output end of the second adjustment unit; the positive input end of the operational amplifier is connected to the second end of the ninth resistor module, the negative input end of the operational amplifier is electrically connected to the output end of the operational amplifier, and the output end of the operational amplifier is the output end of the PWM wave adjustment circuit; the first end of the third capacitor module is electrically connected to the negative input end of the operational amplifier, and the second end of the third capacitor module is grounded; the first end of the fourth capacitor module is electrically connected to the positive input end of the operational amplifier, and the second end of the fourth capacitor module is grounded.
[0016] According to another aspect of the present application, an electronic device is provided, and the electronic device includes any one of the above-mentioned PWM wave adjustment circuits.
[0017] By applying the technical solution of the present application, the PWM wave adjustment circuit includes a first adjustment unit and a second adjustment unit, wherein the input end of the first adjustment unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first adjustment unit; the second adjustment unit is electrically connected to the output end of the first adjustment unit, and the second adjustment unit includes a peak adjustment module and a valley adjustment module, wherein the input end of the peak adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a valley signal to obtain a peak signal of the second PWM signal, and the input end of the valley adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a peak signal to obtain a peak signal of the second PWM signal. The voltage of the peak signal of the above-mentioned first PWM signal is adjusted to obtain the valley signal of the second PWM signal. Compared with the prior art, the solution of the present application utilizes a first adjustment unit to flip the original PWM signal to obtain the first PWM signal, and inputs the first PWM signal to the second adjustment unit. When the input first PWM signal is a valley signal, the peak adjustment module of the second adjustment unit flips the valley signal into a peak signal and adjusts the voltage of the peak signal. When the input first PWM signal is a peak signal, the valley adjustment module of the second adjustment unit flips the peak signal into a valley signal and adjusts the voltage of the valley signal. In this way, both the peak voltage and the valley voltage can be adjusted, thereby further solving the problem that both the peak voltage and the valley voltage of the PWM signal cannot be adjusted in the prior art. BRIEF DESCRIPTION OF THE DRAWINGS
[0018] The drawings constituting part of the present application are used to provide a further understanding of the present application. The exemplary embodiments and descriptions of the present application are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:
[0019] Figure 1 A schematic diagram of a PWM wave adjustment circuit provided according to an embodiment of the present application is shown;
[0020] Figure 2 A circuit diagram of a PWM wave adjustment circuit provided according to an embodiment of the present application is shown;
[0021] Figure 3 A PWM wave peak and trough adjustment diagram of a PWM wave adjustment circuit provided according to an embodiment of the present application is shown;
[0022] The above drawings include the following reference numerals:
[0023] 100, first regulating unit; 110, flip module; 200, second regulating unit; 210, peak regulating module; 220, trough regulating module; 300, voltage following unit. DETAILED DESCRIPTION
[0024] It should be noted that the following detailed descriptions are all illustrative and are intended to provide optional descriptions of the present application. Unless otherwise specified, all technical and scientific terms used herein have the same meanings as those commonly understood by those skilled in the art to which the present application belongs.
[0025] It should be noted that the terms used herein are only for describing specific embodiments and are not intended to limit the exemplary embodiments according to the present application. As used herein, unless the context clearly indicates otherwise, the singular form is also intended to include the plural form. In addition, it should be understood that when the terms "comprise" and / or "include" are used in this specification, it indicates the presence of features, steps, operations, devices, components and / or combinations thereof.
[0026] It should be understood that when an element (such as a layer, film, region, or substrate) is described as being "on" another element, the element may be directly on the other element, or there may be intermediate elements. Moreover, in the specification and claims, when an element is described as being "connected" to another element, the element may be "directly connected" to the other element, or "connected" to the other element through a third element.
[0027] As introduced in the background technology, the prior art lacks a method for adjusting both the peak voltage and the valley voltage of the PWM signal. In order to solve the above problem, the present application proposes a PWM wave adjustment circuit and electronic device.
[0028] According to an embodiment of the present application, a PWM wave adjustment circuit is provided, such as Figure 1 As shown, the PWM wave adjustment circuit includes a first adjustment unit 100 and a second adjustment unit 200; Figure 2 As shown, the first regulating unit 100 includes an input end and an output end, wherein the input end of the first regulating unit 100 is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first regulating unit, and the waveform of the first PWM signal is opposite to that of the input PWM signal; the second regulating unit 200 is electrically connected to the output end of the first regulating unit 100, and the second regulating unit 200 includes a peak regulating module 210 and a trough regulating module 220, and the input end of the peak regulating module 210 is connected to the output end of the first regulating unit 100 and is used to When the first regulating unit 100 outputs a valley signal, the voltage of the valley signal of the first PWM signal is adjusted to obtain a peak signal of the second PWM signal. The input end of the valley regulating module 220 is connected to the output end of the first regulating unit 100 and is used to adjust the voltage of the peak signal of the first PWM signal to obtain a valley signal of the second PWM signal when the first regulating unit 100 outputs a peak signal. The output end of the valley regulating module 220 is electrically connected to the output end of the peak regulating module 210 and serves as the output end of the second regulating unit 200.
[0029] Specifically, the PWM input signal is driven by the first regulating unit 100 to perform signal amplification and flipping, and the output of the first regulating unit 100 is used as the input of the second regulating unit 200. The second regulating unit 200 mainly realizes stepless adjustment and flipping. The peak regulation module 210 mainly realizes stepless adjustment of the level voltage of the PWM pulse peak. The trough regulation module 220 mainly realizes stepless adjustment of the level voltage of the PWM pulse trough. Therefore, the signal is input from the first regulating unit 100 to the second regulating unit 200 and output after two level flips. The signal polarity remains unchanged, that is, the level voltage of the PWM pulse peak and trough is steplessly adjustable.
[0030] The PWM wave adjustment circuit includes a first adjustment unit and a second adjustment unit. The input end of the first adjustment unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first adjustment unit. The second adjustment unit is electrically connected to the output end of the first adjustment unit. The second adjustment unit includes a peak adjustment module and a valley adjustment module. The input end of the peak adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a valley signal to obtain a peak signal of the second PWM signal. The input end of the valley adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a peak signal to obtain a peak signal of the second PWM signal. The voltage of the peak signal of the first PWM signal is obtained to obtain the valley signal of the second PWM signal. Compared with the prior art, the solution of the present application utilizes the first adjustment unit to flip the original PWM signal to obtain the first PWM signal, and inputs the first PWM signal to the second adjustment unit. When the input first PWM signal is a valley signal, the peak adjustment module of the second adjustment unit flips the valley signal into a peak signal and adjusts the voltage of the peak signal. When the input first PWM signal is a peak signal, the valley adjustment module of the second adjustment unit flips the peak signal into a valley signal and adjusts the voltage of the valley signal. In this way, both the peak voltage and the valley voltage can be adjusted, thereby further solving the problem that both the peak voltage and the valley voltage of the PWM signal cannot be adjusted in the prior art.
[0031] In one embodiment of the present application, Figure 2 As shown, the first regulating unit 100 includes a flip module 110 and a first resistor module R4; the flip module 110 includes a first NMOS tube NMOS_1, the gate of the first NMOS tube NMOS_1 is used to input the original PWM signal, and the source of the first NMOS tube NMOS_1 is grounded; the first end of the first resistor module R4 is used to input the power supply voltage, and the second end of the first resistor module R4 is electrically connected to the drain of the first NMOS tube NMOS_1. In this embodiment, the voltage of the original PWM signal is flipped more accurately through the formation of the flip module 110 and the first resistor module R4.
[0032] In order to further enhance the stability and reliability of the flip module 110, in one embodiment of the present application, Figure 2 As shown, the flip module 110 further includes a first parasitic diode Q4, an anode of the first parasitic diode Q4 is electrically connected to the source of the first NMOS transistor NMOS_1, and a cathode of the first parasitic diode Q4 is electrically connected to the drain of the first NMOS transistor NMOS_1.
[0033] In another example, if Figure 2 As shown, the first regulating unit 100 further includes a second resistor module R7, a first end of the second resistor module R7 is electrically connected to the gate of the flip module 110, and a second end of the second resistor module R7 is grounded. In this embodiment, when the input PWM signal is in a suspended state, the second resistor module R7 can be used to determine the input voltage Vin of the circuit to be 0, thereby further realizing the regulation and control of the input voltage Vin of the circuit.
[0034] In order to further protect the flip module, in an embodiment of the present application, the first adjustment unit 100 further includes a third resistance module R6, and the third resistance module R6 is connected to a connection branch between the gate of the flip module 110 and the first end of the second resistance module R7.
[0035] Specifically, the second resistance module R7, the third resistance module R6, the first resistance module R4, the first NMOS tube NMOS_1 and the first parasitic diode Q4 constitute the first adjustment unit 100. The first parasitic diode Q4 can amplify the input PWM signal through the switch and flip the signal. The second resistance module R7 is an input pull-down resistor, which can achieve that when the input PWM signal is a high-impedance input, the input circuit can maintain a clear low-level state. The first resistance module R4 is used as an output pull-up resistor for voltage conversion.
[0036] In yet another embodiment, Figure 2As shown, the peak adjustment module 210 includes a fourth resistor module R2, a first PMOS tube PMOS_1, a fifth resistor module R3, a second PMOS tube PMOS_2 and a first potentiometer R1; the first end of the fourth resistor module R2 is electrically connected to the output end of the first adjustment unit 100; the gate of the first PMOS tube PMOS_1 is electrically connected to the second end of the fourth resistor module R2; the first end of the fifth resistor module R3 is electrically connected to the output end of the first adjustment unit 100; the gate of the second PMOS tube PMOS_2 is electrically connected to the second end of the fifth resistor module R3, the drain of the second PMOS tube PMOS_2 is electrically connected to the drain of the first PMOS tube PMOS_1, and the source of the second PMOS tube PMOS_2 is the output end of the peak adjustment module 210; the first end of the first potentiometer R1 is used to input the power supply voltage, the second end of the first potentiometer R1 is grounded, and the adjustable end of the potentiometer R1 is electrically connected to the source of the first PMOS tube PMOS_1. In this embodiment, the first PMOS transistor PMOS_1 is used to further modulate and convert the first PWM signal, and the peak level voltage of the PWM waveform is more accurately adjusted by adjusting the value of the first potentiometer R1.
[0037] In order to further solve the forbidden adjustment range of the first potentiometer R1, in one embodiment of the present application, as Figure 2 As shown, the above-mentioned peak adjustment module also includes a first capacitor module C1 and a sixth resistor module R10; the first end of the above-mentioned first capacitor module C1 is used to input the above-mentioned power supply voltage, and the second end of the above-mentioned first capacitor module C1 is grounded; the first end of the above-mentioned sixth resistor module R10 is electrically connected to the second end of the above-mentioned first potentiometer R1, and the second end of the above-mentioned sixth resistor module R10 is grounded.
[0038] Specifically, for the source voltage V p It is equal to the first potentiometer R1 adjusting the output voltage. According to the voltage division principle, we have:
[0039]
[0040] Among them, R 1调 is the resistance value after the adjustable resistor is adjusted. Its function is to adjust the voltage level of the PWM wave peak. VCC is the power supply voltage. The conversion can obtain the source voltage V of the first potentiometer R1. p :
[0041]
[0042] Since the first potentiometer R1 is in the upper voltage division, R 1调The maximum value is R1, so V P The range is If the conduction condition of Q1 tube needs to be met, VQ1 must be met g -V P <VQ1 gs , where VQ1 g is the gate G input voltage of the first PMOS tube PMOS_1, VQ1 gs It is the minimum threshold voltage for the first PMOS tube PMOS_1 to conduct. At this time, the voltage at point T2 in the circuit is VCC, that is, VQ1 g =VCC, so choose R 10 The size needs to meet:
[0043]
[0044] Right now
[0045]
[0046] When the condition is met, when the gate voltage of the first PMOS tube PMOS_1 is 0, the first PMOS tube PMOS_1 is turned on, and when the gate voltage of the first PMOS tube PMOS_1 is VCC, the first PMOS tube PMOS_1 is not turned on.
[0047] In yet another embodiment, Figure 2 As shown, the valley adjustment module 220 includes a seventh resistor module R5, a second NMOS tube NMOS_2 and a second potentiometer R8; the first end of the seventh resistor module R5 is electrically connected to the output end of the first adjustment unit 100; the gate of the second NMOS tube is electrically connected to the second end of the seventh resistor module, and the drain of the second NMOS tube NMOS_2 is the output end of the valley adjustment module 220; the first end of the second potentiometer R8 is used to input the power supply voltage, the second end of the second potentiometer R8 is grounded, and the adjustable end of the second potentiometer is electrically connected to the source of the second NMOS tube. In the embodiment, the valley adjustment module 220 uses the second NMOS tube NMOS_2 to further realize the modulation conversion of the PWM valley level voltage, and uses the second potentiometer R8 to further realize the adjustment of the PWM valley level voltage.
[0048] In order to further solve the forbidden adjustment range of the second adjustable device R8, in one embodiment of the present application, as Figure 2As shown, the above-mentioned valley adjustment module 220 also includes a second capacitor module C4 and an eighth resistor module R11; the first end of the above-mentioned second capacitor module C4 is used to input the above-mentioned power supply voltage, and the second end of the above-mentioned second capacitor module C4 is grounded; the first end of the above-mentioned eighth resistor module R11 is used to input the power supply voltage, and the second end of the above-mentioned eighth resistor module R11 is electrically connected to the first end of the above-mentioned second potentiometer R8.
[0049] Specifically, the source voltage of the second NMOS tube NMOS_2 is equal to the output voltage V adjusted by the second potentiometer R8. n , according to the voltage division principle, we have:
[0050]
[0051] Among them, R 8调 is the resistance value after the adjustable resistor is adjusted. Its function is to adjust the voltage level of the PWM valley. VCC is the power supply voltage. The conversion can obtain the source voltage V of the second NMOS tube NMOS_2. n :
[0052]
[0053] Since the second potentiometer R8 is in the lower voltage division, R 8调 The maximum value is R8, so V n The range is If the conduction condition of the second NMOS tube NMOS_2 needs to be met, VQ3 must be met g -V n >VQ3 gs , VQ3 g is the gate input voltage of the second NMOS tube NMOS_2, VQ3 gs It is the minimum threshold voltage for the second NMOS tube NMOS_2 to conduct. At this time, the voltage at point T2 in the circuit is VCC, that is, VQ3 g =VCC, so choose R 10 The size needs to meet:
[0054]
[0055] Right now:
[0056]
[0057] After the condition is met, when the gate voltage of the second NMOS transistor NMOS_2 is 0, the second NMOS transistor NMOS_2 is not turned on, and when the gate voltage of the second NMOS transistor NMOS_2 is VCC, the Q3 transistor is turned on.
[0058] Specifically, the function of the peak adjustment module 210 is to adjust the peak level voltage of the PWM waveform by adjusting the value of the first potentiometer R1; the function of the trough adjustment module 220 is to adjust the trough level voltage of the PWM waveform by adjusting the value of the second potentiometer R8.
[0059] Specifically, therefore, when the PWM input signal is logic 0, the gate-source voltage Vg - Vs of the flip module 110 is equal to 0, which is less than the turn-on threshold Vgs of the flip module 110, then the Q4 transistor is turned off, and the T2 point in the circuit is directly pulled up to the power supply VCC by the first resistor module R4, so the voltage at the T2 point is equal to VCC. At this time, in the first PMOS transistor PMOS_1, (VQ1g - V P ) = (VCC - V P ) > 0, then the first PMOS transistor PMOS_1 is not conducting, the gate voltage of the second NMOS transistor is equal to VCC. At this time, for the second NMOS transistor, (VQ3g - V_n) = (VCC - Vn) > VQ3 gs , then the second NMOS transistor is conducting. Ignoring the internal resistance of the second NMOS transistor, the voltage at the T3 point is also equal to the source voltage Vn of the second NMOS transistor. For the gate voltage of the second PMOS transistor being VCC, the second PMOS transistor satisfies (VQ2g - Vn) = (VCC - Vn) > 0 at this time, then the second PMOS transistor is not conducting. At this time, the voltage at the T3 point is equal to the output voltage Vn adjusted by the second potentiometer, thus realizing the adjustment of the PWM pulse trough level voltage. The trough level voltage is equal to Vn, and its waveform is as Figure 3 shown.
[0060] Specifically, when the PWM input signal is Vin (i.e., logic 1), the gate-source voltage Vg - Vs of the flip module is greater than 0 and also greater than the turn-on threshold Vgs of the flip module, then the first NMOS transistor of the flip module is conducting, the first resistor module R4 loop is conducting, and the voltage at the T2 point is equal to 0. At this time, for the first PMOS transistor, (VQ1g - V P ) = (0 - V P ) < VQ1gs, satisfying the conduction condition, the first PMOS transistor is conducting. Also, because the gate voltage of the second NMOS transistor is also equal to 0, at this time, for the second NMOS transistor, (VQ3g - Vn) = (VCC - Vn) < 0, so the second NMOS transistor is not conducting. Since the first NMOS transistor in the flip module is conducting, the drain voltage of the second PMOS transistor is equal to V P , at this time, the voltage at the T3 point is lower than V P , the parasitic diode conducts, and the source voltage of the second PMOS transistor is equal to V P - VQ2rmp, where VQ2rmp is the conduction voltage difference of the parasitic diode. At this time, the second PMOS transistor also satisfies (VQ2 g - (V P-VQ2rmp))=(VQ2rmp-V P ) <VQ2 gs , the second PMOS tube is turned on, and the voltage at point T3 is equal to the output voltage V after the first potentiometer R1 is adjusted. P , the adjustment of the PWM pulse peak level voltage has been achieved, and the peak level voltage is equal to V P , its waveform is as follows Figure 3 shown.
[0061] In order to further increase the driving capability of the PWM signal, in one embodiment of the present application, Figure 2 As shown, the voltage follower unit 300 of the PWM wave also includes a voltage follower unit 310, and the voltage follower unit includes a ninth resistor module R9, an operational amplifier U1A, a third capacitor module C2 and a fourth capacitor module C3; the first end of the ninth resistor module R9 is connected to the output end of the second adjustment unit 200; the positive input end of the operational amplifier U1A is connected to the second end of the ninth resistor module R9, the negative input end of the operational amplifier U1A is electrically connected to the output end of the operational amplifier U1A, and the output end of the operational amplifier U1A is the output end of the PWM wave adjustment circuit; the first end of the third capacitor module C2 is electrically connected to the negative input end of the operational amplifier U1A, and the second end of the third capacitor module C2 is grounded; the first end of the fourth capacitor module C3 is electrically connected to the positive input end of the operational amplifier U1A, and the second end of the fourth capacitor module C3 is grounded.
[0062] Specifically, the common output of the peak regulation module and the valley regulation module is used as the input of the voltage following unit. The voltage following unit mainly amplifies the output signal of the second regulation unit to enhance the current driving capability of the PWM output signal. The voltage following unit does not flip the signal.
[0063] Specifically, the voltage follower unit has a high impedance input and a low impedance output, and its input and output voltages remain unchanged. Since the PWM peak and valley level voltages have been adjusted after being driven by the second adjustment unit, the output impedance of the PWM is large at this time and is easily affected by the load size of the subsequent circuit. Therefore, it is necessary to increase the PWM driving capability.
[0064] Each resistor module in the above circuit can be a resistor or a plurality of resistors connected in series. The capacitor modules in the above circuit all have filtering functions, which can more effectively reduce ripple and interference in the circuit and improve signal quality and stability.
[0065] According to another aspect of the present application, an electronic device is provided, and the electronic device includes any one of the above-mentioned PWM wave adjustment circuits.
[0066] The above-mentioned electronic device includes any one of the above-mentioned PWM wave adjustment circuits, and the PWM wave adjustment circuit includes a first adjustment unit and a second adjustment unit. The input end of the above-mentioned first adjustment unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the above-mentioned first adjustment unit; the second adjustment unit is electrically connected to the output end of the above-mentioned first adjustment unit, and the above-mentioned second adjustment unit includes a peak adjustment module and a valley adjustment module. The input end of the above-mentioned peak adjustment module is connected to the output end of the above-mentioned first adjustment unit and is used to adjust the voltage of the valley signal of the above-mentioned first PWM signal when the above-mentioned first adjustment unit outputs a valley signal to obtain a peak signal of the second PWM signal. The input end of the above-mentioned valley adjustment module is connected to the output end of the above-mentioned first adjustment unit and is used to adjust the voltage of the valley signal of the above-mentioned first PWM signal when the above-mentioned first adjustment unit outputs a valley signal to obtain a peak signal of the second PWM signal. In the case of a peak signal, the voltage of the peak signal of the above-mentioned first PWM signal is adjusted to obtain a valley signal of the second PWM signal. Compared with the prior art, the solution of the present application utilizes a first adjustment unit to flip the original PWM signal to obtain a first PWM signal, and inputs the first PWM signal to the second adjustment unit. When the input first PWM signal is a valley signal, the peak adjustment module of the second adjustment unit flips the valley signal into a peak signal and adjusts the voltage of the peak signal. When the input first PWM signal is a peak signal, the valley adjustment module of the second adjustment unit flips the peak signal into a valley signal and adjusts the voltage of the valley signal. In this way, both the peak voltage and the valley voltage can be adjusted, thereby further solving the problem that both the peak voltage and the valley voltage of the PWM signal cannot be adjusted in the prior art.
[0067] From the above description, it can be seen that the above embodiments of the present application achieve the following technical effects:
[0068] The PWM wave adjustment circuit of the present application includes a first adjustment unit and a second adjustment unit. The input end of the first adjustment unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first adjustment unit; the second adjustment unit is electrically connected to the output end of the first adjustment unit, and the second adjustment unit includes a peak adjustment module and a valley adjustment module. The input end of the peak adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a valley signal to obtain a peak signal of the second PWM signal. The input end of the valley adjustment module is connected to the output end of the first adjustment unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first adjustment unit outputs a peak signal to obtain a peak signal of the second PWM signal. The voltage of the peak signal of the first PWM signal is obtained to obtain the valley signal of the second PWM signal. Compared with the prior art, the solution of the present application utilizes the first adjustment unit to flip the original PWM signal to obtain the first PWM signal, and inputs the first PWM signal to the second adjustment unit. When the input first PWM signal is a valley signal, the peak adjustment module of the second adjustment unit flips the valley signal into a peak signal and adjusts the voltage of the peak signal. When the input first PWM signal is a peak signal, the valley adjustment module of the second adjustment unit flips the peak signal into a valley signal and adjusts the voltage of the valley signal. In this way, both the peak voltage and the valley voltage can be adjusted, thereby further solving the problem that both the peak voltage and the valley voltage of the PWM signal cannot be adjusted in the prior art.
[0069] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A PWM wave adjustment circuit, characterized in that: include: a first regulating unit, comprising an input end and an output end, wherein the input end of the first regulating unit is used to flip the input original PWM signal to obtain a first PWM signal and output it through the output end of the first regulating unit, and the waveform of the first PWM signal is opposite to that of the input PWM signal; A second regulating unit is electrically connected to the output end of the first regulating unit, and the second regulating unit includes a peak regulating module and a valley regulating module. The input end of the peak regulating module is connected to the output end of the first regulating unit and is used to adjust the voltage of the valley signal of the first PWM signal when the first regulating unit outputs a valley signal to obtain a peak signal of the second PWM signal. The input end of the valley regulating module is connected to the output end of the first regulating unit and is used to adjust the voltage of the peak signal of the first PWM signal when the first regulating unit outputs a peak signal to obtain a valley signal of the second PWM signal. The output end of the valley regulating module is electrically connected to the output end of the peak regulating module and serves as the output end of the second regulating unit.
2. The PWM wave adjustment circuit according to claim 1, characterized in that: The first adjustment unit comprises: A flip module, comprising a first NMOS tube, wherein a gate of the first NMOS tube is used to input the original PWM signal, and a source of the first NMOS tube is grounded; A first resistance module, wherein a first end of the first resistance module is used to input a power supply voltage, and a second end of the first resistance module is electrically connected to a drain of the first NMOS tube.
3. The PWM wave adjustment circuit according to claim 2, characterized in that: The flip module further includes a first parasitic diode, wherein an anode of the first parasitic diode is electrically connected to a source of the first NMOS tube, and a cathode of the first parasitic diode is electrically connected to a drain of the first NMOS tube.
4. The PWM wave adjustment circuit according to claim 2, characterized in that: The first adjustment unit also includes: A second resistance module, wherein a first end of the second resistance module is electrically connected to the gate of the flip module, and a second end of the second resistance module is grounded.
5. The PWM wave adjustment circuit according to claim 4, characterized in that: The first adjustment unit also includes: The third resistance module is connected to a connection branch between the gate of the flip module and the first end of the second resistance module.
6. The PWM wave adjustment circuit according to claim 1, characterized in that: The peak adjustment module comprises: a fourth resistance module, wherein a first end of the fourth resistance module is electrically connected to an output end of the first regulating unit; A first PMOS transistor, wherein a gate of the first PMOS transistor is electrically connected to the second end of the fourth resistor module; a fifth resistance module, wherein a first end of the fifth resistance module is electrically connected to an output end of the first regulating unit; A second PMOS tube, wherein the gate of the second PMOS tube is electrically connected to the second end of the fifth resistor module, the drain of the second PMOS tube is electrically connected to the drain of the first PMOS tube, and the source of the second PMOS tube is the output end of the peak adjustment module; A first potentiometer, wherein a first end of the first potentiometer is used to input a power supply voltage, a second end of the first potentiometer is grounded, and an adjustable end of the potentiometer is electrically connected to a source of the first PMOS tube.
7. The PWM wave adjustment circuit according to claim 6, characterized in that: The peak adjustment module also includes: A first capacitor module, wherein a first end of the first capacitor module is used to input the power supply voltage, and a second end of the first capacitor module is grounded; A sixth resistor module, wherein a first end of the sixth resistor module is electrically connected to a second end of the first potentiometer, and a second end of the sixth resistor module is grounded.
8. The PWM wave adjustment circuit according to claim 1, characterized in that: The trough adjustment module comprises: a seventh resistance module, wherein a first end of the seventh resistance module is electrically connected to an output end of the first regulating unit; A second NMOS tube, wherein the gate of the second NMOS tube is electrically connected to the second end of the seventh resistor module, and the drain of the second NMOS tube is the output end of the valley adjustment module; A second potentiometer, wherein a first end of the second potentiometer is used to input a power supply voltage, a second end of the second potentiometer is grounded, and an adjustable end of the potentiometer is electrically connected to a source of the second NMOS tube.
9. The PWM wave adjustment circuit according to claim 8, characterized in that: The trough adjustment module further includes: A second capacitor module, wherein a first end of the second capacitor module is used to input the power supply voltage, and a second end of the second capacitor module is grounded; An eighth resistance module, wherein a first end of the eighth resistance module is used to input a power supply voltage, and a second end of the eighth resistance module is electrically connected to a first end of the second potentiometer.
10. The PWM wave adjustment circuit according to claim 1, characterized in that: The PWM wave adjustment circuit further includes a voltage following unit, and the voltage following unit includes: a ninth resistance module, wherein a first end of the ninth resistance module is connected to an output end of the second regulating unit; an operational amplifier, wherein the positive input terminal of the operational amplifier is connected to the second end of the ninth resistor module, the negative input terminal of the operational amplifier is electrically connected to the output terminal of the operational amplifier, and the output terminal of the operational amplifier is the output terminal of the PWM wave adjustment circuit; A third capacitor module, wherein a first end of the third capacitor module is electrically connected to the negative input end of the operational amplifier, and a second end of the third capacitor module is grounded; A fourth capacitor module, wherein a first end of the fourth capacitor module is electrically connected to the positive input end of the operational amplifier, and a second end of the fourth capacitor module is grounded.
11. An electronic device, characterized in that: A PWM wave adjustment circuit comprising the PWM wave adjustment circuit as claimed in any one of claims 1 to 10.