High common-mode transient suppression capacitance isolation type high-voltage gate driving circuit

Abstract

The invention discloses a high common mode transient suppression capacitance isolation type high voltage gate drive circuit. According to the invention, common-mode transient suppression enhancement measures are adopted in the transmitting TX sub-chip and the receiving RX sub-chip at the same time, so that higher common-mode transient suppression characteristics are realized. Firstly, a high common-mode transient suppression difference OOK modulation circuit is adopted in a transmitting TX sub-chip, and common-mode interference signals coupled by a receiving RX sub-chip through a high-voltage isolation capacitor are suppressed at an OOK signal transmitting end; then, a high common-mode transient suppression differential OOK receiving circuit and a common-mode suppression output driving circuit are adopted in the receiving RX sub-chip, and the high common-mode transient suppression differential OOK receiving circuit is adopted to compensate and suppress common-mode errors contained in differential OOK signals sent by the transmitting TX sub-chip; and the common-mode noise is further suppressed by adopting the common-mode suppression output driving circuit.

Description

Technical Field

[0001] The invention relates to a high common mode transient suppression capacitor isolation type high voltage gate drive circuit for a high voltage gate drive chip, belonging to the technical field of integrated circuits. Background Art

[0002] The new generation of power electronic systems based on wide bandgap power semiconductor devices have higher requirements on the speed and reliability of their internal high-voltage gate driver chips. As the switching frequency of the whole machine increases, the whole system has put forward extremely strict requirements on the common-mode transient interference suppression index of the high-voltage gate driver chip. Therefore, how to improve the common-mode transient interference suppression index of the high-voltage gate driver chip has become an important research direction.

[0003] Figure 1 A schematic diagram of a capacitor isolation driving circuit architecture in the prior art is given, wherein two signal communication modules: a transmitting end circuit and a receiving end circuit are each connected to a ground voltage V GND1 and V GND2 , wherein the isolation circuit 20 is provided to separate the two ground voltages V GND1 and V GND2 DI is the input of the capacitor isolation drive circuit, and RO is its output. The input DI controls the transmitter circuit to generate a set of differential signals, which are coupled to the receiver circuit through the isolation capacitor. After signal demodulation and output drive, the output signal RO is obtained. However, due to the two ground voltages V GND1 and V GND2 There is usually a certain degree of common mode transient interference between the two, which will cause errors in the signal transmission process. For example, a spike between two ground voltages, a power loop, or any system loss is one of the common transient interference factors.

[0004] like Figure 2 The figure shows the interference waveform diagram formed by common mode transient interference. The common mode transient interference V GND That is equal to (V GND1 -V GND2 ), which can quickly increase from 0V to 5KV between 1.1ms and 1.10001ms, and then quickly decrease from 5KV to 0V between 1.101ms and 1.10101ms. Assuming that the input common-mode voltage Vcm at the receiving circuit end is 2.4V, then at V GND Under the interference of Vcm, Vcm will quickly rise to 6.405V within the time from 1.1ms to 1.10001ms, and then drop to -364mV between 1.101ms and 1.10101ms. The peak error of Vcm voltage will inevitably cause data errors in the receiving circuit. In addition, with the common mode transient interference VGND As the slope of change increases, the fluctuation of Vcm voltage will become more serious. Therefore, providing a high-voltage gate drive circuit with high common-mode transient interference suppression capability is of great significance and market value for the application and promotion of wide-bandgap power semiconductor devices. Summary of the invention

[0005] The purpose of the present invention is to provide a high common mode transient suppression capacitor isolated high voltage gate drive circuit for the inevitable common mode transient interference noise problem in the system application of high voltage insulation isolation gate drive chip.

[0006] The high common mode transient suppression capacitor isolation type high voltage gate driving circuit provided by the present invention comprises: a transmitting TX sub-chip and a receiving RX sub-chip, wherein the differential OOK transmission signals TXP and TXN generated in the transmitting TX sub-chip are respectively connected to one end of the positive terminal transmission capacitor Ctph and the negative terminal transmission capacitor Ctnh in the chip, and the other ends of the positive terminal transmission capacitor Ctph and the negative terminal transmission capacitor Ctnh are respectively connected to one end of the positive terminal reception capacitor Crph and the negative terminal reception capacitor Crnh in the receiving RX sub-chip, and the other ends of the positive terminal reception capacitor Crph and the negative terminal reception capacitor Crnh are respectively differential reception signals RXP and RXN; the transmitting TX sub-chip further comprises a first input receiving circuit, a high common mode transient suppression differential OOK modulation circuit, and an OSC oscillation generating circuit, and the receiving RX sub-chip further comprises a high common mode transient suppression differential OOK receiving circuit and a common mode suppression output driving circuit;

[0007] The ground potentials of all circuits inside the transmitting TX sub-chip are connected to the ground voltage GND, and the ground potentials of all circuits inside the receiving RX sub-chip are connected to the ground voltage GND2;

[0008] The first input receiving circuit adopts the power supply voltage VCC, the high common mode transient suppression differential OOK modulation circuit and the OSC oscillation generating circuit adopt the low voltage power supply voltage VCCL; the common mode suppression output driving circuit adopts the power supply voltage VDD, and the high common mode transient suppression differential OOK receiving circuit adopts the low voltage power supply voltage VDDL;

[0009] The first input receiving circuit receives external input data IN and converts it into input data Din with a high level of power supply voltage VCC; the input data Din and the high-frequency OSC signal output by the OSC oscillation generating circuit are connected to a high common-mode transient suppression differential OOK modulation circuit, and the high common-mode transient suppression differential OOK modulation circuit performs OOK modulation on the input data Din and the high-frequency OSC signal to obtain differential OOK transmission signals TXP and TXN;

[0010] The differential receiving signals RXP and RXN are connected to the high common-mode transient suppression differential OOK receiving circuit to obtain the output data Dout after processing; the output data Dout is connected to the common-mode suppression output driving circuit, and the output driving signal GO with large current driving capability is obtained after buffering driving.

[0011] Specifically, the high common-mode transient suppression differential OOK modulation circuit includes: an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a NAND gate NAND1, a NAND gate NAND2, a PMOS tube M1, an NMOS tube M2, a PMOS tube M3, an NMOS tube M4, a P-end inverter substrate modulation signal generating circuit, an N-end inverter substrate modulation signal generating circuit and an output common-mode detection circuit;

[0012] The input end of the inverter INV1 is connected to the input data Din, and the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1 and the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2 through the inverter INV2;

[0013] The source of the PMOS tube M1 is connected to the power supply voltage VCCL; the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the positive terminal transmission capacitor Ctph, and the node generates a TXP signal connected to the P-end input signal end of the output common mode detection circuit;

[0014] The input end of the inverter INV3 is connected to the OSC signal, the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND1 and the input end of the inverter INV4, and the output end of the inverter INV4 is connected to the second input end of the NAND gate NAND2; the output end of the NAND gate NAND2 is connected to the gate of the PMOS tube M3 and the gate of the NMOS tube M4 through the inverter INV5;

[0015] The source of the PMOS tube M3 is connected to the power supply voltage VCCL; the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M4 and one end of the positive terminal transmission capacitor Ctnh, and the node generates a TXN signal connected to the N-terminal input signal terminal of the output common mode detection circuit;

[0016] The output common mode detection circuit is also connected to the positive phase reference voltage Vrp and the negative phase reference voltage Vrn. The output common mode detection circuit outputs two signals, wherein the first common mode signal D1 is connected to the input end of the P-end inverter substrate modulation signal generating circuit, and the second common mode signal D2 is connected to the input end of the N-end inverter substrate modulation signal generating circuit;

[0017] The substrate of the PMOS tube M1 is connected to the output signal bpp of the P-end inverter substrate modulation signal generating circuit, the substrate of the NMOS tube M2 is connected to the output signal bpn of the P-end inverter substrate modulation signal generating circuit, and the source of the NMOS tube M2 is connected to the ground voltage GND;

[0018] The substrate of the PMOS tube M3 is connected to the output signal bnp of the N-terminal inverter substrate modulation signal generating circuit, the substrate of the NMOS tube M4 is connected to the output signal bnn of the N-terminal inverter substrate modulation signal generating circuit, and the source of the NMOS tube M4 is connected to the ground voltage GND;

[0019] When the output common-mode detection circuit detects rising-edge common-mode transient coupling interference on the signals TXP and TXN, the pull-down capability of the NMOS tubes M2 and M4 is enhanced by modulating the substrate voltage to reduce the bpp and bnp voltages and increase the bnn and bpn voltages at the same time, while the pull-up capability of the PMOS tubes M1 and M3 is reduced, so as to achieve balanced compensation for the rising-edge common-mode transient coupling interference and keep the flip threshold voltages of the two inverters unchanged; when falling-edge common-mode transient coupling interference appears on the signals TXP and TXN, the pull-down capability of the NMOS tubes M2 and M4 is reduced by modulating the substrate voltage to reduce the bpn and bnn voltages and increase the bnp and bpp voltages at the same time, while the pull-up capability of the PMOS tubes M1 and M3 is increased, so as to achieve balanced compensation for the falling-edge common-mode transient coupling interference and keep the flip threshold voltages of the two inverters unchanged.

[0020] Specifically, the output common mode detection circuit includes: a resistor R1, a resistor R2, a comparator A1, a comparator A2, an inverter INV11, an inverter INV12, a transmission gate TG1, and a transmission gate TG2;

[0021] The upper end of the resistor R1 is connected to the OOK positive phase signal TXP, and the lower end of the resistor R1 is connected to the upper end of the resistor R2. The node generates an OOK common mode voltage Vcm which is connected to the inverting input end of the comparator A1, the inverting input end of the comparator A2, the input end of the transmission gate TG1, and the input end of the transmission gate TG2. The lower end of the resistor R2 is connected to the OOK inverting signal TXN.

[0022] The non-inverting input terminal of the comparator A1 is connected to the non-inverting reference voltage Vrp, the output terminal of the comparator A1 is connected to the input terminal of the inverter INV11, the C inverting control terminal of the transmission gate TG1, and the locking signal SP; the output terminal of the inverter INV11 is connected to the C control terminal of the transmission gate TG1, and the output terminal of the transmission gate TG1 is connected to the first common mode signal D1 output by the output common mode detection circuit;

[0023] The positive input terminal of the comparator A2 is connected to the negative reference voltage Vrn, the output terminal of the comparator A2 is connected to the input terminal of the inverter INV12, the C inverting control terminal of the transmission gate TG2, and the locking signal SN; the output terminal of the inverter INV12 is connected to the C control terminal of the transmission gate TG2; the output terminal of the transmission gate TG2 is connected to the second common mode signal D2 output by the output common mode detection circuit.

[0024] The output common-mode detection circuit first detects the common-mode level of the differential OOK signals TXP and TXN through resistors R1 and R2 to obtain the OOK common-mode voltage Vcm. Under normal circumstances, the common-mode voltage Vcm is VCCL / 2. When common-mode transient interference occurs, the Vcm voltage will change; comparators A1 and A2 compare the OOK common-mode voltage Vcm with the positive reference voltage Vrp and the negative reference voltage Vrn respectively to obtain the locking signal SP and the locking signal SN, and respectively judge the rising edge and falling edge of the common-mode transient interference; then, the locking signal SP and the locking signal SN output the first common-mode signal D1 and the second common-mode signal D2 through the transmission gate TG1 and the transmission gate TG2 respectively, and respectively control the P-end inverter substrate modulation signal generating circuit and the N-end inverter substrate modulation signal generating circuit.

[0025] Specifically, the P-end inverter substrate modulation signal generating circuit and the N-end inverter substrate modulation signal generating circuit are implemented by using the same inverter substrate modulation signal generating circuit, and the circuit structure includes: PMOS tube MP2, PMOS tube MP3, NMOS tube MN2, NMOS tube MN3, resistor Rt1, resistor Rt2, transmission gate TG7, inverter INV70;

[0026] The source of the PMOS tube MP2 and the upper end of the resistor Rt2 are connected to the power supply VCC; the lower end of the resistor Rt1 and the source of the NMOS tube MN3 are connected to the ground voltage GND;

[0027] The gate of the PMOS tube MP2 is connected to the first positive phase bias voltage Vbtp1; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, and is also connected to the output end of the transmission gate TG7; the source of the NMOS tube MN2 is connected to the drain of the NMOS tube MN3, and is also connected to the output end of the transmission gate TG7; the gate of the NMOS tube MN3 is connected to the first negative phase bias voltage Vbtn1, and the gate of the NMOS tube MN2 is connected to the second negative phase bias voltage Vbtn2;

[0028] The gate of the PMOS tube MP3 is connected to the second positive phase bias voltage Vbtp2; the drain of the PMOS tube MP3 is connected to the upper end of the resistor Rt1, and outputs an inverse substrate signal; the drain of the NMOS tube MN2 is connected to the lower end of the resistor Rt2, and outputs a positive phase substrate signal;

[0029] The input end of the transmission gate TG7 is connected to the OOK common mode voltage Vcm, and one of the two control ends of the transmission gate TG7 is connected to the common mode signal D1 or D2, and the other is connected to the inverse signal obtained by the common mode signal D1 or D2 through the inverter INV70.

[0030] The PMOS tube MP2, the PMOS tube MP3 and the resistor Rt1 form a first cascode amplifier, the drain of the PMOS tube MP2 and the source of the PMOS tube MP3 are the input terminals of the first cascode amplifier, and the positive phase substrate signal is the output terminal of the first cascode amplifier;

[0031] The NMOS transistor MN2, the NMOS transistor MN3 and the resistor Rt2 form a second cascode amplifier, the source of the NMOS transistor MN2 and the drain of the NMOS transistor MN3 are the input terminals of the second cascode amplifier, and the inverted substrate signal is the output terminal thereof;

[0032] The transmission gate TG7 and the inverter INV70 are used to simultaneously transmit the OOK common-mode voltage Vcm to the first cascode amplifier input terminal and the second cascode amplifier input terminal when the common-mode signal D1 or D2 is valid.

[0033] Specifically, the common-mode suppression output drive circuit includes: a source of a PMOS tube M801, a source of a MOS tube M804, a source of a PMOS tube M807, a source of a PMOS tube M809, a source of a PMOS tube M811, a source of a PMOS tube M813, a source of a PMOS tube M815, a source of a PMOS tube M817, a source of a PMOS tube M819, a source of a PMOS tube M821, a source of a HVPMOS tube HM81, and an upper end of a resistor R81 are all connected to a power supply voltage VDD;

[0034] The source of NMOS tube M808, the source of NMOS tube M810, the source of NMOS tube M812, the source of NMOS tube M814, the source of NMOS tube M816, the source of NMOS tube M818, the source of NMOS tube M820, the source of NMOS tube M822, and the source of HVNMOS tube HM82 are all connected to the chip ground voltage GND2; the source of NMOS tube M803 and the source of NMOS tube M806 are connected to the ground signal GND1 buffered by deep N well isolation of GND2;

[0035] The gate of the PMOS tube M801, the drain of the PMOS tube M804, the source of the PMOS tube M805, and the gate of the PMOS tube M807 are connected to the circuit node B; the drain of the PMOS tube M801, the gate of the PMOS tube M804, the lower end of the resistor R81, the source of the PMOS tube M802, and the gate of the PMOS tube M809 are connected to the circuit node A;

[0036] The gates of the PMOS tube M802 and the PMOS tube M805 are connected to the floating bias voltage signal Vsh; the drain of the PMOS tube M802 is connected to the drain of the NMOS tube M803; the drain of the PMOS tube M805 is connected to the drain of the NMOS tube M806; the signal Dout is connected to the gate of the NMOS tube M806, and is connected to the gate of the NMOS tube M803 through the inverter INV81;

[0037] The drain of the PMOS tube M807, the drain of the NMOS tube M808, and the gate of the NMOS tube M810 are connected to the circuit node C; the gate of the NMOS tube M808, the drain of the PMOS tube M809, the drain of the NMOS tube M810, the gate of the PMOS tube M811, the gate of the NMOS tube M812, the gate of the PMOS tube M817, and the gate of the NMOS tube M818 are connected to the circuit node D;

[0038] The drain of the PMOS tube M811 is connected to the drain of the NMOS tube M812, the gate of the PMOS tube M813, and the gate of the NMOS tube M814; the drain of the PMOS tube M813 is connected to the drain of the NMOS tube M814, the gate of the PMOS tube M815, and the gate of the NMOS tube M816; the drain of the PMOS tube M815 is connected to the drain of the NMOS tube M816 and the gate of the HVPMOS tube HM81;

[0039] The drain of the PMOS tube M817 is connected to the drain of the NMOS tube M818, the gate of the PMOS tube M819, and the gate of the NMOS tube M820; the drain of the PMOS tube M819 is connected to the drain of the NMOS tube M820, the gate of the PMOS tube M821, and the gate of the NMOS tube M822; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822 and the gate of the HVNMOS tube HM82;

[0040] The drain of the HVPMOS tube HM81 is connected to the drain of the HVNMOS tube HM82 and outputs a driving signal GO.

[0041] The resistor R81, the inverter INV81, the PMOS tube M801, the PMOS tube M802, the NMOS tube M803, the PMOS tube M804, the PMOS tube M805 and the NMOS tube M806 constitute a differential input level conversion buffer amplifier; the gate of the NMOS tube M803 is connected to the output of the signal Dout reversed by the inverter INV81, and the gate of the NMOS tube M806 is connected to the signal Dout, so the gate of the NMOS tube M803 and the gate of the NMOS tube M806 are differential complementary low swing signals, and the source of the NMOS tube M803 and the source of the NMOS tube M806 are connected to the ground signal GND1 buffered by the deep N well isolation of the ground voltage GND2, so as to improve the influence of the common mode transient interference of GND2 on the differential input level conversion buffer amplifier;

[0042] The PMOS tube M811, the NMOS tube M812, the PMOS tube M813, the NMOS tube M814, the PMOS tube M815 and the NMOS tube M816 form a three-stage inverter chain of step-by-step amplification, which is used to drive the gate of the HVPMOS tube HM81; the PMOS tube M817, the NMOS tube M818, the PMOS tube M819, the NMOS tube M820, the PMOS tube M821 and the NMOS tube M822 form a three-stage inverter chain of step-by-step amplification, which is used to drive the gate of the HVNMOS tube HM82;

[0043] The two PMOS transistors M801 and M802 are interlockedly connected to form positive feedback, and the two NMOS transistors M809 and M810 are interlockedly connected to form positive feedback, which are used to accelerate the voltage flipping speed of the four nodes A, B, C, and D.

[0044] The advantages of the present invention are:

[0045] (1) The present invention adopts a high common-mode transient suppression differential OOK modulation circuit in the transmitting TX sub-chip, and suppresses the common-mode interference signal coupled from the receiving RX sub-chip through the high-voltage isolation capacitor at the OOK signal transmitting end;

[0046] (2) The present invention adopts a high common-mode transient suppression differential OOK receiving circuit and a common-mode suppression output driving circuit in the receiving RX sub-chip. The high common-mode transient suppression differential OOK receiving circuit is used to compensate and suppress the common-mode error contained in the differential OOK signal sent by the transmitting TX sub-chip, and the common-mode suppression output driving circuit is used to further suppress the common-mode noise.

[0047] The present invention can be widely applied to various high-voltage power device application systems. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] Figure 1 A schematic diagram of a capacitor isolation driving circuit architecture.

[0049] Figure 2 This is a schematic diagram of the common-mode transient interference waveform of the capacitor isolation drive circuit.

[0050] Figure 3 This is an overall block diagram of the high common mode transient suppression capacitor isolated high voltage gate drive circuit of the present invention.

[0051] Figure 4 This is a typical implementation method of the OOK differential modulation circuit in the prior art.

[0052] Figure 5 Block diagram of the high common-mode transient suppression differential OOK modulation circuit of the present invention.

[0053] Figure 6 This is an embodiment of the OOK output common mode detection circuit of the present invention.

[0054] Figure 7 This is an embodiment of the inverter substrate modulation signal generating circuit of the present invention.

[0055] Figure 8 This is a block diagram of the high common-mode transient suppression differential OOK receiving circuit of the present invention.

[0056] Fig. 9 This is an embodiment of the common-mode suppression output drive circuit of the present invention. DETAILED DESCRIPTION

[0057] The present invention is further described in detail below with reference to the accompanying drawings and embodiments.

[0058] like Figure 3 As shown, the high common mode transient suppression capacitor isolated high voltage gate drive circuit includes: a first input receiving circuit 1, a high common mode transient suppression differential OOK modulation circuit 2, an OSC oscillation generating circuit 3, a positive terminal sending capacitor Ctph, a negative terminal sending capacitor Ctnh, a positive terminal receiving capacitor Crph, a negative terminal receiving capacitor Crnh, a high common mode transient suppression differential OOK receiving circuit 4, and a common mode suppression output drive circuit 5.

[0059] The first input receiving circuit 1, the high common mode transient suppression differential OOK modulation circuit 2, the OSC oscillation generating circuit 3, the positive terminal transmission capacitor Ctph, and the negative terminal transmission capacitor Ctnh constitute a transmitting TX sub-chip 10. The positive terminal receiving capacitor Crph, the negative terminal receiving capacitor Crnh, the high common mode transient suppression differential OOK receiving circuit 4, and the common mode suppression output driving circuit 5 constitute a receiving RX sub-chip 30.

[0060] The ground potential of all circuits inside the transmitting TX sub-chip 10 is connected to the ground voltage GND, and the ground potential of all circuits inside the receiving RX sub-chip 30 is connected to the ground voltage GND2. The first input receiving circuit 1 uses the power supply voltage VCC, and the high common mode transient suppression differential OOK modulation circuit 2 and the OSC oscillation generation circuit 3 use the low voltage power supply voltage VCCL. The common mode suppression output drive circuit 5 uses the power supply voltage VDD, and the high common mode transient suppression differential OOK receiving circuit 4 uses the low voltage power supply voltage VDDL.

[0061] The first input receiving circuit 1 receives external input data IN and converts it into input data Din with a high level of power supply voltage VCC; the high common mode transient suppression differential OOK modulation circuit 2 performs OOK modulation on the input data Din and the high frequency OSC signal output by the OSC oscillation generating circuit 3 to obtain differential OOK transmission signals TXP and TXN; the differential OOK transmission signals TXP and TXN are respectively connected to the left ends of the positive transmission capacitor Ctph and the negative transmission capacitor Ctnh; the right ends of the positive transmission capacitor Ctph and the negative transmission capacitor Ctnh are respectively connected to the left ends of the positive receiving capacitor Crph and the negative receiving capacitor Crnh; the right ends of the positive receiving capacitor Crph and the negative receiving capacitor Crnh are differential receiving signals RXP and RXN respectively; the differential receiving signals RXP and RXN are connected to the high common mode transient suppression differential OOK receiving circuit 4 to obtain output data Dout after processing; the output data Dout is connected to the common mode suppression output driving circuit 5, and the output driving signal GO is obtained after buffering driving.

[0062] Figure 3 In the circuit shown, since there is a large voltage difference between the substrate potential of the transmitting end circuit and the receiving end circuit, the high and low voltage circuits must be electrically isolated. The input data IN is first converted by the first input receiving circuit 1 to obtain the internal input data Din, and then Din and the oscillation signal provided by the OSC oscillation generating circuit 3 enter the high common mode transient suppression differential OOK modulation circuit 2 to generate differential OOK signals TXP and TXN, and differential receiving signals RXP and RXN are obtained through differential capacitor coupling, and enter the high common mode transient suppression differential OOK receiving circuit 4 to obtain the output data Dout after processing; the output data Dout is buffered and driven by the common mode suppression output driving circuit 5 to obtain the output drive signal GO with large current driving capability.

[0063] In order to improve the common-mode transient suppression characteristics, the present invention adopts optimization measures in multiple circuit modules, and adopts common-mode transient suppression enhancement measures in both the transmitting TX sub-chip 10 and the receiving RX sub-chip 30 to achieve higher common-mode transient suppression characteristics. First, a high common-mode transient suppression differential OOK modulation circuit 2 is adopted in the transmitting TX sub-chip 10, and the common-mode interference signal coupled from the receiving RX sub-chip 30 through the high-voltage isolation capacitor is suppressed at the OOK signal transmitting end; secondly, a high common-mode transient suppression differential OOK receiving circuit 4 and a common-mode suppression output driving circuit 5 are adopted in the receiving RX sub-chip 30, and the high common-mode transient suppression differential OOK receiving circuit 4 is adopted to compensate and suppress the common-mode error contained in the differential OOK signal sent by the transmitting TX sub-chip 10, and the common-mode suppression output driving circuit 5 is adopted to further suppress the common-mode noise.

[0064] Figure 4It is a typical implementation of the existing OOK differential modulation circuit. The oscillation signal OSC obtains two complementary clocks through the inverter IN4, which are modulated with the internal input data Din through the NAND gates NAND1 and NAND2 to obtain two complementary data signals, and then the differential OOK signals TXP and TXN are obtained through the inverter composed of the PMOS tube M1 and the NMOS tube M2, and the inverter composed of the PMOS tube M3 and the NMOS tube M4. The inverter composed of M1 and M2 and the inverter composed of M3 and M4 are usually inverters of the same size, and the substrate of the PMOS tube is connected to the source power supply VDD, and the substrate of the NMOS tube is connected to the source ground GND. When the receiving RX sub-chip 30 generates common-mode transient interference, it will be coupled to the differential OOK signals TXP and TXN signals through the positive end sending capacitor Ctph and the negative end sending capacitor Ctnh to perform signal superposition.

[0065] like Figure 4 As shown in the figure, when rising edge common mode coupling interference appears on the differential OOK signals TXP and TXN, it is equivalent to increasing the pull-up capability of the PMOS tubes M1 and M3, which will increase the flip threshold voltage of the two inverters; when falling edge common mode coupling interference appears on the differential OOK signals TXP and TXN, it is equivalent to increasing the pull-down capability of the NMOS tubes M2 and M4, which will reduce the flip threshold voltage of the two inverters; when the flip threshold voltage of the two inverters is reduced or increased by a certain magnitude, the differential OOK signals TXP and TXN output by the two inverters will have waveform distortion and bit errors.

[0066] In order to suppress the influence of common-mode transient interference generated by the receiving RX sub-chip 30 on the differential OOK signals TXP and TXN, the present invention provides a dynamic compensation measure. When the rising common-mode transient coupling interference appears on the differential OOK signals TXP and TXN signals to increase the flip threshold voltage of the two inverters, by enhancing the pull-down capability of the NMOS tube M2 and the NMOS tube M4, the equivalent increase of the pull-up capability of the PMOS tube M1 and the PMOS tube M3 is balanced, and the flip threshold voltage of the two inverters can remain unchanged, so that the influence of the rising common-mode transient coupling interference is offset and suppressed; when the falling common-mode transient coupling interference appears on the differential OOK signals TXP and TXN signals to reduce the flip threshold voltage of the two inverters, by enhancing the pull-up capability of the PMOS tube M1 and the PMOS tube M3, the equivalent increase of the pull-down capability of the NMOS tube M2 and the NMOS tube M4 is balanced, and the flip threshold voltage of the two inverters can remain unchanged, so that the influence of the falling common-mode transient coupling interference is offset and suppressed.

[0067] Figure 5The circuit block diagram of the high common mode transient suppression differential OOK modulation circuit 2 of the present invention includes Figure 4 Inverter INV1, inverter INV2, inverter INV3, inverter INV4, inverter INV5, NAND gate NAND1, NAND gate NAND2, PMOS tube M1, NMOS tube M2, PMOS tube M3, NMOS tube M4, positive end sending capacitor Ctph, positive end sending capacitor Ctnh, in addition to the P-end inverter substrate modulation signal generating circuit 21, N-end inverter substrate modulation signal generating circuit 22 and output common mode detection circuit 23.

[0068] The input end of the inverter INV1 is connected to the input data signal Din; the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1 and the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the input end of the inverter INV2; the output end of the inverter INV2 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2; the source of the PMOS tube M1 is connected to the power supply voltage VCCL; the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and the left side of the positive terminal transmission capacitor Ctph, and is connected to the P terminal input signal TXP of the output common mode detection circuit 23. The other end of the positive terminal transmission capacitor Ctph is the P terminal output signal OP.

[0069] The substrate of the PMOS tube M1 is connected to the output signal bpp of the P-end inverter substrate modulation signal generating circuit 21; the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the positive end transmission capacitor Ctph, and the node generates a TXP signal connected to the P-end input signal end of the output common mode detection circuit 23; the substrate of the NMOS tube M2 is connected to the output signal bpn of the P-end inverter substrate modulation signal generating circuit 21, and the source of the NMOS tube M2 is connected to the ground voltage GND;

[0070] The input end of the inverter INV3 is connected to the clock signal OSC; the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND1 and the input end of the inverter INV4; the output end of the inverter INV4 is connected to the second input end of the NAND gate NAND2; the output end of the NAND gate NAND2 is connected to the input end of the inverter INV5; the output end of the inverter INV5 is connected to the gate of the PMOS tube M3 and the gate of the NMOS tube M4; the source of the PMOS tube M3 is connected to the power supply voltage VCCL; the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M4 and one end of the positive terminal sending capacitor Ctnh, and the node generates a TXN signal connected to the N-terminal input signal end of the output common mode detection circuit 23; the other end of the positive terminal sending capacitor Ctnh is the N-terminal output signal ON.

[0071] The substrate of the PMOS tube M3 is connected to the output signal bnp of the N-end inverter substrate modulation signal generating circuit 22; the source of the NMOS tube M4 is connected to the chip ground signal GND; the substrate of the NMOS tube M4 is connected to the output signal bnn of the N-end inverter substrate modulation signal generating circuit 22, and the source of the NMOS tube M4 is connected to the ground voltage GND.

[0072] The output common mode detection circuit 23 is also connected to the positive phase reference voltage Vrp and the negative phase reference voltage Vrn. The output common mode detection circuit 23 outputs two signals, wherein the first common mode signal D1 is connected to the input end of the P-end inverter substrate modulation signal generating circuit 21, and the second common mode signal D2 is connected to the input end of the N-end inverter substrate modulation signal generating circuit 22;

[0073] Figure 5 The high common-mode transient suppression differential OOK modulation circuit shown in Figure 4 Based on the basic OOK differential modulation circuit given, a P-end inverter substrate modulation signal generating circuit 21, an N-end inverter substrate modulation signal generating circuit 22, and an output common mode detection circuit 23 are added. At the same time, the substrates of the PMOS tube M1 and the NMOS tube M2 are changed to be controlled by the output of the P-end inverter substrate modulation signal generating circuit 21, and the substrates of the PMOS tube M3 and the NMOS tube M4 are changed to be controlled by the output of the N-end inverter substrate modulation signal generating circuit 22. When the output common mode detection circuit 23 detects Figure 4 When rising-edge common-mode transient coupling interference occurs on the differential OOK signals TXP and TXN described in the specification, by modulating the substrate voltage to reduce bpp and bnp, and increasing the bnn and bpn voltages, the pull-down capabilities of the NMOS tubes M2 and M4 will be enhanced, and the pull-up capabilities of the PMOS tubes M1 and M3 will be reduced, so as to achieve balanced compensation for the rising-edge common-mode transient coupling interference, and keep the flip threshold voltages of the two inverters unchanged; when falling-edge common-mode transient coupling interference occurs on the differential OOK signals TXP and TXN, by modulating the substrate voltage to reduce bpn and bnn, and increasing the bnp and bpp voltages, the pull-down capabilities of the NMOS tubes M2 and M4 will be reduced, and the pull-up capabilities of the PMOS tubes M1 and M3 will be increased, so as to achieve balanced compensation for the falling-edge common-mode transient coupling interference, and keep the flip threshold voltages of the two inverters unchanged.

[0074] Figure 6 An embodiment of the OOK output common mode detection circuit 23 of the present invention includes: a resistor R1, a resistor R2, a comparator A1, a comparator A2, an inverter INV11, an inverter INV12, a transmission gate TG1, and a transmission gate TG2.

[0075] The upper end of the resistor R1 is connected to the OOK positive phase signal TXP; the lower end of the resistor R1 is connected to the upper end of the resistor R2, the inverting input end of the comparator A1, the inverting input end of the comparator A2, the input end of the transmission gate TG1, and the input end of the transmission gate TG2, and the OOK common mode voltage Vcm is generated at this node;

[0076] The lower end of the resistor R2 is connected to the OOK inversion signal TXN; the positive input end of the comparator A1 is connected to the positive reference voltage Vrp; the output end of the comparator A1 is connected to the input end of the inverter INV11, the C inverting control end of the transmission gate TG1, and is connected to the locking signal SP; the output end of the inverter INV11 is connected to the C control end of the transmission gate TG1; the output end of the transmission gate TG1 is connected to the first common mode signal D1 output by the output common mode detection circuit 23; the positive input end of the comparator A2 is connected to the negative reference voltage Vrn; the output end of the comparator A2 is connected to the input end of the inverter INV12, the C inverting control end of the transmission gate TG2, and is connected to the locking signal SN; the output end of the inverter INV12 is connected to the C control end of the transmission gate TG2; the output end of the transmission gate TG2 is connected to the second common mode signal D2 output by the output common mode detection circuit 23.

[0077] Figure 6 The OOK output common-mode detection circuit 23 shown in the figure first detects the common-mode level of the differential OOK signals TXP and TXN through the resistors R1 and R2 to obtain the OOK common-mode voltage Vcm. Under normal circumstances, the common-mode voltage Vcm is VCCL / 2. When common-mode transient interference occurs, the Vcm voltage will change; comparators A1 and A2 respectively use the positive reference voltage Vrp and the negative reference voltage Vrn to compare with the OOK common-mode voltage Vcm to obtain the locking signal SP and the locking signal SN, and respectively judge the rising edge and falling edge of the common-mode transient interference; then, the locking signal SP and the locking signal SN respectively output the first common-mode signal D1 and the second common-mode signal D2 through the transmission gates TG1 and TG2, respectively controlling Figure 5 The P-end inverter substrate modulation signal generating circuit 21 and the N-end inverter substrate modulation signal generating circuit 22.

[0078] The P-end inverter substrate modulation signal generating circuit 21 and the N-end inverter substrate modulation signal generating circuit 22 are both implemented by the same inverter substrate modulation signal generating circuit. Figure 7 shown. Figure 7 The signal names are described by taking the P-terminal inverter substrate modulation signal generating circuit 21 as an example. The circuit includes: PMOS transistor MP2, PMOS transistor MP3, NMOS transistor MN2, NMOS transistor MN3, resistor Rt1, resistor Rt2, transmission gate TG7, and inverter INV70.

[0079] The source of the PMOS tube MP2 and the upper end of the resistor Rt2 are connected to the power supply VCC; the lower end of the resistor Rt1 and the source of the NMOS tube MN3 are connected to the chip ground voltage GND;

[0080] The gate of the PMOS tube MP2 is connected to the first positive phase bias voltage Vbtp1; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, and is also connected to the output end of the transmission gate TG7; the source of the NMOS tube MN2 is connected to the drain of the NMOS tube MN3, and is also connected to the output end of the transmission gate TG7; the gate of the NMOS tube MN3 is connected to the first negative phase bias voltage Vbtn1, and the gate of the NMOS tube MN2 is connected to the second negative phase bias voltage Vbtn2;

[0081] The gate of the PMOS tube MP3 is connected to the second positive phase bias voltage Vbtp2; the drain of the PMOS tube MP3 is connected to the upper end of the resistor Rt1, and outputs the negative phase substrate signal Vbpn; the drain of the NMOS tube MN2 is connected to the lower end of the resistor Rt2, and outputs the positive phase substrate signal Vbpp;

[0082] An input terminal of the transmission gate TG7 is connected to the OOK common mode voltage Vcm, and two control terminals of the transmission gate TG7 are respectively connected to control the first common mode signal D1 and its inverse signal obtained through the inverter INV70.

[0083] Figure 7 In the inverter substrate modulation signal generating circuit, the PMOS tube MP2, the PMOS tube MP3 and the resistor Rt1 constitute a first cascode amplifier, the drain of the PMOS tube MP2 and the source of the PMOS tube MP3 are the input terminals of the first cascode amplifier, and the positive substrate signal Vbpp is the output terminal of the first cascode amplifier; the NMOS tube MN2, the NMOS tube MN3 and the resistor Rt2 constitute a second cascode amplifier, the source of the NMOS tube MN2 and the drain of the NMOS tube MN3 are the input terminals, and the negative substrate signal Vbpn is the output terminal; the transmission gate TG7 and the inverter INV70 are used to simultaneously transmit the OOK common mode voltage Vcm to the input terminals of the first cascode amplifier and the second cascode amplifier when D1 is valid.

[0084] Figure 8 The block diagram of the embodiment of the high common-mode transient suppression differential OOK receiving circuit 4 of the present invention includes: a second input receiving circuit 41, X-stage cascaded common-mode adjustable amplifier circuits 42 (CM1-CMX), a high-sensitivity common-mode adjustable amplifier circuit 43 (CMN), an output shaping circuit 44 and a common-mode adaptive adjustment circuit 45.

[0085] The second input receiving circuit 41 first receives Figure 3The differential signals coupled into the transmitting TX sub-chip through the isolation capacitor, namely the positive receiving signal RXP and the negative receiving signal RXN, are filtered to obtain the positive input signal Vip and the negative input signal Vin; the positive input signal Vip and the negative input signal Vin then enter the X-stage cascaded common-mode adjustable amplifier circuit 42 (CM1~CMX) to obtain the positive output signal VoXp and the negative output signal VoXn of the X-stage common-mode adjustable amplifier circuit CMX; the positive output signal VoXp and the negative output signal VoXn are respectively connected to the positive input terminal and the negative input terminal of the high-sensitivity common-mode adjustable amplifier circuit 43 to obtain the differential output signal positive output signal VoXp and the negative output signal VoXn of the high-sensitivity common-mode adjustable amplifier circuit 43; the output shaping circuit 44 processes the size of the positive output signal VoXp and the negative output signal VoXn to obtain the final data output Dout. The common mode adaptive adjustment circuit 45 adaptively generates common mode adjustment signals C11, C12, C21, C22, ..., CX1, CX2, CN1, CN2 for each level of amplifier circuits and the high-sensitivity common mode adjustable amplifier circuit 43 according to the changes of the power supply and ground voltage signals. The common mode adjustment signal C11 and the common mode adjustment signal C12 generated by the common mode adaptive adjustment circuit 45 are respectively connected to the common mode adjustment signal input terminal of the first-level common mode adjustable amplifier circuit CM1; the common mode adjustment signal C21 and the common mode adjustment signal C22 are respectively connected to the common mode adjustment signal input terminal of the second-level common mode adjustable amplifier circuit CM2; ... and so on, the common mode adjustment signal CX1 and the common mode adjustment signal CX2 are respectively connected to the common mode adjustment signal input terminal of the X-th level common mode adjustable amplifier circuit CMX; the common mode adjustment signal CN1 and the common mode adjustment signal CN2 are respectively connected to the common mode adjustment signal input terminal of the high-sensitivity common mode adjustable amplifier circuit 43 (CMN). Wherein, X is an integer greater than 1, and N is an integer greater than X.

[0086] The receiving circuit automatically detects the transient common mode noise caused by the fluctuation of the power supply voltage VDDL and the ground potential GND2, and when the transient common mode noise exceeds a certain threshold, adjusts the value of the common mode adjustment signal C11, C12, C21, C22, ..., CX1, CX2, CN1, CN2 and outputs it to the X-stage cascaded common mode adjustable amplifier circuits CM1 to CMX and the high-sensitivity common mode adjustable amplifier circuit 3 (CMN), thereby adjusting the common mode level of the X-stage cascaded common mode adjustable amplifier circuits CM1 to CMX and the high-sensitivity common mode adjustable amplifier circuit 43 to compensate for the influence of the transient common mode noise. In addition to the common mode adaptive adjustment, the present invention also adopts a high-reliability output shaping circuit 44, and adopts RC low-pass filtering and Schmitt trigger combined filtering to filter out the influence of high-frequency noise, and finally obtains the data output Dout that is not affected by the transient common mode noise.

[0087] Fig. 9 It is an embodiment of the common-mode suppression output drive circuit 5 of the present invention, which includes: a PMOS tube M801, a PMOS tube M802, an NMOS tube M803, a PMOS tube M804, a PMOS tube M805, an NMOS tube M806, a PMOS tube M807, an NMOS tube M808, a PMOS tube M809, an NMOS tube M810, a PMOS tube M811, an NMOS tube M812, a PMOS tube M813, an NMOS tube M814, a PMOS tube M815, an NMOS tube M816, a PMOS tube M817, an NMOS tube M818, a PMOS tube M819, an NMOS tube M820, a PMOS tube M821, an NMOS tube M822, an HVPMOS tube HM81, an HVNMOS tube HM82, a resistor R81, and an inverter INV81.

[0088] The source of the PMOS tube M801 is connected to the source of the MOS tube M804, the source of the PMOS tube M807, the source of the PMOS tube M809, the source of the PMOS tube M811, the source of the PMOS tube M813, the source of the PMOS tube M815, the source of the PMOS tube M817, the source of the PMOS tube M819, the source of the PMOS tube M821, the source of the HVPMOS tube HM81, and the upper end of the resistor R81, and is connected to the power supply voltage VDD ; The source of the NMOS tube M808, the source of the NMOS tube M810, the source of the NMOS tube M812, the source of the NMOS tube M814, the source of the NMOS tube M816, the source of the NMOS tube M818, the source of the NMOS tube M820, the source of the NMOS tube M822, and the source of the HVNMOS tube HM82 are connected to the chip ground signal GND2; the source of the NMOS tube M803 is connected to the source of the NMOS tube M806, and is connected to GND1;

[0089] The gate of the PMOS tube M801 is connected to the drain of the PMOS tube M804, the source of the PMOS tube M805, the gate of the PMOS tube M807, and is connected to the signal at point B; the drain of the PMOS tube M801 is connected to the gate of the PMOS tube M804, the lower end of the resistor R81, the source of the PMOS tube M802, the gate of the PMOS tube M809, and is connected to the signal at point A;

[0090] The gate of the PMOS tube M802 is connected to the gate of the PMOS tube M805 and to the floating bias voltage signal Vsh; the drain of the PMOS tube M802 is connected to the drain of the NMOS tube M803; the drain of the PMOS tube M805 is connected to the drain of the NMOS tube M806; the signal Dout is connected to the gate of the NMOS tube M806 and connected to the gate of the NMOS tube M803 through the inverter INV81;

[0091] The drain of the PMOS tube M807 is connected to the drain of the NMOS tube M808, the gate of the NMOS tube M810, and connected to the C point signal; the gate of the NMOS tube M808 is connected to the drain of the PMOS tube M809, the drain of the NMOS tube M810, the gate of the PMOS tube M811, the gate of the NMOS tube M812, the gate of the PMOS tube M817, and the gate of the NMOS tube M818, and connected to the D point signal;

[0092] The drain of the PMOS tube M811 is connected to the drain of the NMOS tube M812, the gate of the PMOS tube M813, and the gate of the NMOS tube M814; the drain of the PMOS tube M813 is connected to the drain of the NMOS tube M814, the gate of the PMOS tube M815, and the gate of the NMOS tube M816; the drain of the PMOS tube M815 is connected to the drain of the NMOS tube M816 and the gate of the HVPMOS tube HM81;

[0093] The drain of the PMOS tube M817 is connected to the drain of the NMOS tube M818, the gate of the PMOS tube M819, and the gate of the NMOS tube M820; the drain of M819 is connected to the drain of the NMOS tube M820, the gate of the PMOS tube M821, and the gate of the NMOS tube M822; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822 and the gate of the HVNMOS tube HM82; the drain of the HVPMOS tube HM81 is connected to the drain of the HVNMOS tube HM82 and is connected to the output voltage signal GO.

[0094] Fig. 9 In the circuit shown, the resistor R81, the inverter INV81, the PMOS tube M801, the PMOS tube M802, the NMOS tube M803, the PMOS tube M804, the PMOS tube M805, and the NMOS tube M806 constitute a differential input level conversion buffer amplifier; the gate of the NMOS tube M803 is connected to the reverse output of Dout through the inverter INV81, and the gate of the NMOS tube M806 is connected to the Dout signal. The gate is a differential complementary low-swing signal; the source of the NMOS tube M803 and the source of the NMOS tube M806 are connected to GND1, and GND1 is a power supply signal of GND2 buffered by deep N-well isolation; by setting the gate of the NMOS tube M803 and the gate of the NMOS tube M806 as differential complementary signals, and connecting the source of the NMOS tube M803 and the source of the NMOS tube M806 to GND1, the influence of the common-mode transient interference of GND2 on the differential input level conversion buffer amplifier is improved.

[0095] The PMOS tube M811, the NMOS tube M812, the PMOS tube M813, the NMOS tube M814, the PMOS tube M815 and the NMOS tube M816 constitute a three-stage inverter chain of progressive amplification for driving the gate of the HVPMOS tube HM81; the PMOS tube M817, the NMOS tube M818, the PMOS tube M819, the NMOS tube M820, the PMOS tube M821 and the NMOS tube M822 constitute a three-stage inverter chain of progressive amplification for driving the gate of the HVNMOS tube HM82.

[0096] The two PMOS transistors M801 and M802 are interlockedly connected to form positive feedback, and the two NMOS transistors M809 and M810 are interlockedly connected to form positive feedback, which is used to speed up the voltage flipping speed of the four nodes A, B, C, and D.

[0097] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A high common mode transient suppression capacitor isolation type high voltage gate drive circuit, comprising a transmitting TX sub-chip (10) and a receiving RX sub-chip (30), wherein the differential OOK transmission signals TXP and TXN generated in the transmitting TX sub-chip (10) are respectively connected to one end of the positive terminal transmission capacitor Ctph and the negative terminal transmission capacitor Ctnh in the chip, and the other ends of the positive terminal transmission capacitor Ctph and the negative terminal transmission capacitor Ctnh are respectively connected to one end of the positive terminal reception capacitor Crph and the negative terminal reception capacitor Crnh in the receiving RX sub-chip (30), and the other ends of the positive terminal reception capacitor Crph and the negative terminal reception capacitor Crnh are respectively differential reception signals RXP and RXN; wherein the circuit is characterized in that: The transmitting TX sub-chip (10) further comprises a first input receiving circuit (1), a high common mode transient suppression differential OOK modulation circuit (2), and an OSC oscillation generating circuit (3); the receiving RX sub-chip (30) further comprises a high common mode transient suppression differential OOK receiving circuit (4) and a common mode suppression output driving circuit (5); The ground potentials of all circuits inside the transmitting TX sub-chip (10) are connected to the ground voltage GND, and the ground potentials of all circuits inside the receiving RX sub-chip (30) are connected to the ground voltage GND2; The first input receiving circuit (1) adopts a power supply voltage VCC, the high common mode transient suppression differential OOK modulation circuit (2) and the OSC oscillation generating circuit (3) adopt a low voltage power supply voltage VCCL; the common mode suppression output driving circuit (5) adopts a power supply voltage VDD, and the high common mode transient suppression differential OOK receiving circuit (4) adopts a low voltage power supply voltage VDDL; The first input receiving circuit (1) receives external input data IN and converts it into input data Din whose high level is the power supply voltage VCC; the input data Din and the high-frequency OSC signal output by the OSC oscillation generating circuit (3) are connected to the high common-mode transient suppression differential OOK modulation circuit (2); the high common-mode transient suppression differential OOK modulation circuit (2) performs OOK modulation on the input data Din and the high-frequency OSC signal to obtain differential OOK transmission signals TXP and TXN; The differential receiving signals RXP and RXN are connected to a high common mode transient suppression differential OOK receiving circuit (4) to obtain output data Dout after processing; the output data Dout is connected to a common mode suppression output driving circuit (5) to obtain an output driving signal GO with a large current driving capability after buffering driving.

2. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 1, characterized in that: The high common mode transient suppression differential OOK modulation circuit (2) comprises: an inverter INV1, an inverter INV2, an inverter INV3, an inverter INV4, an inverter INV5, a NAND gate NAND1, a NAND gate NAND2, a PMOS tube M1, an NMOS tube M2, a PMOS tube M3, an NMOS tube M4, a P-end inverter substrate modulation signal generating circuit (21), an N-end inverter substrate modulation signal generating circuit (22) and an output common mode detection circuit (23); The input end of the inverter INV1 is connected to the input data Din, and the output end of the inverter INV1 is connected to the first input end of the NAND gate NAND1 and the first input end of the NAND gate NAND2; the output end of the NAND gate NAND1 is connected to the gate of the PMOS tube M1 and the gate of the NMOS tube M2 through the inverter INV2; The source of the PMOS tube M1 is connected to the power supply voltage VCCL; the drain of the PMOS tube M1 is connected to the drain of the NMOS tube M2 and one end of the positive end transmission capacitor Ctph, and the node generates a TXP signal connected to the P-end input signal end of the output common mode detection circuit (23); The input end of the inverter INV3 is connected to the OSC signal, the output end of the inverter INV3 is connected to the second input end of the NAND gate NAND1 and the input end of the inverter INV4, and the output end of the inverter INV4 is connected to the second input end of the NAND gate NAND2; the output end of the NAND gate NAND2 is connected to the gate of the PMOS tube M3 and the gate of the NMOS tube M4 through the inverter INV5; The source of the PMOS tube M3 is connected to the power supply voltage VCCL; the drain of the PMOS tube M3 is connected to the drain of the NMOS tube M4 and one end of the positive end transmission capacitor Ctnh, and the node generates a TXN signal connected to the N-end input signal end of the output common mode detection circuit (23); The output common mode detection circuit (23) is also connected to a positive phase reference voltage Vrp and a negative phase reference voltage Vrn. The output common mode detection circuit (23) outputs two signals, wherein a first common mode signal D1 is connected to an input end of a P-end inverter substrate modulation signal generating circuit (21), and a second common mode signal D2 is connected to an input end of an N-end inverter substrate modulation signal generating circuit (22); The substrate of the PMOS tube M1 is connected to the output signal bpp of the P-end inverter substrate modulation signal generating circuit (21), the substrate of the NMOS tube M2 is connected to the output signal bpn of the P-end inverter substrate modulation signal generating circuit (21), and the source of the NMOS tube M2 is connected to the ground voltage GND; The substrate of the PMOS tube M3 is connected to the output signal bnp of the N-end inverter substrate modulation signal generating circuit (22), the substrate of the NMOS tube M4 is connected to the output signal bnn of the N-end inverter substrate modulation signal generating circuit (22), and the source of the NMOS tube M4 is connected to the ground voltage GND; When the output common mode detection circuit (23) detects that rising edge common mode transient coupling interference occurs on the signals TXP and TXN, the substrate voltage is modulated to reduce the bpp and bnp voltages while increasing the bnn and bpn voltages, thereby enhancing the pull-down capability of the NMOS tubes M2 and M4 and reducing the pull-up capability of the PMOS tubes M1 and M3, thereby achieving balanced compensation for the rising edge common mode transient coupling interference and keeping the flip threshold voltages of the two inverters unchanged; when falling edge common mode transient coupling interference occurs on the signals TXP and TXN, the substrate voltage is modulated to reduce the bpn and bnn voltages while increasing the bnp and bpp voltages, thereby reducing the pull-down capability of the NMOS tubes M2 and M4 and increasing the pull-up capability of the PMOS tubes M1 and M3, thereby achieving balanced compensation for the falling edge common mode transient coupling interference and keeping the flip threshold voltages of the two inverters unchanged.

3. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 2, characterized in that: The output common mode detection circuit (23) comprises: a resistor R1, a resistor R2, a comparator A1, a comparator A2, an inverter INV11, an inverter INV12, a transmission gate TG1, and a transmission gate TG2; The upper end of the resistor R1 is connected to the OOK positive phase signal TXP, and the lower end of the resistor R1 is connected to the upper end of the resistor R2. The node generates an OOK common mode voltage Vcm which is connected to the inverting input end of the comparator A1, the inverting input end of the comparator A2, the input end of the transmission gate TG1, and the input end of the transmission gate TG2. The lower end of the resistor R2 is connected to the OOK inverting signal TXN. The positive phase input terminal of the comparator A1 is connected to the positive phase reference voltage Vrp, the output terminal of the comparator A1 is connected to the input terminal of the inverter INV11, the C inverting control terminal of the transmission gate TG1, and the locking signal SP; the output terminal of the inverter INV11 is connected to the C control terminal of the transmission gate TG1, and the output terminal of the transmission gate TG1 is connected to the first common mode signal D1 output by the output common mode detection circuit (23); The positive phase input terminal of the comparator A2 is connected to the negative phase reference voltage Vrn, the output terminal of the comparator A2 is connected to the input terminal of the inverter INV12, the C inverting control terminal of the transmission gate TG2, and the locking signal SN; the output terminal of the inverter INV12 is connected to the C control terminal of the transmission gate TG2; the output terminal of the transmission gate TG2 is connected to the second common mode signal D2 output by the output common mode detection circuit (23).

4. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 3, characterized in that: The output common-mode detection circuit (23) first detects the common-mode level of the differential OOK signals TXP and TXN through the resistors R1 and R2 to obtain the OOK common-mode voltage Vcm. Under normal circumstances, the common-mode voltage Vcm is VCCL / 2. When common-mode transient interference occurs, the Vcm voltage will change. Comparators A1 and A2 compare the OOK common-mode voltage Vcm with the positive-phase reference voltage Vrp and the negative-phase reference voltage Vrn respectively to obtain the locking signal SP and the locking signal SN, respectively judging the rising edge and the falling edge of the common-mode transient interference. Then, the locking signal SP and the locking signal SN respectively output the first common mode signal D1 and the second common mode signal D2 through the transmission gate TG1 and the transmission gate TG2, respectively controlling the P-end inverter substrate modulation signal generating circuit (21) and the N-end inverter substrate modulation signal generating circuit (22).

5. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 3, characterized in that: The P-end inverter substrate modulation signal generating circuit (21) and the N-end inverter substrate modulation signal generating circuit (22) are implemented by using the same inverter substrate modulation signal generating circuit, and the circuit structure includes: PMOS tube MP2, PMOS tube MP3, NMOS tube MN2, NMOS tube MN3, resistor Rt1, resistor Rt2, transmission gate TG7, inverter INV70; The source of the PMOS tube MP2 and the upper end of the resistor Rt2 are connected to the power supply VCC; the lower end of the resistor Rt1 and the source of the NMOS tube MN3 are connected to the ground voltage GND; The gate of the PMOS tube MP2 is connected to the first positive phase bias voltage Vbtp1; the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP3, and is also connected to the output end of the transmission gate TG7; the source of the NMOS tube MN2 is connected to the drain of the NMOS tube MN3, and is also connected to the output end of the transmission gate TG7; the gate of the NMOS tube MN3 is connected to the first negative phase bias voltage Vbtn1, and the gate of the NMOS tube MN2 is connected to the second negative phase bias voltage Vbtn2; The gate of the PMOS tube MP3 is connected to the second positive phase bias voltage Vbtp2; the drain of the PMOS tube MP3 is connected to the upper end of the resistor Rt1, and outputs an inverse substrate signal; the drain of the NMOS tube MN2 is connected to the lower end of the resistor Rt2, and outputs a positive phase substrate signal; The input end of the transmission gate TG7 is connected to the OOK common mode voltage Vcm, and one of the two control ends of the transmission gate TG7 is connected to the common mode signal D1 or D2, and the other is connected to the inverse signal obtained by the common mode signal D1 or D2 through the inverter INV70.

6. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 5, characterized in that: The PMOS tube MP2, the PMOS tube MP3 and the resistor Rt1 form a first cascode amplifier, the drain of the PMOS tube MP2 and the source of the PMOS tube MP3 are the input terminals of the first cascode amplifier, and the positive phase substrate signal is the output terminal of the first cascode amplifier; The NMOS transistor MN2, the NMOS transistor MN3 and the resistor Rt2 form a second cascode amplifier, the source of the NMOS transistor MN2 and the drain of the NMOS transistor MN3 are the input terminals of the second cascode amplifier, and the inverted substrate signal is the output terminal thereof; The transmission gate TG7 and the inverter INV70 are used to simultaneously transmit the OOK common-mode voltage Vcm to the first cascode amplifier input terminal and the second cascode amplifier input terminal when the common-mode signal D1 or D2 is valid.

7. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 1, characterized in that: The common-mode suppression output drive circuit (5) comprises: a source of a PMOS tube M801, a source of a MOS tube M804, a source of a PMOS tube M807, a source of a PMOS tube M809, a source of a PMOS tube M811, a source of a PMOS tube M813, a source of a PMOS tube M815, a source of a PMOS tube M817, a source of a PMOS tube M819, a source of a PMOS tube M821, a source of a HVPMOS tube HM81, and an upper end of a resistor R81, all of which are connected to a power supply voltage VDD; The source of NMOS tube M808, the source of NMOS tube M810, the source of NMOS tube M812, the source of NMOS tube M814, the source of NMOS tube M816, the source of NMOS tube M818, the source of NMOS tube M820, the source of NMOS tube M822, and the source of HVNMOS tube HM82 are all connected to the chip ground voltage GND2; the source of NMOS tube M803 and the source of NMOS tube M806 are connected to the ground signal GND1 buffered by deep N well isolation of GND2; The gate of the PMOS tube M801, the drain of the PMOS tube M804, the source of the PMOS tube M805, and the gate of the PMOS tube M807 are connected to the circuit node B; the drain of the PMOS tube M801, the gate of the PMOS tube M804, the lower end of the resistor R81, the source of the PMOS tube M802, and the gate of the PMOS tube M809 are connected to the circuit node A; The gates of the PMOS tube M802 and the PMOS tube M805 are connected to the floating bias voltage signal Vsh; the drain of the PMOS tube M802 is connected to the drain of the NMOS tube M803; the drain of the PMOS tube M805 is connected to the drain of the NMOS tube M806; the signal Dout is connected to the gate of the NMOS tube M806, and is connected to the gate of the NMOS tube M803 through the inverter INV81; The drain of the PMOS tube M807, the drain of the NMOS tube M808, and the gate of the NMOS tube M810 are connected to the circuit node C; the gate of the NMOS tube M808, the drain of the PMOS tube M809, the drain of the NMOS tube M810, the gate of the PMOS tube M811, the gate of the NMOS tube M812, the gate of the PMOS tube M817, and the gate of the NMOS tube M818 are connected to the circuit node D; The drain of the PMOS tube M811 is connected to the drain of the NMOS tube M812, the gate of the PMOS tube M813, and the gate of the NMOS tube M814; the drain of the PMOS tube M813 is connected to the drain of the NMOS tube M814, the gate of the PMOS tube M815, and the gate of the NMOS tube M816; the drain of the PMOS tube M815 is connected to the drain of the NMOS tube M816 and the gate of the HVPMOS tube HM81; The drain of the PMOS tube M817 is connected to the drain of the NMOS tube M818, the gate of the PMOS tube M819, and the gate of the NMOS tube M820; the drain of the PMOS tube M819 is connected to the drain of the NMOS tube M820, the gate of the PMOS tube M821, and the gate of the NMOS tube M822; the drain of the PMOS tube M821 is connected to the drain of the NMOS tube M822 and the gate of the HVNMOS tube HM82; The drain of the HVPMOS tube HM81 is connected to the drain of the HVNMOS tube HM82 and outputs a driving signal GO.

8. The high common mode transient suppression capacitor isolated high voltage gate drive circuit according to claim 7, characterized in that: The resistor R81, the inverter INV81, the PMOS tube M801, the PMOS tube M802, the NMOS tube M803, the PMOS tube M804, the PMOS tube M805 and the NMOS tube M806 constitute a differential input level conversion buffer amplifier; the gate of the NMOS tube M803 is connected to the output of the signal Dout reversed by the inverter INV81, and the gate of the NMOS tube M806 is connected to the signal Dout, so the gate of the NMOS tube M803 and the gate of the NMOS tube M806 are differential complementary low swing signals, and the source of the NMOS tube M803 and the source of the NMOS tube M806 are connected to the ground signal GND1 buffered by the deep N well isolation of the ground voltage GND2, so as to improve the influence of the common mode transient interference of GND2 on the differential input level conversion buffer amplifier; The PMOS tube M811, the NMOS tube M812, the PMOS tube M813, the NMOS tube M814, the PMOS tube M815 and the NMOS tube M816 form a three-stage inverter chain of step-by-step amplification, which is used to drive the gate of the HVPMOS tube HM81; the PMOS tube M817, the NMOS tube M818, the PMOS tube M819, the NMOS tube M820, the PMOS tube M821 and the NMOS tube M822 form a three-stage inverter chain of step-by-step amplification, which is used to drive the gate of the HVNMOS tube HM82; The two PMOS transistors M801 and M802 are interlockedly connected to form positive feedback, and the two NMOS transistors M809 and M810 are interlockedly connected to form positive feedback, which are used to accelerate the voltage flipping speed of the four nodes A, B, C, and D.

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