A calibration method and apparatus for Fibonacci capacitance arrays based on the relationship between squares and preceding and following terms.

Abstract

This invention relates to a calibration method and apparatus for a Fibonacci capacitor array based on the relationship between the square and preceding and following terms, belonging to the field of integrated circuit technology. The capacitor array includes two capacitor array controllers (CDACs): a main CDAC and a correction CDAC. The main CDAC capacitor array is arranged according to the ratios of the Fibonacci sequence. The correction CDAC is used to store a certain range of capacitor mismatch and is connected to the main CDAC via a series capacitor. The calibration method includes a calibration phase and an operating phase. This invention calibrates the capacitor array by utilizing the characteristics of the relationship between the square and preceding and following terms of the Fibonacci sequence, correcting errors caused by mismatch between adjacent capacitors in the array.

Description

Technical Field

[0001] This invention relates to a calibration method and calibration device for a Fibonacci capacitance array based on the square and preceding-following terms relationship, belonging to the field of integrated circuit technology. Background Technology

[0002] An analog-to-digital converter (ADC) is a device (circuit) that converts analog signals into digital signals, such as converting information like temperature, humidity, pressure, and position into digital signals.

[0003] Currently, DACs in SAR ADC (Successive Approximation Register Analog-to-Digital Converter) generally use charge redistribution capacitor arrays.

[0004] The Fibonacci sequence, also known as the golden ratio sequence, has the following values: 1, 1, 2, 3, 5, 8, 13, 21, 34… Starting from the third term, each term is equal to the sum of the two preceding terms. Mathematically, this sequence is defined recursively as follows: F(0) = 0, F(1) = 1, F(n) = F(n-1) + F(n-2) (n ≥ 2, n ∈ N*).

[0005] The main CDAC capacitor array adopts a Fibonacci sequence ratio arrangement, where the weight value of each higher-order capacitor is less than the sum of the weight values ​​of its lower-order capacitors, satisfying a sub-binary relationship. The capacitor array has excellent redundancy characteristics; therefore, if a comparison error occurs in a higher order, it can be corrected by comparing lower orders, while also providing greater flexibility for subsequent calibration. Factors determining the accuracy of a SAR ADC include thermal noise from the sampling switch, input noise from the comparator, capacitor mismatch, and parasitic capacitance. Among these, capacitor mismatch has the greatest impact; the greater the mismatch ratio, the worse the ADC's accuracy. The accuracy of the capacitor array arranged using Fibonacci sequence ratios directly determines the overall accuracy of the SAR ADC. To achieve high accuracy and high linearity, SAR ADCs with 12 bits or more require capacitor array calibration to reduce the impact of system and random mismatches. Therefore, this invention is proposed. Summary of the Invention

[0006] To address the shortcomings of existing technologies, this invention provides a calibration method and apparatus for a Fibonacci capacitor array based on the relationship between the square and preceding and following terms. The method calibrates the capacitor array by utilizing the characteristics of the relationship between the square and preceding and following terms of the Fibonacci sequence, thereby correcting errors caused by mismatch between adjacent capacitors in the capacitor array.

[0007] The technical solution of the present invention is as follows:

[0008] A calibration method for a Fibonacci capacitor array based on the relationship between squares and preceding and following terms is proposed. The capacitor array includes two CDACs, namely a main CDAC and a correction CDAC. The main CDAC capacitor array adopts a ratio arrangement layout of the Fibonacci sequence. The correction CDAC is used to store a certain range of capacitor mismatch and is connected to the main CDAC through a series capacitor.

[0009] The calibration method consists of two stages:

[0010] (1) During the calibration phase, the error weight of the capacitor is measured and stored by using the characteristics of the preceding and following terms and the square of the Fibonacci sequence.

[0011] (2) During the working phase, the error weights stored in the calibration phase are converted into analog quantities by the calibration CDAC and superimposed on the main CDAC, thereby eliminating the capacitor mismatch of the main CDAC.

[0012] The purpose of calibrating the CDAC is to obtain the error voltage and the compensation calibration voltage. The calibration principle is to obtain the weight error by using the characteristics of the relationship between the square of the Fibonacci sequence and its preceding and following terms. By changing the capacitance value on the capacitor array, the mismatched capacitor weights are corrected, thereby reducing the deviation between the output encoded value and the input.

[0013] According to a further preferred embodiment of the present invention, in step (1), the error weight ξ in the calibration stage i The calculation is as follows:

[0014] Under a CDAC with N-bit weights, the capacitance value C for each weight is... n satisfy:

[0015] C n =F n *C*(1+ξ n ), n=1,2,3,...,N;

[0016] F n The general term formula for the Fibonacci sequence The characteristic is that, starting from the third term, each term is the sum of the previous two terms, where C represents unit capacitance, and ξ... n This represents the weighted error of the capacitance value of the nth capacitor, which reflects the influence of a series of factors including capacitor mismatch and parasitic capacitance of the lower plate.

[0017] Define the actual weight of each bit as follows:

[0018] Under ideal CDAC, assume ξ i =0, then the ideal weight is: w i,ideal =F i ;

[0019] Error weight ξ i The expression is: ξ i =w i -w i,ideal .

[0020] In the above formula, F i With F n C i With C n In this context, the subscripts i and n have the same meaning.

[0021] According to a preferred embodiment of the present invention, the specific steps of the working stage in step (2) are as follows:

[0022] Weighted error ξ i The binary encoding on the calibrated CDAC is x. i Let the i-th element in x be denoted as x(i), and the weight represented by x is: w x =k A x DEC x DEC The binary code x is converted to its decimal representation. Due to various non-ideal factors, there will be some error in correcting the CDAC weights. Therefore, a coefficient k that is not equal to 1 is used. A To indicate;

[0023] The squares of the Fibonacci sequence and its preceding and following terms exhibit the following properties: starting from the second term (forming a new sequence, with the first term being 1, the second term being 2, and so on), the square of each even-numbered term is 1 more than the product of the two preceding and following terms, and the square of each odd-numbered term is 1 less than the product of the two preceding and following terms. This can be expressed using the general term: F n 2 -F n-1 F n+1 =(-1) n-1 n≥2;

[0024] Under ideal conditions, the weights of the i-th capacitor, the (i-1)-th capacitor, and the (i+1)-th capacitor satisfy the following:

[0025] w i 2 -w i-1 w i+1 =(-1) n-1

[0026] Due to the presence of non-ideal factors, both parts also have errors, denoted as ξt. i (i = 1, 2, ..., N), ξt i The result, represented by the corrected CDAC encoding, is obtained through circuit operation and denoted as y. i ;

[0027] The following system of equations is derived:

[0028]

[0029] In the formula, w total Given the total weight of all bit capacitors in the main CDAC, the first equation in the above system of equations is clearly true; the second equation reflects the deviation ξt between the actual weight of the i-th bit capacitor and the actual weights of the (i-1)-th and i+1-th bit capacitors based on the square and the relationship between the preceding and following terms. i y is represented by a corrected CDAC. i The third equation reflects the deviation ξ between the actual weight and the ideal weight of the i-th element. i denoted as x using a corrected CDAC i y i The error weight code x is obtained by using circuit operations and solving a system of equations. i ;

[0030] Using a corrected CDAC to encode x based on error weights i Perform corresponding operations to offset the errors in the main CDAC, so that the weight change in the CDAC satisfies the general formula of the Fibonacci sequence for each time.

[0031] According to a further preferred embodiment of the present invention, in step (2), the corrected CDAC is encoded according to the error weights x. i The corresponding operations performed are as follows:

[0032] When converting the main CDAC weights, after converting to a certain bit, the error weight encoding x corresponding to that bit is... i The error weights stored during the calibration phase are immediately fed back into the corresponding calibration CDAC. The error weights are converted into analog values ​​by the calibration CDAC and superimposed on the main CDAC to achieve calibration of that bit.

[0033] A calibration device for a Fibonacci capacitor array based on the square and the relationship between the preceding and following terms includes a main CDAC, a voltage comparator, a digital control circuit, a data register, and a calibration CDAC. The output of the main CDAC capacitor array is connected to the input of the voltage comparator. The voltage comparator is used to determine the magnitude of the output voltage of the upper-level board of the main CDAC capacitor array. Specifically, the voltage comparator compares the output voltage of the upper-level board of the Fibonacci capacitor array with 0. If it is greater than 0, the comparator outputs 1; otherwise, the output is 0. The input of the main CDAC capacitor array is connected to the digital control circuit. The digital control circuit is connected to the calibration CDAC through the data register. The calibration CDAC is connected to the main CDAC through a series capacitor.

[0034] The digital control circuit is used to control the switching sequence of the switches on the lower-level board of the main CDAC capacitor array and to control the enable in the data register. The data register is used to store nonlinear calibration items, which are digital codes. When calibrating the main CDAC capacitor array, the calibration items are passed to the calibration CDAC. The calibration CDAC is used to convert the nonlinear calibration items into analog values ​​and feed them back to the main CDAC capacitor array when calibrating the main CDAC capacitor array.

[0035] The beneficial effects of this invention are as follows:

[0036] The improvement in the accuracy of successive approximation analog-to-digital converters is mainly limited by parasitic and mismatched effects caused by the excessively large area of ​​CDAC capacitors and by trace parasitics. Using a CDAC capacitor array structure based on the Fibonacci sequence can improve the effects of parasitic and mismatched effects. This invention proposes a self-calibration method for Fibonacci capacitor arrays based on the relationship between the square and the preceding and following terms. By changing the amount of charge stored in the capacitors, the weights are changed, which greatly corrects the problem of proportional imbalance caused by mismatch between adjacent capacitors and effectively improves the accuracy. Attached Figure Description

[0037] Figure 1 Connection diagram for 8-bit calibrated CDAC;

[0038] Figure 2 This is a schematic diagram of the main CDAC connection during the pre-charging stage of the capacitor array in Embodiment 1 of the present invention;

[0039] Figure 3 This is a schematic diagram of the main CDAC connection during the charge redistribution stage of the capacitor array in Embodiment 1 of the present invention;

[0040] Figure 4 This is a schematic diagram of the self-calibration implementation circuit of Embodiment 2 of the present invention. Detailed Implementation

[0041] The present invention will be further described below with reference to the embodiments and accompanying drawings, but is not limited thereto.

[0042] Example 1:

[0043] This embodiment provides a calibration method for a Fibonacci capacitor array based on the square and preceding / following terms relationship. The capacitor array includes two CDACs: a main CDAC and a correction CDAC. The main CDAC is a charge redistribution CDAC. The capacitor array is arranged in a ratio layout according to the Fibonacci sequence. The correction CDAC is used to store a certain range of capacitor mismatch and is connected to the main CDAC through a series capacitor. The error weight of each capacitor in the main CDAC capacitor array is quantified to obtain a digital error weight. The digital error weight is used as a nonlinear calibration term and stored in a data register.

[0044] When calibrating the main CDAC capacitor array, the data register passes the calibration terms to the calibration CDAC. The calibration CDAC converts the nonlinear calibration terms into analog values ​​and feeds them back to the main CDAC capacitor array.

[0045] The calibration method consists of two stages:

[0046] (1) During the calibration phase, the error weight of the capacitor is measured and stored by using the characteristics of the preceding and following terms and the square of the Fibonacci sequence.

[0047] Error weight ξ i The calculation is as follows:

[0048] Under a CDAC with N-bit weights, the capacitance value C for each weight is... n satisfy:

[0049] C n =F n *C*(1+ξ n ), n=1,2,3,...,N;

[0050] F n The general term formula for the Fibonacci sequence The characteristic is that, starting from the third term, each term is the sum of the previous two terms, where C represents unit capacitance, and ξ... n This represents the weighted error of the capacitance value of the nth capacitor, which reflects the influence of a series of factors including capacitor mismatch and parasitic capacitance of the lower plate.

[0051] Define the actual weight of each bit as follows:

[0052] Under ideal CDAC, assume ξ i =0, then the ideal weight is: w i,ideal =F i ;

[0053] Error weight ξ i The expression is: ξ i =w i -w i,ideal .

[0054] (2) During the working phase, the error weights stored in the calibration phase are converted into analog quantities by the calibration CDAC and superimposed on the main CDAC, thereby eliminating the capacitor mismatch of the main CDAC.

[0055] Weighted error ξ i The binary encoding on the calibrated CDAC is x. i Let the i-th element in x be denoted as x(i), and the weight represented by x is: w x=k A x DEC x DEC The binary code x is converted to its decimal representation. Due to various non-ideal factors, there will be some error in correcting the CDAC weights. Therefore, a coefficient k that is not equal to 1 is used. A To indicate;

[0056] The squares of the Fibonacci sequence and its preceding and following terms exhibit the following properties: starting from the second term (forming a new sequence, with the first term being 1, the second term being 2, and so on), the square of each even-numbered term is 1 more than the product of the two preceding and following terms, and the square of each odd-numbered term is 1 less than the product of the two preceding and following terms. This can be expressed using the general term: F n 2 -F n-1 F n+1 =(-1) n-1 n≥2;

[0057] Under ideal conditions, the weights of the i-th capacitor, the (i-1)-th capacitor, and the (i+1)-th capacitor satisfy the following:

[0058] w i 2 -w i-1 w i+1 =(-1) n-1

[0059] Due to the presence of non-ideal factors, both parts also have errors, denoted as ξt. i (i = 1, 2, ..., N), ξt i The result, represented by the corrected CDAC encoding, is obtained through circuit operation and denoted as y. i ;

[0060] The following system of equations is derived:

[0061]

[0062] In the formula, w total Given the total weight of all bit capacitors in the main CDAC, the first equation in the above system of equations is clearly true; the second equation reflects the deviation ξt between the actual weight of the i-th bit capacitor and the actual weights of the (i-1)-th and i+1-th bit capacitors based on the square and the relationship between the preceding and following terms. i y is represented by a corrected CDAC. i The third equation reflects the deviation ξ between the actual weight and the ideal weight of the i-th element. i denoted as x using a corrected CDAC i y i The error weight code x is obtained by using circuit operations and solving a system of equations. i ;

[0063] Using a corrected CDAC to encode x based on error weights i Perform corresponding operations to offset the errors in the main CDAC, so that the weight change in the CDAC satisfies the general formula of the Fibonacci sequence for each time.

[0064] Corrected CDAC encoding x based on error weights i The corresponding operations performed are as follows:

[0065] When converting the main CDAC weights, after converting to a certain bit, the error weight encoding x corresponding to that bit is... i The error weights stored during the calibration phase are immediately fed back into the corresponding calibration CDAC. The error weights are converted into analog values ​​by the calibration CDAC and superimposed on the main CDAC to achieve calibration of that bit.

[0066] Example 2:

[0067] This embodiment provides a calibration device for a Fibonacci capacitor array based on the square and preceding-following terms relationship, including a main CDAC, a voltage comparator, a digital control circuit, a data register, and a correction CDAC. The output of the main CDAC capacitor array is connected to the input of the voltage comparator. The voltage comparator is used to determine the magnitude of the output voltage of the upper-level board of the main CDAC capacitor array. Specifically, the voltage comparator compares the output voltage of the upper-level board of the Fibonacci capacitor array with 0. If it is greater than 0, the comparator outputs 1; otherwise, the output is 0. The input of the main CDAC capacitor array is connected to the digital control circuit. The digital control circuit is connected to the correction CDAC through the data register. The correction CDAC is connected to the main CDAC through a series capacitor.

[0068] The digital control circuit is used to control the switching sequence of the switches on the lower-level board of the main CDAC capacitor array and to control the enable in the data register. The data register is used to store nonlinear calibration items, which are digital codes. When calibrating the main CDAC capacitor array, the calibration items are passed to the calibration CDAC. The calibration CDAC is used to convert the nonlinear calibration items into analog values ​​and feed them back to the main CDAC capacitor array when calibrating the main CDAC capacitor array.

Claims

1. A calibration method for a Fibonacci capacitance array based on the relationship between the square and the preceding and following terms, characterized in that, The capacitor array includes two CDACs: a main CDAC and a correction CDAC. The main CDAC capacitor array is arranged in a Fibonacci sequence ratio layout. The correction CDAC is used to store a certain range of capacitor mismatch and is connected to the main CDAC through a series capacitor. The calibration method consists of two stages: (1) During the calibration phase, the error weight of the capacitor is measured and stored by using the characteristics of the preceding and following terms and the square of the Fibonacci sequence; Error weights ξ during calibration i The calculation is as follows: Under a CDAC with N-bit weights, the capacitance value C for each weight is... n satisfy: ； F n The general term formula for the Fibonacci sequence The characteristic is that, starting from the third term, each term is the sum of the previous two terms, where C represents the unit capacitance, and ξ... n This represents the weighted error of the capacitance value of the nth capacitor. Define the actual weight of each bit as follows: ; Under ideal CDAC, assume ξ i =0, then the ideal weight is: w i,ideal =F i ; Error weight ξ i The expression is: ξ i =w i - w i,ideal ; (2) During the working phase, the error weights stored in the calibration phase are converted into analog quantities by the calibration CDAC and superimposed on the main CDAC, thereby eliminating the capacitor mismatch of the main CDAC; The specific steps are as follows: Weighted error ξ i The binary encoding on the calibrated CDAC is x. i Let the i-th element in x be denoted as x(i), and the weight represented by x is: w x =k A x DEC x DEC The binary code x is converted to its decimal representation. Due to various non-ideal factors, there will be some error in correcting the CDAC weights. Therefore, a coefficient k that is not equal to 1 is used. A To indicate; The squares of the Fibonacci sequence and its preceding and following terms share the following properties: starting from the second term, the square of each even-numbered term is 1 more than the product of the two preceding and following terms, and the square of each odd-numbered term is 1 less than the product of the two preceding and following terms. This can be expressed using a general term as follows: ; Under ideal conditions, the weights of the i-th capacitor, the (i-1)-th capacitor, and the (i+1)-th capacitor satisfy the following: Due to the existence of non-ideal factors, denoted as ξt i , i=1,2,…,N,ξt i The result, represented by the corrected CDAC encoding, is obtained through circuit operation and denoted as y. i ; The following system of equations is derived: In the formula, w total Given the total weight of all bit capacitors in the main CDAC, the first equation in the above system of equations is clearly true; the second equation reflects the deviation ξt between the actual weight of the i-th bit capacitor and the actual weights of the (i-1)-th and i+1-th bit capacitors based on the square and the relationship between the preceding and following terms. i y is represented by a corrected CDAC. i The third equation reflects the deviation ξ between the actual weight and the ideal weight of the i-th element. i denoted as x using a corrected CDAC i y i The error weight code x is obtained by using circuit operations and solving a system of equations. i ; Using a corrected CDAC to encode x based on error weights i Perform corresponding operations to offset the errors in the main CDAC, so that the weight change in the CDAC satisfies the general formula of the Fibonacci sequence for each time.

2. The calibration method for a Fibonacci capacitance array based on the square and preceding / sub-term relationship as described in claim 1, characterized in that, In step (2), the corrected CDAC encodes x according to the error weights. i The corresponding operations performed are as follows: When converting the main CDAC weights, after converting to a certain bit, the error weight encoding x corresponding to that bit is... i The error weights stored during the calibration phase are immediately fed back into the corresponding calibration CDAC. The error weights are converted into analog values ​​by the calibration CDAC and superimposed on the main CDAC to achieve calibration of that bit.

3. A calibration device for a Fibonacci capacitance array based on the relationship between squares and preceding and following terms, characterized in that, The calibration method for the Fibonacci capacitor array based on the square and preceding / sub-term relationship as described in claim 1 includes a main CDAC, a voltage comparator, a digital control circuit, a data register, and a correction CDAC. The output of the main CDAC capacitor array is connected to the input of the voltage comparator, which is used to determine the magnitude of the output voltage of the upper-level board of the main CDAC capacitor array. The input of the main CDAC capacitor array is connected to the digital control circuit, which is connected to the correction CDAC through the data register. The correction CDAC is connected to the main CDAC through a series capacitor. The digital control circuit is used to control the switching sequence of the switches on the lower-level board of the main CDAC capacitor array and to control the enable in the data register. The data register is used to store nonlinear calibration items, which are digital codes. When calibrating the main CDAC capacitor array, the calibration items are passed to the calibration CDAC. The calibration CDAC is used to convert the nonlinear calibration items into analog values ​​and feed them back to the main CDAC capacitor array when calibrating the main CDAC capacitor array.

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