Analog signal acquisition and processing circuit and method

Abstract

The application belongs to the technical field of analog signal conversion, and particularly relates to an analog signal acquisition and processing circuit and method. The analog signal receiving interface is provided with dozens of analog signal receiving endpoints for distributed parallel analog signal receiving. The data processing module integrates an ARM processor and an FPGA chip. The data processing module is used to perform complex data processing and logic control tasks, realize high-integration analog signal receiving, structured hardware design, reduce data receiving cost and power consumption, and improve data receiving accuracy. The dozens of ports are designed to simultaneously receive analog signals, and the data processing module is used to perform parallel processing, so that the conversion from analog signals to digital signals at the receiving end is realized, the real-time performance of time-sensitive change data processing is greatly improved, and the analog signal information is accurately calibrated through the method of step-by-step calibration of multi-channel analog signal data, so that the precision and reliability of the analog signal acquisition and processing circuit are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of analog signal receiving, and particularly relates to an analog signal acquisition and processing circuit and method. BACKGROUND

[0002] The analog signal acquisition and processing circuit is an electronic circuit for measuring and recording analog signal information. It can convert analog signals on the surface of an object into electrical signals and process and transmit them through a digitizing circuit. The analog signal sensor is the core component, which can physically perceive analog signals in the environment and convert the perceived analog signals into electrical signals. These electrical signals are then converted into digital signals by an analog-to-digital converter, and the internal processing chip further processes the digital signals and sends them to the host computer or controller.

[0003] However, the existing analog signal acquisition and processing circuit is affected by environmental factors, which causes the analog signal acquisition and processing circuit to receive analog signals with high or low values in various environments, and the received analog signal values may also have large errors. Moreover, the accuracy of the analog signal acquisition and processing circuit is limited by the hardware of the receiving module and the changes of the analog signal.

[0004] Therefore, how to improve the accuracy of the analog signal receiving result of the analog signal acquisition and processing circuit, reduce the errors existing in the analog signal receiving process, and simplify the hardware structure design and reduce the cost of the system is a technical problem that needs to be solved at present. SUMMARY

[0005] The purpose of the present application is to provide an analog signal acquisition and processing circuit to improve the accuracy of the analog signal receiving result of the analog signal acquisition and processing circuit, reduce the errors existing in the analog signal receiving process, and simplify the hardware structure design and reduce the cost of the system.

[0006] To solve the above technical problems, the technical solution adopted by the present application is as follows:

[0007] In a first aspect, an analog signal acquisition and processing circuit is provided, comprising a power module, a storage module, a communication module, an analog signal receiving interface, and a data processing module. The power module, the storage module, the communication module, and the analog signal receiving interface are connected to the data processing module.

[0008] The analog signal receiving interface is provided with tens or hundreds of analog signal receiving endpoints for distributed parallel analog signal receiving. The data processing module integrates an ARM processor and an FPGA chip.

[0009] The power module is used to provide working voltage for the analog signal acquisition and processing circuit.

[0010] The analog signal receiving interface is configured to receive analog signals collected by sensors.

[0011] The data processing module is configured to locally and in parallel process the analog signals received by each of the analog signal receiving interfaces and convert the analog signals into digital signals.

[0012] The storage module is configured to store the received analog signals, the converted digital signals, and processing programs.

[0013] The communication module is configured to transmit the received analog signals to the data processing module and transmit the converted digital signals to a remote terminal.

[0014] Preferably, the analog signal receiving interface is configured to receive temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals, and angle analog signals.

[0015] Preferably, the analog signal receiving interface is provided with N channels, the N channels are tens or hundreds of channels, and each end point of the N channels is connected to a sensor chip. The first interface FORCE2 1, FORCE_P1 of the N channels of the analog signal receiving interface is connected to the FORCE2 1, FORCE_P1 port of the first sensor chip, the second interface FORCE2 2, FORCE_P2 is connected to the FORCE2 2, FORCE_P2 port of the second sensor chip, the third interface FORCE2 3, FORCE_P3 is connected to the FORCE2 3, FORCE_P3 port of the first sensor chip, and so on, and the Nth interface FORCE2 N, FORCE_PN is connected to the FORCE2 N, FORCE_PN port of the Nth sensor chip.

[0016] The analog signal receiving interface further comprises an eighth 855 capacitor, an eighth 854 capacitor, a fourth 418 resistor, the RTDIN+ and RTDIN- ports of the sensor chip are connected through the eighth 855 capacitor, the BIAS, REFIN- and REFIN-, ISENSOR are connected through the fourth 418 resistor, and the VDD and DVDD ports are grounded through the eighth 854 capacitor.

[0017] Preferably, the storage module comprises a storage chip, and the / CS port, DO port, / WP port, HOLD port, CLK port, and DI port of the storage chip are respectively connected to the QSPI_CS port, QSPI_DAT1 port, QSPI_DAT2 port, QSPI_DAT3 port, QSPI_CLK port, and QSPI_DAT0 port of the data processing module.

[0018] Preferably, the storage module is externally connected with N' pieces of DDR memory chips for program cache, wherein N' is a positive integer greater than or equal to 1.

[0019] Preferably, the communication module comprises a communication chip and an Ethernet communication interface, the communication chip is connected with the data processing module, and the communication chip is connected with the Ethernet communication interface for transmitting analog signal information and accepting remote control commands.

[0020] The communication chip comprises a third R81 resistor, a third R82 resistor, a third R83 resistor, a third R91 resistor, a third R92 resistor, a third R93 resistor, a third R94 resistor, a third R95 resistor, a third R96 resistor, a third R97 resistor, a third R98 resistor, a third R99 resistor, a fourth R100 resistor, a fourth R101 resistor, a fourth R102 resistor, a first D82 diode, and a second D42 diode.

[0021] The SCSN port, the INTN port, the RSTN port, the SPDLED port, the DUPLED port, the PMODE0 port, the PMODE1 port, the PMODE2 port, the RSVD1 port, the RSVD2 port, the RSVD3 port, the RSVD4 port, and the RSVD5 port of the communication chip are respectively connected with the third R81 resistor, the third R82 resistor, the third R83 resistor, the first D82 diode, the second D42 diode, the third R93 resistor, the third R94 resistor, the third R95 resistor, the third R97 resistor, the third R98 resistor, the third R99 resistor, the fourth R100 resistor, the fourth R101 resistor, and the fourth R102 resistor.

[0022] Preferably, the power module comprises a first power conversion module, a second power conversion module, a third power conversion module, a fourth power conversion module, and a fifth power conversion module.

[0023] The first power conversion module is used for converting 24V voltage into 5V voltage, and comprises a first conversion chip, a ninth R39 capacitor, an eighth C42 capacitor, a ninth R38 capacitor, an eighth C47 capacitor, a ninth C40 capacitor, a ninth C41 capacitor, a third R64 resistor, a third R65 resistor, a third R66 resistor, a fourth R02 resistor, and an inductor.

[0024] The ninth R39 capacitor, the eighth C42 capacitor, and the ninth R38 capacitor are connected in parallel, and one end of the parallel connection is connected with a 24V voltage output end, and the other end is connected with a VIN port of the first conversion chip; an ON#OFF port of the first conversion chip is connected with the third R64 resistor; a VOUT port of the first conversion chip is connected with the third R65 resistor, the third R66 resistor, and the fourth R02 resistor in series through an inductor; and the inductor is connected with the eighth C47 capacitor, the ninth C40 capacitor, and the ninth C41 capacitor in sequence and then grounded.

[0025] Preferably, the second power conversion module is used to realize the conversion from 5V voltage to 1V voltage, comprising a second conversion chip, a fourth R61 resistor, a fourth R64 resistor, a fourth R65 resistor, a ninth C42 capacitor, a ninth C43 capacitor, a ninth C45 capacitor, and a ninth C44 capacitor;

[0026] One end of the ninth C42 capacitor is grounded, and the other end is connected to 5V voltage, a VIN port of the second conversion chip, and the fourth R61 resistor, respectively. The fourth R61 resistor is connected to an EN port of the second conversion chip. An SS port of the second conversion chip is grounded through the ninth C43 capacitor.

[0027] A VOUT port of the second conversion chip is connected to the fourth R64 resistor and the ninth C45 capacitor, respectively. The ninth C45 capacitor and the ninth C44 capacitor are connected in parallel, one end of which is connected to a 1V voltage output end, and the other end is grounded. The fourth R64 resistor and the fourth R65 resistor are connected to an ADJ port of the second conversion chip and grounded.

[0028] Preferably, the electronic components and connection relationships of the third power conversion module, the fourth power conversion module, and the fifth power conversion module are the same as those of the second power conversion module.

[0029] The display module is further included, which is connected to the data processing module and used to display the measured real-time analog signal information and configure parameters through a visual interface of the display module.

[0030] In a second aspect, an analog signal acquisition and processing method is provided, comprising the following steps:

[0031] S1: N analog signal collection ports simultaneously receive analog signals transmitted from sensors and add receiving labels;

[0032] S2: Each analog signal collection port synchronously and in parallel transmits the received analog signals to a data processing module. The data processing module synchronously and in parallel processes and converts the acquired analog signals into digital signals.

[0033] S3: An internal device or object monitoring state algorithm is built in to process abnormal conditions of the monitored device or object in real time.

[0034] S4: The converted digital signals are stored on a storage module and synchronously and in parallel transmitted to a remote digital platform for digital construction.

[0035] S5: A communication interface of the communication module receives instructions from the remote digital platform and controls or intervenes in the monitored device or object.

[0036] After the conversion of each analog signal in step S2, the data processing module performs synchronous and parallel calibration processing on each received digital signal through a preset calibration coefficient.

[0037] Preferably, step S2 further comprises the following steps:

[0038] S21: The data processing module calibrates the first digital signal information with the converted second digital signal information;

[0039] S22: The data processing module performs second-level calibration on the first digital signal information after the first-level calibration with the converted third digital signal information;

[0040] S23: The data processing module performs third-level calibration on the first digital signal information after the second-level calibration with the converted fourth digital signal information;

[0041] S24: Similarly, the last-level calibration is performed on the digital signal information after the previous calibration with the converted last digital signal information;

[0042] S25: The last-calibrated digital signal information is obtained as the current digital signal information, and the display module is used for digital signal information display.

[0043] Preferably, the data processing module pre-stores the calibration coefficient of each level of digital signal information, and the corresponding level of digital signal information calibration coefficient is used for calibration in the calibration process of each level of digital signal information.

[0044] The beneficial effects of the present application include:

[0045] The analog signal acquisition and processing circuit provided by the present application comprises a power module, a storage module, a communication module, an analog signal receiving interface, and a data processing module. The analog signal receiving interface is provided with dozens of analog signal receiving endpoints for distributed parallel analog signal receiving. The data processing module integrates an ARM processor and an FPGA chip. The data processing module is used to perform complex data processing and logic control tasks, realize high-integration analog signal receiving, structure the hardware design, reduce the data receiving cost and power consumption, and improve the accuracy of data receiving. The simultaneous receiving through dozens of ports and the parallel processing through the data processing module realize the conversion of the analog signal at the receiving end into a digital signal, greatly improve the real-time performance of the time-sensitive change data processing, and realize the accurate calibration of the analog signal information through the step-by-step calibration method of the multi-channel analog signal data, thereby improving the precision and reliability of the analog signal acquisition and processing circuit. BRIEF DESCRIPTION OF DRAWINGS

[0046] Figure 1It is the circuit structure schematic view of the first analog signal receiving interface of the analog signal acquisition processing circuit of the application.

[0047] Figure 2 It is the circuit structure schematic view of the second analog signal receiving interface of the analog signal acquisition processing circuit of the application.

[0048] Figure 3 It is the circuit structure schematic view of the storage module of the analog signal acquisition processing circuit of the application.

[0049] Figure 4 It is the circuit structure schematic view of the communication module of the analog signal acquisition processing circuit of the application.

[0050] Figure 5 It is the circuit structure schematic view of the first power conversion module of the analog signal acquisition processing circuit of the application.

[0051] Figure 6 It is the circuit structure schematic view of the second power conversion module of the analog signal acquisition processing circuit of the application. DETAILED DESCRIPTION

[0052] The following will be combined with the accompanying Figures 1-6 The application is further described in detail:

[0053] Example 1

[0054] An analog signal acquisition processing circuit, comprising a power module, a storage module, a communication module, an analog signal receiving interface and a data processing module; the power module, the storage module, the communication module and the analog signal receiving interface are connected with the data processing module.

[0055] The analog signal receiving interface is provided with tens of channels or hundreds of channels of analog signal receiving endpoints for distributed parallel analog signal receiving, the data processing module integrates an ARM processor and an FPGA chip; the power module is used for providing working voltage for the analog signal acquisition processing circuit; the analog signal receiving interface is used for receiving analog signals collected by sensors; the data processing module is used for locally and in parallel processing the analog signals received by each channel of the analog signal receiving interface to convert the analog signals into digital signals; the storage module is used for storing the received analog signals, the digital signals converted from the analog signals and processing programs; and the communication module is used for transmitting the received analog signals to the data processing module and transmitting the converted digital signals to a remote end.

[0056] The analog signal receiving interface is used for receiving temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals and angle analog signals.

[0057] The data processing module is integrated with an ARM processor and an FPGA chip to perform complex data processing and logic control tasks on the same module, realize a high-integration analog signal receiving system, and perform distributed parallel analog signal receiving through tens of channels to process the received analog signals simultaneously, thereby greatly improving the real-time performance of data processing, especially for analog signal receiving in time-sensitive application scenarios. The number of analog signal collection ports can be adjusted as needed, and the number of channels, data processing algorithms, communication protocols, and other parameters can be set in the display module, thereby improving the flexibility and scalability of the analog signal acquisition and processing circuit. Subsequent addition of new functions does not require changes to the hardware, thereby improving the overall performance.

[0058] The data encryption transmission module and the remote monitoring module are integrated in the communication module to improve the security and adaptability of the system.

[0059] Embodiment 2

[0060] Based on Embodiment 1, referring to Figure 1 and Figure 2 , the analog signal receiving interface is provided with N channels, the N channels are tens or hundreds of channels, and each channel is connected to a sensor chip. The N channels of the analog signal receiving interface are respectively connected to the FORCE2 1, FORCE_P1 port of the first sensor chip through the first interface FORCE2 1, FORCE_P1, the FORCE2 2, FORCE_P2 port of the second sensor chip through the second interface FORCE2 2, FORCE_P2, the FORCE2 3, FORCE_P3 port of the first sensor chip through the third interface FORCE2 3, FORCE_P3, and so on, and the FORCE2 N, FORCE_PN port of the Nth sensor chip through the Nth interface FORCE2 N, FORCE_PN.

[0061] The analog signal receiving interface further includes an eighth 855 capacitor, an eighth 854 capacitor, a fourth 418 resistor, the RTDIN+ and RTDIN- ports of the sensor chip are connected through the eighth 855 capacitor, the BIAS, REFIN- and REFIN- ports are connected through the fourth 418 resistor, and the VDD and DVDD ports are grounded through the eighth 854 capacitor. The analog signal receiving interface is a convenient and fast analog signal endpoint connection interface that supports hot swapping and plug-and-play.

[0062] The analog signal receiving interface is an SPI interface extended from the FPGA chip, and can realize PT100 / PT1000 measurement of 2-wire system, 3-wire system and 4-wire system. Users can also connect different numbers and performances of endpoints according to actual needs on site.

[0063] Referring to Figure 3 The storage module includes a storage chip, and a / CS port, a DO port, a / WP port, a HOLD port, a CLK port and a DI port of the storage chip are connected with a QSPI_CS port, a QSPI_DAT1 port, a QSPI_DAT2 port, a QSPI_DAT3 port, a QSPI_CLK port and a QSPI_DAT0 port of the data processing module respectively. The storage module externally connects N' pieces of DDR storage chips for program caching, and N' is a positive integer greater than or equal to 1.

[0064] The storage module is used for storing a starting program, a data processing program and analog signal receiving information in an analog signal receiving process.

[0065] Referring to Figure 4 The communication module includes a communication chip and an Ethernet communication interface, the communication chip is connected with the data processing module, and the communication chip is connected with the Ethernet communication interface and used for transmitting analog signal information and accepting remote control commands.

[0066] The communication chip includes a third R81 resistor, a third R82 resistor, a third R83 resistor, a third R91 resistor, a third R92 resistor, a third R93 resistor, a third R94 resistor, a third R95 resistor, a third R96 resistor, a third R97 resistor, a third R98 resistor, a third R99 resistor, a fourth R100 resistor, a fourth R101 resistor, a fourth R102 resistor, a first D82 diode and a second D42 diode.

[0067] An SCSN port, an INTN port, an RSTN port, an SPDLED port, a DUPLED port, a PMODE0 port, a PMODE1 port, a PMODE2 port, an RSVD1 port, an RSVD2 port, an RSVD3 port, an RSVD4 port, an RSVD5 port of the communication chip are connected with the third R81 resistor, the third R82 resistor, the third R83 resistor, the first D82 diode, the second D42 diode, the third R93 resistor, the third R94 resistor, the third R95 resistor, the third R97 resistor, the third R98 resistor, the third R99 resistor, the fourth R100 resistor, the fourth R101 resistor, the fourth R102 resistor respectively, and the first D82 diode and the second D42 diode are connected with the third R91 resistor and the third R92 resistor respectively. An FPGA is used to extend one SPI interface for extending one 100M network, and used for uploading analog signal information and accepting remote control commands.

[0068] Embodiment 3

[0069] Based on the embodiment 1 or the embodiment 2, referring to Figure 5 and Figure 6 , the power module comprises a first power conversion module, a second power conversion module, a third power conversion module, a fourth power conversion module and a fifth power conversion module.

[0070] The first power conversion module is used for realizing conversion from 24V voltage to 5V voltage, and comprises a first conversion chip, a ninth capacitor, an eighth capacitor, a ninth capacitor, an eighth capacitor, a ninth capacitor, a ninth capacitor, a third resistor, a third resistor, a third resistor, a fourth resistor, an inductor.

[0071] The ninth capacitor, the eighth capacitor and the ninth capacitor are connected in parallel, one end of which is connected with a 24V voltage output end, and the other end is connected with a VIN port of the first conversion chip, an ON#OFF port of the first conversion chip is connected with the third resistor, a VOUT port of the first conversion chip is connected with the third resistor, the third resistor and the fourth resistor in series through an inductor, and the inductor is connected with the eighth capacitor, the ninth capacitor and the ninth capacitor in series and grounded.

[0072] The second power conversion module is used for realizing conversion from 5V voltage to 1V voltage, and comprises a second conversion chip, a fourth resistor, a fourth resistor, a fourth resistor, a ninth capacitor, a ninth capacitor, a ninth capacitor, a ninth capacitor.

[0073] One end of the ninth capacitor is grounded, and the other end is connected with a 5V voltage, a VIN port of the second conversion chip and the fourth resistor, respectively, the fourth resistor is connected with an EN port of the second conversion chip, and a SS port of the second conversion chip is grounded through the ninth capacitor.

[0074] A VOUT port of the second conversion chip is connected with the fourth resistor and the ninth capacitor, respectively, the ninth capacitor and the ninth capacitor are connected in parallel, one end of which is connected with a 1V voltage output end, and the other end is grounded, and the fourth resistor and the fourth resistor are connected with an ADJ port of the second conversion chip and grounded.

[0075] Electronic elements and connection relationship of the third power conversion module, the fourth power conversion module and the fifth power conversion module are the same as those of the second power conversion module.

[0076] The voltage input of the overall circuit of the analog signal acquisition and processing circuit is 24V, but different modules need different voltages in normal working condition, therefore, a plurality of voltage conversion modules are arranged in the power module to supply each module with suitable voltage.

[0077] The analog signal acquisition and processing circuit further comprises a display module connected with the data processing module, for displaying the measured real-time analog signal information and configuring parameters through the visual interface of the display module.

[0078] An analog signal acquisition and processing method, comprising the following steps:

[0079] S1: N analog signal collection ports simultaneously receive analog signals transmitted from sensors and add receiving labels;

[0080] S2: Each analog signal collection port synchronously and in parallel transmits the received analog signals to a data processing module, and the data processing module synchronously and in parallel processes and converts the acquired analog signals into digital signals, which can greatly simplify the transmission line of analog signals, greatly reduce the hardware cost, and effectively improve the accuracy of the final receiving result due to the absence of long-distance analog signal transmission process and almost no transmission loss of analog signals.

[0081] S3: A built-in device or object monitoring state algorithm is used to process abnormal conditions of the monitored device or object in real time.

[0082] S4: The converted digital signals are stored in a storage module and synchronously and in parallel transmitted to a remote digital platform for digital construction.

[0083] S5: The communication interface of the communication module receives instructions from the remote digital platform and controls or intervenes in the monitored device or object.

[0084] In step S2, after the conversion of each analog signal, the data processing module performs synchronous and parallel calibration processing on each received digital signal through a preset calibration coefficient.

[0085] In the above scheme, the data processing module compares the normal operation state data of the monitored device or object with the collected and transmitted analog signals of the monitored device or object in real time, and when the monitored device or object exceeds the set safe state range, the data processing module uploads instructions to the remote digital platform through the communication module to stop the monitored device or object for protection and push alarm information.

[0086] In step S2, the following steps are further included:

[0087] S21: The data processing module calibrates the first digital signal information with the converted second digital signal information;

[0088] S22: The data processing module performs second-level calibration on the first digital signal information after the first-level calibration with the converted third digital signal information.

[0089] S23: The data processing module performs third-level calibration on the second-level calibrated first digital signal information using the converted fourth digital signal information.

[0090] S24: In this way, the last-level calibration is performed on the digital signal information calibrated in the previous step using the converted last digital signal information.

[0091] S25: The last-calibrated digital signal information is obtained as the current digital signal information, and the digital signal information is displayed through the display module.

[0092] In the data processing module, the calibration coefficients of each level of digital signal information are pre-stored, and the calibration coefficients of the corresponding level are used for calibration during the calibration process of each level of digital signal information.

[0093] In another embodiment, the analog calibration coefficients can also be pre-set in the data processing module of the analog signal acquisition and processing circuit, and the built-in processing module compares the analog signal conversion into digital signal coefficients of the calibration processing module in real time through power sampling, to ensure the accuracy of conversion.

[0094] In summary, the analog signal acquisition and processing circuit provided by the present application performs complex data processing and logical control tasks through the data processing module, realizes high-integration analog signal reception, and receives the analog signals collected by the sensor through tens or hundreds of ports in a synchronous manner. The data processing module processes the analog signals in parallel to obtain digital signals. The data processing module is built-in conversion and state algorithm of the monitored collection equipment or object. The converted data is stored synchronously and transmitted to the digital platform through the communication module, which is used for digital construction and receiving the back transmission instruction of the digital platform, and is used for real-time intervention on the safety and other operating states of the monitored collection equipment or object. The system can be directly arranged on the equipment or object that needs to be collected and monitored by the sensor, and the analog signals of the collection equipment or object are received and processed in parallel to convert them into non-attenuated digital signals, avoiding signal attenuation in the transmission process of the analog signals, ensuring the accuracy of the obtained equipment or object signals, and providing reliable guarantee for the digital construction platform to provide accurate equipment or object state data.

Claims

1. A method for processing analog signal acquisition, based on an analog signal acquisition processing circuit, characterized in that, The analog signal acquisition processing circuit comprises an analog signal receiving interface and a data processing module. The analog signal receiving interface is configured to receive analog signals collected by sensors. The data processing module is configured to locally and in parallel process and convert the analog signals received by each analog signal receiving interface into digital signals. The analog signal acquisition processing method comprises the following steps: S1: N analog signal collection ports simultaneously receive analog signals transmitted by sensors and add receiving labels; S2: Each analog signal collection port synchronously and in parallel transmits the received analog signals to the data processing module, and the data processing module synchronously and in parallel processes and converts the acquired analog signals into digital signals; After the conversion of the analog signals in step S2, the data processing module synchronously and in parallel calibrates the received digital signals by using preset calibration coefficients, including the following specific steps: S21: The data processing module calibrates the first digital signal information by using the converted second digital signal information; S22: The data processing module performs second-level calibration on the first digital signal information after the first-level calibration by using the converted third digital signal information; S23: The data processing module performs third-level calibration on the first digital signal information after the second-level calibration by using the converted fourth digital signal information; S24: Similarly, the data processing module performs last-level calibration on the digital signal information after the previous calibration by using the converted last digital signal information; S25: The data processing module obtains the digital signal information after the last calibration as the current digital signal information and displays the digital signal information by using a display module. The data processing module pre-stores calibration coefficients of each level of digital signal information, and uses the calibration coefficients of the corresponding level of digital signal information for calibration during the calibration of each level of digital signal information. The analog signal acquisition processing circuit further comprises a power module, a storage module, and a communication module.

2. The method of claim 1, wherein, The power module is configured to provide working voltage for the analog signal acquisition processing circuit. The storage module is configured to store the received analog signals, the converted digital signals, and processing programs. The communication module is configured to transmit the received analog signals to the data processing module and transmit the converted digital signals to a remote terminal. The analog signal receiving interface is configured to receive temperature analog signals, voltage analog signals, current analog signals, pressure analog signals, flow analog signals, liquid analog signals, vibration analog signals, displacement analog signals, speed analog signals, and angle analog signals.

3. The method of claim 2, wherein, ​ 4. The method of claim 2, wherein, The analog signal receiving interface is provided with N paths, the N paths are tens or hundreds of paths, and each path end is connected with a sensor chip, the first interface FORCE2 1, FORCE_P1 of the N paths of the analog signal receiving interface is connected with the FORCE2 1, FORCE_P1 port of the first sensor chip, the second interface FORCE2 2, FORCE_P2 is connected with the FORCE2 2, FORCE_P2 port of the second sensor chip, the third interface FORCE2 3, FORCE_P3 is connected with the FORCE2 3, FORCE_P3 port of the first sensor chip, and the like, and the Nth interface FORCE2 N, FORCE_PN is connected with the FORCE2 N, FORCE_PN port of the Nth sensor chip; The analog signal receiving interface further comprises an eighth 855 capacitor, an eighth 854 capacitor, a fourth 418 resistor, the RTDIN+ and RTDIN- ports of the sensor chip are connected through the eighth 855 capacitor, the BIAS, the REFIN- and the REFIN- are connected through the fourth 418 resistor, and the VDD and the DVDD ports are grounded through the eighth 854 capacitor.

5. The method of claim 2, wherein the method further comprises: The storage module comprises a storage chip, and the / CS port, the DO port, the / WP port, the HOLD port, the CLK port and the DI port of the storage chip are connected with the QSPI_CS port, the QSPI_DAT1 port, the QSPI_DAT2 port, the QSPI_DAT3 port, the QSPI_CLK port and the QSPI_DAT0 port of the data processing module respectively.

6. The method of claim 5, wherein, The storage module is externally hung with N' pieces of DDR storage chips for program caching, and N' is a positive integer greater than or equal to 1.

7. The method of claim 2, wherein the method further comprises: The communication module comprises a communication chip and an Ethernet communication interface, the communication chip is connected with the data processing module, and the communication chip is connected with the Ethernet communication interface and used for transmitting analog signal information and accepting remote control commands. The communication chip comprises a third 81 resistor, a third 82 resistor, a third 83 resistor, a third 91 resistor, a third 92 resistor, a third 93 resistor, a third 94 resistor, a third 95 resistor, a third 96 resistor, a third 97 resistor, a third 98 resistor, a third 99 resistor, a fourth 100 resistor, a fourth 101 resistor, a fourth 102 resistor, a first 82 diode and a second 42 diode. The SCSN port, the INTN port, the RSTN port, the SPDLED port, the DUPLED port, the PMODE0 port, the PMODE1 port, the PMODE2 port, the RSVD1 port, the RSVD2 port, the RSVD3 port, the RSVD4 port, and the RSVD5 port of the communication chip are respectively connected with the third eighth one resistor, the third eighth two resistor, the third eighth three resistor, the first eighth diode, the second fourth diode, the third ninth three resistor, the third ninth four resistor, the third ninth five resistor, the third ninth seven resistor, the third ninth eight resistor, the third ninth nine resistor, the fourth zero zero resistor, the fourth zero one resistor, and the fourth zero two resistor.

8. The method of claim 1, wherein, The power module comprises a first power conversion module, a second power conversion module, a third power conversion module, a fourth power conversion module, and a fifth power conversion module, and the electronic components and the connection relationship of the third power conversion module, the fourth power conversion module, and the fifth power conversion module are the same as those of the second power conversion module. The first power conversion module is used for converting 24V voltage into 5V voltage, and comprises a first conversion chip, an eighth three hundred and thirty ninth capacitor, an eighth four hundred and second capacitor, an eighth three hundred and thirty eighth capacitor, an eighth four hundred and seventh capacitor, an eighth four hundred and zero capacitor, an eighth four hundred and one capacitor, a third six hundred and fourth resistor, a third six hundred and fifth resistor, a third six hundred and sixth resistor, a fourth zero two resistor, and an inductor. The eighth three hundred and thirty ninth capacitor, the eighth four hundred and second capacitor, and the eighth three hundred and thirty eighth capacitor are connected in parallel, and one end thereof is connected with a 24V voltage output end, and the other end is connected with a VIN port of the first conversion chip; an ON#OFF port of the first conversion chip is connected with the third six hundred and fourth resistor; a VOUT port of the first conversion chip is connected with the third six hundred and fifth resistor, the third six hundred and sixth resistor, and the fourth zero two resistor through an inductor; and the inductor is connected with the eighth four hundred and seventh capacitor, the eighth four hundred and zero capacitor, and the eighth four hundred and one capacitor.

9. The method of claim 7, wherein the method further comprises: The second power conversion module is used for converting 5V voltage into 1V voltage, and comprises a second conversion chip, a fourth six hundred and first resistor, a fourth six hundred and fourth resistor, a fourth six hundred and fifth resistor, an eighth four hundred and second capacitor, an eighth four hundred and third capacitor, an eighth four hundred and fifth capacitor, and an eighth four hundred and fourth capacitor. One end of the eighth four hundred and second capacitor is grounded, and the other end is connected with a 5V voltage, a VIN port of the second conversion chip, and the fourth six hundred and first resistor; the fourth six hundred and first resistor is connected with an EN port of the second conversion chip; and a SS port of the second conversion chip is grounded through the eighth four hundred and third capacitor. A VOUT port of the second conversion chip is connected with the fourth six hundred and fourth resistor and the eighth four hundred and fifth capacitor; the eighth four hundred and fifth capacitor and the eighth four hundred and fourth capacitor are connected in parallel, one end thereof is connected with a 1V voltage output end, and the other end is grounded; and the fourth six hundred and fourth resistor and the fourth six hundred and fifth resistor are connected with an ADJ port of the second conversion chip and grounded.

10. The method of claim 1, wherein, The method further comprises the following steps: S3: a built-in device or object monitoring state algorithm is used to process abnormal conditions of a monitored device or object in real time; S4: the converted digital signal is stored on a storage module and is synchronously and in parallel transmitted to a remote digital platform for digital construction. S5: The communication interface of the communication module receives the instruction from the remote digital platform and controls or intervenes in the monitored equipment or object.

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