Universal interconnection bus-based FPGA embedded radio frequency unit test method

Abstract

The application discloses a kind of FPGA embedded radio frequency unit test methods based on universal interconnect bus, comprising: using FPGA embedded processor, to FPGA embedded radio frequency unit is configured;Based on FPGA internal programmable logic resource, first radio frequency signal is generated in embedded radio frequency unit;Establish the first radio frequency channel of FPGA embedded radio frequency unit receiving first radio frequency signal;The received first radio frequency signal is detected, and first detection data is obtained, and first detection data is transmitted to FPGA embedded processor, and compared with specification value, and the test result of first radio frequency channel is obtained;Configuration parameters, first radio frequency signal and first detection data are transmitted by universal interconnect bus, and using FPGA on-chip memory is cached.Can realize the automatic test of FPGA embedded radio frequency unit, and processing speed is accelerated, and external test equipment is not needed, and test cost is saved.

Description

Technical Field

[0001] This invention belongs to the field of integrated circuit technology, specifically relating to a test method for FPGA embedded radio frequency units based on a universal interconnect bus. Background Technology

[0002] FPGA (Field Programmable Gate Array) has been widely used in product design and prototyping. An FPGA integrates various unit modules and IP cores, including programmable radio frequency (RF) processors, digital signal processors, high-performance memory, high-speed serial interfaces, PCIe (Peripheral Component Interconnect Express), and Ethernet, enabling a single chip to support an entire system application. It features miniaturization, low cost, high performance, and flexible design.

[0003] Testing FPGA-embedded radio frequency (RF) units presents challenges such as complex external test platforms and high testing costs. Furthermore, establishing a connection between the RF unit and the FPGA typically involves manually modifying configuration parameters, which is unsuitable for automated production testing. Summary of the Invention

[0004] To overcome the shortcomings of existing technologies, this invention provides a testing method for FPGA embedded radio frequency units based on a universal interconnect bus. The method includes: configuring the FPGA embedded radio frequency unit using an FPGA embedded processor; generating a first radio frequency signal in the embedded radio frequency unit based on the FPGA's internal programmable logic resources; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the received first radio frequency signal to obtain first detection data; transmitting the first detection data to the FPGA embedded processor and comparing it with a specified value to obtain the test result of the first radio frequency channel; and transmitting the configuration parameters, the first radio frequency signal, and the first detection data via a universal interconnect bus, using the FPGA's on-chip memory for caching. This method enables automated testing of the FPGA embedded radio frequency unit, accelerates test processing speed, eliminates the need for external test equipment, and saves test costs.

[0005] The technical solution adopted by this invention to solve its technical problem is as follows:

[0006] Step 1: Using the FPGA embedded processor, configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode;

[0007] Step 2: Based on the programmable logic resources inside the FPGA, generate the first radio frequency signal corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA;

[0008] Step 3: Establish the first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal;

[0009] Step 4: Detect the first radio frequency signal received by the first radio frequency channel to obtain the first detection data, and transmit the first detection data to the FPGA embedded processor;

[0010] Step 5: Transmit the configuration parameters, the first radio frequency signal, and the first detection data through the general interconnect bus and cache them using the FPGA on-chip memory; use the FPGA embedded processor to compare the first detection data with the specification value to obtain the test results of the first radio frequency channel.

[0011] Preferably, step 1 specifically comprises:

[0012] Step 1-1: Based on the configuration parameters, use the FPGA embedded processor to write the initial value of the FPGA embedded RF unit configuration register;

[0013] Steps 1-2: Configure the FPGA embedded RF unit to transmit / receive full-duplex mode and determine the operating parameters;

[0014] Steps 1-3: Use the FPGA embedded processor to call the hardware abstraction layer function to initialize the states of multiple working parameters in the FPGA application layer.

[0015] Preferably, step 2 specifically comprises:

[0016] Step 2-1: Utilize the programmable logic resources inside the FPGA to generate the first single-tone signal through direct digital frequency synthesis;

[0017] Step 2-2: Based on the first single-tone signal, configure the phase word and frequency word corresponding to the configuration parameters in the FPGA embedded radio frequency unit, and output the first radio frequency signal corresponding to the configuration parameters.

[0018] Preferably, step 3 specifically comprises:

[0019] By connecting one RF transmit pin of the FPGA embedded RF unit to multiple RF receive pins of the FPGA embedded RF unit through a power divider, multiple first RF channels for the FPGA embedded RF unit to receive the first RF signal are obtained.

[0020] Preferably, step 4 specifically comprises:

[0021] Step 4-1: The first radio frequency signal received by the first radio frequency channel is buffered across clock domains using the FPGA on-chip memory;

[0022] Step 4-2: Convert the buffered first radio frequency signal into a parallel-to-serial signal according to the corresponding radio frequency channel to obtain the converted signal;

[0023] Step 4-3: Perform a Fast Fourier Transform on the parallel-to-serial conversion signal to obtain the transformed signal;

[0024] Step 4-4: Determine the signal strength and signal-to-noise ratio of the received first radio frequency signal based on the transformed signal;

[0025] Steps 4-5: Determine the first detection data based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal;

[0026] Steps 4-6: Transmit the first detection data to the FPGA embedded processor.

[0027] Preferably, step 5 specifically comprises:

[0028] Step 5-1: Using the FPGA embedded processor, compare the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding specification values ​​in the electrical parameter table;

[0029] Step 5-2: When the signal strength, signal-to-noise ratio, and transmitted signal power all differ from the corresponding standard values ​​by no more than the preset value, the first radio frequency channel is determined to be working normally; when the signal strength, signal-to-noise ratio, or transmitted signal power differs from the corresponding standard values ​​by more than the preset value, the first radio frequency channel is determined to be working abnormally.

[0030] Preferably, the FPGA embedded radio frequency unit testing method further includes:

[0031] Using an automated test machine, a second radio frequency signal is generated according to the configuration parameters;

[0032] Establish a second radio frequency channel for receiving the second radio frequency signal using the FPGA embedded radio frequency unit;

[0033] The second radio frequency signal received by the second radio frequency channel is detected to obtain the second detection data, and the second detection data is transmitted to the FPGA embedded processor.

[0034] The second detection data and the specification value are compared using the FPGA embedded processor to obtain the test results of the second RF channel.

[0035] When the test results of the first RF channel and the second RF channel are both normal, the FPGA embedded RF unit based on the universal interconnect bus passes the test.

[0036] Preferably, the step of using an automated testing machine to generate a second radio frequency signal according to configuration parameters includes:

[0037] The second monotone signal is generated using an automated testing machine.

[0038] Use an automated test bench to configure the FPGA embedded RF unit according to the configuration parameters;

[0039] Based on the second single-tone signal, the second radio frequency signal corresponding to the configuration parameters is output by the radio frequency unit embedded in the FPGA.

[0040] Preferably, establishing the second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal includes: connecting a signal generator and a spectrum analyzer to an automatic test bench via a GPIB interface, connecting one radio frequency receiving pin of the FPGA embedded radio frequency unit to the signal generator, and connecting one radio frequency transmitting pin of the FPGA embedded radio frequency unit to the spectrum analyzer, thereby obtaining the second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal.

[0041] Preferably, the step of detecting the second radio frequency signal received by the second radio frequency channel to obtain second detection data includes: the automatic test equipment acquiring the received second radio frequency signal through the GPIB interface, and calculating the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reading the spectrum analyzer through the GPIB interface to acquire the transmission power of the second radio frequency signal; and determining the second detection data based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.

[0042] The beneficial effects of this invention are as follows:

[0043] This invention employs an in-chip FPGA testing method, performing signal processing within the chip. It achieves automated testing of the FPGA's embedded RF unit based on a universal interconnect bus, eliminating the need for external testing equipment and saving testing costs. It boasts strong versatility, allowing testing of multiple frequency points, bandwidths, and other parameters by loading different configuration files. Based on the FPGA's embedded RF unit and embedded processor, and other internal programmable logic resources, it uses a universal interconnect bus for data exchange within the FPGA, enabling pipelined processing of test signal transmission, reception, and judgment. This accelerates testing speed, reduces test buffer size, and eliminates the need for additional hardware design. FPGA-integrated testing can be achieved using only the FPGA's on-chip memory for caching, without requiring external DDR or other memory.

[0044] By comparing the test results of the automatic test machine with the test results of the FPGA embedded RF unit based on the universal interconnect bus, the reliability of the final test results can be enhanced. Attached Figure Description

[0045] Figure 1 This is a flowchart of the method of the present invention;

[0046] Figure 2 This is a flowchart of the software module design for the method of this invention;

[0047] Figure 3 This is a hardware circuit block diagram of the FPGA initialization radio frequency unit of the present invention;

[0048] Figure 4 This is a flowchart of the FPGA embedded radio frequency unit testing method of the present invention. Detailed Implementation

[0049] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0050] This invention provides a test method for FPGA embedded radio frequency units based on a universal interconnect bus, which can realize automated testing of FPGA embedded radio frequency units without the need for external test equipment, thus saving test costs.

[0051] The present invention provides a test method for FPGA embedded radio frequency units based on a universal interconnect bus, comprising: configuring the FPGA embedded radio frequency unit according to configuration parameters and transmit / receive duplex mode using an FPGA embedded processor; generating a first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit based on the FPGA's internal programmable logic resources; establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor; transmitting the configuration parameters, the first radio frequency signal, and the first detection data through the universal interconnect bus, and caching them using the FPGA's on-chip memory; and comparing the first detection data with a specified value using the FPGA embedded processor to obtain the test result of the first radio frequency channel.

[0052] Specifically, the FPGA embedded processor is used to configure the FPGA embedded radio frequency unit according to the configuration parameters and transmit / receive duplex mode. This includes: using the FPGA embedded processor to write the initial value of the FPGA embedded radio frequency unit configuration register according to the configuration parameters; configuring the FPGA embedded radio frequency unit to transmit / receive duplex mode and determining the operating parameters; and using the FPGA embedded processor to call the hardware abstraction layer function to initialize the states of multiple operating parameters in the FPGA application layer.

[0053] Specifically, based on the programmable logic resources inside the FPGA, a first radio frequency signal corresponding to the configuration parameters is generated in the radio frequency unit embedded in the FPGA, including: using the programmable logic resources inside the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, configuring the phase word and frequency word corresponding to the configuration parameters in the radio frequency unit embedded in the FPGA, and outputting the first radio frequency signal corresponding to the configuration parameters.

[0054] Specifically, establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal includes: connecting one radio frequency transmitting pin of the FPGA embedded radio frequency unit to multiple radio frequency receiving pins of the FPGA embedded radio frequency unit through a power divider, thereby obtaining multiple first radio frequency channels for the FPGA embedded radio frequency unit to receive the first radio frequency signal.

[0055] Specifically, detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data and transmitting the first detection data to the FPGA embedded processor includes: buffering the first radio frequency signal received by the first radio frequency channel across clock domains using the FPGA on-chip memory; converting the buffered first radio frequency signal into a parallel-to-serial converter according to the corresponding radio frequency channel to obtain a parallel-to-serial converter signal; performing a fast Fourier transform on the parallel-to-serial converter signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio of the received first radio frequency signal based on the transformed signal; determining the first detection data based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal; and transmitting the first detection data to the FPGA embedded processor.

[0056] Specifically, using the FPGA embedded processor, the first detection data and the standard value are compared to obtain the test results of the first radio frequency channel. This includes: using the FPGA embedded processor, comparing the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding standard values ​​in the electrical parameter table; when the difference between the signal strength, signal-to-noise ratio, and transmit signal power and the corresponding standard value does not exceed a preset value, the first radio frequency channel is determined to be working normally; when the difference between the signal strength, signal-to-noise ratio, or transmit signal power and the corresponding standard value exceeds a preset value, the first radio frequency channel is determined to be working abnormally.

[0057] Specifically, the FPGA embedded RF unit testing method based on a universal interconnect bus provided by this invention further includes: using an automatic test bench to generate a second RF signal according to configuration parameters; establishing a second RF channel for the FPGA embedded RF unit to receive the second RF signal; detecting the second RF signal received by the second RF channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the specification value to obtain the test result of the second RF channel; when the test results of the first RF channel and the second RF channel are both normal, the FPGA embedded RF unit based on the universal interconnect bus passes the test.

[0058] Specifically, using an automated test bench to generate a second radio frequency signal according to configuration parameters includes: using the automated test bench to generate a second single-tone signal; using the automated test bench to configure the FPGA embedded radio frequency unit according to the configuration parameters; and based on the second single-tone signal, outputting the second radio frequency signal corresponding to the configuration parameters from the FPGA embedded radio frequency unit.

[0059] Specifically, establishing a second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal includes: connecting a signal generator and a spectrum analyzer to an automatic test bench via a GPIB interface, connecting one radio frequency receiving pin of the FPGA embedded radio frequency unit to the signal generator, and connecting one radio frequency transmitting pin of the FPGA embedded radio frequency unit to the spectrum analyzer, thereby obtaining a second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal.

[0060] Specifically, the second radio frequency signal received by the second radio frequency channel is detected to obtain second detection data, including: the automatic test equipment acquires the received second radio frequency signal through the GPIB interface and calculates the signal strength and signal-to-noise ratio of the received second radio frequency signal; the automatic test equipment reads the spectrum analyzer through the GPIB interface to obtain the transmission power of the second radio frequency signal; and the second detection data is determined based on the transmission power of the second radio frequency signal and the signal strength and signal-to-noise ratio of the received second radio frequency signal.

[0061] Example:

[0062] Taking the design of internal test software code using Verilog and C as an example, the following combines... Figure 1 The steps in the embodiments of the present invention will be described in detail below.

[0063] The FPGA embedded RF unit testing method based on a universal interconnect bus according to an embodiment of the present invention includes steps S1 to S6, each step described in detail below:

[0064] S1: Use the FPGA embedded processor to configure the FPGA embedded RF unit according to the configuration parameters and transmit / receive duplex mode.

[0065] S2: Based on the programmable logic resources inside the FPGA, the first radio frequency signal corresponding to the configuration parameters is generated by the radio frequency unit embedded in the FPGA.

[0066] S3: Establish the first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal.

[0067] S4: Detect the first radio frequency signal received by the first radio frequency channel, obtain the first detection data, and transmit the first detection data to the FPGA embedded processor.

[0068] S5: Transmits configuration parameters, first RF signal and first detection data through a universal interconnect bus, and uses FPGA on-chip memory for caching.

[0069] S6: Using the FPGA embedded processor, the first detection data and the standard value are compared to obtain the test results of the first RF channel.

[0070] In the above embodiments, an in-chip FPGA testing method is adopted to complete signal processing within the chip, realizing automated testing of the FPGA embedded RF unit based on a universal interconnect bus. This eliminates the need for external testing equipment, saving testing costs. It is highly versatile, allowing testing of multiple frequency points, bandwidths, and other parameters by loading different configuration files. Based on the FPGA's embedded RF unit and embedded processor, and other internal programmable logic resources, the universal interconnect bus enables pipelined processing of test signal transmission, reception, and judgment, accelerating test processing speed, reducing test buffer size, and eliminating the need for additional hardware design. FPGA-integrated testing can be achieved using only the FPGA's on-chip memory for caching, without the need for external DDR or other memory.

[0071] In some specific embodiments of step S1, the FPGA embedded processor is used to configure the FPGA embedded RF unit according to configuration parameters and transmit / receive duplex mode. This includes: writing the initial value of the FPGA embedded RF unit configuration register using the FPGA embedded processor according to the configuration parameters; configuring the FPGA embedded RF unit in transmit / receive duplex mode and determining the operating parameters; and using the FPGA embedded processor to call the Hardware Abstraction Layer (HAL) C language function to initialize multiple operating parameter states at the FPGA application layer, so as to enable subsequent testing of the RF unit at different frequencies and with different operating parameters. The aforementioned operating parameters include key parameters such as operating frequency, gain, and attenuation.

[0072] For example, the operating parameters for testing the FPGA-embedded RF unit are as follows: Under the maximum, minimum, and typical frequency points and bandwidths specified in the configuration parameters, the signal-to-noise ratio (SNR) of the received signal from the RF unit is measured. This allows for the measurement of RF parameters such as transmit attenuation range, receive gain range, maximum operating bandwidth, minimum operating bandwidth, maximum operating frequency, minimum operating frequency, transmit signal strength, and receive signal-to-noise ratio. The testing method remains the same when testing different frequency points or bandwidths; only the FPGA's configuration bitstream needs to be changed to make the RF unit operate in the specified mode.

[0073] In some specific embodiments of step S2, based on the programmable logic resources inside the FPGA, a first radio frequency signal corresponding to the configuration parameters is generated in the FPGA-embedded radio frequency unit. This includes: using the programmable logic resources inside the FPGA to generate a first single-tone signal through direct digital frequency synthesis; based on the first single-tone signal, configuring the phase word and frequency word corresponding to the configuration parameters in the FPGA-embedded radio frequency unit, and outputting the first radio frequency signal corresponding to the configuration parameters. Specifically, based on direct digital frequency synthesis, a single-tone signal is generated inside the FPGA using digital frequency synthesis. After configuring the phase word and frequency word, a digital quadrature intermediate frequency signal of the required frequency is output. Direct digital frequency synthesis refers to generating a series of digital signals and converting them into analog signals via a digital-to-analog converter. DDS is the abbreviation for Direct Digital Synthesizer. DDS converts a series of digital signals into analog signals via a digital-to-analog converter. DDS directly synthesizes the required waveform based on the phase concept. Compared with traditional frequency synthesizers, DDS has advantages such as low cost, low power consumption, high resolution, and fast conversion time.

[0074] In some specific embodiments of step S3, establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal includes: connecting one radio frequency transmit pin of the FPGA embedded radio frequency unit to multiple radio frequency receive pins of the FPGA embedded radio frequency unit through a power divider, thereby obtaining multiple first radio frequency channels for the FPGA embedded radio frequency unit to receive the first radio frequency signal. For example, using an SMA (SubMiniature version A) cable, one radio frequency transmit pin TX1 of the FPGA embedded radio frequency unit is connected to multiple radio frequency receive pins RX11, RX12, to RX1N of the FPGA embedded radio frequency unit through a power divider. The established one or more first radio frequency channels are self-transmitting and self-receiving channels of the FPGA embedded radio frequency unit, used for testing single-tone signals inside the FPGA, realizing the self-transmitting and self-receiving of the FPGA embedded radio frequency unit. By detecting the transmitted and received signals of the first radio frequency channels, the FPGA embedded radio frequency unit is tested.

[0075] In some specific embodiments of step S4, detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor, includes: buffering the first radio frequency signal received by the first radio frequency channel across clock domains using the FPGA on-chip memory; converting the buffered first radio frequency signal into a parallel-to-serial converter according to the corresponding radio frequency channel to obtain a parallel-to-serial converter signal; performing a Fast Fourier Transform on the parallel-to-serial converter signal to obtain a transformed signal; determining the signal strength and signal-to-noise ratio of the received first radio frequency signal based on the transformed signal; determining the first detection data based on the first radio frequency signal transmission power and the signal strength and signal-to-noise ratio of the received first radio frequency signal; and transmitting the first detection data to the FPGA embedded processor. The transmit and receive signal parameters, i.e., the first detection data, collected in step S4 serve as the basis for testing the FPGA embedded radio frequency unit.

[0076] In step S5, the configuration parameters, the first radio frequency signal, and the first detection data from the preceding steps are transmitted via the general-purpose interconnect bus, and the above data and related data are cached using the FPGA on-chip memory. Specifically, the basic configuration of the hardware platform, the configuration of the radio frequency unit parameters, and the transmission of the intermediate frequency digital signal are read and written using the general-purpose interconnect bus. On the FPGA embedded processor, the frequency point is checked for correctness, and the signal-to-noise ratio result is printed via serial port and GPIO (General-purpose input / output).

[0077] In existing technologies, testing of FPGA-embedded RF units involves complex external test platforms, generating a large amount of test data. This massive amount of test data relies on the complex processing flow of these external test platforms, requiring data transfer between different external test platform data interfaces. This results in multiple unnecessary data conversion processes and necessitates multiple verifications of the converted data, leading to long data processing times. Consequently, much of this data cannot be processed in real time and needs to be cached in memory for later retrieval. While FPGA on-chip memory offers fast processing speeds as a cache, its small cache size cannot meet the large amount of cached data generated by FPGA-embedded RF unit testing in existing technologies. Therefore, in current technologies, DDR (Double Data Rate Synchronous Dynamic Random Access Memory) is typically used as an external memory for FPGA on-chip systems to cache data. DDR has a large storage capacity, but as an external device, the data stored in DDR needs to be transferred to the FPGA before test data can be exchanged, which reduces the test data processing speed. Furthermore, external DDR also increases the cost of FPGA-embedded RF unit testing.

[0078] In step S5, based on the FPGA's internal programmable logic resources such as the FPGA's embedded radio frequency unit and embedded processor, a general-purpose interconnect bus is used to interact with the FPGA's internal data, avoiding multiple unnecessary data conversion processes, improving data transmission speed, enabling pipelined processing of test signal transmission, reception, and judgment, accelerating test processing speed, reducing test buffer size, and eliminating the need for additional hardware design. Only the FPGA's on-chip memory is used to buffer configuration parameters, the first radio frequency signal, the first detection data, and other related data, which enables FPGA-built-in testing without the need for external DDR or other memory.

[0079] In some specific embodiments of step S6, the FPGA embedded processor is used to compare the first detection data with the standard value to obtain the test result of the first radio frequency channel. This includes: using the FPGA embedded processor to compare the signal strength, signal-to-noise ratio, and transmit signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding standard values ​​in the electrical parameter table; when the difference between the signal strength, signal-to-noise ratio, and transmit signal power and the corresponding standard value does not exceed a preset value, the first radio frequency channel is determined to be working normally; when the difference between the signal strength, signal-to-noise ratio, or transmit signal power and the corresponding standard value exceeds a preset value, the first radio frequency channel is determined to be working abnormally.

[0080] Step S6 completes the single-tone signal test inside the FPGA, realizing the self-transmission and self-reception of the FPGA's embedded RF unit. The FPGA's embedded RF unit is tested by detecting the transmit and receive signals of the first RF channel.

[0081] The above steps S1 to S6 are used for FPGA internal single-tone signal testing. In actual testing, FPGA external single-tone signal testing can also be added. The consistency of the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results is judged. When both the FPGA internal single-tone signal test results and the FPGA external single-tone signal test results pass, the FPGA embedded RF unit test is determined to be passed.

[0082] In some specific implementations of adding external single-tone signal testing to the FPGA described above, automated processing can be achieved by designing corresponding software modules. The design process of the corresponding software modules is as follows: Figure 2 As shown, it includes the following steps:

[0083] Step 1: Based on the programmable logic resources inside the FPGA, develop an RF unit test stimulus generation module to generate the first RF signal.

[0084] Step 2: Generate the RF unit configuration module and configure the RF unit to the corresponding working mode to enable testing of the RF unit at different frequencies and under different working conditions.

[0085] Step 3: Based on the programmable logic resources inside the FPGA, develop an RF unit test response analysis module to detect the first RF signal received by the first RF channel, obtain the first detection data, and transmit the first detection data to the FPGA embedded processor; or to detect the second RF signal received by the second RF channel, obtain the second detection data, and transmit the second detection data to the FPGA embedded processor.

[0086] Step 4: Implement data interaction between the test stimulus generation module, RF unit configuration module, test response analysis module, and RF unit through the FPGA's internal universal interconnect bus.

[0087] Step 5: Establish the physical connection of the RF channel, complete the FPGA code stream configuration, generate the input signal required for testing through the FPGA or an external signal source, and process the RF output result through the FPGA's internal test response analysis module to realize the built-in self-test of the FPGA's embedded RF unit.

[0088] Data interaction of the above software modules, such as Figure 3 As shown, RFSoC (Radio Frequency System on Chip) represents a system-on-a-chip with an embedded radio frequency unit within an FPGA. This embedded RF unit receives and transmits radio frequency signals via a universal interconnect bus. The configuration module is based on the FPGA's embedded processor. GPIO is a general-purpose input / output interface. Data interaction between the test stimulus generation module, configuration module, test response analysis module, and the RF unit is conducted via the universal interconnect bus.

[0089] In some specific implementations of adding external single-tone signal testing to the FPGA, the present invention provides a test method for an FPGA embedded radio frequency unit based on a universal interconnect bus, which further includes: using an automatic test machine to generate a second radio frequency signal according to configuration parameters; establishing a second radio frequency channel for the FPGA embedded radio frequency unit to receive the second radio frequency signal; detecting the second radio frequency signal received by the second radio frequency channel to obtain second detection data, and transmitting the second detection data to the FPGA embedded processor; using the FPGA embedded processor to compare the second detection data with the specification value to obtain the test result of the second radio frequency channel; when the test results of the first radio frequency channel and the test results of the second radio frequency channel are both normal, the FPGA embedded radio frequency unit based on the universal interconnect bus passes the test.

[0090] For example, such as Figure 4As shown, hardware and software test platforms were built. The software platform refers to the aforementioned software modules, and the hardware platform refers to the external automated test bench. Physical connections for the RF channel were established, FPGA code stream configuration was completed, and the GPIB control signal source generated the required input signals and external reference clock. The automated test bench configured the FPGA via SMAP. The FPGA's embedded processor configured the FPGA's embedded RF units and automatically established connections.

[0091] Figure 4 Transmit channel 1 and receive channel 1 correspond to the second radio frequency (RF) channel, used for the transmission and reception of the second RF signal on the hardware platform. The second RF signal received by the second RF channel is detected to obtain second detection data. For example, an automated test instrument reads the spectrum analyzer through the GPIB interface to obtain the transmit power of the second RF signal. Based on the transmit power of the second RF signal and the signal strength and signal-to-noise ratio of the received second RF signal, the second detection data is determined. A decision is made on the second RF channel: the second detection data is compared with the specified value to obtain the test result of the second RF channel, and the function and performance of the second RF channel are judged.

[0092] Figure 4 The remaining channels, corresponding to the first RF channels, are used for RF signal transmission and reception by the software platform, i.e., the FPGA's embedded RF unit's self-transmission and self-reception of the first RF signal. Specifically, multiple first RF channels can be formed by establishing one-to-many pin connections. For example, one RF transmit pin TX1 of the FPGA's embedded RF unit can be connected to multiple RF receive pins RX11, RX12, and RX1N of the FPGA's embedded RF unit through a power divider, thus obtaining multiple first RF channels such as TX1 to RX11, TX1 to RX12, and TX1 to RX13. The first RF channels are then judged: the first detection data of each of the multiple first RF channels is compared with the standard value to obtain the test results of the multiple first RF channels.

[0093] Figure 4 In the process, the RF output results are processed by the FPGA internal test response analysis module, and the decision results of the first RF channel and the second RF channel are processed to realize the built-in self-test of the FPGA embedded RF unit and end the test.

[0094] In the above-described implementation scheme with an automated test bench, comparing the test results from the automated test bench with the test results of the FPGA embedded RF unit based on the universal interconnect bus of this invention enhances the reliability of the final test results. Furthermore, by adding only the automated test bench, the number of external test platforms required for testing the FPGA embedded RF unit in existing technologies is reduced, simplifying the complex external test platforms in the prior art.

[0095] In some specific implementations, an automated test bench is used to generate a second radio frequency (RF) signal according to configuration parameters. This includes: generating a second single-tone signal using the automated test bench; configuring the FPGA-embedded RF unit according to the configuration parameters using the automated test bench; and outputting the second RF signal corresponding to the configuration parameters from the FPGA-embedded RF unit based on the second single-tone signal. For example, the automated test bench configures the FPGA using SMAP (Service Management Access Point); after successful configuration of the FPGA code stream, the FPGA-embedded processor starts and automatically configures the FPGA-embedded RF unit, enabling the FPGA-embedded RF unit to operate in a preset working state.

[0096] In some specific implementations, establishing a second radio frequency (RF) channel for the FPGA-embedded RF unit to receive a second RF signal includes: connecting a signal generator and a spectrum analyzer to an automated test bench via a GPIB (General-Purpose Interface Bus) interface; connecting one RF receiver pin of the FPGA-embedded RF unit to the signal generator; and connecting one RF transmitter pin of the FPGA-embedded RF unit to the spectrum analyzer, thus obtaining a second RF channel for the FPGA-embedded RF unit to receive the second RF signal. For example, using an SMA cable, the RF receiver pin RX2 of the FPGA-embedded RF unit is externally connected to a signal generator, and the RF transmitter pin TX2 of the FPGA-embedded RF unit is externally connected to a spectrum analyzer. The signal generator and spectrum analyzer are connected to the automated test bench via a GPIB interface.

[0097] The general interconnect bus, GPIO, and GPIB mentioned above are different. The general interconnect bus is used for internal signal interconnection in FPGA, GPIO is a general I / O interface, and GPIB is an interface for an ATE (Automatic Test Equipment) machine. GPIB controls the signal source to generate the required input signals and external reference clock.

[0098] In some specific implementations, the second radio frequency (RF) signal received by the second RF channel is detected to obtain second detection data. This includes: an automated test instrument acquiring the received RF signal via a GPIB interface and calculating the signal strength and signal-to-noise ratio (SNR) of the received RF signal; the automated test instrument reading from a spectrum analyzer via the GPIB interface to obtain the transmit power of the RF signal; and determining the second detection data based on the transmit power and the signal strength and SNR of the received RF signal. For example, the automated test instrument captures digital interface data and calculates the signal strength and received SNR of the received RF signal; the automated test instrument reading from the spectrum analyzer via GPIB to obtain the transmit power of the RF signal. The second detection data, including the transmit power, signal strength, and SNR of the received RF signal, is transmitted to the FPGA embedded processor. Using the standard values ​​in the electrical parameter table as standard values, the FPGA embedded processor compares the second detection data with the standard values ​​to obtain the test results of the second RF channel, thereby determining the function and performance of the second RF channel. When both the test results of the second RF channel and the test results of the first RF channel pass, that is, when both the test results of the single-tone signal inside the FPGA and the test results of the single-tone signal outside the FPGA pass, the FPGA embedded RF unit test is deemed to have passed.

Claims

1. A universal interconnect bus based FPGA embedded radio frequency unit testing method, characterized in that, The method comprises the following steps: Step 1: using the FPGA embedded processor, configuring the FPGA embedded radio frequency unit according to the configuration parameters and the transmitting-receiving duplex mode; Step 2: based on the programmable logic resources inside the FPGA, generating a first radio frequency signal corresponding to the configuration parameters in the FPGA embedded radio frequency unit; Step 3: establishing a first radio frequency channel for the FPGA embedded radio frequency unit to receive the first radio frequency signal; Step 4: detecting the first radio frequency signal received by the first radio frequency channel to obtain first detection data, and transmitting the first detection data to the FPGA embedded processor; Step 5: transmitting the configuration parameters, the first radio frequency signal and the first detection data through a general interconnection bus, and using the on-chip memory of the FPGA for caching; comparing the first detection data with the specification value using the FPGA embedded processor to obtain the test result of the first radio frequency channel.

2. The universal interconnect bus based FPGA embedded RF unit testing method according to claim 1, wherein, The step 1 is specifically: Step 1-1: according to the configuration parameters, using the FPGA embedded processor to write the initial value of the FPGA embedded radio frequency unit configuration register; Step 1-2: configuring the FPGA embedded radio frequency unit as the transmitting-receiving duplex mode to determine the working parameters; Step 1-3: using the FPGA embedded processor to call the hardware abstraction layer function to initialize multiple working parameter states in the FPGA application layer.

3. The universal interconnect bus based FPGA embedded RF unit testing method according to claim 2, wherein, The step 2 is specifically: Step 2-1: using the programmable logic resources inside the FPGA to generate a first single-tone signal through direct digital frequency synthesis; Step 2-2: based on the first single-tone signal, configuring the phase word and the frequency word corresponding to the configuration parameters in the FPGA embedded radio frequency unit to output the first radio frequency signal corresponding to the configuration parameters.

4. The universal interconnect bus based FPGA embedded RF unit testing method according to claim 3, wherein, The step 3 is specifically: connecting one radio frequency transmitting pin of the FPGA embedded radio frequency unit to multiple radio frequency receiving pins of the FPGA embedded radio frequency unit through a power divider to obtain multiple first radio frequency channels for the FPGA embedded radio frequency unit to receive the first radio frequency signal.

5. The universal interconnect bus based FPGA embedded RF unit testing method of claim 4, wherein, The step 4 is specifically: Step 4-1: using the on-chip memory of the FPGA to cache the first radio frequency signal received by the first radio frequency channel across the clock domain; Step 4-2: performing parallel-serial conversion on the cached first radio frequency signal according to the corresponding radio frequency channel to obtain a signal after parallel-serial conversion; Step 4-3: performing fast Fourier transform on the signal after parallel-serial conversion to obtain a transformed signal; Step 4-4: determining the signal strength and the signal-to-noise ratio of the received first radio frequency signal according to the transformed signal; Step 4-5: determining the first detection data according to the transmitting signal power and the signal strength and the signal-to-noise ratio of the received first radio frequency signal; Step 4-6: transmitting the first detection data to the FPGA embedded processor.

6. The universal interconnect bus based FPGA embedded RF unit testing method of claim 5, wherein, The step 5 is specifically: Step 5-1: using the FPGA embedded processor to compare the signal strength, the signal-to-noise ratio and the transmitting signal power of the first radio frequency signal received by the first radio frequency channel with the corresponding specification value in the electrical parameter table; Step 5-2: when the signal strength, signal-to-noise ratio and transmitting signal power are all within a preset value from the corresponding standard value, it is determined that the first radio frequency channel is working normally; when the signal strength or the signal-to-noise ratio or the transmitting signal power is beyond the preset value from the corresponding standard value, it is determined that the first radio frequency channel is working abnormally.

7. The universal interconnect bus based FPGA embedded RF unit testing method of claim 6, wherein, The FPGA-embedded radio frequency unit testing method further comprises: using an automatic test machine to generate a second radio frequency signal according to configuration parameters; establishing a second radio frequency channel of the FPGA-embedded radio frequency unit to receive the second radio frequency signal; detecting the second radio frequency signal received by the second radio frequency channel to obtain second detection data, and transmitting the second detection data to the FPGA-embedded processor; using the FPGA-embedded processor to compare the second detection data with a standard value to obtain a test result of the second radio frequency channel; when the test result of the first radio frequency channel and the test result of the second radio frequency channel are both normal, the FPGA-embedded radio frequency unit testing based on the general interconnection bus is passed.

8. The universal interconnect bus based FPGA embedded RF unit testing method of claim 7, wherein, The FPGA-embedded radio frequency unit testing based on the general interconnection bus further comprises: using the automatic test machine to generate a second single-tone signal; using the automatic test machine to configure the FPGA-embedded radio frequency unit according to the configuration parameters; based on the second single-tone signal, outputting a second radio frequency signal corresponding to the configuration parameters by the FPGA-embedded radio frequency unit.

9. The universal interconnect bus based FPGA embedded RF unit testing method of claim 8, wherein, The FPGA-embedded radio frequency unit testing based on the general interconnection bus further comprises:

10. The universal interconnect bus based FPGA embedded RF unit testing method of claim 9, wherein, connecting the signal generator and the spectrum analyzer to the automatic test machine through a GPIB interface, connecting a radio frequency receiving pin of the FPGA-embedded radio frequency unit to the signal generator, and connecting a radio frequency transmitting pin of the FPGA-embedded radio frequency unit to the spectrum analyzer to obtain the second radio frequency channel of the FPGA-embedded radio frequency unit to receive the second radio frequency signal. The FPGA-embedded radio frequency unit testing based on the general interconnection bus further comprises: the automatic test machine acquires the received second radio frequency signal through the GPIB interface, and calculates the signal strength and the signal-to-noise ratio of the received second radio frequency signal; the automatic test machine reads the spectrum analyzer through the GPIB interface to acquire the transmitting power of the second radio frequency signal; and the second detection data is determined according to the transmitting power of the second radio frequency signal and the signal strength and the signal-to-noise ratio of the received second radio frequency signal.

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