TTE-based real-time Ethernet bus telemetry data integrated system

Abstract

The invention discloses a TTE-based real-time Ethernet bus telemetry data integration system, which comprises M levels of TTE bus network architectures and a plurality of cascade interaction machines, and is characterized in that the cascade interaction machines are used for realizing interaction of the two levels of TTE bus network architectures; each level of TTE bus network architecture comprises two pairs of data integrated devices which are redundant to each other, two pairs of switches which are redundant to each other, and at least one data collecting and editing device; each cascade interaction machine comprises two switches in pairs, wherein the two switches are redundant to each other, and all the devices are connected through a category 5 enhanced network cable. According to the multi-level TTE bus network architecture design for redundant transmission, the TTE bus data scheduling technology for optimizing the TDMA is adopted, and the TTE bus telemetering data integration technology for resetting and resetting and reframing of the data integration equipment is utilized, so that the large-bandwidth, strong-real-time and high-reliability transmission characteristics of the telemetering system are realized.

Description

Technical Field

[0001] The invention relates to the technical field of telemetry systems, in particular to a telemetry data integration system based on a TTE real-time Ethernet bus. Background Art

[0002] As avionics continues to develop in the direction of distributed integrated modularization, higher requirements are placed on the data bandwidth, high speed, real-time, stability and reliability of telemetry systems. Traditional telemetry systems usually use RS485, RS422, and 1553B buses, and choose different transmission methods according to the data transmission requirements of different devices, resulting in a wide variety of telemetry system interfaces and limited data transmission bandwidth. Summary of the invention

[0003] The present invention provides a TTE real-time Ethernet bus telemetry data integration system, constructs a multi-level TTE bus networking architecture with redundant transmission characteristics, adopts a TTE bus data scheduling technology that optimizes TDMA, and utilizes a TTE bus telemetry data integration technology that resets and re-frames a data integration device, thereby realizing a large-bandwidth, strong real-time, and highly reliable system design for a telemetry system.

[0004] In a first aspect, a telemetry data integration system based on a TTE real-time Ethernet bus is provided, comprising an M-level TTE bus network architecture and a plurality of cascaded interactive machines, where M is an integer greater than 1, and the cascaded interactive machines are used to implement the interaction of two-level TTE bus network architectures; each level of the TTE bus network architecture comprises two paired data integration devices for mutual redundancy, two paired switches for mutual redundancy, and at least one data acquisition and editing device; each cascaded interactive machine comprises two paired switches for mutual redundancy;

[0005] The two switches in each level of the TTE bus network architecture are connected by Category 5e network cables;

[0006] The data integration equipment and data collection and editing equipment in each level of the TTE bus network architecture are connected to the switch of the TTE bus network architecture through Category 5e network cables;

[0007] The M-level TTE bus network architecture includes a primary TTE bus network architecture and a secondary TTE bus network architecture. Two pairs of data integration devices in the primary TTE bus network architecture are connected to a telemetry transmitter, and two pairs of data integration devices in the primary TTE bus network architecture and two pairs of data integration devices in the secondary TTE bus network architecture are connected to a cascade switch via a Category 5e network cable.

[0008] In conjunction with the first aspect, in some implementations of the first aspect, the data processing flow of the system includes:

[0009] Two paired data integration devices in the first-level TTE bus network architecture are selected as two synchronization masters. In each TTE synchronization cycle, after the two synchronization masters jointly form a synchronization clock source, they send a time synchronization protocol control frame PCF containing transparent clock information to multiple synchronization clients. The synchronization clients include data acquisition and editing devices in the first-level TTE bus network architecture, data integration devices and / or data acquisition and editing devices in other levels of TTE bus network architecture except the first-level TTE bus network architecture;

[0010] After receiving the PCF, the synchronization client completes the clock synchronization with the two synchronization masters after solidification and compression;

[0011] Time division multiplexing (TDMA) is used to complete data transmission and data integration between end nodes in the multi-level TTE bus networking architecture.

[0012] In combination with the first aspect, in some implementations of the first aspect, the transparent clock measurement method is as follows:

[0013] A. Select time t1, end node 1 sends a message to end node 2 and records time t1 locally;

[0014] B. After receiving the information, end node 2 uses DMA to cache the data into the content and records the time t2 locally;

[0015] C. End node 2 sends the data frame containing time information t2 to end node 1, and records time t3 locally;

[0016] D. End node 2 sends a data frame containing time information t3 to end node 1;

[0017] E. End node 1 receives two messages from end node 2 using DMA, records the time when the first message from end node 2 is received, records time t4 locally, and obtains time t2 and t3;

[0018] F. The transmission delay between end node 1 and end node 2 in the TTE network is obtained as t_delay=[(t4-t1)-(t3-t2)] / 2.

[0019] In combination with the first aspect, in certain implementations of the first aspect, a maximum temperature drift error of the crystal oscillator within a TTE synchronization period is t_temperature, and a TTE clock synchronization window time is greater than t_temperature+t_delay.

[0020] In combination with the first aspect, in certain implementations of the first aspect, the TTE network synchronization clock cycle is consistent with the telemetry frame transmission cycle; each telemetry frame cycle is evenly divided into N TTE bus scheduling cycles, and within each TTE bus scheduling cycle, each TTE bus scheduling cycle is evenly divided into M time slot units according to the total amount of transmitted data, and virtual link 1, virtual link 2,..., virtual link M are calibrated in sequence, and each time slot unit arranges a fixed data transmission task.

[0021] In combination with the first aspect, in some implementations of the first aspect, the data transmission task arranged by the time slot unit includes any of the following:

[0022] The data integration equipment sends a downlink instruction information flow to the data acquisition and editing equipment via the switch;

[0023] The data collection and editing equipment sends the uplink data information flow to the data integration equipment via the switch;

[0024] The data integration device in the primary TTE bus network architecture sends a downlink instruction information flow to the data integration device in the secondary TTE bus network architecture via the cascade interactive machine;

[0025] The data integration device in the secondary TTE bus network architecture sends an uplink data information flow to the data integration device in the primary TTE bus network architecture via the cascade interactive machine.

[0026] In combination with the first aspect, in certain implementations of the first aspect, if the total amount of data transmitted by the data acquisition and editing device is higher than the maximum TTE transmission data amount, the data is divided into multiple virtual link numbers for data transmission.

[0027] In combination with the first aspect, in some implementations of the first aspect, t_1d>t_fifo; wherein,

[0028] t_1d=t_1-t_d, t_d is the start time of each TTE bus scheduling cycle, t_1 is the data transmission time of virtual link 1;

[0029] t_fifo=M_1 / V_1, M_1 is the amount of data transmitted by end node 1 on virtual link 1, and V_1 is the rate at which the internal SOC of end node 1 writes into the cache.

[0030] In combination with the first aspect, in certain implementations of the first aspect, the data integration device clears the SOC cache in each TTE bus scheduling cycle.

[0031] In conjunction with the first aspect, in certain implementations of the first aspect, the data integration device performs data processing actions of shearing, routing, and framing the data of each end node according to a specified frame format to form first-level telemetry full-frame data;

[0032] The first-level telemetry full-frame data is reframed into a frame format with a bandwidth higher than the first-level full-frame data in an asynchronous transmission manner to envelop the jitter range of the first-level telemetry full-frame data, form the second-level telemetry full-frame data, and wirelessly transmit it through the antenna.

[0033] Compared with the prior art, the solution provided by the present invention includes at least the following beneficial technical effects:

[0034] The present invention proposes a telemetry data integration system based on TTE real-time Ethernet bus, which realizes the transmission characteristics of large bandwidth, strong real-time and high reliability of the telemetry system through the design of multi-level TTE bus network architecture with redundant transmission, the use of TTE bus data scheduling technology with optimized TDMA, and the use of TTE bus telemetry data integration technology with data integration equipment reset and reframe. The specific contents are as follows:

[0035] 1. A multi-level TTE bus network architecture with redundant transmission characteristics was constructed, and multiple data integration devices were selected as synchronization masters to provide a clock reference for global clock synchronization. A transparent clock and crystal oscillator jitter combination strategy was proposed to overcome the problem of end node synchronization failure caused by crystal oscillator temperature drift in the multi-level network, and achieved reliable transmission with a synchronization clock accuracy of less than 100ns and a transmission rate of 1000Mbps. A redundant transmission architecture with a single-end node and dual transmission paths was constructed, which overcame the single-point failure mode of the traditional Ethernet master-slave architecture and provided redundancy for the TTE network. A modular multi-level TTE bus network architecture was proposed, which provided a solution for the multi-level cascade technology of the TTE network.

[0036] 2. The TTE bus data redundant transmission technology with optimized TDMA is adopted. By dividing the TTE bus synchronization cycle into multiple scheduling cycles, the data delay of the telemetry frame is reduced. In each bus scheduling cycle, each end node transmits data information flow and instruction information flow according to the pre-planned time slot unit, ensuring the independence of various types of data transmission and improving the fault isolation capability of the TTE bus network. It is proposed to formulate the starting time of each virtual link based on the actual write cache rate of the TTE SOC in each TTE bus scheduling cycle, ensuring the orderly and complete transmission of data at each end node.

[0037] 3. The data integration equipment reset and reframe technology is adopted. At the beginning of each TTE bus scheduling cycle, the data integration equipment clears the SOC cache to solve the problem of telemetry full frame error caused by the electromagnetic interference generated at the moment of power-on of the end node in the TTE bus network. Relying on the TTE bus technology, the data integrator realizes data collection and the first telemetry frame framing of each end node, and adopts the internal reframing technology of the data integrator to overcome the TTE bus network synchronization clock jitter problem, and finally realizes stable framing that can be used for wireless downlink. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Figure 1 This is a schematic diagram of the architecture of a comprehensive system for telemetry data based on TTE real-time Ethernet bus.

[0039] Figure 2 This is a data processing flow chart of a telemetry system based on TTE bus technology. DETAILED DESCRIPTION

[0040] The present invention is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0041] Time Triggered Ethernet (TTE) uses "clock synchronization" and "time triggering" on the basis of traditional Ethernet to ensure the real-time and deterministic communication of safety-critical data, and improves the reliability of the network through redundant transmission and fault detection / isolation mechanisms. Compared with the master-slave communication architecture such as 1553B adopted in traditional telemetry systems, the TTE bus network uses multiple synchronous masters (SMs) to send time synchronization protocol control frames (PCFs) to provide redundancy for the TTE network. The telemetry system design based on the TTE bus adopts a multi-level TTE bus networking architecture with redundant synchronization characteristics, a TTE bus data scheduling technology that optimizes TDMA, and a TTE bus telemetry data integration technology that uses data integration equipment reset and re-frame, realizing a large bandwidth, strong real-time, and highly reliable system design for the telemetry system.

[0042] The present invention provides a telemetry data integration system based on TTE real-time Ethernet bus, including an M-level TTE bus network architecture and multiple cascaded interactive machines. Figure 1 As shown, the M-level TTE bus network architecture may include a primary TTE bus network architecture and a secondary TTE bus network architecture.

[0043] In the first-level TTE bus network architecture, data integration equipment 11, data integration equipment 12, data collection and editing equipment 11, data collection and editing equipment 12, ..., data collection and editing equipment 1N, switch 11, switch 12 are arranged, and a first-level TTE bus network architecture with redundant transmission characteristics is formed by connecting the super five-category network cables between the devices. Among them, data integration equipment 11, data integration equipment 12, data collection and editing equipment 11, data collection and editing equipment 12, ..., data collection and editing equipment 1N are the end nodes of the first-level TTE bus network architecture. The number N of data collection and editing equipment can be set according to the actual number of end nodes of the system.

[0044] The two-level TTE bus network architecture is similar to the one-level TTE bus network architecture. The two-level network is cascaded through switches G1 and G2. This network architecture can be expanded to a multi-level TTE bus network architecture by cascading switches GN1 and GN2 according to system requirements.

[0045] like Figure 1 As shown, data integration devices 11 and 12 are connected to switches 11 and 12 via Category 5e network cables, and data integration devices 21 and 22 are connected to switches 21 and 22 via Category 5e network cables. In each level of the TTE bus network architecture, multiple data integration devices can obtain the same data from switches 1 and 2 in the network architecture, forming redundant transmission.

[0046] like Figure 1 As shown, data integration devices 11 and 12 are respectively connected to the telemetry transmitter via interface 422 to form mutually redundant PCM1 and PCM2 telemetry data streams, which are modulated by the telemetry transmitter and sent out via the antenna.

[0047] like Figure 1 As shown, data integration devices 11, 12, 21, 22 are connected to cascade switches G1, G2 via Category 5e network cables. Each end node has two transmission paths in the network, which are mutually redundant.

[0048] like Figure 1 As shown, the switch 11 is connected to the switch 12 via a Category 5e network cable; the switch 21 is connected to the switch 22 via a Category 5e network cable; the switches 11, 12 and the switches 21, 22 form a mutually redundant network transmission path.

[0049] In the first-level TTE bus network architecture, the data integration device 11, the data integration device 12, the data collection and editing devices 11, 12, ..., 1N are connected to the switches 11, 12 through Category 5e network cables; in the second-level TTE bus network architecture, the data integration device 21, the data integration device 22, the data collection and editing devices 21, 22, ..., 2N are connected to the switches 21, 22 through Category 5e network cables.

[0050] Through system redundancy design, it is ensured that there are at least two transmission paths between each end node. When data is lost in one transmission line, the data integration equipment can obtain data from another line. Each device is connected by a Category 5e network cable, which supports a data communication rate of 1000Mbps.

[0051] like Figure 2 As shown, the data processing flow of the telemetry system based on TTE bus technology is as follows.

[0052] Step (1): select data integration device 11 and data integration device 12 as synchronization masters. According to the AS6802 protocol, in each TTE synchronization cycle, the two synchronization masters jointly form a synchronization clock source and send a time synchronization protocol control frame (PCF) containing transparent clock information to multiple synchronization clients.

[0053] Combination Figure 1 In the illustrated embodiment, multiple synchronization clients include data acquisition and editing device 11, data acquisition and editing device 12, ..., data acquisition and editing device 1N, data integration type device 21, data integration type device 22, data acquisition and editing device 21, data acquisition and editing device 22, ..., data acquisition and editing device 2N.

[0054] Step (2), after the synchronization client receives the PCF, it completes the clock synchronization with the two synchronization masters through solidification and compression.

[0055] The transparent clock is the transmission delay of a PCF frame from one end node to another in a TTE network. The transmission delay is related to the transmission distance between the end nodes and the transparent transmission delay of the switch. The transparent clock measurement method is as follows:

[0056] A. Select time t1, end node 1 sends a message to end node 2 and records time t1 locally;

[0057] B. After receiving the information, end node 2 uses DMA (Direct Memory Access) to cache the data into the content and records the time t2 locally in order to avoid CPU delay in calling storage to read information after the message arrives and obtain accurate network transmission delay;

[0058] C. End node 2 sends a data frame containing time information t2 to end node 1, and records time t3 locally; since the first message sent by end node 2 does not contain time information t3, end node 2 sends a data frame containing time information t3 to end node 1;

[0059] D. End node 1 also uses DMA to receive two messages from end node 2, and records the time t4 when the first message from end node 2 is received, and obtains time t2 and t3;

[0060] Therefore, the transmission delay between the two end nodes in the TTE network can be obtained as t_delay=[(t4-t1)-(t3-t2)] / 2.

[0061] Since the data transmission between the end nodes in the TTE bus network adopts a periodic transmission mechanism, it is affected by the clock error caused by the temperature drift of the crystal oscillator inside the end node. If each endpoint completes clock synchronization only based on the transparent clock, it may cause the end node synchronization failure. To ensure that each end node in the multi-level TTE bus networking system can maintain synchronization, if the maximum temperature drift error of a crystal oscillator within a TTE synchronization cycle is t_temperature, the TTE clock synchronization window time is required to be greater than t_temperature+t_delay. This avoids the problem of multi-end node synchronization failure caused by crystal oscillator temperature drift in the actual use of the multi-level TTE bus network.

[0062] Step (3), in order to increase the transmission speed of telemetry information, time division multiplexing (TDMA) is used to complete data transmission and data integration between end nodes in the multi-level TTE bus networking architecture.

[0063] According to the characteristics of the TTE bus, the data transmission of each end node will be sent strictly according to the specified time. In order to reduce the delay of telemetry data, the TTE network synchronization clock cycle is set to be consistent with the telemetry frame transmission cycle; each telemetry frame cycle is evenly divided into N TTE bus scheduling cycles (N is an even number, N>2). In each TTE bus scheduling cycle, according to the total amount of data transmitted by each end node, each TTE bus scheduling cycle is evenly divided into M time slot units, and virtual link 1, virtual link 2, ..., virtual link M are calibrated in turn. A fixed data transmission task is arranged for each time slot unit.

[0064] Combination Figure 1 In the embodiment shown, the data transmission tasks arranged by the time slot unit include any of the following: the data integration devices 11, 12 send downlink instruction information flows to the data acquisition and editing devices 11~1N via the switches 11, 12, the data integration devices 21, 22 send downlink instruction information flows to the data acquisition and editing devices 21~2N via the switches 21, 22, and the data integration devices 11, 12 send downlink instruction information flows to the data integration devices 21, 22 via the switches 21, 22; the data acquisition and editing devices 11~1N send uplink data information flows to the data integration devices 11, 12 via the switches 11, 12, the data acquisition and editing devices 21~2N send uplink data information flows to the data integration devices 21, 22 via the switches 21, 22, and the data integration devices 21, 22 send uplink data information flows to the data integration devices 11, 12 via the switches G1, G2.

[0065] The data sent by each end node can be unicast, multicast, or broadcast. According to the IEEE802.3 standard Ethernet protocol, the amount of TTE network frame data that can be transmitted by the end node in each time slot unit is 46-1499 bytes. If the total amount of data transmitted by a data acquisition and editing device exceeds the maximum TTE transmission data amount, it needs to be transmitted in multiple time slot units, that is, divided into multiple virtual link numbers for data transmission.

[0066] There are two paths for information interaction between each end node. Taking data integration devices 11 and 12 as an example, when data integration devices 11 and 12 receive transmission data from one of switches 11 and 12, they automatically shield the transmission data from the other switch to complete data integration under the premise of ensuring redundancy of information transmission channels.

[0067] Since the data of each end node is continuously sent in cycles, in order to avoid erroneous framing of the data in the adjacent cycles and ensure the integrity of the framing data in a telemetry frame cycle, if the start time of each TTE bus scheduling cycle is t_d, the data transmission time of virtual link 1 is t_1, and the time difference between the two is t_1d=t_1-t_d. The amount of data transmitted by end node 1 on virtual link 1 is M_1, the rate of SOC writing cache inside end node 1 is V_1, and the total time for end node 1 to prepare to send data M_1 to write into the cache is t_fifo=M_1 / V_1. It is required that t_1d>t_fifo. That is, it is ensured that at the time of data transmission of virtual link 1, end node 1 has completed the preparation for sending data. Since the time when each end node is ready to send data is t_d, according to the sending time of each end node and the total amount of data sent, the minimum time interval between each virtual link number can be calculated to ensure the orderly and complete transmission of data of each end node.

[0068] The data integration equipment can clear the SOC cache in each TTE bus scheduling cycle to solve the telemetry frame misalignment problem caused by inconsistent power-on timing of nodes at each end of the network. Figure 2 As shown in the figure, after the data integration device forms a complete telemetry full frame, a two-level data integration technology is used to form a PCM data stream that can be used for telemetry transmission. Affected by the electromagnetic interference generated by the power-on moment of the multi-level TTE bus network end node, uncontrolled TTE frame data will be generated in the TTE network, resulting in errors in the telemetry full frame collected by the data integration device. Therefore, the data integration device is required to clear the SOC cache at the beginning of each TTE bus scheduling cycle t_d to ensure that the data collected by the data integration device within a TTE network synchronization clock cycle is valid data sent by all end nodes within the current telemetry frame cycle.

[0069] The data integration equipment performs data processing actions such as cutting, routing, and framing on the data of each end node according to the pre-specified frame format to form the first-level telemetry full-frame data. Since the TTE bus time synchronization adopts the time iteration convergence and time compensation mechanism, it is affected by the crystal oscillator jitter. In actual applications, there is a certain jitter in the TTE bus scheduling cycle. The position of the frame synchronization code of the first data integration in the telemetry frame is unstable, which will cause the telemetry station to lose the lock or lose the telemetry frame when it is directly transmitted. Therefore, the re-frame technology is adopted. The data integration equipment re-frames the first-level telemetry full-frame data in an asynchronous transmission mode to a frame format with a bandwidth higher than the first-level full-frame data through its own data scheduling. The jitter range of the first-level telemetry full-frame data is enveloped by a higher telemetry bandwidth, and finally a stable PCM data stream is formed to send to the telemetry transmitter equipment, and wirelessly transmitted through the antenna.

[0070] Although the present invention is disclosed as above in the form of a preferred embodiment, it is not intended to limit the present invention. Any person skilled in the art may make possible changes and modifications without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be based on the scope defined by the claims of the present invention.

Claims

1. A telemetry data integration system based on TTE real-time Ethernet bus, characterized in that: It includes an M-level TTE bus network architecture and a plurality of cascade interactive machines, where M is an integer greater than 1, and the cascade interactive machine is used to realize the interaction of the two-level TTE bus network architecture; each level of the TTE bus network architecture includes two pairs of data integration devices for mutual redundancy, two pairs of switches for mutual redundancy, and at least one data collection and editing device; each cascade interactive machine includes two pairs of switches for mutual redundancy; The two switches in each level of the TTE bus network architecture are connected by Category 5e network cables; The data integration equipment and data collection and editing equipment in each level of the TTE bus network architecture are connected to the switch of the TTE bus network architecture through Category 5e network cables; The M-level TTE bus network architecture includes a primary TTE bus network architecture and a secondary TTE bus network architecture. Two pairs of data integration devices in the primary TTE bus network architecture are connected to a telemetry transmitter, and two pairs of data integration devices in the primary TTE bus network architecture and two pairs of data integration devices in the secondary TTE bus network architecture are connected to a cascade switch via a Category 5e network cable.

2. The system according to claim 1, characterized in that The data processing flow of the system includes: Two paired data integration devices in the first-level TTE bus network architecture are selected as two synchronization masters. In each TTE synchronization cycle, after the two synchronization masters jointly form a synchronization clock source, they send a time synchronization protocol control frame PCF containing transparent clock information to multiple synchronization clients. The synchronization clients include data acquisition and editing devices in the first-level TTE bus network architecture, data integration devices and / or data acquisition and editing devices in other levels of TTE bus network architecture except the first-level TTE bus network architecture; After receiving the PCF, the synchronization client completes the clock synchronization with the two synchronization masters after solidification and compression; Time division multiplexing (TDMA) is used to complete data transmission and data integration between end nodes in the multi-level TTE bus networking architecture.

3. The system according to claim 2, characterized in that The transparent clock is measured as follows: A. Select time t1, end node 1 sends a message to end node 2 and records time t1 locally; B. After receiving the information, end node 2 uses DMA to cache the data into the content and records the time t2 locally; C. End node 2 sends the data frame containing time information t2 to end node 1, and records time t3 locally; D. End node 2 sends a data frame containing time information t3 to end node 1; E. End node 1 receives two messages from end node 2 using DMA, records the time when the first message from end node 2 is received, records time t4 locally, and obtains time t2 and t3; F. The transmission delay between end node 1 and end node 2 in the TTE network is obtained as t_delay=[(t4-t1)-(t3-t2)] / 2.

4. The system according to claim 3, characterized in that The maximum temperature drift error of the crystal oscillator within a TTE synchronization period is t_temperature, and the TTE clock synchronization window time is greater than t_temperature + t_delay.

5. The system according to claim 2, characterized in that The TTE network synchronization clock cycle is consistent with the telemetry frame transmission cycle; each telemetry frame cycle is evenly divided into N TTE bus scheduling cycles. Within each TTE bus scheduling cycle, each TTE bus scheduling cycle is evenly divided into M time slot units according to the total amount of transmitted data, and virtual link 1, virtual link 2, ..., virtual link M are calibrated in turn, and each time slot unit arranges a fixed data transmission task.

6. The system according to claim 5, characterized in that The data transmission tasks arranged by the time slot unit include any of the following: The data integration equipment sends a downlink instruction information flow to the data acquisition and editing equipment via the switch; The data collection and editing equipment sends the uplink data information flow to the data integration equipment via the switch; The data integration device in the primary TTE bus network architecture sends a downlink instruction information flow to the data integration device in the secondary TTE bus network architecture via the cascade interactive machine; The data integration device in the secondary TTE bus network architecture sends an uplink data information flow to the data integration device in the primary TTE bus network architecture via the cascade interactive machine.

7. The system according to claim 2, characterized in that If the total amount of data transmitted by the data acquisition and editing equipment exceeds the maximum TTE transmission data amount, the data is divided into multiple virtual link numbers for data transmission.

8. The system according to claim 2, characterized in that t_1d>t_fifo; where, t_1d=t_1-t_d, t_d is the start time of each TTE bus scheduling cycle, t_1 is the data transmission time of virtual link 1; t_fifo=M_1 / V_1, M_1 is the amount of data transmitted by end node 1 on virtual link 1, and V_1 is the rate at which the internal SOC of end node 1 writes into the cache.

9. The system according to claim 2, characterized in that The data integration device clears the SOC cache in each TTE bus scheduling cycle.

10. The system according to claim 2, characterized in that The data integration equipment performs data processing actions such as cutting, routing, and framing on the data of each end node according to the specified frame format to form the first-level telemetry full-frame data; The first-level telemetry full-frame data is reframed into a frame format with a bandwidth higher than the first-level full-frame data in an asynchronous transmission manner to envelop the jitter range of the first-level telemetry full-frame data, form the second-level telemetry full-frame data, and wirelessly transmit it through the antenna.

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