Dpu-based udp order entry system, method, electronic device, medium

Abstract

The disclosure provides a DPU-based UDP order system, method, electronic device and medium. The system comprises an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembling module and a sending module. The initialization module is configured to initialize and configure received static data. The static data is used to represent the header information of the current transaction order. The arbitration module is configured to sequentially transmit the order data received by the software order data receiving module and the order data received by the hardware order data receiving module to the UDP packet assembling module according to the transmission priority. The order data is the service data transmitted for each transaction order. The UDP packet assembling module is configured to assemble the static data and the order data when the order data is received, and obtain a UDP data packet. The sending module is configured to send the UDP data packet to a transaction network port.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the field of order placement in financial transaction systems such as securities trading, and in particular to a DPU-based UDP order placement system, method, electronic device and medium. BACKGROUND

[0002] High-frequency trading in the financial transaction field is an important application field of ultra-low latency, and is also the field that pursues performance to the extreme. Financial institutions and exchanges need to conduct transactions at the level of microseconds or even nanoseconds to gain market advantages. Therefore, it is crucial for transaction platforms and network infrastructure to achieve ultra-low latency. In the field of high-frequency trading, with the popularization of the ultra-low latency technology of DPU (Data Processing Unit), it has become the consensus of financial institutions to develop ultra-low latency high-speed trading systems based on DPU.

[0003] In the related art, the CPU (Central Processing Unit) end assembles the received data into a UDP data packet conforming to the exchange order placement format, and sends the UDP data packet to the DPU through the general serial connection standard PCIe (Peripheral Component Interconnect Express). Since the complete UDP data packet needs to be assembled on the CPU, and the assembly is performed after the complete UDP data packet is received, the transmission delay is high. Therefore, in the transaction scenario, how to faster send the transaction order to the exchange is a problem to be solved. SUMMARY

[0004] To solve the above technical problems or at least partially solve the above technical problems, the present disclosure provides a DPU-based UDP order placement system, method, electronic device and medium, which can faster send the transaction order to the exchange in the transaction scenario.

[0005] To achieve the above purpose, the technical solutions of the embodiments of the present disclosure are provided as follows.

[0006] In a first aspect, the embodiments of the present disclosure provide a DPU-based UDP order placement system, which comprises an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembly module and a sending module.

[0007] The initialization module is configured to initialize and configure the received static data. The static data is used to represent the header information of the current transaction order.

[0008] The arbitration module is configured to transmit the order data received by the software order data receiving module and the order data received by the hardware order data receiving module to the UDP packet assembling module in sequence according to the transmission priority; the order data is service data transmitted for each transaction order;

[0009] The UDP packet assembling module is configured to perform packet assembling processing on the static data and the order data when the order data is received, and obtain a UDP data packet.

[0010] The sending module is configured to send the UDP data packet to a transaction network interface.

[0011] As an optional implementation of the embodiment of the present disclosure, the software order data receiving module is configured to receive order data transmitted based on direct memory access (DMA) through a software order data interface.

[0012] As an optional implementation of the embodiment of the present disclosure, the hardware order data receiving module is configured to receive order data sent by a transaction strategy module through a hardware order data interface; and the transaction strategy module is configured to store the order data.

[0013] As an optional implementation of the embodiment of the present disclosure, the arbitration module is specifically configured to read order data from a first-in-first-out queue of the hardware order data receiving module and transmit the order data to the UDP packet assembling module when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module.

[0014] As an optional implementation of the embodiment of the present disclosure, the arbitration module is specifically configured to read order data from a first-in-first-out queue of the software order data receiving module and transmit the order data to the UDP packet assembling module when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module.

[0015] As an optional implementation of the embodiment of the present disclosure, the UDP packet assembling module is further configured to switch a working state of the UDP packet assembling module from an idle state to a start state when it is detected that the initialization module has static data input.

[0016] As an optional implementation of the embodiment of the present disclosure, the UDP packet assembling module is further configured to, when the working state of the UDP packet assembling module is in the start state, read order data from a first-in-first-out queue of the arbitration module and perform packet assembling processing on the static data and the order data to obtain a UDP data packet when it is detected that the first-in-first-out queue of the arbitration module is not empty.

[0017] When it is monitored that the first-in-first-out queue of the arbitration module is empty, if it is monitored that the initialization module has end information input, the working state of the UDP packet module is switched from the start state to an idle state.

[0018] In a second aspect, the embodiments of the present disclosure provide a DPU-based UDP order method, comprising:

[0019] initializing and configuring received static data; the static data is used to represent the header information of a current transaction order;

[0020] According to the transmission priority, the order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted.

[0021] When the order data is received, the static data and the order data are packetized to obtain a UDP data packet.

[0022] The UDP data packet is sent to a transaction network port.

[0023] As an optional implementation of the embodiments of the present disclosure, the method further comprises:

[0024] The order data based on direct memory access (DMA) transmission is received through a software order data interface.

[0025] As an optional implementation of the embodiments of the present disclosure, the method further comprises:

[0026] The order data sent by a transaction strategy module is received through a hardware order data interface; the transaction strategy module is used to store order data.

[0027] As an optional implementation of the embodiments of the present disclosure, the sequentially transmitting the order data received through the software order data interface and the order data received through the hardware order data interface according to the transmission priority comprises:

[0028] When the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module, order data is read from the first-in-first-out queue of the hardware order data receiving module first, and the order data is transmitted to the UDP packet module.

[0029] As an optional implementation of the embodiments of the present disclosure, the sequentially transmitting the order data received through the software order data interface and the order data received through the hardware order data interface according to the transmission priority comprises:

[0030] When the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module, order data is read from the first-in first-out queue of the software order data receiving module first, and the order data is transmitted to the UDP packet assembling module.

[0031] As an optional implementation of the embodiment of the present disclosure, before the static data and the order data are packetized to obtain the UDP data packet, the method further comprises:

[0032] When it is detected that the initialization module has static data input, the working state of the UDP packet assembling module is switched from the idle state to the start state.

[0033] As an optional implementation of the embodiment of the present disclosure, the method further comprises:

[0034] When the working state of the UDP packet assembling module is the start state, and it is detected that the first-in first-out queue of the arbitration module is not empty, order data is read from the first-in first-out queue of the arbitration module, the static data and the order data are packetized to obtain the UDP data packet.

[0035] When it is detected that the first-in first-out queue of the arbitration module is empty, if it is detected that the initialization module has end information input, the working state of the UDP packet assembling module is switched from the start state to the idle state.

[0036] In a third aspect, an electronic device is provided, which includes a memory and a processor. The memory stores a computer program. When the processor executes the computer program, the DPU-based UDP order method in the second aspect or any of the implementations of the second aspect is implemented.

[0037] In a fourth aspect, a computer readable storage medium is provided, which stores a computer program. When the computer program is executed by a processor, the DPU-based UDP order method in the second aspect or any of the implementations of the second aspect is implemented.

[0038] The DPU-based UDP order system provided by the present disclosure comprises an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembling module, and a sending module. The received static data is initialized and configured by the initialization module. The order data received through the software order data interface and the order data received through the hardware order data interface are sequentially transmitted to the UDP packet assembling module according to the transmission priority by the arbitration module. When the order data is received, the UDP packet assembling module performs packet assembling processing on the static data and the order data to obtain a UDP data packet. Finally, the sending module sends the UDP data packet to a transaction network port. The DPU-based UDP order system of the present application realizes simultaneous software and hardware ordering, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the static data is pre-stored on the DPU card through the architecture pre-configured by the packet header information, and only the necessary transaction information (i.e. order data) is transmitted for each subsequent order, so as to reduce the data transmission amount of PCIe and thus reduce the system latency. BRIEF DESCRIPTION OF DRAWINGS

[0039] The accompanying drawings, which are incorporated herein and constitute part of the specification, illustrate embodiments consistent with the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0040] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings required to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0041] Figure 1 An application scenario diagram of the DPU-based UDP order system in an embodiment;

[0042] Figure 2 A structure diagram of the DPU-based UDP order system in an embodiment;

[0043] Figure 3 A flow diagram of the DPU-based UDP order system in an embodiment;

[0044] Figure 4 A structure diagram of the electronic device described in the embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the prior art, the drawings required to be used in the embodiments or the prior art description will be briefly introduced. Obviously, for those skilled in the art, other drawings can also be obtained from these drawings without creative labor.

[0046] In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present disclosure. The present disclosure, however, can be practiced without the specific details. In other instances, well-known methods, procedures, components, and circuits have not been described in detail since not to unnecessarily obscure aspects of the present disclosure.

[0047] In the present disclosure, the word "exemplary" or "for example" is used to mean "an example of" or "an example, only. As used in this disclosure, "exemplary" or "for example" is not used to imply that a described embodiment or example is preferred or better than other embodiments or examples. In other words, use of "exemplary" or "for example" is not intended to convey that a referenced embodiment or example is preferred or a best example. Rather, "exemplary" or "for example" is simply used to indicate that a described embodiment or example is one of a possible plurality of embodiments or examples.

[0048] Glossary:

[0049] High-frequency trading (HFT) is an automated trading method that uses high-speed computer algorithms and network technology to execute a large number of trades in a very short period of time. This trading strategy relies on small market changes, such as small fluctuations in stock prices or price differences between different exchanges, to achieve profits. The characteristics of high-frequency trading include fast execution of trading orders, low-latency trading systems, and fast response to market data. High-frequency trading (HFT) systems may use automated algorithms to quickly generate and execute trading orders to take advantage of small market fluctuations.

[0050] DPU is a processor designed specifically for data centers, used to efficiently handle large-scale data workloads, including data transfer, protocol, protection, compression, analysis, and encryption tasks. Compared with traditional CPU and GPU, DPU focuses on data-centric workloads such as network, storage, and security operations in data centers.

[0051] UDP is a connectionless network protocol used to transmit data over IP networks. It belongs to the transport layer protocol, along with TCP (Transmission Control Protocol), but the main difference between UDP and TCP is that UDP is stateless and does not guarantee the order, integrity, and reliability of data packets. UDP provides a simple way to send encapsulated IP packets, but does not sort or ensure that data reaches its destination.

[0052] A trade order, often referred to as a trade ticket, is an instruction issued by an investor or trader to buy or sell financial products such as securities, stocks, futures, or foreign exchange in financial markets. These orders contain detailed information about the transaction, such as the financial product code, transaction direction (buy or sell), transaction quantity, and price. The execution of trade orders is usually carried out through trading systems of exchanges, which determine the order execution method based on the type and duration of the order. The basic types of trade orders include market orders, limit orders, stop-loss orders, stop-profit orders, and iceberg orders. Market orders are instructions to buy or sell immediately at the current market price. Limit orders are instructions to set a specific price, and the order will only be executed when the market price reaches or is better than this price. Stop-loss orders are triggered when the market price reaches a certain level, usually used to limit losses. Stop-profit orders are similar to stop-loss orders but are used to lock in profits when the price reaches a predetermined level. Iceberg orders are large transaction orders that only show a small portion of the transaction volume, with the rest hidden to avoid having a significant impact on the market price.

[0053] A trading strategy is a set of rules and methods developed to achieve profit goals in financial markets. Different traders adopt different trading strategies based on their risk tolerance, market analysis, and ability to manage funds. Some common types of trading strategies include technical analysis strategies, fundamental analysis strategies, quantitative trading strategies, trend-following strategies, hedging strategies, arbitrage strategies, and value investment strategies. Technical analysis strategies rely on charts and historical price data to predict future market trends. Fundamental analysis strategies make trading decisions based on information such as a company's financial situation, industry conditions, and macroeconomic indicators. Quantitative trading strategies use mathematical models and algorithms to identify trading opportunities. Trend-following strategies involve following market trends, buying stocks in an upward trend, and selling stocks in a downward trend. Hedging strategies involve reducing market risk by holding positions in multiple related assets. Arbitrage strategies take advantage of price differences in different markets or at different times to generate risk-free profits. Value investment strategies involve finding stocks whose market prices are lower than their intrinsic values and holding them for a long time.

[0054] RAM (Random Access Memory) is a hardware used in computers and other electronic devices to temporarily store data and programs. It is the main memory of a computer, used to store data and instructions currently in use while the computer is running. RAM is usually volatile, meaning that the data stored in RAM will be lost when the power is turned off. RAM allows fast reading and writing of data, which enables computers to quickly access and process information.

[0055] PCIe is a computer bus and expansion card standard for connecting computer hardware devices. PCIe uses high-speed serial connections, supporting different data transfer rates.

[0056] In the related art, the CPU (Central Processing Unit) end assembles the received data into a UDP data packet conforming to the exchange order format, and sends the UDP data packet to the DPU through the Peripheral Component Interconnect Express (PCIe). Since the complete UDP data packet needs to be packaged on the CPU, transmitting the complete UDP data packet to the low-latency network card DPU through the Peripheral Component Interconnect Express (PCIe) will cause high transmission latency. In addition, when the trading strategy itself is implemented on the DPU low-latency network card, the data content of the order needs to be uploaded to the CPU (Central Processing Unit) through the Peripheral Component Interconnect Express (PCIe), and then the CPU sends it to the low-latency network card DPU through the PCIe, which increases the latency of the two PCIe transmissions. Therefore, in the trading scenario, how to send the trading order to the exchange faster is a problem that needs to be solved.

[0057] To solve the above problems, the present disclosure provides a DPU-based UDP order system, which includes an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembly module, and a sending module. The initialization module is configured to initialize the received static data, the arbitration module is configured to transmit the order data received through the software order data interface and the order data received through the hardware order data interface to the UDP packet assembly module in turn according to the transmission priority, when the order data is received, the UDP packet assembly module is configured to package the static data and the order data, obtain a UDP data packet, and finally, the sending module is configured to send the UDP data packet to the trading network port. The DPU-based UDP order system of the present application realizes simultaneous software and hardware ordering, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current trading order, through the architecture of pre-configuring the header information, the static data is pre-stored on the DPU card, and only the necessary trading information (i.e. order data) is transmitted for each subsequent order, so as to reduce the data transmission amount of PCIe and thus reduce the system latency.

[0058] Referring to Figure 1 , as shown in Figure 1For the application scenario of the DPU-based UDP order system in the embodiments of the present disclosure, it can be seen that the system is composed of six modules, which are: an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembling module, and a sending module. The modules are connected through FIFO. When the input FIFO of each module is not empty, data is read from the FIFO, the calculation of the module is completed, and the result is written into the output FIFO of the module.

[0059] The DPU-based UDP order system in the embodiments of the present disclosure is described in detail below.

[0060] Referring to Figure 2 Figure 2 For a structure diagram of the DPU-based UDP order system in the embodiments of the present disclosure, it includes:

[0061] The initialization module 210 is configured to initialize and configure the received static data. The static data is used to represent the header information of the current trading order.

[0062] In the embodiments of the present disclosure, when using the UDP protocol for data transmission, the data packet will be encapsulated in sequence through the Ethernet frame, the IP (Internet Protocol) header, and the UDP header. The header information of the current trading order includes the source MAC, the destination MAC, the source port, the destination port, the message format, the message length, and the like. Since the header information of the current trading order does not change with the specific trading order, it can be pre-configured and issued in the form of initialization parameters in the initialization module. The static data includes: Ethernet frame header data, IP header data, the preset order protocol header data, and message header data. Among them, the Ethernet frame header data includes: Ethernet type, source MAC address, and destination MAC address. The IP header data includes: IP protocol version, IP header length, service type, total length, identification, source IP address, and destination IP address. The UDP header data includes: source port, destination port, length, checksum, and the like. The message header is used to distinguish different types of message information, such as stop-loss order, stop-profit order, and iceberg order. The initialization module pre-configures the public information (i.e. static data) in the exchange order format that is irrelevant to the specific trading information by the initialization process on the CPU to initiate DMA transmission. These static data are issued to the DPU card for pre-storage. Subsequently, only the necessary trading information (i.e. order data) is transmitted for each order to reduce the data transmission amount of PCIe, thereby reducing the system latency.

[0063] ​The arbitration module 220 is configured to transmit the order data received by the software order data receiving module 230 and the order data received by the hardware order data receiving module 240 to the UDP packet assembling module in sequence according to a transmission priority; the order data is service data transmitted for each transaction order.

[0064] In the embodiments of the present disclosure, the order data is used to describe detailed information of a transaction, and the order data includes, for example, a financial product code of the transaction, a transaction direction, a transaction quantity, a price, etc. The transmission priority can be set according to an actual application scenario, for example, the order data received by the software order data receiving module 230 can be set to be transmitted preferentially, or the order data received by the hardware order data receiving module 240 can be set to be transmitted preferentially.

[0065] Optionally, the software order data receiving module 230 is configured to receive order data transmitted based on DMA through a software order data interface.

[0066] In the embodiments of the present disclosure, when a transaction order is initiated by software, the software order data receiving module receives message content data transmitted based on DMA from an order process of a CPU through a software order data receiving interface.

[0067] Optionally, the hardware order data receiving module 240 is configured to receive order data transmitted by a transaction strategy module through a hardware order data interface; the transaction strategy module is configured to store the order data.

[0068] In the embodiments of the present disclosure, when a transaction order is initiated internally by a DPU (i.e., the transaction strategy module is implemented on the DPU), the hardware order data receiving module receives message content data transmitted from the transaction strategy module through a hardware order data receiving interface.

[0069] In an optional embodiment, the arbitration module 220 is specifically configured to, when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module, first read order data from a first-in-first-out queue of the hardware order data receiving module, and transmit the order data to the UDP packet assembling module.

[0070] In the embodiments of the present disclosure, for the arbitration module, since the software order data is buffered in a software FIFO and the hardware order data is buffered in a hardware FIFO, the arbitration switch is used to first determine whether the hardware FIFO is empty in each clock cycle. When the hardware FIFO is not empty, the order data is read from the hardware FIFO and transmitted to the UDP packet assembling module; when the hardware FIFO is empty, it is further determined whether the software FIFO is empty, and when the software FIFO is not empty, the order data is read from the software FIFO and transmitted to the UDP packet assembling module.

[0071] In an optional implementation, the arbitration module 220 is specifically configured to read order data from the first-in-first-out queue of the software order data receiving module first when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module, and transmit the order data to the UDP packet assembling module.

[0072] In the embodiments of the present disclosure, for the arbitration module, since the software order data is buffered in the software FIFO and the hardware order data is buffered in the hardware FIFO, the arbitration switch is used to first determine whether the software FIFO is empty in each clock cycle. When the software FIFO is not empty, order data is read from the software FIFO and transmitted to the UDP packet assembling module. When the software FIFO is empty, it is further determined whether the hardware FIFO is empty. When the hardware FIFO is not empty, order data is read from the hardware FIFO and transmitted to the UDP packet assembling module.

[0073] In addition, it should be noted that when the hardware FIFO and the software FIFO are both empty, no data is transmitted.

[0074] The UDP packet assembling module 250 is configured to perform packet assembling processing on the static data and the order data when the order data is received, and obtain a UDP data packet.

[0075] In the embodiments of the present disclosure, when the UDP packet assembling module receives the order data sent by the arbitration module, the static data stored in the initialization module is packet assembled with the order data sent by the arbitration module to obtain a complete UDP data packet.

[0076] In an optional implementation, the UDP packet assembling module 250 is further configured to switch the working state of the UDP packet assembling module from an idle state to a start state when it is detected that the initialization module has static data input.

[0077] In the embodiments of the present disclosure, the working state of the UDP packet assembling module includes an idle state and a start state. The initial working state of the UDP packet assembling module is the idle state, and the FIFO queue data of the initialization module is monitored. When the initialization module issues initialization configuration information, the initialization configuration information is buffered in the on-chip RAM of the initialization module, and the working state of the UDP packet assembling module is switched from the idle state to the start state.

[0078] In an alternative embodiment, the UDP packet assembling module 250 is further configured to, when the working state of the UDP packet assembling module is in the start state, read order data from the first-in-first-out queue of the arbitration module when it is detected that the first-in-first-out queue of the arbitration module is not empty, assemble the static data and the order data to obtain a UDP data packet; and when it is detected that the first-in-first-out queue of the arbitration module is empty, switch the working state of the UDP packet assembling module from the start state to the idle state if it is detected that the initialization module has an end information input.

[0079] In the embodiment of the present disclosure, when the working state of the UDP packet assembling module is in the start state, it is detected whether the first-in-first-out queue of the arbitration module has order data: when it is detected that the first-in-first-out queue of the arbitration module is not empty, read order data from the first-in-first-out queue of the arbitration module, assemble the static data and the order data to obtain a UDP data packet; and when it is detected that the first-in-first-out queue of the arbitration module is empty, switch the working state of the UDP packet assembling module from the start state to the idle state if it is detected that the initialization module has an end information input.

[0080] The sending module 260 is configured to send the UDP data packet to a transaction network interface.

[0081] In the embodiment of the present disclosure, the complete UDP data packet is sent to the transaction network interface for transaction.

[0082] The DPU-based UDP order system provided by the present disclosure comprises an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembling module, and a sending module. The received static data is initialized and configured by the initialization module. The arbitration module is used to sequentially transmit order data received through a software order data interface and order data received through a hardware order data interface to the UDP packet assembling module according to a transmission priority. When the order data is received, the UDP packet assembling module assembles the static data and the order data to obtain a UDP data packet. Finally, the sending module sends the UDP data packet to a transaction network interface. The DPU-based UDP order system of the present application realizes simultaneous software and hardware order submission, which can increase the flexibility of the system. In addition, since the static data is used to represent the header information of the current transaction order, the architecture of the packet header information pre-configuration is used to pre-store the static data on the DPU card. Subsequently, only necessary transaction information (i.e., order data) is transmitted for each order, so as to reduce the data transmission amount of the PCIe and thus reduce the system latency.

[0083] Corresponding to the above system embodiment, the present disclosure further provides a DPU-based UDP order method. As shown in Figure 3 Fig. 2,Figure 3 A flowchart of a DPU-based UDP order method, which comprises the following steps S31-S34.

[0084] S31, initialize and configure the received static data.

[0085] The static data is used to represent the header information of the current transaction order.

[0086] S32, according to the transmission priority, sequentially transmit the order data received through the software order data interface and the order data received through the hardware order data interface.

[0087] S33, when the order data is received, packetize the static data and the order data to obtain a UDP data packet.

[0088] S34, send the UDP data packet to a transaction network port.

[0089] As an optional implementation of the embodiment of the present disclosure, the method further comprises:

[0090] Receiving order data based on direct memory access (DMA) transmission through a software order data interface.

[0091] As an optional implementation of the embodiment of the present disclosure, the method further comprises:

[0092] Receiving order data sent by a transaction strategy module through a hardware order data interface; the transaction strategy module is used to store order data.

[0093] As an optional implementation of the embodiment of the present disclosure, the sequentially transmitting the order data received through the software order data interface and the order data received through the hardware order data interface according to the transmission priority comprises:

[0094] When the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module, read order data from the first-in-first-out queue of the hardware order data receiving module first, and transmit the order data to the UDP packetizing module.

[0095] As an optional implementation of the embodiment of the present disclosure, the sequentially transmitting the order data received through the software order data interface and the order data received through the hardware order data interface according to the transmission priority comprises:

[0096] When the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module, order data is read from the first-in-first-out queue of the software order data receiving module first, and the order data is transmitted to the UDP packet assembling module.

[0097] As an optional implementation of the embodiment of the present disclosure, before the static data and the order data are packetized to obtain the UDP data packet when the order data is received, the method further comprises:

[0098] When it is detected that the initialization module has static data input, the working state of the UDP packet assembling module is switched from the idle state to the start state.

[0099] As an optional implementation of the embodiment of the present disclosure, the method further comprises:

[0100] When the working state of the UDP packet assembling module is the start state, and it is detected that the first-in-first-out queue of the arbitration module is not empty, order data is read from the first-in-first-out queue of the arbitration module, the static data and the order data are packetized to obtain the UDP data packet.

[0101] When it is detected that the first-in-first-out queue of the arbitration module is empty, if it is detected that the initialization module has end information input, the working state of the UDP packet assembling module is switched from the start state to the idle state.

[0102] The DPU-based UDP order method provided by the present disclosure comprises the following steps: initializing and configuring received static data, transmitting order data received through a software order data interface and order data received through a hardware order data interface in sequence according to a transmission priority, packetizing the static data and the order data to obtain a UDP data packet when the order data is received, and finally sending the UDP data packet to a transaction network port. The DPU-based UDP order method of the present application realizes simultaneous software and hardware order, can increase the flexibility of the system, and additionally, since the static data is used to represent the header information of the current transaction order, the static data is pre-stored on the DPU card through the architecture of pre-configuring the header information, and only necessary transaction information (i.e., order data) is transmitted for each subsequent order, so as to reduce the data transmission amount of the PCIe, thereby reducing the system latency.

[0103] For specific limitations of the DPU-based UDP order method, refer to the limitations of the DPU-based UDP order system in the foregoing, which will not be repeated here.

[0104] The present disclosure further provides an electronic device, Figure 4This is a schematic diagram of the structure of an electronic device provided in an embodiment of this disclosure. Figure 4 As shown, the electronic device provided in this embodiment includes a memory 41 and a processor 42. The memory 41 is used to store computer programs; the processor 42 is used to execute the steps performed in any embodiment of the DPU-based UDP packet method provided in the above method embodiments when the computer program is invoked. The electronic device includes a processor, a memory, a communication interface, a display screen, and an input device connected via a system bus. The processor of the electronic device provides computing and control capabilities. The memory of the electronic device includes a non-volatile storage medium and internal memory. The non-volatile storage medium stores an operating system and computer programs. The internal memory provides an environment for the operation of the operating system and computer programs in the non-volatile storage medium. When the computer program is executed by the processor, it implements a DPU-based UDP packet method. The display screen of the electronic device can be a liquid crystal display screen or an e-ink display screen. The input device of the electronic device can be a touch layer covering the display screen, or buttons, a trackball, or a touchpad provided on the casing of a computer device, or an external keyboard, touchpad, or mouse, etc.

[0105] Those skilled in the art will understand that Figure 4 The structure shown is merely a block diagram of a portion of the structure related to the present disclosure and does not constitute a limitation on the computer device to which the present disclosure is applied. Specific electronic devices may include more or fewer components than those shown in the figure, or combine certain components, or have different component arrangements.

[0106] In one embodiment, the DPU-based UDP message system provided in this disclosure can be implemented as a computer, and the computer program can be used in, for example... Figure 4 The electronic device shown operates on this device. The memory of the electronic device can store the various program modules that make up the DPU-based UDP message system of the electronic device.

[0107] This disclosure also provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the DPU-based UDP packet method provided in the above-described method embodiments.

[0108] Those skilled in the art will understand that embodiments of this disclosure can be provided as methods, systems, or computer program products. Therefore, this disclosure can take the form of a completely hardware embodiment, a completely software embodiment, or an embodiment combining software and hardware aspects. Furthermore, this disclosure can take the form of a computer program product embodied on one or more computer-usable storage media containing computer-usable program code.

[0109] The processor can be a central processing unit (CPU), a general purpose processor, a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or the like. The general purpose processor can be a microprocessor, or the processor can be any conventional processor, etc.

[0110] The memory can include non-persistent memory and / or volatile memory, e.g., random access memory (RAM) and / or non-volatile memory, e.g., read only memory (ROM), flash memory, etc. The memory is an example of computer readable media.

[0111] Computer readable media includes permanent and non-permanent, movable and non-movable storage media. The storage media can be implemented by any method or technology to store information, which can be computer readable instructions, data structures, program modules or other data. Examples of computer storage media include, but are not limited to, phase change memory (PRAM), static random access memory (SRAM), dynamic random access memory (DRAM), other types of random access memory (RAM), read only memory (ROM), electrically erasable programmable read only memory (EEPROM), flash memory or other memory technology, compact disc read only memory (CD-ROM), digital versatile disc (DVD) or other optical storage, magnetic cassette, magnetic disk storage or other magnetic storage device, or any other non-transmission medium that can be used to store information accessible to a computing device. According to the definition herein, computer readable media does not include transitory media, such as modulated data signals and carriers.

[0112] It should be noted that, in this document, the terms "comprising", "including", or any other variant thereof are intended to cover non-exclusive inclusion, so that processes, methods, articles or devices including a series of elements not only include those elements, but also include other elements not explicitly listed, or inherent to such processes, methods, articles or devices. Without more limitations, the element defined by the statement "including a" does not exclude the presence of another identical element in the process, method, article or device including the element.

[0113] The foregoing is merely illustrative of the various implementations of the present disclosure and the general principles thereof. Numerous modifications can be made to these illustrations, and equivalents can be substituted therefor, without departing from the scope of the present disclosure. The specific embodiments commensurate with the specific application are intended to be illustrative only and not limiting of the scope of the application as set forth in the following claims.

Claims

1. A DPU-based UDP order ticket system, characterized in that, The DPU-based UDP order system comprises an initialization module, a software order data receiving module, a hardware order data receiving module, an arbitration module, a UDP packet assembling module and a sending module. The initialization module is configured to initialize and configure received static data; the static data is used to represent the header information of a current transaction order; the initialization configuration is that when the initialization module issues initialization configuration information, the initialization configuration information is cached in the on-chip RAM of the initialization module, and the working state of the UDP packet assembling module is switched from an idle state to a start state. The arbitration module is configured to transmit order data received by the software order data receiving module and order data received by the hardware order data receiving module to the UDP packet assembling module in sequence according to the transmission priority; the order data is service data transmitted for each transaction order; the order data received by the software order data receiving module is message content data transmitted based on DMA from an order process of a CPU through a software order data receiving interface when a transaction order is initiated by software; the order data received by the hardware order data receiving module is message content data transmitted from a transaction strategy module through a hardware order data receiving interface when a transaction order is initiated by the DPU internally; and the transaction strategy module is configured to store order data. The UDP packet assembling module is configured to assemble and process the static data and the order data to obtain a UDP data packet when the order data is received. The sending module is configured to send the UDP data packet to a transaction network interface.

2. The system of claim 1, wherein, The software order data receiving module is configured to receive order data transmitted based on DMA through a software order data interface.

3. The system of claim 1, wherein, The hardware order data receiving module is configured to receive order data transmitted from a transaction strategy module through a hardware order data interface.

4. The system of claim 1, wherein, The arbitration module is specifically configured to read order data from a first-in-first-out queue of the hardware order data receiving module and transmit the order data to the UDP packet assembling module when the priority of the software order data receiving module is lower than the priority of the hardware order data receiving module.

5. The system of claim 1, wherein, The arbitration module is specifically configured to read order data from a first-in-first-out queue of the software order data receiving module and transmit the order data to the UDP packet assembling module when the priority of the software order data receiving module is higher than the priority of the hardware order data receiving module.

6. The system of claim 1, wherein, The UDP packet assembling module is further configured to switch the working state of the UDP packet assembling module from an idle state to a start state when static data input of the initialization module is monitored.

7. The system of claim 6, wherein, The UDP packet assembling module is further configured to read order data from a first-in-first-out queue of the arbitration module, assemble and process the static data and the order data to obtain a UDP data packet when the working state of the UDP packet assembling module is in the start state and the first-in-first-out queue of the arbitration module is monitored to be non-empty. When it is monitored that the first-in first-out queue of the arbitration module is empty, if it is monitored that the initialization module has end information input, the working state of the UDP packet module is switched from the start state to the idle state.

8. A method for DPU-based UDP order sheet, characterized in that, The application relates to a DPU-based UDP order method. initializing configuration of received static data; The static data is used for representing head information of a current transaction order; the initialization configuration is that when the initialization module issues initialization configuration information, the initialization configuration information is buffered in an on-chip RAM of the initialization module, and the working state of the UDP packet module is switched from the idle state to the start state; According to a transmission priority, order data received through a software order data interface and order data received through a hardware order data interface are sequentially transmitted; wherein the order data received by the software order data receiving module is that when a transaction order is initiated by software, order content data transmitted based on DMA from an order process of a CPU is received through a software order data receiving interface; the order data received by the hardware order data receiving module is that when a transaction order is initiated internally by a DPU, message content data sent from a transaction strategy module is received through a hardware order data receiving interface; the transaction strategy module is used for storing order data; When the order data is received, the static data and the order data are packetized to obtain a UDP data packet; The UDP data packet is sent to a transaction network interface. 9.An electronic device comprising a memory and a processor, the memory storing a computer program, wherein, The processor executes the computer program to realize the DPU-based UDP order method in claim 8.

10. A computer-readable storage medium, characterized in that, The computer program is stored on the processor and is executed by the processor to realize the DPU-based UDP order method in claim 8.

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