Resolution switching control method and device suitable for encoder

Abstract

The invention discloses a resolution switching control method and device suitable for an encoder, and relates to the field of video format conversion in airborne avionics display.The resolution switching control method suitable for the encoder comprises the steps that soft core work is executed on the resolution switching device, and a peripheral communication interface of the resolution switching device is initialized; establishing communication connection between the communication interface and the video decoding chip, and performing initialization configuration on the video decoding chip; and monitoring connection information between the video decoding chip and the video source signal, and if it is monitored that the video decoding chip is correctly connected with the video source signal and the video resolution is changed, configuring the resolution signal and the locking signal. The method supports the real-time conversion of the three-channel HDMI video source into the ARINC818 format, and is suitable for the application scene in which the format conversion of video sources with different resolutions needs to be carried out in the field of airborne avionics display.

Description

Technical Field

[0001] The present invention relates to the field of video format conversion in airborne avionics display, and in particular to a resolution switching control method and device suitable for an encoder. Background Art

[0002] In airborne applications, the input video is usually a video source that complies with the VESA display protocol standard. In actual application design, it is usually necessary to convert it into a common airborne video protocol such as ARINC818 optical fiber to achieve video transmission through optical fiber. However, the method of relying on logic to judge the change of video resolution and lock status is prone to misjudgment, resulting in reduced system reliability. In addition, the use of FPGA for logic development alone fails to fully utilize the development convenience and control advantages of SOC, making the logic more complex when the resolution changes, and increasing the difficulty of engineering implementation.

[0003] For example, Chinese patent CN116233349A discloses a 4K video data conversion system and method between ARINC818 and HDMI. The video data conversion system performs codec conversion of HDMI video through a dedicated HDMI Video PHY, and stores data through an integrated DDR controller and an off-chip cache. However, the real-time performance of the video data conversion system is reduced under the ARINC818 protocol, and the video resolution is fixed. In addition, there is a lack of judgment conditions for video stability in the video data conversion system.

[0004] Currently, no effective solution has been proposed for the problems in the related technologies. Summary of the invention

[0005] In view of the problems in the related art, the present invention proposes a resolution switching control method and device suitable for an encoder to overcome the above technical problems existing in the existing related art.

[0006] To this end, the specific technical solution adopted by the present invention is as follows:

[0007] According to one aspect of the present invention, a resolution switching control method applicable to an encoder is provided, and the resolution switching control method applicable to the encoder comprises:

[0008] S1, using the soft core processor built into the field programmable gate array to perform soft core work on the resolution switching device and initialize the communication interface of the peripherals of the resolution switching device;

[0009] S2, establishing a communication connection between the communication interface and the video decoding chip, and initializing the configuration of the video decoding chip to obtain an initialization configuration result;

[0010] S3, based on the initialization configuration result, monitoring the connection information between the video decoding chip and the video source signal, if it is monitored that the video decoding chip and the video source signal are correctly connected and the video resolution changes, configuring the resolution signal and the lock signal;

[0011] S4. After the resolution signal and the lock signal are configured, the video width conversion module, the on-chip buffer module and the encoding module are reset in sequence and step S3 is repeated to achieve resolution switching control when the video resolution changes.

[0012] Further, a communication connection is established between the communication interface and the video decoding chip, and the video decoding chip is initialized and configured, and the initialization configuration result includes:

[0013] S21, establishing a communication connection between the communication interface of the peripheral device of the resolution switching device and the video decoding chip, and initializing the configuration of the video decoding chip;

[0014] S22. If the initialization configuration is unsuccessful, the video decoding chip is reset and step S21 is re-executed. If the communication interface and the video decoding chip still cannot establish a communication connection within the preset parameter number of times, a fault instruction is sent and the initialization configuration is exited; if the initialization configuration is successful, step S3 is executed.

[0015] Further, based on the initialization configuration result, the connection information between the video decoding chip and the video source signal is monitored. If it is detected that the video decoding chip and the video source signal are correctly connected and the video resolution changes, the resolution signal and the lock signal are configured, including:

[0016] S31, based on the initialization configuration result, initialize the configuration resolution signal and the lock signal, read the connection information between the video decoding chip and the video source signal, and cyclically determine whether there is a video source signal input;

[0017] S32, if there is no video source signal input, then return to step S31 until a video source signal input is detected; if there is a video source signal input, then execute step S33;

[0018] S33, respectively configuring a locking signal and a resolution signal, and adjusting the locking signal based on a connection change state between the video decoding chip and the video source signal.

[0019] Further, respectively configuring a lock signal and a resolution signal, and adjusting the lock signal based on a connection change state between the video decoding chip and the video source signal includes:

[0020] S331, configuring the locking signal parameters, and configuring the resolution signal based on the video resolution of the input video source signal, and combining the configuration result of the resolution signal, cyclically determining whether the connection between the video decoding chip and the video source signal is stable and whether the video resolution has changed;

[0021] S332: If the connection between the video decoding chip and the video source signal is stable and the video resolution changes, the loop is exited and step S333 is executed; otherwise, step S331 is repeated;

[0022] S333: Adjust the locking signal parameters, and use the reset control state module to start the reset state machine according to the adjusted locking signal parameters.

[0023] Furthermore, the lock signal parameter includes 0 and 1; when the lock signal parameter is 1, it indicates that the video source signal is locked; when the lock signal parameter is 0, it indicates that the video source signal is not locked.

[0024] Furthermore, the video decoding chip is a MS7200 video decoding chip, and the video decoding chip is used to convert the data format of the video source signal into an RGB24bit data format.

[0025] Furthermore, the soft-core processor built into the field programmable gate array is used to execute the soft-core work of the resolution switching device in an independent operation mode, and the resolution switching device is configured to interact with the field programmable gate array through the communication interface and bus protocol of the peripheral.

[0026] According to another aspect of the present invention, there is also provided a resolution switching control device applicable to an encoder, the resolution switching control device comprising a video decoding chip, a video bit width conversion module, an on-chip cache module, a soft core processing module, a reset control state module, an encoding module, a serial transceiver module and an optoelectronic conversion module;

[0027] Video decoding chip, used to convert the data format of the video source signal;

[0028] A video bit width conversion module, used for converting the data bit width of the video source signal;

[0029] On-chip buffer module for buffering video source signals;

[0030] Soft core processing module, used to realize the driver configuration, information interaction and resolution switching mechanism control of the video decoding chip;

[0031] A reset control state module is used to receive the resolution signal and the lock signal sent by the soft core processing module to realize the reset control of the video transmission channel during the switching process;

[0032] An encoding module, used for encoding the video source signal into a data message that meets the protocol requirements;

[0033] The serial transceiver module is used to receive the data message sent by the encoding module and complete the serial-to-parallel conversion;

[0034] The photoelectric conversion module is used to transmit the data message after the serial-to-parallel conversion.

[0035] Furthermore, the video bit width conversion module converts the data bit width of the video source signal into a 32-bit data bit width.

[0036] Furthermore, the on-chip cache module is composed of a queue data structure for caching video source signals, and the cache capacity is 512*32 bits.

[0037] The beneficial effects of the present invention are:

[0038] 1. The present invention can realize adaptive switching of ARINC818 encoding when the resolution of the input video source changes, and supports the control functions of various common airborne video sources after resolution switching. At the same time, the resolution switching control device provided by the present invention supports real-time conversion of three-channel HDMI video sources into ARINC818 format, which is suitable for application scenarios in the field of airborne avionics display that require format conversion of video sources with different resolutions.

[0039] 2. The present invention has the function of automatically converting video formats of different resolutions into ARINC818 encoding, and the resolution switching control device provided by the present invention supports the format conversion of three-way HDMI video sources into three-way ARINC818 fiber optic video, has a resolution switching control function, can support the resolution switching of common airborne video sources, and also has a self-detection function, and reports self-detection information through the serial port, thereby improving the monitorability and stability of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0041] Figure 1 is a flow chart of a resolution switching control method applicable to an encoder according to an embodiment of the present invention;

[0042] Figure 2 A schematic structural diagram of a resolution switching control device applicable to an encoder according to an embodiment of the present invention;

[0043] Figure 3 A principle block diagram of a resolution switching control device applicable to an encoder according to an embodiment of the present invention;

[0044] Figure 4 A diagram of an FPGA design architecture in a resolution switching control device suitable for an encoder according to an embodiment of the present invention.

[0045] In the figure:

[0046] 1. Video decoding chip; 2. Video bit width conversion module; 3. On-chip cache module; 4. Soft core processing module; 5. Reset control state module; 6. Encoding module; 7. Serial transceiver module; 8. Photoelectric conversion module. DETAILED DESCRIPTION

[0047] To further illustrate each embodiment, the present invention provides drawings, which are part of the disclosure of the present invention and are mainly used to illustrate the embodiments. They can be used in conjunction with the relevant descriptions in the specification to explain the operating principles of the embodiments. With reference to these contents, ordinary technicians in this field should be able to understand other possible implementation methods and advantages of the present invention.

[0048] According to an embodiment of the present invention, a resolution switching control method and device applicable to an encoder are provided.

[0049] The present invention will now be further described with reference to the accompanying drawings and specific embodiments. Figure 1 As shown, according to an embodiment of the present invention, a resolution switching control method applicable to an encoder includes:

[0050] S1. Utilize the soft-core processor built into the field programmable gate array to perform soft-core work on the resolution switching device and initialize the communication interface of the peripherals of the resolution switching device.

[0051] The soft core processor built into the field programmable gate array is used to perform the soft core work of the resolution switching device in an independent operation mode, and the resolution switching device is configured and interacted with the field programmable gate array through the communication interface and bus protocol of the peripheral.

[0052] S2. Establish a communication connection between the communication interface and the video decoding chip 1, and initialize the configuration of the video decoding chip 1 to obtain an initialization configuration result.

[0053] The video decoding chip 1 is a MS7200 video decoding chip, and the video decoding chip 1 is used to convert the data format of the video source signal into an RGB 24-bit data format.

[0054] Wherein, a communication connection is established between the communication interface and the video decoding chip 1, and the video decoding chip 1 is initialized and configured, and the initialization configuration result is obtained, including:

[0055] S21, establishing a communication connection between the communication interface of the peripheral device of the resolution switching device and the video decoding chip 1, and initializing the configuration of the video decoding chip 1;

[0056] S22. If the initialization configuration is unsuccessful, the video decoding chip 1 is reset and step S21 is re-executed. If the communication interface still cannot establish a communication connection with the video decoding chip 1 within the preset parameter number of times, a fault instruction is sent and the initialization configuration is exited; if the initialization configuration is successful, step S3 is executed.

[0057] S3. Based on the initialization configuration result, monitor the connection information between the video decoding chip 1 and the video source signal. If it is detected that the video decoding chip 1 and the video source signal are correctly connected and the video resolution changes, configure the resolution signal and the lock signal.

[0058] Wherein, based on the initialization configuration result, the connection information between the video decoding chip 1 and the video source signal is monitored, and if it is monitored that the video decoding chip 1 and the video source signal are correctly connected and the video resolution changes, the resolution signal and the lock signal are configured, including:

[0059] S31, based on the initialization configuration result, initialize the configuration resolution signal and the lock signal, read the connection information between the video decoding chip 1 and the video source signal, and cyclically determine whether there is a video source signal input;

[0060] S32, if there is no video source signal input, then return to step S31 until a video source signal input is detected; if there is a video source signal input, then execute step S33;

[0061] S33, respectively configuring a locking signal and a resolution signal, and adjusting the locking signal based on the connection change state between the video decoding chip 1 and the video source signal.

[0062] Wherein, respectively configuring the locking signal and the resolution signal, and adjusting the locking signal based on the connection change state between the video decoding chip 1 and the video source signal includes:

[0063] S331, configure the locking signal parameters, and configure the resolution signal based on the video resolution of the input video source signal, and combine the configuration result of the resolution signal to cyclically determine whether the connection between the video decoding chip 1 and the video source signal is stable and whether the video resolution changes.

[0064] The lock signal parameter includes 0 and 1; when the lock signal parameter is 1, it indicates that the video source signal is locked; when the lock signal parameter is 0, it indicates that the video source signal is not locked.

[0065] S332: If the connection between the video decoding chip 1 and the video source signal is stable and the video resolution changes, the loop is exited and step S333 is executed; otherwise, step S331 is repeated;

[0066] S333, adjusting the locking signal parameters, and using the reset control state module 5 to start the reset state machine according to the adjusted locking signal parameters.

[0067] S4. After the resolution signal and the lock signal are configured, the video width conversion module 2, the on-chip buffer module 3 and the encoding module 6 are reset in sequence and step S3 is repeated to achieve resolution switching control when the video resolution changes.

[0068] It should be noted that the present invention is mainly used in the field of airborne optoelectronic video format conversion, and when it comes to different resolution image inputs, it is necessary to ensure reliable switching and use the original output channel for transmission. The usual method is to use FPGA (Field-Programmable Gate Array) to match the resolution of input and output videos. Using logic development alone has disadvantages in resolution switching control process design and development difficulty.

[0069] The present invention uses MB soft core (MB soft core is an embedded soft core, equivalent to the soft core processing module 4 in the present invention) instantiated on FPGA to realize SOC (System on Chip) architecture, making full use of the technical advantages of software development to design a reliable switching control process when the resolution changes. The soft core works in Standalone mode, and the peripherals are configured with I2C communication interface and serial port, and configure and interact with FPGA through Axi-lite bus (Axi-lite bus is a lightweight bus protocol).

[0070] It should be noted that the specific implementation diagram of the resolution switching control method applicable to the encoder provided by the present invention is as follows Figure 2 As shown, including:

[0071] 1) After the device is powered on, the soft core starts and initializes the peripheral interfaces.

[0072] 2) Use the I2C interface to communicate with the video decoding chip 1 and perform initialization configuration operations.

[0073] 3) Determine whether the initialization work is successful. If it is unsuccessful, reset the video decoding chip 1 and reconnect the I2C communication. If the connection fails after five times, report the failure and exit. If the mode signal (equivalent to the resolution signal in the present invention) and the lock signal (equivalent to the lock signal in the present invention) on the logic side are successfully configured through the Axi-lite interface.

[0074] The mode signal is the definition of video resolution. Different encodings correspond to different video formats. The current definition is 2 bits, where 2'b 00 represents 1920*1080@60; 2'b 01 represents 1920*1080@30; 2'b 10 represents 1280*1024@60; and 2'b 11 represents 1280*1024@30. It can be expanded according to specific applications.

[0075] The lock signal is a 1-bit signal. A lock signal of 0 indicates that the video source signal is unlocked, and a lock signal of 1 indicates that the video source signal is locked. The mode signal and the lock signal in the initialization state are represented as: mode=2'b 00, lock=0.

[0076] 4) Enter a loop to determine the working status of the video decoding chip 1 and the connection video source information until a stable source is input.

[0077] 5) Set the lock signal to 1 and configure the mode signal according to the actual resolution.

[0078] 6) Enter a loop to determine whether the current connection is stable and continuous, and exit the loop state when the video lock information or resolution changes.

[0079] 7) Configure the lock signal to 0, and the logic reset state machine starts the reset state machine according to the lock state change.

[0080] 8) Initialize and reset the video bit width conversion module 2, the on-chip buffer module 3 and the encoding module 6, and then return to step 4) to perform a loop judgment.

[0081] like Figure 3 As shown, according to another embodiment of the present invention, a resolution switching control device suitable for an encoder is further provided, the resolution switching control device comprising a video decoding chip 1, a video bit width conversion module 2, an on-chip cache module 3, a soft core processing module 4, a reset control state module 5, an encoding module 6, a serial transceiver module 7 and an optoelectronic conversion module 8;

[0082] Video decoding chip 1, used for converting the data format of the video source signal;

[0083] The video bit width conversion module 2 is used to convert the data bit width of the video source signal;

[0084] On-chip cache module 3, used for caching video source signals;

[0085] The soft core processing module 4 is used to realize the drive configuration, information interaction and resolution switching mechanism control of the video decoding chip 1;

[0086] The reset control state module 5 is used to receive the resolution signal and the lock signal sent by the soft core processing module 4 to realize the reset control of the video transmission channel during the switching process;

[0087] Coding module 6, used for encoding the video source signal into a data message that meets the protocol requirements;

[0088] The serial transceiver module 7 is used to receive the data message sent by the encoding module 6 and complete the serial-to-parallel conversion;

[0089] The photoelectric conversion module 8 is used to transmit the data message after the serial-to-parallel conversion.

[0090] The video bit width conversion module 2 is used to convert the data bit width of the video source signal into a 32-bit data bit width.

[0091] The on-chip cache module 3 is composed of a queue data structure, which is used to cache the video source signal, and the cache capacity is 512*32 bits.

[0092] It should be noted that the resolution switching control device for encoders provided by the present invention is mainly composed of a video decoding chip 1, a soft core processing module 4, a photoelectric conversion module 8 and the like. The hardware design supports three independent ARINC818 resolution switching codes, which cooperates with the FPGA design architecture in the resolution switching control method for encoders provided by the present invention as shown in FIG. Figure 4 shown.

[0093] The video decoding chip 1 is implemented using a hardware video decoding chip, including but not limited to the MS7200 video decoding chip in the resolution switching control device provided by the present invention. This type of chip generally has the function of converting video source data into a VESA (Video Electronics Standards Association) display standard RGB24bit data format, and supports external chip configuration and status information reading.

[0094] The SOC architecture is implemented using the FPGA logic device model JFM7K325T. The architecture design is as follows Figure 4 As shown, the MB soft core is used as the soft core processing module 4, and uses the I2C communication interface to implement the drive configuration, information interaction and resolution reliable switching mechanism control of the video decoding chip 1, which is the software running platform of the SOC.

[0095] Each ARINC818 encoding channel includes a 24-bit / 32-bit video bit width conversion module 2, which is connected to the video decoding chip 1, converts the input image data from 24 bits to 32 bits of data bit width and stores it in the on-chip cache module 3;

[0096] The on-chip cache module 3 is mainly composed of a fifo (First In, First Out, i.e., first in, first out, fifo is a data structure used to output data in the order of input), which realizes the temporary cache of video input data, and the size is 512*32bit;

[0097] The reset control state module 5 is connected to the MB soft core (equivalent to the soft core processing module 4), receives the MODE signal and LOCK signal control of the soft core, and realizes the overall reset control of the video transmission channel during the switching process;

[0098] The encoding module 6 is responsible for encoding the video data into a data message that complies with the ARINC818 (ARINC818 is a protocol designed specifically for airborne video transmission, supporting high-speed, real-time video and image transmission) protocol requirements. The data message is transmitted to the GTX module (equivalent to the serial transceiver module 7) to complete the serial-to-parallel conversion and is transmitted through a standard optoelectronic conversion device (equivalent to the optoelectronic conversion module 8).

[0099] The present invention can realize adaptive switching of ARINC818 encoding when the resolution of the input video source changes, and supports the control functions of various common airborne video sources after resolution switching. At the same time, the resolution switching control device provided by the present invention supports real-time conversion of three-channel HDMI video sources into ARINC818 format (such as Figure 4 As shown, the video decoding chip 1 includes a video decoding chip 1, a video decoding chip 2 and a video decoding chip 3 respectively arranged on three channels; the video bit width conversion module 2 includes a video bit width conversion module 1, a video bit width conversion module 2 and a video bit width conversion module 3 respectively arranged on three channels; the on-chip cache module 3 includes an on-chip cache module 1, an on-chip cache module 2 and an on-chip cache module 3 respectively arranged on three channels; the reset control state module 5 includes a reset control state machine module 1, a reset control state machine module 2 and a reset control state machine module 3 respectively arranged on three channels; the encoding module 6 includes an encoding module 1, an encoding module 2 and an encoding module 3 respectively arranged on three channels; the photoelectric conversion module 8 includes a photoelectric conversion module 1, a photoelectric conversion module 2 and a photoelectric conversion module 3 respectively arranged on three channels; GTX1 is equivalent to the serial transceiver module 7; the MB soft core is an embedded soft core, which is equivalent to the soft core processing module 4) and is suitable for application scenarios in the field of airborne avionics display that require conversion of video source formats of different resolutions.

[0100] It should be noted that the resolution switching control method suitable for the encoder provided by the present invention realizes resolution switching control and configures rate parameters to the ARINC818 encoder through SOC control on the FPGA when the input video resolution changes. This method can realize the video format conversion function of multiple interfaces by replacing different video decoding chips, and expand the number of conversion channels by multiplexing logic modules.

[0101] The resolution switching control method is applied to a resolution switching control device that converts HDMI (High-Definition Multimedia Interface) video source into ARINC818 protocol encoding. The design currently only supports three channels of HDMI video source. The logic design has modular characteristics and can expand more ARINC818 conversion channels to adapt to larger-scale ARINC818 video encoding needs.

[0102] Specifically, the resolution switching control device provided by the present invention is uniformly powered by a connector, has three HDMI video inputs, and is connected to a serial port; the resolution switching control device is a single-board module, which physically includes only one PCB board, and its structural size is as follows: Figure 2 As shown; the resolution switching control device can be installed in an application scenario where the HDMI video format needs to be converted into an ARINC818 format output.

[0103] In summary, with the help of the above technical solution of the present invention, the present invention can realize the adaptive switching of ARINC818 encoding when the resolution of the input video source changes, and support the control function of various common airborne video sources after resolution switching. At the same time, the resolution switching control device provided by the present invention supports the real-time conversion of three-channel HDMI video source to ARINC818 format, which is suitable for application scenarios in the field of airborne avionics display that require format conversion of video sources with different resolutions; the present invention has the function of automatically converting video formats with different resolutions into ARINC818 encoding, and the resolution switching control device provided by the present invention supports the format conversion of three-channel HDMI video sources into three-channel ARINC818 fiber optic videos, has a resolution switching control function, can support the resolution switching of common airborne video sources, and also has a self-detection function, and reports self-detection information through the serial port, thereby improving the monitorability and stability of the system.

[0104] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims

1. A resolution switching control method applicable to an encoder, characterized in that: The resolution switching control method applicable to the encoder includes: S1, using the soft core processor built into the field programmable gate array to perform soft core work on the resolution switching device and initialize the communication interface of the peripherals of the resolution switching device; S2, establishing a communication connection between the communication interface and the video decoding chip, and initializing the configuration of the video decoding chip to obtain an initialization configuration result; S3, based on the initialization configuration result, monitoring the connection information between the video decoding chip and the video source signal, if it is monitored that the video decoding chip and the video source signal are correctly connected and the video resolution changes, configuring the resolution signal and the lock signal; S4. After the resolution signal and the lock signal are configured, the video width conversion module, the on-chip buffer module and the encoding module are reset in sequence and step S3 is repeated to achieve resolution switching control when the video resolution changes.

2. A resolution switching control method applicable to an encoder according to claim 1, characterized in that: The establishing of the communication connection between the communication interface and the video decoding chip, and initializing the configuration of the video decoding chip to obtain the initialization configuration result includes: S21, establishing a communication connection between the communication interface of the peripheral device of the resolution switching device and the video decoding chip, and initializing the configuration of the video decoding chip; S22. If the initialization configuration is unsuccessful, the video decoding chip is reset and step S21 is re-executed. If the communication interface and the video decoding chip still cannot establish a communication connection within the preset parameter number of times, a fault instruction is sent and the initialization configuration is exited; if the initialization configuration is successful, step S3 is executed.

3. A resolution switching control method applicable to an encoder according to claim 1, characterized in that: The monitoring of the connection information between the video decoding chip and the video source signal based on the initialization configuration result, if it is monitored that the video decoding chip and the video source signal are correctly connected and the video resolution changes, configuring the resolution signal and the lock signal includes: S31, based on the initialization configuration result, initialize the configuration resolution signal and the lock signal, read the connection information between the video decoding chip and the video source signal, and cyclically determine whether there is a video source signal input; S32, if there is no video source signal input, then return to step S31 until a video source signal input is detected; if there is a video source signal input, then execute step S33; S33, respectively configuring a locking signal and a resolution signal, and adjusting the locking signal based on a connection change state between the video decoding chip and the video source signal.

4. A resolution switching control method applicable to an encoder according to claim 3, characterized in that: The configuring of the locking signal and the resolution signal respectively and adjusting the locking signal based on the connection change state between the video decoding chip and the video source signal comprises: S331, configuring the locking signal parameters, and configuring the resolution signal based on the video resolution of the input video source signal, and combining the configuration result of the resolution signal, cyclically determining whether the connection between the video decoding chip and the video source signal is stable and whether the video resolution has changed; S332: If the connection between the video decoding chip and the video source signal is stable and the video resolution changes, the loop is exited and step S333 is executed; otherwise, step S331 is repeated; S333: Adjust the locking signal parameters, and use the reset control state module to start the reset state machine according to the adjusted locking signal parameters.

5. A resolution switching control method applicable to an encoder according to claim 4, characterized in that: The locking signal parameter includes 0 and 1; when the locking signal parameter is 1, it indicates that the video source signal is locked; when the locking signal parameter is 0, it indicates that the video source signal is not locked.

6. A resolution switching control method applicable to an encoder according to claim 1, characterized in that: The video decoding chip is a MS7200 video decoding chip, and the video decoding chip is used to convert the data format of the video source signal into an RGB24bit data format.

7. A resolution switching control method applicable to an encoder according to claim 1, characterized in that: The soft core processor built into the field programmable gate array is used to perform the soft core work of the resolution switching device in an independent operation mode, and the resolution switching device is configured and interacted with the field programmable gate array through the communication interface and bus protocol of the peripheral.

8. A resolution switching control device applicable to an encoder, used to implement the resolution switching control of the resolution switching control method applicable to an encoder according to any one of claims 1 to 7, characterized in that: The resolution switching control device includes a video decoding chip, a video bit width conversion module, an on-chip cache module, a soft core processing module, a reset control state module, an encoding module, a serial transceiver module and a photoelectric conversion module; The video decoding chip is used to convert the data format of the video source signal; The video bit width conversion module is used to convert the data bit width of the video source signal; The on-chip buffer module is used to buffer the video source signal; The soft core processing module is used to implement the drive configuration, information interaction and resolution switching mechanism control of the video decoding chip; The reset control state module is used to receive the resolution signal and the lock signal sent by the soft core processing module to realize the reset control of the video transmission channel during the switching process; An encoding module, used for encoding the video source signal into a data message that meets the protocol requirements; The serial transceiver module is used to receive the data message sent by the encoding module and complete the serial-to-parallel conversion; The photoelectric conversion module is used to transmit the data message after the serial-to-parallel conversion.

9. A resolution switching control device suitable for an encoder according to claim 8, characterized in that: The video bit width conversion module converts the data bit width of the video source signal into a 32-bit data bit width.

10. A resolution switching control device suitable for an encoder according to claim 9, characterized in that: The on-chip buffer module is composed of a queue data structure, which is used to buffer the video source signal, and the buffer capacity is 512*32bit.

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