Semiconductor memory device

Abstract

A semiconductor memory device is provided. The semiconductor device includes: a word line extending in a lateral direction; a sensing line separated from the word line, the sensing line overlapping the word line in a vertical direction and extending in a lateral direction; a vertical semiconductor structure passing through the word line and the sense line in a vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in a lateral direction; and a gate dielectric film between the vertical channel region and the word line. The vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type sequentially provided in a vertical direction.

Description

Background Art

[0001] The present disclosure relates to a semiconductor memory device, and more particularly, to a semiconductor memory device including a plurality of memory cells arranged three-dimensionally.

[0002] Due to the latest developments in electronic technology, the shrinking of semiconductor devices has been rapidly developed. Therefore, the miniaturization of memory cells is required, and current memory cells have limitations in maintaining high integration and reliability. Therefore, it is necessary to develop a semiconductor memory device with a structure having smaller memory cells and increased memory cell integration density. Summary of the invention

[0003] One or more embodiments provide a semiconductor memory device having a structure that facilitates scaling down of memory cells and increases integration density of memory cells.

[0004] According to one aspect of the embodiment, a semiconductor memory device includes: a word line extending in a lateral direction; a sensing line separated from the word line, the sensing line overlapping the word line in a vertical direction and extending in a lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in a vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in a lateral direction; and a gate dielectric film between the vertical channel region and the word line. The vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type sequentially provided in a vertical direction. The vertical channel region includes the first lightly doped film or the second lightly doped film. The sensing line contacts the first heavily doped film of the vertical semiconductor structure.

[0005] According to another aspect of the embodiment, a semiconductor memory device includes a memory cell string, which includes a plurality of memory cells arranged in a row in a vertical direction. Each of the plurality of memory cells includes: a word line extending in a lateral direction; a sensing line separated from the word line, the sensing line overlapping the word line in a vertical direction and extending in a lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in a vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in a lateral direction; and a gate dielectric film between the vertical channel region and the word line. In each of the plurality of memory cells, the vertical semiconductor structure includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of a first conductivity type, and a second heavily doped film of a second conductivity type sequentially provided in a vertical direction. The vertical channel region includes the first lightly doped film or the second lightly doped film in each of the plurality of memory cells. The sensing line contacts the first heavily doped film of the vertical semiconductor structure in each of the plurality of memory cells.

[0006] According to another aspect of the embodiment, a semiconductor memory device includes: a memory cell array, the memory cell array includes a plurality of memory cells arranged three-dimensionally and repeatedly on a substrate in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction intersects the second lateral direction, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction. The memory cell array includes: a plurality of sensing lines and a plurality of word lines arranged alternately one after another in the vertical direction, the plurality of sensing lines and the plurality of word lines being separated from each other in the vertical direction; a plurality of insulating films, respectively located between the plurality of sensing lines and the plurality of word lines; a stacked structure, passing through the plurality of sensing lines, the plurality of word lines, and the plurality of insulating films in the vertical direction, the stacked structure including a plurality of vertical semiconductor structures overlapping each other in the vertical direction, each of the plurality of vertical semiconductor structures having a vertical channel region; an insulating column, passing through the plurality of vertical semiconductor structures in the vertical direction; a plurality of gate dielectric films, located between the corresponding vertical channel regions of the plurality of vertical semiconductor structures and the plurality of word lines; and a plurality of bit lines passing through the plurality of insulating films. Among the plurality of memory cells, the memory cells arranged in a row in the vertical direction share a selected bit line among the plurality of bit lines. Each of the plurality of vertical semiconductor structures includes a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type sequentially provided in a vertical direction. A vertical channel region of each of the plurality of vertical semiconductor structures includes the first lightly doped film or the second lightly doped film. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The above and other aspects and features will become more apparent through the following description of embodiments in conjunction with the accompanying drawings, in which:

[0008] Figure 1 is a plan layout diagram of some regions of a semiconductor memory device according to an embodiment;

[0009] Figure 2A is along Figure 1 A cross-sectional view taken along the line X1-X1';

[0010] Figure 2B is along Figure 1 A cross-sectional view taken along the line Y1-Y1';

[0011] Figure 2C yes Figure 2A An enlarged cross-sectional view of the "EX1" portion;

[0012] Figure 2D yes Figure 2B An enlarged cross-sectional view of the "EX2" portion;

[0013] Figure 3A , 3B, 3C and 3D are cross-sectional views of semiconductor memory devices according to embodiments;

[0014] Figure 3C yes Figure 3A An enlarged cross-sectional view of the "EX3" portion;

[0015] Figure 3D yes Figure 3B An enlarged cross-sectional view of the "EX4" portion;

[0016] Figure 4 is a cross-sectional view of a semiconductor memory device according to an embodiment;

[0017] Figure 5A is a partial cross-sectional perspective view of a memory cell included in a semiconductor memory device according to an embodiment;

[0018] Figure 5B yes Figure 5A An equivalent circuit diagram of the memory cell shown;

[0019] Figure 5C It is used to explain Figure 5A and 5B A graph of operating characteristics of a memory cell shown in ;

[0020] Fig. 6A is a partial cross-sectional perspective view of a memory cell included in a semiconductor memory device according to an embodiment;

[0021] Figure 6B yes Fig. 6A An equivalent circuit diagram of a memory cell shown in ;

[0022] Figure 6C It is used to explain Fig. 6A and 6B A graph of operating characteristics of a memory cell shown in ;

[0023] Figure 7 is a circuit diagram of a semiconductor memory device according to an embodiment;

[0024] Figure 8 Is has Figure 7 A timing diagram of a selected memory cell in a semiconductor memory device having the circuit configuration shown;

[0025] Fig. 9 is based on Figure 7 A perspective view of a semiconductor memory device in which the circuit configuration shown in is arranged in a 3×3×3 array;

[0026] Fig.10 is based on Figure 7 A side view of a semiconductor memory device in which the circuit configuration shown in is arranged in a 3×3×3 array;

[0027] Fig.11 is a circuit diagram of a semiconductor memory device according to an embodiment;

[0028] Fig.12 Is has Fig.11 A timing diagram of a selected memory cell in a semiconductor memory device having the circuit configuration shown; and

[0029] Figures 13A to 33B is a diagram of a method of manufacturing a semiconductor memory device according to an embodiment, wherein Fig.13A , 14A , 15A, 16, 17, 18A, 19A, 20, 21, 22A, 24A, 25A, 26A, 27A, 29, 30, 32A and 33A correspond to the Figure 1 A cross-sectional view of a portion of a cross section taken along line X1-X1' according to a process sequence, Fig. 13B , 14B , 15B, 18B, 19B, 22B, 23, 24B, 25B, 26B, 27B, 28, 31, 32B and 33B correspond to the Figure 1 A cross-sectional view of a portion of a cross section taken along line Y1-Y1' according to a process sequence, Fig. 18C yes Fig.18A An enlarged cross-sectional view of the "EXA" section in FIG. 1 , and Fig.19C yes Fig.19A An enlarged cross-sectional view of the “EXA” portion of FIG. DETAILED DESCRIPTION

[0030] Hereinafter, the embodiment will be described in detail with reference to the accompanying drawings.The embodiment described herein is an example embodiment, and therefore, the present disclosure is not limited thereto, and can be realized in various other forms.Each embodiment provided in the following description does not exclude the association with one or more features of another example or another embodiment that is also provided herein or is not provided herein but is consistent with the present disclosure.It should be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on another element or layer, directly connected or coupled to another element or layer, or there can be an intermediate element or layer.By contrast, when an element is referred to as being "directly on another element or layer", "directly connected to" or "directly coupled to" another element or layer, there is no intermediate element or layer.As used herein, the term "and / or" includes any and all combinations of one or more associated listed items.Expressions such as "at least one of ..." modify the entire element list when it is before the element list, rather than modifying the individual elements in the list. For example, the expression "at least one of a, b, and c" should be understood to include only a, only b, only c, both a and b, both a and c, both b and c, or all of a, b, and c. It should also be understood that even if a certain step or operation of manufacturing a device or structure is described later than another step or operation, the step or operation may be performed later than the other steps or operations unless the other steps or operations are described as being performed after the step or operation. The same reference numerals are used to represent the same elements in the drawings, and their repeated descriptions will be omitted.

[0031] Figure 1 and FIG. 2A to FIG. 2D is a diagram of a semiconductor memory device 100 according to an embodiment. Figure 1 is a plan layout diagram of some regions of the semiconductor memory device 100 . Figure 2A is along Figure 1 A cross-sectional view taken along line X1-X1'. Figure 2B is along Figure 1 A cross-sectional view taken along line Y1-Y1'. Figure 2C yes Figure 2A An enlarged cross-sectional view of the "EX1" portion of the PCB. Figure 2D yes Figure 2B An enlarged cross-sectional view of the “EX2” portion of the PCB.

[0032] refer to Figure 1 and FIG. 2A to FIG. 2D The semiconductor memory device 100 may include a substrate 102, a memory cell array unit MCA on the substrate 102, and a first connection unit AR1 and a second connection unit AR2, the first connection unit AR1 and the second connection unit AR2 being separated from each other on the substrate 102 and in a first lateral direction (X direction), and the memory cell array unit MCA being between the first connection unit AR1 and the second connection unit AR2.

[0033] The memory cell array unit MCA may include a plurality of memory cells MC, which are three-dimensionally and repeatedly arranged in a first lateral direction (X direction) and a second lateral direction (Y direction) that intersect and may be perpendicular to each other, and a vertical direction (Z direction) perpendicular to each of the first lateral direction (X direction) and the second lateral direction (Y direction).

[0034] The substrate 102 may include a semiconductor substrate including silicon (Si), germanium (Ge), or SiGe.

[0035] The memory cell array unit MCA may include a plurality of sensing lines SL and a plurality of word lines WL that are alternately arranged one by one in a vertical direction (Z direction) and separated from each other in the vertical direction (Z direction). A selected one of the plurality of insulating films 110A, 110B, and 110C may be located between a lowermost sensing line SL of the plurality of sensing lines SL and the substrate 102, and between each of the plurality of sensing lines SL and each of the plurality of word lines WL.

[0036] A plurality of stacked structures SST may be in the memory cell array unit MCA, each of the plurality of stacked structures SST including a plurality of vertical semiconductor structures VSS overlapping each other in the vertical direction (Z direction). Each of the plurality of vertical semiconductor structures VSS may pass through the word line WL, the sensing line SL, and the plurality of insulating films 110A, 110B, and 110C in the vertical direction (Z direction).

[0037] Each of the plurality of word lines WL and the plurality of sense lines SL may be planar and extend in a lateral direction (or a direction along an XY plane) parallel to the main surface 102M of the substrate 102. The plurality of word lines WL and the plurality of sense lines SL may overlap each other in a vertical direction (Z direction).

[0038] The plurality of word lines WL and the plurality of sensing lines SL may each include tungsten (W), aluminum (Al), molybdenum (Mo), ruthenium (Ru), cobalt (Co), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten nitride (WN), titanium silicon nitride (TiSiN), tungsten silicon nitride (WSiN), doped polysilicon, or a combination thereof, but are not limited thereto. Each of the plurality of insulating films (e.g., 110A, 110B, and 110C) may include a silicon oxide film, but is not limited thereto.

[0039] Each of the plurality of vertical semiconductor structures VSS may include a first heavily doped film HDS1, a first lightly doped film DS1, a second lightly doped film DS2, and a second heavily doped film HDS2, which are stacked sequentially in the vertical direction (Z direction) from a portion of the vertical semiconductor structure VSS closest to the substrate 102. In each of the plurality of vertical semiconductor structures VSS, the first heavily doped film HDS1 and the second lightly doped film DS2 may have a first conductivity type, and the first lightly doped film DS1 and the second heavily doped film HDS2 may have a second conductivity type opposite to the first conductivity type. As used herein, the terms "heavily doped" and "lightly doped" are relative terms. A heavily doped film refers to a film having a higher dopant concentration than a lightly doped film, and a lightly doped film refers to a film having a lower dopant concentration than a heavily doped film.

[0040] In an embodiment, in each of the plurality of vertical semiconductor structures VSS, the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second heavily doped film HDS2 may each include a doped silicon (Si) film, and the dopant concentration of each of the first heavily doped film HDS1 and the second heavily doped film HDS2 may be higher than the dopant concentration of each of the first lightly doped film DS1 and the second lightly doped film DS2. For example, the first heavily doped film HDS1 and the second lightly doped film DS2 may each include a polysilicon film doped with n-type impurities, and the dopant concentration of the n-type impurities in the first heavily doped film HDS1 may be higher than the dopant concentration of the n-type impurities in the second lightly doped film DS2. In addition, the first lightly doped film DS1 and the second heavily doped film HDS2 may each include a polysilicon film doped with p-type impurities, and the dopant concentration of the p-type impurities in the second heavily doped film HDS2 may be higher than the dopant concentration of the p-type impurities in the first lightly doped film DS1. In an embodiment, the n-type impurity may be selected from phosphorus (P), arsenic (As), and antimony (Sb), and the p-type impurity may be selected from boron (B) and gallium (Ga).

[0041] In an example, each of the dopant concentration of the n-type impurity in the first heavily doped film HDS1 and the dopant concentration of the p-type impurity in the second heavily doped film HDS2 may be about 1×10 19 Atom / cm 3 About 9×10 20 Atom / cm 3 , each of the dopant concentration of the p-type impurity in the first lightly doped film DS1 and the dopant concentration of the n-type impurity in the second lightly doped film DS2 may be within a range of about 1×10 17 Atom / cm 3 About 9×10 18 Atom / cm 3 The range of selection is, but not limited to.

[0042] Each of the plurality of vertical semiconductor structures VSS may include a vertical channel region, and the vertical channel region may include any one selected from the first lightly doped film DS1 and the second lightly doped film DS2 . Figures 2A to 2D A structure is shown in which the vertical channel region includes the second lightly doped film DS2 in each of the plurality of vertical semiconductor structures VSS. In each of the plurality of vertical semiconductor structures VSS, the second lightly doped film DS2 serving as the vertical channel region may face the word line WL in a lateral direction (or a direction along the XY plane) parallel to the main surface 102M of the substrate 102. The plurality of sensing lines SL may contact the first heavily doped films HDS1 of the plurality of vertical semiconductor structures VSS, respectively.

[0043] In other embodiments, FIG. 2A to FIG. 2D Unlike the illustrated embodiment, in each of the plurality of vertical semiconductor structures VSS, the vertical channel region may include a first lightly doped film DS1. In this case, each of the plurality of word lines WL may face the first lightly doped film DS1 of the vertical semiconductor structure VSS.

[0044] The gate dielectric film 130 may be formed in a vertical channel region (refer to FIG. 2A to FIG. 2D between the second lightly doped film DS2 in the vertical channel region and the word line WL adjacent to the vertical channel region. In an embodiment, the gate dielectric film 130 may include a paraelectric material. For example, the gate dielectric film 130 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof. In other embodiments, the gate dielectric film 130 may include a high-k dielectric material. The high-k dielectric material may have a dielectric constant of approximately 10 to approximately 25. For example, the high-k dielectric material may include hafnium oxide, aluminum oxide, zirconium oxide, or a combination thereof, but is not limited thereto. In other embodiments, the gate dielectric film 130 may include a combination of a paraelectric material and a high-k dielectric material.

[0045] The semiconductor memory device 100 may include an insulating pillar 124 that passes through a plurality of vertical semiconductor structures VSS arranged to overlap each other in the vertical direction (Z direction) in the vertical direction (Z direction). In each of the plurality of vertical semiconductor structures VSS, the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second heavily doped film HDS2 may have a hollow portion HH that accommodates the insulating pillar 124. Each of the plurality of vertical semiconductor structures VSS may have a tube shape surrounding the insulating pillar 124 and have a ring shape when viewed from above (on the XY plane).

[0046] like Figure 2B and 2DAs shown, the semiconductor memory device 100 may include a plurality of bit lines BL that pass through a plurality of insulating films 110B and 110C in a vertical direction (Z direction). The plurality of bit lines BL may be separated from the plurality of word lines WL and the plurality of sensing lines SL in a second lateral direction (Y direction). Each of the plurality of bit lines BL may be connected to the second heavily doped film HDS2 included in the vertical semiconductor structure VSS through a conductive connection structure CNS. The conductive connection structure CNS may contact the second heavily doped film HDS2 included in the vertical semiconductor structure VSS and surround the second heavily doped film HDS2. The plurality of bit lines BL and the plurality of conductive connection structures CNS connected to the plurality of bit lines BL may each include W, Al, Mo, Ru, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof, but are not limited thereto.

[0047] Each of the plurality of bit lines BL may extend long in the vertical direction (Z direction) and face the vertical semiconductor structure VSS in the second lateral direction (Y direction) with the plurality of word lines WL and the plurality of sensing lines SL located therebetween. In the semiconductor memory device 100, a plurality of memory cells MC arranged in a row in the vertical direction (Z direction) may constitute a memory cell string. A plurality of memory cells MC included in one memory cell string may share a selected one of the plurality of bit lines BL.

[0048] The semiconductor memory device 100 may include a plurality of inter-cell insulating films 118 and a plurality of inter-cell local insulating films 120. Each of the plurality of inter-cell insulating films 118 may be located between two adjacent memory cells among a plurality of memory cells MC arranged in a row in the vertical direction (Z direction). The plurality of inter-cell local insulating films 120 may be between an insulating pillar 124 and the inter-cell insulating film 118 and surround the insulating pillar 124. The inter-cell insulating film 118 and the inter-cell local insulating film 120 may constitute an inter-cell insulating structure between two memory cells MC adjacent to each other in the vertical direction (Z direction) to separate the two memory cells MC from each other.

[0049] In the memory cell array unit MCA, a portion of the buried insulating film 126 may cover the plurality of memory cells MC, the plurality of insulating pillars 124, the uppermost one of the inter-cell insulating films 118, and the plurality of inter-cell local insulating films 120. Figure 2A As shown, in the first and second connection units AR1 and AR2, another portion of the buried insulating film 126 may contact an end portion of each of the plurality of word lines WL and the plurality of sensing lines SL in the first lateral direction (X direction).

[0050] like Figure 1 and 2BAs shown, the semiconductor memory device 100 may include a plurality of isolation insulating films 140. Each of the plurality of isolation insulating films 140 may have a strip-shaped plane shape extending long in a first lateral direction (X direction) in a memory cell array unit MCA. Each of the plurality of isolation insulating films 140 may be located between two adjacent memory cell strings in a plurality of memory cell strings arranged in a row in a second lateral direction (Y direction). The plurality of isolation insulating films 140 may pass through the plurality of insulating films 110A, 110B, and 110C, the plurality of inter-cell insulating films 118, and the buried insulating film 126 in a vertical direction (Z direction). Each of the plurality of isolation insulating films 140 may contact a plurality of word lines WL and a plurality of sensing lines SL included in a memory cell string adjacent to the isolation insulating film 140 on one side of the second lateral direction (Y direction).

[0051] The plurality of insulating pillars 124 , the plurality of inter-cell insulating films 118 , the plurality of inter-cell local insulating films 120 , the buried insulating film 126 , and the plurality of isolation insulating films 140 may each include a silicon oxide film, but are not limited thereto.

[0052] like Figure 2A As shown, in the first connection unit AR1 and the second connection unit AR2, a plurality of word lines WL and a plurality of sensing lines SL may extend in a first lateral direction (X direction) with varying lengths. Therefore, in the first connection unit AR1 and the second connection unit AR2, a plurality of step units including a plurality of word lines WL and a plurality of sensing lines SL may be formed. In the first connection unit AR1 and the second connection unit AR2, a space defined by a plurality of step units may be filled with a mold insulating film 119. The mold insulating film 119 may include a silicon oxide film.

[0053] A plurality of word line contacts WLC may be in the first connection unit AR1. Each of the plurality of word line contacts WLC may be separated from the vertical semiconductor structure VSS of the memory cell MC in a first lateral direction (X direction) and connected to a selected one of the plurality of word lines WL.

[0054] A plurality of sensing line contacts SLC may be in the second connection unit AR2. Each of the plurality of sensing line contacts SLC may be separated from the vertical semiconductor structure VSS of the memory cell MC in the first lateral direction (X direction) and connected to a selected one of the plurality of sensing lines SL.

[0055] The plurality of word line contacts WLC and the plurality of sensing line contacts SLC may each pass through the insulating structure including the buried insulating film 126 and the mold insulating film 119 in the vertical direction (Z direction). The plurality of word line contacts WLC and the plurality of sensing line contacts SLC may each include W, Al, Mo, Ru, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof, but are not limited thereto.

[0056] A related DRAM device may have a structure in which one memory cell includes one transistor and one capacitor (i.e., a 1T-1C structure). As the related DRAM device becomes more highly integrated, the number of capacitors may increase, which may result in an increase in leakage current. The increase in leakage current may affect data reliability. Therefore, the capacitor may become an obstacle to scaling down using a vertical stacking structure.

[0057] By using a positive feedback loop, a memory device based on a feedback field effect transistor (FBFET) can have a low operating voltage and a sharp subthreshold swing (SS) of less than 60mV / decade. Unlike related DRAM devices, a memory device based on an FBFET has the advantage of low power consumption because a refresh operation is not required. In addition, a semiconductor memory device based on an FBFET can have a wide current sensing margin due to a high on-off current ratio, and has the advantage of ensuring compatibility with current processes for manufacturing complementary metal oxide semiconductor (CMOS) transistors.

[0058] In the plurality of vertical semiconductor structures VSS included in the semiconductor memory device 100 according to the embodiment, the first heavily doped film HDS1 may include an n-type dopant doped therein. + doped regions, the first lightly doped film DS1 may include a p-doped region doped with a p-type dopant, the second lightly doped film DS2 may include an n-doped region doped with an n-type dopant, and the second heavily doped film HDS2 may include a p-doped region doped with a p-type dopant. + The n-type dopant may be selected from P, As and Sb. The p-type dopant may be selected from B and Ga.

[0059] In an embodiment, in each of the plurality of vertical semiconductor structures VSS, the second lightly doped film DS2 including an n-doped region may be used as a vertical channel region. In this case, the word line WL may face the second lightly doped film DS2 including an n-doped region in a lateral direction with the gate dielectric film 130 therebetween. The memory cell MC may constitute a p-FBFET-based DRAM cell that does not include a capacitor but includes one transistor.

[0060] In other embodiments, in each of the plurality of vertical semiconductor structures VSS, the first lightly doped film DS1 including a p-doped region may be used as a vertical channel region. In this case, the word line WL may face the first lightly doped film DS1 including a p-doped region in a lateral direction with the gate dielectric film 130 therebetween. The memory cell MC may constitute a DRAM cell based on an n-FBFET, which does not include a capacitor but includes one transistor.

[0061] As described above, the semiconductor memory device 100 according to the embodiment can be implemented as a p-FBFET-based DRAM cell or an n-FBFET-based DRAM cell and is compatible with the current process of manufacturing CMOS transistors. In addition, by using an FBFET-based memory cell that does not require a capacitor as a DRAM cell with one transistor, a structure that is conducive to high integration can be provided.

[0062] In addition, because each of the plurality of memory cells MC includes a transistor and does not include a capacitor, the semiconductor memory device 100 according to the embodiment can be miniaturized to provide a high-density, compact three-dimensional (3D) array structure. In addition, in the semiconductor memory device 100 according to the embodiment, the plurality of memory cells MC overlapping each other in the vertical direction (Z direction) can include a 3D stacked memory cell array sharing a bit line BL. Therefore, the semiconductor memory device 100 according to the embodiment can overcome the problems caused by the density limitation of the bit line encountered in a semiconductor memory device having a two-dimensional (2D) structure, provide a structure that is conducive to the high integration of the semiconductor memory device, and provide excellent competitiveness in various aspects including performance, power, chip area and cost.

[0063] Figures 3A to 3D 2 is a diagram of a semiconductor memory device 200 according to an embodiment. Specifically, Figure 3A is corresponding to along Figure 1 A cross-sectional view of a portion of a cross section taken along line X1-X1'. Figure 3B is corresponding to along Figure 1 A cross-sectional view of a portion of a cross section taken along line Y1-Y1'. Figure 3C yes Figure 3A An enlarged cross-sectional view of the “EX3” portion of the PCB. Figure 3D yes Figure 3B The semiconductor memory device 200 may basically have the same Figure 1 The floor plan is the same as the floor plan shown. FIG. 3A to FIG. 3D In the drawings, the same reference numerals are used to denote Figure 1 and FIG. 2A to FIG. 2D The same figure numbers are used in the drawings, and their detailed descriptions are omitted here.

[0064] refer to Figures 3A to 3D , the semiconductor memory device 300 may basically have the same Figure 1 and 2A The semiconductor memory device 200 has the same configuration as the semiconductor memory device 100 described in 2D. However, the semiconductor memory device 200 may include a plurality of word lines WL2 instead of Figures 2A to 2D , and includes a gate dielectric film 230 instead of Figures 2A to 2D The gate dielectric film 130 is shown in FIG.

[0065] The plurality of word lines WL2 and the gate dielectric film 230 may have substantially the same structure as that already described with reference to FIG. Figure 1 and FIG. 2A to FIG. 2D The plurality of word lines WL2 and the gate dielectric film 130 are configured the same as described above. However, in each of the plurality of word lines WL2, the sidewall facing the second lightly doped film DS2 included in the vertical semiconductor structure VSS, the bottom surface facing the insulating film 110B, and the top surface facing the insulating film 110C may each be covered by the gate dielectric film 230. Figure 3A As shown, in the first connection unit AR1 , each of the plurality of word line contacts WLC may pass through the gate dielectric film 230 and be connected to a selected one of the plurality of word lines WL.

[0066] Figure 4 is a cross-sectional view of a semiconductor memory device 300 according to an embodiment. Figure 4 shows the corresponding Figure 1 A cross-sectional structure of a portion of a cross-sectional area taken along the line X1-X1'. Figure 4 In the drawings, the same reference numerals are used to denote Figure 1 and FIG. 2A to FIG. 2D The same figure numbers are used in the drawings, and their detailed descriptions are omitted here.

[0067] refer to Figure 4 , the semiconductor memory device 300 may basically have the same Figure 1 and Figures 2A to 2D The semiconductor memory device 300 has the same configuration as described above for the semiconductor memory device 100. However, the semiconductor memory device 300 may include a peripheral circuit structure PCS that overlaps the memory cell array unit MCA, the first connection unit AR1, and the second connection unit AR2 in the vertical direction (Z direction).

[0068] The peripheral circuit structure PCS may include a plurality of peripheral circuits and a multilayer wiring structure MWS. The plurality of peripheral circuits may be formed on the peripheral circuit substrate 352. The multilayer wiring structure MWS may connect the plurality of peripheral circuits to each other or to conductive elements located in the memory cell array unit MCA, the first connection unit AR1, and the second connection unit AR2.

[0069] The active area PA may be defined by a device isolation film 354 in the peripheral circuit substrate 352. The details of the peripheral circuit substrate 352 may be similar to those described in reference Figure 2A and 2B The details of the described substrate 102 are substantially the same. A plurality of transistors TR3 may be formed on the active area PA of the peripheral circuit substrate 352. Each of the plurality of transistors TR3 may include a peripheral gate PG and a peripheral source / drain region PSD formed in the active area PA on both sides of the peripheral gate PG. In an embodiment, the peripheral circuit structure PCS may further include unit devices such as resistors and capacitors. An interlayer insulating film 370 may be formed on the plurality of transistors TR3. The interlayer insulating film 370 may include a silicon oxide film, a silicon nitride film, a silicon oxynitride (SiON) film, a silicon oxycarbon nitride (SiOCN) film, or a combination thereof.

[0070] In the peripheral circuit structure PCS, the multilayer wiring structure MWS may also include a plurality of peripheral circuit layers ML30, ML31, ML32 and a plurality of peripheral circuit contacts MC30, MC31, MC32. Some of the plurality of peripheral circuit layers ML30, ML31, and ML32 may be electrically connected to a plurality of transistors TR3. The plurality of peripheral circuit contacts MC30, MC31, and MC32 may be configured to connect some peripheral circuit layers selected from the plurality of peripheral circuit layers ML30, ML31, and ML32 to each other. The plurality of peripheral circuit layers ML30, ML31, and ML32 and the plurality of peripheral circuit contacts MC30, MC31, and MC32 may be covered by an interlayer insulating film 370.

[0071] The plurality of peripheral circuit layers ML30, ML31 and ML32 and the plurality of peripheral circuit contacts MC30, MC31 and MC32 may each include a metal, a conductive metal nitride, a metal silicide or a combination thereof. For example, the plurality of peripheral circuit layers ML30, ML31 and ML32 and the plurality of peripheral circuit contacts MC30, MC31 and MC32 may each include a conductive material such as tungsten, molybdenum, titanium, cobalt, tantalum, nickel, tungsten silicide, titanium silicide, cobalt silicide, tantalum silicide and nickel silicide. Figure 4 An example is shown in which the plurality of peripheral circuit layers ML30, ML31, and ML32 have a triple wiring structure in the vertical direction (Z direction), but the embodiment is not limited to Figure 4 For example, the plurality of peripheral circuit layers ML30, ML31, ML32 may also have a multilayer wiring structure of two layers or at least four layers.

[0072] In an embodiment, a plurality of word line contacts WLC in the first connection unit AR1, a plurality of sense line contacts SLC in the second connection unit AR2, and a plurality of bit lines (refer to Figure 2BThe BLs in the peripheral circuit structure PCS may be respectively connected to selected ones of a plurality of peripheral circuit layers ML30, ML31, and ML32 included in the peripheral circuit structure PCS.

[0073] Figure 5A and 5B is a diagram of a semiconductor memory device 400A according to an embodiment. More specifically, Figure 5A is a partial cross-sectional perspective view of an example of the structure of a memory cell MCP included in the semiconductor memory device 400A, and Figure 5B yes Figure 5A The equivalent circuit diagram of the memory cell MCP is shown in FIG. Figure 5A In the figure, the insulating film between the conductive elements for insulating the conductive elements from each other is omitted. Figure 5A and 5B In the drawings, the same reference numerals are used to denote Figure 1 and 2A The same figure marks as in 2D are used, and their detailed descriptions are omitted here.

[0074] refer to Figure 5A and 5B , the semiconductor memory device 400A may basically have the same Figure 1 and 2A The semiconductor memory device 400A has the same configuration as the semiconductor memory device 100 described in 2D. However, the semiconductor memory device 400A may also include memory cells MCP instead of memory cells MC.

[0075] The memory cell MCP may basically have a reference Figures 2A to 2D The memory cell MCP may include a vertical semiconductor structure VSS. The vertical semiconductor structure VSS may include an n + The first heavily doped film HDS1 including the p-doped region, the first lightly doped film DS1 including the p-doped region, the second lightly doped film DS2 including the n-doped region, and the second lightly doped film DS3 including the p-doped region. + The second heavily doped film HDS2 of the doped region.

[0076] In the semiconductor memory device 400A, the bit line BL4 may pass through the word line WL and the sensing line WL in the vertical direction (Z direction). The bit line BL4 may be separated from each of the word line WL and the sensing line WL in the lateral direction (or the direction along the XY plane). An insulating film may be located between the bit line BL4 and the word line WL and between the bit line BL4 and the sensing line WL.

[0077] The memory cell MCP may constitute a 1T-DRAM cell having a vertical channel structure, which does not include a capacitor but includes one transistor having a structure based on a p-FBFET. In the vertical semiconductor structure VSS of the memory cell MCP, the second lightly doped film DS2 including an n-doped region may be used as a vertical channel region, and the gate dielectric film 130 may be between the word line WL and the second lightly doped film DS2. The sensing line SL may be connected to the n-doped region. + The first heavily doped film HDS1 of the doped region is in contact with the conductive connection structure CNS connected to the bit line BL4 and may be connected to the conductive connection structure CNS including the p + The doped region is in contact with the second heavily doped film HDS2.

[0078] Figure 5C It is used to explain Figure 5A and 5B FIG. 1 is a diagram showing the operating characteristics of the memory cell MCP. Figure 5C In the figure, the horizontal axis represents the word line (reference Figure 5A The voltage V at WL in WL , the ordinate represents the sensing line (reference Figure 5A The current I at SL SL Table 1 shows Figure 5A and 5B The operating conditions in the memory cell MCP are shown in FIG.

[0079] [Table 1]

[0080] <![CDATA[V BL (V)]]> <![CDATA[V WL (V)]]> Write "1" <![CDATA[V DD ]]> <![CDATA[V Wp ]]> Write "0" <![CDATA[-V DD ]]> <![CDATA[V Wp <!-- 8 -->]]> Read <![CDATA[V DD ]]> 0 Read 0 0

[0081] In Table 1, V BL represents the voltage at the bit line BL, V DD and -V DD Each of V represents a voltage applied to the bit line BL. WL represents the voltage at the word line WL, V Wp represents the voltage applied to the word line WL. In an embodiment, the voltage V DD The voltage can be selected in the range of about 0.5V to about 3V. DD The voltage V can be selected in the range of about -3V to about -0.5V. Wp It may be selected within the range of about -2 V to about -0.5 V, but is not limited thereto.

[0082] refer to Figure 5C and Table 1, to enable write operation, when V WL =V Wp When the voltage V DD applied to the bit line BL to write “1”, and when V WL =V Wp When the voltage -VDD Applied to the bit line BL to perform writing of "0".

[0083] To enable a read operation, when V BL =V DD When 0V is applied as the voltage V WL When V BL =V DD And apply 0V voltage as voltage V WL , the memory cell MCP may have a bistable characteristic, thus enabling a read operation. That is, when V BL =V DD When 0V is applied as the voltage V WL (i.e., V WL =0V), therefore, the current I of the sensing line SL can be SL The value of MCP is used to read the status of the memory cell MCP.

[0084] To enable the hold operation, no voltage may be applied externally. That is, V BL can float, or can be equal to 0V, and V WL may be floating, or may be equal to 0 V. Even when no voltage is applied from the outside, the memory cell MCP may be maintained in a storage state for a predetermined period of time due to the charges stored in the vertical channel region.

[0085] exist Figure 5C In the case of sensing line SL, the current I SL The change of the voltage V at the bit line BL BL The change of is shown as line L1. Figure 5C In FIG. 1 , arrows R11 , R12 and R13 indicate the current I at the sensing line SL. SL The path changes along line L1. Figure 5C The current I at the position indicated by the circular dashed line A1 is SL Corresponding to the off current Ioff, the current I SL Corresponding to the on-state current Ion, and the current I at the position in the circular dashed line indicated by A3 SL Corresponding to when the voltage at the word line WL is the voltage V Wp The current value used to write a "0" or write a "1" when the

[0086] Fig. 6A and 6B is a diagram of a semiconductor memory device 400B according to an embodiment. More specifically, Fig. 6A is a partial cross-sectional perspective view of an example of a structure of a memory cell MCN included in a semiconductor memory device 400B, and Figure 6Byes Fig. 6A The equivalent circuit diagram of the memory cell MCN is shown in FIG. Fig. 6A In the figure, the insulating film between the conductive elements for insulating the conductive elements from each other is omitted. Fig. 6A and 6B In the drawings, the same reference numerals are used to denote Figure 1 , FIG. 2A to FIG. 2D and Figure 5A The same figure numbers are used in the drawings, and their detailed descriptions are omitted here.

[0087] refer to Fig. 6A and 6B , the semiconductor memory device 400B may basically have the same Figure 5A The semiconductor memory device 400A has the same configuration as described above. However, the semiconductor memory device 400B may include a memory cell MCN.

[0088] The memory cell MCN may basically have a Figure 5A The memory cell MCP has the same configuration as described above. The memory cell MCN may include a vertical semiconductor structure VSS. The vertical semiconductor structure VSS may include n + The first heavily doped film HDS1 including the p-doped region, the first lightly doped film DS1 including the p-doped region, the second lightly doped film DS2 including the n-doped region, and the second lightly doped film DS3 including the p-doped region. + The second heavily doped film HDS2 of the doped region.

[0089] The memory cell MCN may constitute a 1T-DRAM cell having a vertical channel structure, which does not include a capacitor but includes one transistor having a structure based on an n-FBFET. In the vertical semiconductor structure VSS of the memory cell MCN, the first lightly doped film DS1 including a p-doped region may be used as a vertical channel region, and the gate dielectric film 130 may be between the word line WL and the first lightly doped film DS1. The sensing line SL may be connected to the n-doped region. + The first heavily doped film HDS1 of the doped region is in contact with the conductive connection structure CNS connected to the bit line BL and includes p + The doped region is in contact with the second heavily doped film HDS2.

[0090] Figure 6C It is used to explain Fig. 6A and 6B FIG. 1 is a diagram showing the operating characteristics of a memory cell MCN. Figure 6C In the figure, the horizontal axis represents the word line (reference Fig. 6A The voltage V at WL in WL , and the ordinate represents the sensing line (reference Fig. 6A The current I at SL SL Table 2 shows Fig. 6A and6B The operating conditions in the memory cell MCN are shown in FIG.

[0091] [Table 2]

[0092] <![CDATA[V BL (V)]]> <![CDATA[V WL (V)]]> Write "1" <![CDATA[V DD ]]> <![CDATA[V Wn ]]> Write "0" <![CDATA[-V DD ]]> <![CDATA[V Wn ]]> Read <![CDATA[V DD ]]> 0 Read 0 0

[0093] In Table 2, V BL represents the voltage at the bit line BL, V DD and -V DD Each of V represents a voltage applied to the bit line BL. WL represents the voltage at the word line WL, and V Wn represents the voltage applied to the word line WL. In an embodiment, the voltage V DD The voltage can be selected in the range of about 0.5V to about 3V. DD can be selected in the range of about -3V to about -0.5V, and the voltage V Wn It may be selected within the range of about 0.5V to about 2V, but is not limited thereto.

[0094] refer to Figure 6C and Table 2, to enable write operation, when V WL =V Wn When the voltage V DD applied to the bit line BL to write “1”, and when V WL =V Wn When the voltage -V DD Applied to the bit line BL to perform writing of "0".

[0095] To enable a read operation, when V BL =V DD When 0V is applied as the voltage V WL When V BL =V DD And apply 0V voltage as voltage V WL When V BL =V DD When 0V is applied as voltage V WL (i.e., V WL =0V), therefore, the current I of the sensing line SL can be SL The value of MCN is read from the state of the memory cell MCN.

[0096] To enable the hold operation, no voltage may be applied externally. That is, V BL can float, or can be equal to 0V, and V WLmay be floating, or may be equal to 0 V. Even when no voltage is applied from the outside, the memory cell MCN may be maintained in a storage state for a predetermined period of time due to charges stored in the vertical channel region.

[0097] exist Figure 6C In the case of sensing line SL, the current I SL The change of the voltage V at the bit line BL BL The change in is shown as line L2. Figure 6C In FIG. 1 , arrows R21 , R22 and R23 indicate the current I at the sensing line SL. SL The path changes along line L2. Figure 6C The current I at the position indicated by the circular dashed line B1 is SL Corresponding to the off current Ioff, the current I SL The current I corresponding to the on-current Ion and the current I at the position in the circular dashed line indicated by B3 SL Corresponding to when the voltage at the word line WL is the voltage V Wn The current value used to write a "0" or write a "1" when the

[0098] Figure 7 is a circuit diagram of a semiconductor memory device 500 according to an embodiment.

[0099] Figure 7 A circuit structure is shown in which a plurality of memory cells MC1 are arranged in a 3×3×3 array, and each memory cell MC1 comprises a vertical 1T-DRAM cell. Figure 7 In the embodiment, a group of memory cells MC1 arranged in a row extending in the vertical direction (Z direction) may constitute a memory cell string MCS1.

[0100] In an embodiment, Figure 7 Each of the plurality of memory cells MC1 shown in FIG. 1 may have a Figures 2A to 2D The storage unit MC has the same configuration as described above. In other embodiments, Figure 7 Each of the plurality of memory cells MC1 shown in FIG. 1 may have a Figure 5A The storage unit MCP has the same configuration.

[0101] In having Figure 7In the semiconductor memory device 500 of the circuit configuration shown in , a plurality of memory cells MC1 in one memory cell string MCS1 may share one bit line BL. A plurality of memory cells MC1 in one memory cell string MCS1 may be connected to different word lines WL and different sensing lines SL from each other. A plurality of memory cells MC1 arranged at the same vertical level on one plane (XY plane) may share one word line WL and one sensing line SL.

[0102] Figure 8 Is has Figure 7 2 is a timing diagram of a selected memory cell MC1 in the semiconductor memory device 500 having the circuit configuration shown in FIG.

[0103] refer to Figure 7 and Figure 8 , a desired memory cell string MCS1 can be determined by selecting a bit line BL from a plurality of bit lines BL, and a memory cell MC1 can be selected by selecting a word line WL from a plurality of word lines WL and selecting a sensing line SL from a plurality of sensing lines SL. In the above manner, a signal of the selected memory cell MC1 can be read through the sensing line SL. By applying a desired voltage (e.g., the voltage described with reference to Table 1) to each of the selected bit line BL and the selected word line WL, write, read, and hold operations can be selectively performed only on the selected memory cell MC1.

[0104] Fig. 9 is based on Figure 7 0 is a perspective view of a semiconductor memory device 500 in which the circuit configuration shown in FIG. 5 is arranged in a 3×3×3 array. Fig.10 is based on Figure 7 A side view of a semiconductor memory device 500 in which the circuit configuration shown in FIG. is arranged in a 3×3×3 array. Fig. 9 and Fig.10 In FIG. 1 , a plurality of word lines WL and a plurality of sensing lines SL are shown by dotted lines.

[0105] Figure 7 , Fig. 9 and Fig.10 A semiconductor memory device 500 arranged in a 3×3×3 array is shown, but the embodiment is not limited thereto, the number of memory cells MC1 in the first lateral direction (X direction), the second lateral direction (Y direction), and the vertical direction (Z direction) is not particularly limited, and a 3D structure including various numbers of memory cells MC1 can be formed as needed.

[0106] Fig.11 is a circuit diagram of a semiconductor memory device 600 according to an embodiment.

[0107] Fig.11FIG. 4 shows a circuit configuration in which a plurality of memory cells MC2 are arranged in a 3×3×3 array, each memory cell MC2 comprising a vertical 1T-DRAM cell. Fig.11 In the embodiment, a group of memory cells MC2 arranged in a row extending in the vertical direction (Z direction) may constitute a memory cell string MCS2.

[0108] In an embodiment, Fig.11 Each of the plurality of memory cells MC2 shown in FIG. 1 may have a Fig. 6A The storage unit MCN has the same configuration as described.

[0109] In having Fig.11 In the semiconductor memory device 600 of the circuit configuration shown in , a plurality of memory cells MC2 included in one memory cell string MCS2 may share one bit line BL. A plurality of memory cells MC2 included in one memory cell string MCS2 may be connected to different word lines WL, respectively, and to different sense lines SL, respectively. A plurality of memory cells MC2 arranged in one plane (XY plane) at the same vertical level may share one word line WL and one sense line SL.

[0110] Fig.12 Is has Fig.11 2 is a timing diagram of a selected memory cell MC2 in the semiconductor memory device 600 having the circuit configuration shown in FIG.

[0111] refer to Fig.11 and Fig.12 , a desired memory cell string MCS2 can be determined by selecting a bit line BL from a plurality of bit lines BL, and a memory cell MC2 can be selected by selecting a word line WL from a plurality of word lines WL and selecting a sensing line SL from a plurality of sensing lines SL. In the above manner, a signal of the selected memory cell MC2 can be read through the sensing line SL. By applying a desired voltage (e.g., the voltage described in reference Table 2) to each of the selected bit line BL and the selected word line WL, write, read, and hold operations can be selectively performed only on the selected memory cell MC2.

[0112] Similar to reference Fig. 9 and Fig.10 described, with Fig.11 The semiconductor memory device 600 of the illustrated circuit configuration may be arranged in a 3×3×3 array or implemented as a 3D structure, from which various modifications and changes may be made within the scope of the embodiments.

[0113] According to the reference Figures 1 to 12In the semiconductor memory devices 100, 200, 300, 400A, 400B, 500 and 600 of the described embodiments, a memory cell may include a transistor but does not include a capacitor. Therefore, in the semiconductor memory devices 100, 200, 300, 400A, 400B, 500 and 600 according to the embodiments, unlike the related art in which charges are stored in a capacitor, a single transistor may be used to implement a DRAM cell by storing charges in a vertical channel region of the transistor, thereby making it advantageous to provide a finer and more compact 3D array structure. In addition, in the semiconductor memory devices 100, 200, 300, 400A, 400B, 500 and 600 according to the embodiments, a plurality of memory cells overlapping each other in a vertical direction may include a 3D stacked memory cell array that shares one bit line. Therefore, the semiconductor memory devices 100, 200, 300, 400A, 400B, 500 and 600 according to the embodiments can overcome the problems caused by the density limitation of the bit lines encountered in the semiconductor memory device having the 2D structure, and provide a structure conducive to the high integration of the semiconductor memory device.

[0114] In addition, the semiconductor memory device 100, 200, 300, 400A, 400B, 500 and 600 according to the embodiment can have a relatively low operating voltage and a relatively sharp SS by using a positive feedback loop, and has the advantage of low power consumption, which is different from the related DRAM device because no refresh operation is required. In addition, due to the relatively high on-off current ratio, a wide current sensing margin and a high operating speed can be provided. Therefore, the semiconductor memory device 100, 200, 300, 400A, 400B, 500 and 600 according to the embodiment can provide excellent competitiveness in various aspects including performance, power, chip area and cost.

[0115] Next, a method of manufacturing a semiconductor memory device according to an embodiment is described in detail.

[0116] Figures 13A to 33B is a diagram of a method of manufacturing a semiconductor memory device according to an embodiment. Fig.13A , 14A , 15A, 16, 17, 18A, 19A, 20, 21, 22A, 24A, 25A, 26A, 27A, 29, 30, 32A and 33A correspond to the Figure 1 A cross-sectional view of a portion of a cross section taken along line X1 - X1 ′ according to a process sequence. Fig. 13B , Fig. 14B , Fig. 15B , Fig.18B , Fig.19B , Fig. 22B , Fig.23 , Fig. 24B , Fig.25B , Fig.26B , Fig.27B , Fig.28 , Fig.31 , Fig.32B and Fig.33B corresponds to along Figure 1 A cross-sectional view of a portion of a cross section taken along line Y1 - Y1 ′ according to a process sequence. Fig. 18C yes Fig.18A An enlarged cross-sectional view of the “EXA” portion of FIG. Fig.19C yes Fig.19A An enlarged cross-sectional view of the "EXA" section in the reference Figures 13A to 33B Description Manufacturing Figure 1 and Figures 2A to 2D An example of a method of a semiconductor memory device 100 is shown in FIG. Figures 13A to 33B In the drawings, the same reference numerals are used to denote Figure 1 and Figures 2A to 2D The same figure numbers are used in the drawings, and their detailed descriptions are omitted here.

[0117] refer to Fig.13A and 13B , an insulating film 110A, a plurality of first sacrificial patterns 112 , an insulating film 110B, a plurality of second sacrificial patterns 114 , and an insulating film 110C may be sequentially formed on the substrate 102 .

[0118] Each of the plurality of first sacrificial patterns 112 may be formed to provide a sensing line (refer to FIG. 2A to FIG. 2D SL in the figure), and each of the plurality of second sacrificial patterns 114 may be formed to provide a space for a word line (refer to FIG. 2A to FIG. 2D The plurality of first sacrificial patterns 112 and the plurality of second sacrificial patterns 114 may each be formed to have a line shape extending long in the first lateral direction (X direction). The insulating film 110B may be formed to cover the top surface and sidewalls of each of the plurality of first sacrificial patterns 112 on the insulating film 110A. The insulating film 110C may be formed to cover the top surface and sidewalls of each of the plurality of second sacrificial patterns 114 on the insulating film 110B.

[0119] The insulating films 110A, 110B, and 110C may include a silicon oxide film, and each of the first sacrificial pattern 112 and the second sacrificial pattern 114 may include a film including a material different from the silicon oxide film, and include a material having an etching selectivity different from the silicon oxide film. In an embodiment, the first sacrificial pattern 112 and the second sacrificial pattern 114 may include different films, each selected from a silicon nitride film (SiN), a SiON film, a SiCN film, a SiOCN film, and an aluminum oxide (AlO) film. As used herein, each of the terms "SiN", "SiON", "SiCN", "SiOCN", and "AlO" refers to a material including an element contained therein, rather than a chemical formula representing a stoichiometric relationship. For example, the first sacrificial pattern 112 may include a silicon nitride film, and the second sacrificial pattern 114 may include a SiON film, but is not limited thereto.

[0120] refer to Fig.14A and Fig. 14B , you can Fig.13A and Fig. 13B A plurality of third sacrificial patterns 116 and an inter-cell insulating film 118 are sequentially formed on the resultant structure.

[0121] Each of the plurality of third sacrificial patterns 116 may be formed to have a line shape extending long in the second lateral direction (Y direction). Each of the plurality of third sacrificial patterns 116 may be formed to provide a conductive connection structure (reference FIG. 2A to FIG. 2D The plurality of third sacrificial patterns 116 may include a material different from the constituent material of each of the plurality of first sacrificial patterns 112 and the plurality of second sacrificial patterns 114. The plurality of third sacrificial patterns 116 may include any one of a silicon nitride (SiN) film, a SiON film, a SiCN film, a SiOCN film, and an aluminum oxide (AlO) film. For example, when the plurality of first sacrificial patterns 112 include a silicon nitride film and the plurality of second sacrificial patterns 114 include a SiON film, the plurality of third sacrificial patterns 116 may include an aluminum oxide film, but is not limited thereto. The inter-cell insulating film 118 may be formed to cover the top surface and sidewalls of each of the plurality of third sacrificial patterns 116 on the insulating film 110C. The inter-cell insulating film 118 may include a silicon oxide film.

[0122] exist Fig.14A and 14B The stacked structure RP including a plurality of first sacrificial patterns 112, an insulating film 110B, a plurality of second sacrificial patterns 114, an insulating film 110C, a plurality of third sacrificial patterns 116, and an inter-cell insulating film 118 sequentially stacked on the substrate 102 may be a structure forming a plurality of memory cells (refer to FIG. 2A to FIG. 2DThe plurality of memory cells are arranged at the same vertical level on the substrate 102 in a lateral direction (XY plane) according to the structure required by the MC in the embodiment.

[0123] refer to Fig.15A and 15B ,exist Fig.14A and 14B In the resulting structure, the stacked structure RP may be repeatedly formed a plurality of times in the vertical direction (Z direction) as required. The number of stacked structures RP stacked in the vertical direction (Z direction) may correspond to the number of memory cells (refer to Figures 2A to 2D The number of MCs in . Fig.15A and Fig. 15B An example in which two stack structures RP are formed in the vertical direction (Z direction) is shown, but the embodiment is not limited thereto. The stack structure RP may be repeatedly formed by the same number as the number of memory cells MC required to form one memory cell string.

[0124] refer to Fig.16 ,exist Fig.15A and Fig. 15B In the first connection unit AR1 and the second connection unit AR2 of the resultant structure, corresponding portions of the plurality of stacked structures RP may be etched to form a plurality of step units, and a mold insulating film 119 may be formed to cover the plurality of step units.

[0125] refer to Fig.17 In the memory cell array unit MCA, a plurality of channel holes H1 may be formed to pass through the plurality of stacked structures RP in the vertical direction (Z direction). The insulating film 110A closest to the substrate 102 may be exposed at the bottom of each of the plurality of channel holes H1. The plurality of channel holes H1 may be formed using an anisotropic dry etching process.

[0126] refer to Fig.18A , Fig.18B and Fig. 18C In each of the multiple channel holes H1, the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, the second heavily doped film HDS2 and the inter-cell local insulating film 120 may be repeatedly and sequentially formed along the vertical direction (Z direction) from the bottom of each channel hole H1.

[0127] refer to Fig.19A , Fig.19B and Fig.19C ,exist Fig.18A , Fig.18B and Fig. 18CIn the resulting structure, a hollow portion HH may be formed to pass through the stacked structure including the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, the second heavily doped film HDS2, and the inter-cell local insulating film 120 in the vertical direction (Z direction) inside each of the plurality of channel holes H1. The hollow portion HH may be filled with an insulating pillar 124.

[0128] As a result, each of the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, the second heavily doped film HDS2, and the inter-cell local insulating film 120 may be left in the form of a ring surrounding the insulating pillar 124. In addition, a plurality of vertical semiconductor structures VSS may be obtained, each of which includes the first heavily doped film HDS1, the first lightly doped film DS1, the second lightly doped film DS2, and the second heavily doped film HDS2.

[0129] refer to Fig. 20 , you can Fig.19A , 19B A mask pattern MP1 having a plurality of holes MPH is formed on the resultant structure of the first connection unit AR1 and the second connection unit AR2. After the mask pattern MP1 is formed, in the first connection unit AR1 and the second connection unit AR2, the top surface of the inter-cell insulating film 118 and the top surface of the mold insulating film 119 may be exposed through the plurality of holes MPH. In an embodiment, the mask pattern MP1 may include polysilicon, but is not limited thereto.

[0130] Afterwards, the lower structure exposed by the plurality of holes MPH may be etched by using the mask pattern MP1 as an etching mask, and thus, a plurality of contact holes H2 may be formed. The insulating film 110A closest to the substrate 102 may be exposed at the bottom of each of the plurality of contact holes H2. The plurality of contact holes H2 may be formed by using an anisotropic dry etching process.

[0131] refer to Fig.21 ,exist Fig. 20 In the resulting structure, a portion of each of the plurality of insulating films 110A, 110B, and 110C, the plurality of inter-cell insulating films 118, and the mold insulating film 119 exposed through the plurality of contact holes H2 may be selectively removed. Therefore, the corresponding partial regions of the plurality of contact holes H2 may be expanded in the lateral direction (or the direction along the XY plane) and the vertical direction (Z direction) to form a plurality of expanded contact holes H2A. The plurality of expanded contact holes H2A may be formed by using a wet etching process.

[0132] refer to Fig.22A and Fig. 22B , can be obtained from Fig.21The mask pattern MP1 is removed from the resulting structure to expose the top surface of each of the uppermost inter-cell insulating film 118 and the mold insulating film 119. Thereafter, a buried insulating film 126 may be formed to fill the plurality of extended contact holes H2A and cover the top surface of each of the uppermost inter-cell insulating film 118 and the mold insulating film 119.

[0133] refer to Fig.23 , can be obtained from the memory cell array unit MCA Fig.22A and 22B The resulting structure is etched in partial areas. Therefore, a plurality of slits SH may be formed, each of which has a strip-type planar shape extending long in the first lateral direction (X direction). The insulating film 110A closest to the substrate 102 may be exposed at the bottom of each of the plurality of slits SH. A plurality of first sacrificial patterns 112, a plurality of second sacrificial patterns 114, and a plurality of third sacrificial patterns 116 may be exposed at corresponding inner sidewalls of the plurality of slits SH.

[0134] refer to Fig.24A and 24B , the plurality of second sacrificial patterns 114 may be selectively removed through the plurality of slits SH, and thus, a plurality of word line spaces WLH may be formed. The plurality of second sacrificial patterns 114 may be selectively removed by using a wet etching process. The first lightly doped film DS1 may be exposed in the plurality of word line spaces WLH.

[0135] refer to Fig.25A and 25B , the gate dielectric film 130 may be formed to cover the surface of the first lightly doped film DS1, which is exposed in the plurality of word line spaces WLH. In an embodiment, the gate dielectric film 130 may be formed by using a selective atomic layer deposition (ALD) process.

[0136] In other embodiments, it is possible to form Figures 3A to 3D The gate dielectric film 230 shown in FIG. 1 is not the gate dielectric film 130. The formation of the gate dielectric film 230 may include forming the gate dielectric film 230 by using an ALD process to conformally cover the gate dielectric film 230. Fig.24A and Fig. 24B The exposed surface in the resulting structure is removed, and other portions except for the portions of the gate dielectric film 230 inside the plurality of word line spaces WLH are removed.

[0137] refer to Fig.26A and 26B , the plurality of first sacrificial patterns 112 may be selectively removed through the plurality of slits SH, and thus a plurality of sensing line spaces SLH may be formed. The plurality of first sacrificial patterns 112 may be selectively removed by using a wet etching process. The first heavily doped film HDS1 may be exposed in the plurality of sensing line spaces SLH.

[0138] refer to Fig.27A and Fig.27B ,exist Fig.26A and Fig.26B In the resulting structure, a plurality of word lines WL in a plurality of word line spaces WLH and a plurality of sense lines SL in a plurality of sense line spaces SLH may be formed.

[0139] The formation of the plurality of word lines WL and the plurality of sensing lines SL may include Fig.26A and 26B In the resulting structure, a conductive layer is formed in a plurality of word line spaces WLH and a plurality of sensing line spaces SLH through a plurality of slits SH by using an ALD process or a chemical vapor deposition (CVD) process, and unnecessary portions except for portions of the conductive layer respectively inside the plurality of word line spaces WLH and the plurality of sensing line spaces SLH are removed. The conductive layer may include W, Al, Mo, Ru, Al, Co, Ti, TiN, Ta, TaN, WN, TiSiN, WSiN, doped polysilicon, or a combination thereof, but is not limited thereto.

[0140] refer to Fig.28 ,exist Fig.27A and Fig.27B In the resulting structure, a plurality of isolation insulating films 140 may be formed to fill the plurality of slits SH. The formation of the plurality of isolation insulating films 140 may include forming a silicon oxide film having a sufficient thickness to fill the plurality of slits SH. Fig.27A and 27B A plurality of slits SH are formed in the resulting structure, and a portion of the silicon oxide film is removed to expose the top surface of the buried insulating film 126.

[0141] Reference Fig.29 , a plurality of word line contact holes WLCH may be formed in the first connection unit AR1 in a vertical direction (Z direction) through the insulating structure including the buried insulating film 126 and the mold insulating film 119. A plurality of sense line contacts SLCH may be formed in the second connection unit AR2 in a vertical direction (Z direction) through the insulating structure including the buried insulating film 126 and the mold insulating film 119.

[0142] A plurality of word lines WL and the buried insulating film 126 may be exposed through a plurality of word line contact holes WLCH in the first connection unit AR1 , and a plurality of sensing lines SL and the buried insulating film 126 may be exposed through a plurality of sensing line contacts SLCH in the second connection unit AR2 .

[0143] refer to Fig.30, a plurality of word line contacts WLC may be respectively formed in a plurality of word line contact holes WLCH in the first connection unit AR1 , and a plurality of sensing line contacts SLC may be respectively formed in a plurality of sensing line contacts SLCH in the second connection unit AR2 .

[0144] refer to Fig.31 In the memory cell array unit MCA, a plurality of bit line holes BLH passing through a plurality of insulating films 110A, 110B, and 110C, a plurality of third sacrificial patterns 116, a plurality of inter-cell insulating films 118, and a buried insulating film 126 in a vertical direction (Z direction) may be formed separately from a plurality of vertical semiconductor structures VSS in a lateral direction, and a plurality of word lines WL and a plurality of sensing lines SL are located between the plurality of vertical semiconductor structures VSS and the plurality of bit line holes BLH. The insulating film 110A closest to the substrate 102 may be exposed at the bottom of each of the plurality of bit line holes BLH. The plurality of bit line holes BLH may be formed by using an anisotropic dry etching process.

[0145] refer to Fig.32A and 32B ,exist Fig.31 In the resultant structure, the plurality of third sacrificial patterns 116 may be selectively removed through the plurality of bit line holes BLH, and thus, a plurality of connection spaces CNH may be formed. The second heavily doped film HDS2 may be exposed in each of the plurality of connection spaces CNH.

[0146] refer to Fig.33A and 33B ,exist Fig.32A and 32B In the resulting structure, the plurality of connection spaces CNH and the plurality of bit line holes BLH may be filled with a conductive material, and thus, a plurality of conductive connection structures CNS and a plurality of bit lines BL may be formed.

[0147] Although referenced Figures 13A to 33B Description Manufacturing Figure 1 and Figures 2A to 2D The method of the semiconductor memory device 100 shown in FIG. 1 is a method of the semiconductor memory device 100 shown in FIG. 1 , but it should be understood that the method can be modified by referring to FIG. 1 within the scope of the present disclosure. Figures 13A to 33B The described processes apply various modifications and changes to manufacture semiconductor memory devices having various changed structures.

[0148] While various aspects of the embodiments have been particularly shown and described, it will be understood that various changes in form and details may be made therein without departing from the spirit and scope of the appended claims.

[0149] CROSS-REFERENCE TO RELATED APPLICATIONS

[0150] This application claims the priority of Korean Patent Application No. 10-2023-0119278 filed in the Korean Intellectual Property Office on September 7, 2023, the disclosure of which is incorporated herein by reference in its entirety.

Claims

1. A semiconductor memory device, comprising: a word line extending in a lateral direction; a sensing line separated from the word line, the sensing line overlapping the word line in a vertical direction and extending in the lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in the vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in the lateral direction; as well as a gate dielectric film between the vertical channel region and the word line, wherein the vertical semiconductor structure comprises a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type, which are sequentially provided in the vertical direction; wherein the vertical channel region includes the first lightly doped film or the second lightly doped film, and The sensing line is in contact with the first heavily doped film of the vertical semiconductor structure.

2. The semiconductor memory device according to claim 1 , further comprising an insulating column, the insulating column passing through the vertical semiconductor structure in the vertical direction, the insulating column being separated from each of the word line and the sensing line in the lateral direction, Each of the first heavily doped film, the first lightly doped film, the second lightly doped film, and the second heavily doped film defines a hollow portion for accommodating the insulating pillar. 3 . The semiconductor memory device according to claim 1 , further comprising a bit line separated from each of the word line and the sensing line in the lateral direction, the bit line being connected to the second heavily doped film. 4 . The semiconductor memory device according to claim 3 , wherein the bit line extends long in the vertical direction and faces the vertical semiconductor structure in the lateral direction, and the word line and the sensing line are located between the bit line and the vertical semiconductor structure.

5. The semiconductor memory device according to claim 1, wherein: In the vertical semiconductor structure, the first heavily doped film includes n + doped regions, the first lightly doped film includes a p-doped region, the second lightly doped film includes an n-doped region, and the second heavily doped film includes a p-doped region. + Doped region, wherein the vertical channel region includes the n-doped region, and The word line faces the n-doped region in the lateral direction, and the gate dielectric film is between the word line and the n-doped region.

6. The semiconductor memory device according to claim 1, wherein In the vertical semiconductor structure, the first heavily doped film includes n + doped regions, the first lightly doped film includes a p-doped region, the second lightly doped film includes an n-doped region, and the second heavily doped film includes a p-doped region. + Doped region, wherein the vertical channel region includes the p-doped region, and The word line faces the p-doped region in the lateral direction, and the gate dielectric film is between the word line and the p-doped region.

7. The semiconductor memory device according to claim 1, further comprising: a conductive connection structure, contacting the second heavily doped film and surrounding the second heavily doped film; as well as A bit line connected to the second heavily doped film through the conductive connection structure, The bit line is separated from each of the word line and the sensing line in the lateral direction and extends long in the vertical direction.

8. The semiconductor memory device according to claim 1, further comprising: a conductive connection structure, contacting the second heavily doped film and surrounding the second heavily doped film; as well as A bit line connected to the second heavily doped film through the conductive connection structure, The bit line passes through each of the word line and the sensing line in the vertical direction and is separated from each of the word line and the sensing line.

9. A semiconductor memory device comprising a memory cell string, the memory cell string comprising a plurality of memory cells arranged in a row in a vertical direction, Each of the plurality of storage units comprises: a word line extending in a lateral direction; a sensing line separated from the word line, the sensing line overlapping the word line in the vertical direction and extending in the lateral direction; a vertical semiconductor structure passing through the word line and the sensing line in the vertical direction, the vertical semiconductor structure having a vertical channel region facing the word line in the lateral direction; as well as a gate dielectric film between the vertical channel region and the word line, wherein, in each of the plurality of memory cells, the vertical semiconductor structure comprises a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type sequentially provided in the vertical direction; wherein the vertical channel region includes the first lightly doped film or the second lightly doped film in each of the plurality of memory cells, and The sensing line is in contact with the first heavily doped film of the vertical semiconductor structure in each of the plurality of memory cells.

10. The semiconductor memory device according to claim 9, further comprising a bit line, the bit line being separated from each of the word line and the sensing line in the lateral direction, the bit line extending long in the vertical direction, and the bit line facing the vertical semiconductor structure of each of the plurality of memory cells in the lateral direction, and the word line and the sensing line being between the bit line and the vertical semiconductor structure, The plurality of memory cells share the bit line.

11. The semiconductor memory device according to claim 9, wherein each of the plurality of memory cells includes one transistor and does not include a capacitor.

12. The semiconductor memory device according to claim 9, further comprising an insulating pillar passing through the vertical semiconductor structure of each of the plurality of memory cells in the vertical direction, in, In each of the plurality of memory cells, each of the first heavily doped film, the first lightly doped film, the second lightly doped film, and the second heavily doped film defines a hollow portion accommodating the insulating pillar.

13. The semiconductor memory device according to claim 9, further comprising a plurality of inter-cell insulating structures, each of the plurality of inter-cell insulating structures being between two adjacent memory cells among the plurality of memory cells, wherein the vertical semiconductor structure of each of the plurality of memory cells extends in a straight line in the vertical direction, and wherein the vertical semiconductor structure of a first memory cell among the multiple memory cells is separated from the vertical semiconductor structure of a second memory cell among the multiple memory cells that is adjacent to the first memory cell in the vertical direction, and one of the multiple inter-cell insulation structures is between the vertical semiconductor structure of the first memory cell and the vertical semiconductor structure of the second memory cell.

14. The semiconductor memory device according to claim 9, wherein the lateral direction is a first lateral direction, and the second lateral direction intersects the first lateral direction, and in, The semiconductor memory device further includes: a word line contact separated from the vertical semiconductor structure of each memory cell of the plurality of memory cells in the first lateral direction and connected to the word line; a sense line contact spaced apart from the vertical semiconductor structure of each of the plurality of memory cells in the first lateral direction, the sense line contact spaced apart from the word line contact in the first lateral direction, with the vertical semiconductor structure between the sense line contact and the word line contact; and A bit line is separated from the word line and the sensing line in the second lateral direction, and the bit line is extended long in the vertical direction.

15. The semiconductor memory device according to claim 9, wherein: In the vertical semiconductor structure of each of the plurality of memory cells, the first heavily doped film includes n + doped regions, the first lightly doped film includes a p-doped region, the second lightly doped film includes an n-doped region, and the second heavily doped film includes a p-doped region. + Doped region, wherein the vertical channel region includes the n-doped region, and The word line faces the n-doped region in the lateral direction, and the gate dielectric film is between the word line and the n-doped region.

16. The semiconductor memory device according to claim 9, wherein: In the vertical semiconductor structure of each of the plurality of memory cells, the first heavily doped film includes n + doped regions, the first lightly doped film includes a p-doped region, the second lightly doped film includes an n-doped region, and the second heavily doped film includes a p-doped region. + Doped region, wherein the vertical channel region includes the p-doped region, and The word line faces the p-doped region in the lateral direction, and the gate dielectric film is between the word line and the p-doped region.

17. A semiconductor memory device comprising a memory cell array, the memory cell array comprising a plurality of memory cells three-dimensionally and repeatedly arranged on a substrate in a first lateral direction, a second lateral direction, and a vertical direction, wherein the first lateral direction intersects the second lateral direction, and the vertical direction is perpendicular to each of the first lateral direction and the second lateral direction, The memory cell array comprises: a plurality of sensing lines and a plurality of word lines, arranged alternately one after another in the vertical direction, the plurality of sensing lines and the plurality of word lines being separated from each other in the vertical direction; a plurality of insulating films, respectively between the plurality of sensing lines and the plurality of word lines; a stacked structure passing through the plurality of sensing lines, the plurality of word lines, and the plurality of insulating films in the vertical direction, the stacked structure comprising a plurality of vertical semiconductor structures overlapping each other in the vertical direction, each of the plurality of vertical semiconductor structures having a vertical channel region; an insulating column passing through the plurality of vertical semiconductor structures in the vertical direction; a plurality of gate dielectric films between corresponding vertical channel regions of the plurality of vertical semiconductor structures and the plurality of word lines; as well as a plurality of bit lines passing through the plurality of insulating films, wherein, from the plurality of memory cells, memory cells arranged in a row in the vertical direction share a selected one of the plurality of bit lines, wherein each of the plurality of vertical semiconductor structures comprises a first heavily doped film of a first conductivity type, a first lightly doped film of a second conductivity type, a second lightly doped film of the first conductivity type, and a second heavily doped film of the second conductivity type sequentially provided in the vertical direction; and The vertical channel region of each of the plurality of vertical semiconductor structures includes the first lightly doped film or the second lightly doped film.

18. The semiconductor memory device according to claim 17, wherein the first heavily doped film of each of the plurality of vertical semiconductor structures is in contact with a selected one of the plurality of sensing lines, and The second heavily doped film of each of the plurality of vertical semiconductor structures is in contact with a selected one of the plurality of bit lines.

19. The semiconductor memory device according to claim 17, further comprising: a first connection circuit and a second connection circuit on the substrate, the first connection circuit and the second connection circuit being separated from each other in the first lateral direction, and the memory cell array being between the first connection circuit and the second connection circuit; a plurality of word line contacts, connected to the plurality of word lines in a one-to-one manner in the first connection circuit, respectively, the plurality of word line contacts extending long in the vertical direction; as well as A plurality of sensing line contacts are respectively connected to the plurality of sensing lines in a one-to-one manner in the second connection circuit, and the plurality of sensing line contacts extend in the vertical direction.

20. The semiconductor memory device according to claim 17, wherein each of the plurality of memory cells includes one transistor and does not include a capacitor.

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