Shielded gate trench MOSFET structure and preparation method thereof, and chip

Abstract

The present application belongs to the technical field of power devices, and provides a shielded gate trench MOSFET structure and a preparation method and a chip thereof. A first N-type control gate polysilicon layer, a first N-type shielding gate polysilicon layer, a P-type shielding gate polysilicon layer, a second N-type shielding gate polysilicon layer and a second N-type control gate polysilicon layer are sequentially arranged in parallel in a groove of an N-type drift region, and a first dielectric material layer is used to isolate the control gate and the shielding gate to isolate electrical signals, so that the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer are both in contact with the P-type shielding gate polysilicon layer, and then the low electric field of the P-type shielding gate polysilicon layer is shielded by the reverse-biased PN junction between the shielding gates, so that the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer are in a floating state, so as to further isolate the shielding gate from the control gate, reduce the capacitance of the shielded gate trench MOSFET device, and optimize the switching characteristics of the shielded gate trench MOSFET device.

Description

Technical Field

[0001] The present application belongs to the technical field of power devices, and in particular, relates to a shielded gate trench MOSFET structure and a preparation method and chip thereof. Background Art

[0002] Shielded gate trench MOSFET has the advantages of low internal resistance, large saturation current, strong output capability and low power consumption. It is widely used in digital circuits, analog circuits, power management, radio frequency applications and other fields.

[0003] However, in the related art, a larger overlap area between the control gate and the shielding gate leads to a larger input capacitance, thereby reducing the switching performance of the device. Summary of the invention

[0004] In order to solve the above technical problems, the embodiments of the present application provide a shielded gate trench MOSFET structure and a preparation method and chip thereof, which can reduce the capacitance of the shielded gate trench MOSFET device and optimize the switching characteristics of the shielded gate trench MOSFET device.

[0005] A first aspect of an embodiment of the present application provides a shielded gate trench MOSFET structure, comprising:

[0006] N-type substrate;

[0007] An N-type drift region, wherein the N-type drift region is a concave structure;

[0008] A first dielectric material layer is disposed in the groove of the N-type drift region;

[0009] a first N-type shielding gate polysilicon layer, a second N-type shielding gate polysilicon layer, a P-type shielding gate polysilicon layer, a first N-type control gate polysilicon layer and a second N-type control gate polysilicon layer, the first dielectric material layer wraps the first N-type shielding gate polysilicon layer, the second N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer, the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer are respectively located on both sides of the P-type shielding gate polysilicon layer and contact the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer is isolated from the first N-type shielding gate polysilicon layer by the first dielectric material layer, and the second N-type control gate polysilicon layer is isolated from the second N-type shielding gate polysilicon layer by the first dielectric material layer;

[0010] A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively arranged at two sides of the N-type drift region;

[0011] a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure;

[0012] A drain layer, wherein the drain layer is disposed on the back side of the N-type substrate;

[0013] a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region, and contacting the P-type shielding gate polysilicon layer through the shielding gate source through hole on the first dielectric material layer;

[0014] The gate layer contacts the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer through the control gate through hole on the first dielectric material layer.

[0015] In some embodiments, the depth of the P-type shield gate polysilicon layer is greater than the depth of the first N-type shield gate polysilicon layer and the depth of the second N-type shield gate polysilicon layer.

[0016] In some embodiments, the P-type shield gate polysilicon layer is a stepped structure, and the width of the shield gate polysilicon layer increases step by step from the drain layer to the source layer.

[0017] In some embodiments, when the P-type shield gate polysilicon layer is a P-type shield gate polysilicon layer comprising a step, the depth of the P-type shield gate polysilicon layer is greater than that of the first N-type shield gate polysilicon layer and the portion of the second N-type shield gate polysilicon layer is a convex structure, and the convex portion of the P-type shield gate polysilicon layer faces the N-type substrate.

[0018] In some embodiments, a maximum width of the P-type shield gate polysilicon layer is greater than a width of the first N-type shield gate polysilicon layer and a width of the second N-type shield gate polysilicon layer.

[0019] In some embodiments, a depth of the first N-type shield gate polysilicon layer is the same as a depth of the second N-type shield gate polysilicon layer.

[0020] In some embodiments, the depth of the first N-type shield gate polysilicon layer is greater than the depth of the first N-type control gate polysilicon layer; the depth of the second N-type shield gate polysilicon layer is greater than the depth of the second N-type control gate polysilicon layer.

[0021] In some embodiments, the P-type shield gate polysilicon layer is a rectangular structure, and a width of the P-type shield gate polysilicon layer is smaller than a width of the first N-type shield gate polysilicon layer and a width of the second N-type shield gate polysilicon layer.

[0022] A second aspect of the present application provides a method for preparing a shielded gate trench MOSFET structure, the method comprising:

[0023] Epitaxially forming an N-type drift layer on the front side of the N-type substrate;

[0024] Forming a first deep trench in the central region of the N-type drift layer by etching to form an N-type drift region with a concave structure;

[0025] forming a first dielectric material layer in the groove along the N-type drift region, and etching the first dielectric material layer to form a plurality of second deep grooves;

[0026] Filling N-type polysilicon material and P-type polysilicon material in the second deep trench to form a first N-type shielding gate polysilicon layer, a second N-type shielding gate polysilicon layer, a P-type shielding gate polysilicon layer, a first N-type control gate polysilicon layer and a second N-type control gate polysilicon layer, wherein the first N-type shielding gate polysilicon and the second N-type shielding gate polysilicon are respectively located on both sides of the P-type shielding gate polysilicon layer and are in contact with the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer is isolated from the first N-type shielding gate polysilicon layer by the first dielectric material layer, and the second N-type control gate polysilicon layer is isolated from the second N-type shielding gate polysilicon layer by the first dielectric material layer;

[0027] Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region;

[0028] Implanting N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and making the first P-type base region and the second P-type base region present an L-shaped structure, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure;

[0029] Continue to deposit dielectric material so that the first dielectric material layer wraps the first N-type shield gate polysilicon layer, the second N-type shield gate polysilicon layer, the P-type shield gate polysilicon layer, the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer;

[0030] Forming a shield gate source through hole and a control gate through hole on the first dielectric material layer, and forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region, wherein the source layer is in contact with the P-type shield gate polysilicon layer through the shield gate source through hole;

[0031] forming a gate layer in contact with the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer through the control gate gate through hole;

[0032] A drain layer is formed on the back side of the N-type substrate.

[0033] A third aspect of the embodiments of the present application further provides a chip, comprising the shielded gate trench MOSFET structure as described in any of the above embodiments.

[0034] The beneficial effects of the embodiments of the present application are as follows: by making the first N-type control gate polysilicon layer, the first N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, the second N-type shielding gate polysilicon layer and the second N-type control gate polysilicon layer sequentially arranged in parallel in the groove of the N-type drift region, and being wrapped by the first dielectric material layer, and setting the first N-type control gate polysilicon layer and the first N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer, and the second N-type control gate polysilicon layer and the second N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer, the first dielectric material layer is used to isolate the control gate and the shielding gate from electrical signals; in addition, the present application makes the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer. The crystalline silicon layers are in contact with the P-type shielding gate polysilicon layer, and then the reverse-biased PN junctions between the shielding gates (i.e., the reverse-biased PN junctions between the first N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, and the second N-type shielding gate polysilicon layer) are used to shield the low electric field of the P-type shielding gate polysilicon layer, so as to make the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer in a floating state, and then further isolate the shielding gate from the control gate (i.e., isolate the P-type shielding gate polysilicon layer from the first N-type control gate polysilicon layer, and isolate the P-type shielding gate polysilicon layer from the second N-type control gate polysilicon layer), and finally achieve the purpose of reducing the capacitance of the shielding gate trench MOSFET device and optimizing the switching characteristics of the shielding gate trench MOSFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 is a first structural schematic diagram of a shielded gate trench MOSFET structure provided in an embodiment of the present application;

[0036] Figure 2 is a structural schematic diagram of a comparative structure provided in an embodiment of the present application;

[0037] Figure 3 is a second structural schematic diagram of the shielded gate trench MOSFET structure provided in an embodiment of the present application;

[0038] Figure 4 is a third structural schematic diagram of the shielded gate trench MOSFET structure provided in an embodiment of the present application;

[0039] Figure 5 It is a schematic flow chart of a method for preparing a shielded gate trench MOSFET structure provided in an embodiment of the present application;

[0040] Figure 6 is a schematic diagram of forming an N-type drift layer on an N-type substrate layer provided in an embodiment of the present application;

[0041] Figure 7 is a schematic diagram of forming an N-type drift region provided in an embodiment of the present application;

[0042] Figure 8 It is a schematic diagram of forming a first N-type shield gate polysilicon layer, a second N-type shield gate polysilicon layer, a P-type shield gate polysilicon layer, a first N-type control gate polysilicon layer and a second N-type control gate polysilicon layer provided by an embodiment of the present application;

[0043] Fig. 9 It is a schematic diagram of forming a first P-type base region, a second P-type base region, a first N-type doping region and a second N-type doping region provided in an embodiment of the present application. DETAILED DESCRIPTION

[0044] In order to make the technical problems, technical solutions and beneficial effects to be solved by the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0045] It should be noted that when an element is referred to as being "fixed to" or "disposed on" another element, it can be directly on the other element or indirectly on the other element. When an element is referred to as being "connected to" another element, it can be directly connected to the other element or indirectly connected to the other element.

[0046] It should be understood that the orientation or position relationship indicated by terms such as "length", "width", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside" and "outside" are based on the orientation or position relationship shown in the drawings, and are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0047] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of this application, "plurality" means one or more, unless otherwise clearly and specifically defined.

[0048] Shielded gate MOSFET has the advantages of low internal resistance, large saturation current, strong output capacity, and low power consumption. It is widely used in digital circuits, analog circuits, power management, radio frequency applications, etc. However, when the shield gate and control gate are distributed in the left, middle, and right of the trench, usually, the middle gate acts as a shield gate with a longer downward distance and is connected to the source signal to assist in depleting the drift region and increase the breakdown voltage of the device. The gate structures on both sides are connected to the gate signal as the control gate structure. In this way, the doped silicon in the channel can be reverse biased, so that the device is turned on. However, under this structure, the larger overlap area between the control gate and the shield gate will lead to a larger input capacitance, thereby reducing the switching performance of the device.

[0049] Based on the above problems, an embodiment of the present application provides a shielded gate trench MOSFET structure, which can reduce the capacitance of the shielded gate trench MOSFET device and optimize the switching characteristics of the shielded gate trench MOSFET device.

[0050] See also Figure 1 As shown, the shielded gate trench MOSFET structure in the embodiment of the present application includes: an N-type substrate 210, an N-type drift region 220, a first dielectric material layer 310, a first N-type shielding gate polysilicon layer 411, a second N-type shielding gate polysilicon layer 412, a P-type shielding gate polysilicon layer 413, a first N-type control gate polysilicon layer 414, a second N-type control gate polysilicon layer 415, a first P-type base region 511, a second P-type base region 512, a first N-type doped region 513, a second N-type doped region 514, a drain layer 611, a source layer 612 and a gate layer 613.

[0051] The N-type drift region 220 is a concave structure, the first dielectric material layer 310 is arranged in the groove of the N-type drift region 220, the first dielectric material layer 310 wraps the first N-type shielding gate polysilicon layer 411, the second N-type shielding gate polysilicon layer 412, the P-type shielding gate polysilicon layer 413, the first N-type control gate polysilicon layer 414 and the second N-type control gate polysilicon layer 415, the first N-type shielding gate polysilicon layer 411 and the second N-type shielding gate polysilicon layer 412 are respectively located on both sides of the P-type shielding gate polysilicon layer 413 and contact the P-type shielding gate polysilicon layer 413, the first N-type control gate polysilicon layer 414 is isolated from the first N-type shielding gate polysilicon layer 411 by the first dielectric material layer 310, and the second N-type control gate polysilicon layer 415 is isolated from the second N-type shielding gate polysilicon layer 412 by the first dielectric material layer 310 isolation; the first P-type base region 511 and the second P-type base region 512 are in an L-shaped structure, and are respectively arranged on both sides of the N-type drift region 220; the first N-type doping region 513 is located on the horizontal part of the first P-type base region 511 of the L-shaped structure, and the second N-type doping region 514 is located on the horizontal part of the second P-type base region of the L-shaped structure; the drain layer 611 is arranged on the back side of the N-type substrate 210; the source layer 612 is in contact with the first N-type doping region 513, the second N-type doping region 514, the first P-type base region 511, and the second P-type base region 512, and is in contact with the P-type shielding gate polysilicon layer 413 through the shielding gate source through hole on the first dielectric material layer 310; the gate layer 613 is in contact with the first N-type control gate polysilicon layer 414 and the second N-type control gate polysilicon layer 415 through the control gate gate through hole on the first dielectric material layer 310.

[0052] In the embodiment of the present application, the first N-type control gate polysilicon layer 414, the first N-type shielding gate polysilicon layer 411, the P-type shielding gate polysilicon layer 413, the second N-type shielding gate polysilicon layer 412 and the second N-type control gate polysilicon layer 415 are sequentially arranged in parallel in the groove of the N-type drift region 220, and are wrapped by the first dielectric material layer 310, and the first N-type control gate polysilicon layer 414 and the first N-type shielding gate polysilicon layer 411 are isolated by the first dielectric material layer 310, and the second N-type control gate polysilicon layer 415 and the second N-type shielding gate polysilicon layer 412 are isolated by the first dielectric material layer 310, so as to achieve the isolation of the control gate and the shielding gate by the first dielectric material layer 310. In addition, the present application realizes the isolation of the control gate and the shielding gate by the first dielectric material layer 310. 2 are in contact with the P-type shielding gate polysilicon layer 413, and then the reverse-biased PN junction between the shielding gates (that is, the reverse-biased PN junctions between the first N-type shielding gate polysilicon layer 411, the P-type shielding gate polysilicon layer 413, and the second N-type shielding gate polysilicon layer 412) is used to shield the low electric field of the P-type shielding gate polysilicon layer 413, so as to make the first N-type shielding gate polysilicon layer 411 and the second N-type shielding gate polysilicon layer 412 in a floating state, and then further isolate the shielding gate from the control gate (that is, isolate the P-type shielding gate polysilicon layer 413 from the first N-type control gate polysilicon layer 414, and isolate the P-type shielding gate polysilicon layer 413 from the second N-type control gate polysilicon layer 415), finally achieving the purpose of reducing the capacitance of the shielded gate trench MOSFET device and optimizing the switching characteristics of the shielded gate trench MOSFET device.

[0053] like Figure 2 As shown, it is a comparative structure, which is different from the embodiment of the present application. Figure 1 Compared with the shielded gate trench MOSFET structure shown in the figure, the first N-type shielding gate polysilicon layer 411 and the second N-type shielding gate polysilicon layer 412 are merged into one N-type shielding gate polysilicon layer 410 , and there is no P-type shielding gate polysilicon layer 413 between the first N-type shielding gate polysilicon layer 411 and the second N-type shielding gate polysilicon layer 412 .

[0054] As shown in Table 1 below, Figure 1 The shielded gate trench MOSFET structure (improved structure) shown in Figure 2 The simulation comparison of the comparative structure shown in the figure shows that the FOM value of the advantageous parameter of the improved structure (i.e., BV 2 / Ron) increased by 2.78%, input capacitance Ciss decreased by 4.48%, output capacitance Coss decreased by 62.05%, and reverse transfer capacitance Crss decreased by 62.05%. That is, the shielded gate trench MOSFET structure provided in the embodiment of the present application can improve the FOM value of the device and improve the capacitance characteristics of the device. Among them, Ron in Table 1 is the on-resistance, Idsat is the saturation current, and BV is the breakdown voltage.

[0055] Table 1:

[0056]

[0057] In one embodiment of the present application, Figure 1 As shown, the depth of the P-type shielding gate polysilicon layer 413 is greater than the depth of the first N-type shielding gate polysilicon layer 411 and the depth of the second N-type shielding gate polysilicon layer 412 .

[0058] In one embodiment of the present application, Figure 1 As shown, the depth of the first N-type shield gate polysilicon layer 411 is the same as the depth of the second N-type shield gate polysilicon layer 412 .

[0059] In one embodiment of the present application, Figure 1 As shown, the depth of the first N-type shield gate polysilicon layer 411 is greater than the depth of the first N-type control gate polysilicon layer 414 .

[0060] In one embodiment of the present application, Figure 1 As shown, the depth of the second N-type shield gate polysilicon layer 412 is greater than the depth of the second N-type control gate polysilicon layer 415 .

[0061] In one embodiment of the present application, Figure 1 As shown, the P-type shielding gate polysilicon layer 413 is a rectangular structure, and the width of the P-type shielding gate polysilicon layer 413 is smaller than the width of the first N-type shielding gate polysilicon layer 411 and the width of the second N-type shielding gate polysilicon layer 412 .

[0062] In the embodiment of the present application, by setting the depth of the P-type shield gate polysilicon layer 413 to be greater than the depth of the first N-type shield gate polysilicon layer 411 and the depth of the second N-type shield gate polysilicon layer 412, the depth of the first N-type shield gate polysilicon layer 411 is greater than the depth of the first N-type control gate polysilicon layer 414, and the depth of the second N-type shield gate polysilicon layer 412 is greater than the depth of the second N-type control gate polysilicon layer 415, an auxiliary depletion drift region is realized, which is beneficial to improving the breakdown voltage of the device.

[0063] In one embodiment of the present application, Figure 1As shown, the P-type shielding gate polysilicon layer 413 is a rectangular structure, and the width of the P-type shielding gate polysilicon layer 413 is smaller than the width of the first N-type shielding gate polysilicon layer 411 and the width of the second N-type shielding gate polysilicon layer 412, so as to further isolate the shielding gate from the control gate (that is, isolate the P-type shielding gate polysilicon layer 413 from the first N-type control gate polysilicon layer 414, and isolate the P-type shielding gate polysilicon layer 413 from the second N-type control gate polysilicon layer 415), so as to reduce the capacitance of the shielding gate trench MOSFET device and optimize the switching characteristics of the shielding gate trench MOSFET device.

[0064] In one embodiment of the present application, in order to optimize the electric field of the N-type drift region 220 , the P-type shield gate polysilicon layer 413 is a stepped structure, and the width of the P-type shield gate polysilicon layer 413 increases step by step from the drain layer 611 to the source layer 612 .

[0065] like Figure 3 As shown, a P-type shielding gate polysilicon layer 413 including a step is provided in an embodiment of the present application. In this structure, the P-type shielding gate polysilicon layer 413 is deeper than the first N-type shielding gate polysilicon layer 411 and the second N-type shielding gate polysilicon layer 412, and the portion is a convex structure, and the convex portion of the P-type shielding gate polysilicon layer 413 faces the N-type substrate 210.

[0066] In one embodiment of the present application, Figure 3 As shown, when the P-type shield gate polysilicon layer 413 is a stepped structure, the maximum width of the P-type shield gate polysilicon layer 413 is greater than the width of the first N-type shield gate polysilicon layer 411 and the width of the second N-type shield gate polysilicon layer 412 to optimize the electric field of the N-type drift region 220 .

[0067] In one embodiment of the present application, Figure 1 As shown, the first N-type doping region 513 and the second N-type doping region 514 are both in contact with the first dielectric material layer 310. That is, the first N-type doping region 513 and the first N-type control gate polysilicon layer 414 are isolated by the first dielectric material layer 310, and the second N-type doping region 514 and the second N-type control gate polysilicon layer 415 are isolated by the first dielectric material layer 310.

[0068] In one embodiment of the present application, the first dielectric material layer 310 may be silicon dioxide or hafnium dioxide.

[0069] Since traditional shielded gate MOSFETs usually use silicon dioxide (SiO2) as the gate oxide layer of the shielded gate, this design can improve the device's withstand voltage strength to a certain extent, but limited by the physical characteristics of silicon dioxide's low dielectric constant, the thickness of the gate oxide layer of the shielded gate cannot be too thick, otherwise the shielded gate cannot deplete the drift region, and although a thin SiO2 layer can achieve a better auxiliary depletion effect, it will cause the thin SiO2 of the device to break down. In summary, the above two points lead to a low breakdown voltage of the device.

[0070] In order to increase the breakdown voltage of the device, Figure 4 As shown, in one embodiment of the present application, a second dielectric material layer 311 may also be arranged between the first dielectric material layer 310 and the first N-type shield gate polysilicon layer 411, between the first dielectric material layer 310 and the second N-type shield gate polysilicon layer 412, and between the first dielectric material layer 310 and the P-type shield gate polysilicon layer 413, and the dielectric constant of the second dielectric material layer 311 is greater than the dielectric constant of the first dielectric material layer 310.

[0071] For example, the first dielectric material layer 310 is made of silicon dioxide, and the second dielectric material layer 311 is made of hafnium dioxide.

[0072] In the embodiment of the present application, by arranging the second dielectric material layer 311 between the first dielectric material layer 310 and the first N-type shield gate polysilicon layer 411, between the first dielectric material layer 310 and the second N-type shield gate polysilicon layer 412, and between the first dielectric material layer 310 and the P-type shield gate polysilicon layer 413, and the dielectric constant of the second dielectric material layer 311 is greater than the dielectric constant of the first dielectric material layer 310, a composite dielectric material layer obtained by combining the first dielectric material layer 310 and the second dielectric material layer 311 is achieved to isolate the shield gate level (that is, the shield gate composed of the first N-type shield gate polysilicon layer 411, the second N-type shield gate polysilicon layer 412, and the P-type shield gate polysilicon layer 413) from the N-type drift region 220, and the same auxiliary depletion effect can be achieved with a thicker shield gate oxide layer, thereby enhancing the breakdown voltage at the bottom of the shield gate, and since the auxiliary depletion effect is close, the impact on the on-resistance of the device is low.

[0073] like Figure 5 As shown, the second aspect of the embodiment of the present application further provides a method for preparing a shielded gate trench MOSFET structure, and the preparation method includes: steps S100 to S900.

[0074] Step S100 : forming an N-type drift layer 211 by epitaxial growth on the front surface of the N-type substrate 210 .

[0075] like Figure 6As shown, an N-type drift layer 211 having a thickness greater than that of the N-type substrate 210 may be formed by epitaxial growth on the front side of the N-type substrate 210 .

[0076] In one embodiment of the present application, the thickness of the N-type substrate 210 is 1-5 um, and the concentration of the N-type doping ions is 1e 21 cm -3 The thickness of the N-type drift layer 211 is 5-20 um, and the concentration of the N-type doping ions is 1e 15 ~2e 17 cm -3 .

[0077] Step S200 , forming a first deep trench in the central region of the N-type drift layer 211 by etching to form an N-type drift region 220 with a concave structure.

[0078] like Figure 7 As shown, the depth of the first deep trench may be greater than half of the depth of the N-type drift layer 211 .

[0079] Step S300, forming a first dielectric material layer 310 along the groove of the N-type drift region 220, and etching the first dielectric material layer 310 to form a plurality of second deep grooves;

[0080] In step S400 , N-type polysilicon material and P-type polysilicon material are filled in the second deep trench to form a first N-type shield gate polysilicon layer 411 , a second N-type shield gate polysilicon layer 412 , a P-type shield gate polysilicon layer 413 , a first N-type control gate polysilicon layer 414 and a second N-type control gate polysilicon layer 415 .

[0081] In the present application embodiment, Figure 8 As shown, the first N-type shield gate polysilicon and the second N-type shield gate polysilicon are respectively located on both sides of the P-type shield gate polysilicon layer 413 and are in contact with the P-type shield gate polysilicon layer 413, the first N-type control gate polysilicon layer 414 and the first N-type shield gate polysilicon layer 411 are isolated by the first dielectric material layer 310, and the second N-type control gate polysilicon layer 415 and the second N-type shield gate polysilicon layer 412 are isolated by the first dielectric material layer 310.

[0082] In step S500 , P-type doping ions are implanted into the side of the N-type drift region 220 to form a first P-type base region 511 and a second P-type base region 512 . The first P-type base region 511 and the second P-type base region 512 are respectively disposed on both sides of the N-type drift region 220 .

[0083] In the present application embodiment, Fig. 9As shown, the width of the first P-type base region 511 and the second P-type base region 512 can be equal to the width of the two side portions of the N-type drift region 220 with a concave structure, and the depth of the first P-type base region 511 and the second P-type base region 512 can be less than the depth of the first control gate polysilicon layer and the depth of the second control gate polysilicon layer.

[0084] In step S600, N-type doping ions are injected into partial areas of the first P-type base region 511 and the second P-type base region 512 to form a first N-type doping region 513 and a second N-type doping region 514, and the first P-type base region 511 and the second P-type base region 512 are made into an L-shaped structure, the first N-type doping region 513 is located on the horizontal portion of the first P-type base region 511 of the L-shaped structure, and the second N-type doping region 514 is located on the horizontal portion of the second P-type base region 512 of the L-shaped structure.

[0085] like Fig. 9 As shown, in one embodiment of the present application, the first N-type doping region 513 and the second N-type doping region 514 are located on both sides of the first dielectric material layer 310, and the width of the first N-type doping region 513 and the second N-type doping region 514 is greater than half of the width of the first P-type base region 511 and the second P-type base region 512.

[0086] Step S700 , continue to deposit dielectric material so that the first dielectric material layer 310 wraps the first N-type shield gate polysilicon layer 411 , the second N-type shield gate polysilicon layer 412 , the P-type shield gate polysilicon layer 413 , the first N-type control gate polysilicon layer 414 and the second N-type control gate polysilicon layer 415 .

[0087] Step S800, forming a shield gate source through hole and a control gate through hole on the first dielectric material layer 310, and forming a source layer 612 in contact with the first N-type doping region 513, the second N-type doping region 514, the first P-type base region 511, and the second P-type base region 512, and the source layer 612 is in contact with the P-type shield gate polysilicon layer 413 through the shield gate source through hole;

[0088] Step S900 , forming a gate layer 613 in contact with the first N-type control gate polysilicon layer 414 and the second N-type control gate polysilicon layer 415 through the control gate through hole; and forming a drain layer 611 on the back side of the N-type substrate 210 .

[0089] like Figure 1 As shown, the control gate through hole is located on the left and right sides of the shield gate source through hole.

[0090] A third aspect of the embodiments of the present application further provides a chip, comprising the shielded gate trench MOSFET structure as described in any of the above embodiments.

[0091] The beneficial effects of the embodiments of the present application are as follows: by making the first N-type control gate polysilicon layer, the first N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, the second N-type shielding gate polysilicon layer and the second N-type control gate polysilicon layer sequentially arranged in parallel in the groove of the N-type drift region, and being wrapped by the first dielectric material layer, and setting the first N-type control gate polysilicon layer and the first N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer, and the second N-type control gate polysilicon layer and the second N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer, the first dielectric material layer is used to isolate the control gate and the shielding gate from electrical signals; in addition, the present application makes the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer to be isolated by the first dielectric material layer. The crystalline silicon layers are in contact with the P-type shielding gate polysilicon layer, and then the reverse-biased PN junctions between the shielding gates (i.e., the reverse-biased PN junctions between the first N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, and the second N-type shielding gate polysilicon layer) are used to shield the low electric field of the P-type shielding gate polysilicon layer, so as to make the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer in a floating state, and then further isolate the shielding gate from the control gate (i.e., isolate the P-type shielding gate polysilicon layer from the first N-type control gate polysilicon layer, and isolate the P-type shielding gate polysilicon layer from the second N-type control gate polysilicon layer), and finally achieve the purpose of reducing the capacitance of the shielding gate trench MOSFET device and optimizing the switching characteristics of the shielding gate trench MOSFET device.

[0092] Those skilled in the art can clearly understand that for the convenience and simplicity of description, only the division of the above-mentioned doping regions and devices is used as an example. In actual applications, the above-mentioned functions can be assigned to different doping regions and devices as needed, that is, the internal structure of the device is divided into different doping regions to complete all or part of the functions described above. The doping regions and devices in the embodiments can be integrated into one unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0093] In addition, the specific names of the doping regions and devices are only for the convenience of distinguishing each other and are not used to limit the scope of protection of the present application.

[0094] In the above embodiments, the description of each embodiment has its own emphasis. For parts that are not described or recorded in detail in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.

[0095] In addition, each doping region in each embodiment of the present application may be integrated into one unit, or each unit may exist physically separately, or two or more units may be integrated into one unit.

[0096] The above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit them. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present application, and should all be included in the protection scope of the present application.

Claims

1. A shielded gate trench MOSFET structure, characterized in that: include: N-type substrate; An N-type drift region, wherein the N-type drift region is a concave structure; A first dielectric material layer is disposed in the groove of the N-type drift region; a first N-type shielding gate polysilicon layer, a second N-type shielding gate polysilicon layer, a P-type shielding gate polysilicon layer, a first N-type control gate polysilicon layer and a second N-type control gate polysilicon layer, the first dielectric material layer wraps the first N-type shielding gate polysilicon layer, the second N-type shielding gate polysilicon layer, the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer, the first N-type shielding gate polysilicon layer and the second N-type shielding gate polysilicon layer are respectively located on both sides of the P-type shielding gate polysilicon layer and contact the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer is isolated from the first N-type shielding gate polysilicon layer by the first dielectric material layer, and the second N-type control gate polysilicon layer is isolated from the second N-type shielding gate polysilicon layer by the first dielectric material layer; A first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are in an L-shaped structure and are respectively disposed on two sides of the N-type drift region; a first N-type doping region and a second N-type doping region, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure; A drain layer, wherein the drain layer is disposed on the back side of the N-type substrate; a source layer, contacting the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region, and contacting the P-type shielding gate polysilicon layer through the shielding gate source through hole on the first dielectric material layer; The gate layer contacts the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer through the control gate through hole on the first dielectric material layer.

2. The shielded gate trench MOSFET structure according to claim 1, wherein: The depth of the P-type shielding gate polysilicon layer is greater than the depth of the first N-type shielding gate polysilicon layer and the depth of the second N-type shielding gate polysilicon layer.

3. The shielded gate trench MOSFET structure according to claim 2, characterized in that: The P-type shielding gate polysilicon layer is a stepped structure, and the width of the P-type shielding gate polysilicon layer increases step by step in a direction from the drain layer to the source layer.

4. The shielded gate trench MOSFET structure according to claim 3, characterized in that: When the P-type shielding gate polysilicon layer is a P-type shielding gate polysilicon layer including a step, the depth of the P-type shielding gate polysilicon layer is greater than that of the first N-type shielding gate polysilicon layer and the portion of the second N-type shielding gate polysilicon layer is a convex structure, and the convex portion of the P-type shielding gate polysilicon layer faces the N-type substrate.

5. The shielded gate trench MOSFET structure according to claim 3, characterized in that: The maximum width of the P-type shielding gate polysilicon layer is greater than the width of the first N-type shielding gate polysilicon layer and the width of the second N-type shielding gate polysilicon layer.

6. The shielded gate trench MOSFET structure according to any one of claims 1 to 5, characterized in that: The depth of the first N-type shielding gate polysilicon layer is the same as the depth of the second N-type shielding gate polysilicon layer.

7. The shielded gate trench MOSFET structure according to any one of claims 1 to 5, characterized in that: The depth of the first N-type shielding gate polysilicon layer is greater than the depth of the first N-type control gate polysilicon layer; the depth of the second N-type shielding gate polysilicon layer is greater than the depth of the second N-type control gate polysilicon layer.

8. The shielded gate trench MOSFET structure according to claim 1 or 2, characterized in that: The P-type shielding gate polysilicon layer is a rectangular structure, and the width of the P-type shielding gate polysilicon layer is smaller than the width of the first N-type shielding gate polysilicon layer and the width of the second N-type shielding gate polysilicon layer.

9. A method for preparing a shielded gate trench MOSFET structure, characterized in that: The preparation method comprises: Epitaxially forming an N-type drift layer on the front side of the N-type substrate; Forming a first deep trench in the central region of the N-type drift layer by etching to form an N-type drift region with a concave structure; forming a first dielectric material layer in the groove along the N-type drift region, and etching the first dielectric material layer to form a plurality of second deep grooves; Filling N-type polysilicon material and P-type polysilicon material in the second deep trench to form a first N-type shielding gate polysilicon layer, a second N-type shielding gate polysilicon layer, a P-type shielding gate polysilicon layer, a first N-type control gate polysilicon layer and a second N-type control gate polysilicon layer, wherein the first N-type shielding gate polysilicon and the second N-type shielding gate polysilicon are respectively located on both sides of the P-type shielding gate polysilicon layer and are in contact with the P-type shielding gate polysilicon layer, the first N-type control gate polysilicon layer is isolated from the first N-type shielding gate polysilicon layer by the first dielectric material layer, and the second N-type control gate polysilicon layer is isolated from the second N-type shielding gate polysilicon layer by the first dielectric material layer; Implanting P-type doping ions into the side of the N-type drift region to form a first P-type base region and a second P-type base region, wherein the first P-type base region and the second P-type base region are respectively arranged on both sides of the N-type drift region; Implanting N-type doping ions into partial regions of the first P-type base region and the second P-type base region to form a first N-type doping region and a second N-type doping region, and making the first P-type base region and the second P-type base region present an L-shaped structure, wherein the first N-type doping region is located on a horizontal portion of the first P-type base region of the L-shaped structure, and the second N-type doping region is located on a horizontal portion of the second P-type base region of the L-shaped structure; Continue to deposit dielectric material so that the first dielectric material layer wraps the first N-type shield gate polysilicon layer, the second N-type shield gate polysilicon layer, the P-type shield gate polysilicon layer, the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer; Forming a shield gate source through hole and a control gate through hole on the first dielectric material layer, and forming a source layer in contact with the first N-type doping region, the second N-type doping region, the first P-type base region, and the second P-type base region, wherein the source layer is in contact with the P-type shield gate polysilicon layer through the shield gate source through hole; forming a gate layer in contact with the first N-type control gate polysilicon layer and the second N-type control gate polysilicon layer through the control gate gate through hole; A drain layer is formed on the back side of the N-type substrate.

10. A chip, characterized in that: It comprises the shielded gate trench MOSFET structure as described in any one of claims 1 to 8.

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