Semiconductor Structure and Method of Manufacturing the Same

Abstract

The present application discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: forming a dummy gate on the NMOS device region and the PMOS device region included in the substrate; forming a functional layer on the sidewalls of the dummy gate and on the substrate, and the region outside the PMOS device region under the dummy gate and the functional layer on the sidewalls of the dummy gate is a reserved region; forming a photoresist layer covering the NMOS device region and having an opening on the PMOS device region after the functional layer is formed; using the photoresist layer as a mask to etch the functional layer until the surface of the reserved region is exposed, and then removing the photoresist layer; forming a preliminary trench in the reserved region. Among them, the functional layer is formed by cyclically executing a first step and a second step. The first step includes forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes introducing an etching gas downward from above the substrate to etch the sub-functional layer until the portion of the sub-functional layer on the top of the dummy gate is etched off. The present application achieves the same height of the dummy gates of the NMOS device and the PMOS device at a lower cost.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the process of manufacturing semiconductor structures, in order to improve the drive current of PMOS (i.e., P-type metal-oxide-semiconductor) devices, the germanium-silicon epitaxy technology is widely used. In the germanium-silicon epitaxy technology, after the NMOS (i.e., N-type metal-oxide-semiconductor) devices are covered by a photoresist layer, germanium-silicon trenches are only formed in the substrate of the PMOS devices. In the existing technology for forming germanium-silicon trenches, the dummy gates of the PMOS devices will be severely damaged, resulting in different heights of the dummy gates of the NMOS devices and the PMOS devices. In this way, the chemical mechanical polishing (CMP) of the subsequent formed interlayer dielectric (ILD) is affected, and the higher dummy gate of the NMOS device is also likely to cause gaps in the subsequent formed interlayer dielectric. Summary of the Invention

[0003] In view of the above problems, this application provides a semiconductor structure and a manufacturing method thereof, aiming to achieve equal heights of the dummy gates of the NMOS devices and the PMOS devices at a lower cost.

[0004] According to the first aspect of the present invention, a manufacturing method of a semiconductor structure is provided, including:

[0005] Providing a substrate, the substrate including an NMOS device region and a PMOS device region;

[0006] Forming dummy gates on the NMOS device region and the PMOS device region;

[0007] Forming a functional layer on the sidewalls of the dummy gates and on the substrate, the region of the PMOS device region outside the lower part of the dummy gates and the functional layer on the sidewalls of the dummy gates being a reserved region;

[0008] After the functional layer is formed, forming a photoresist layer covering the NMOS device region and having an opening in the PMOS device region;

[0009] Using the photoresist layer as a mask to etch the functional layer until the surface of the reserved region is exposed, and then removing the photoresist layer;

[0010] Forming a preliminary trench in the reserved region;

[0011] Among them, the functional layer is formed on the sidewalls of the dummy gate and on the substrate by cyclically performing the first step and the second step. The first step includes: forming a sub-functional layer covering the dummy gate and the substrate. The second step includes: introducing an etching gas downward from above the substrate to etch the sub-functional layer until the portion of the sub-functional layer on top of the dummy gate is etched away.

[0012] Optionally, in the first step, any one of atomic layer deposition process, chemical vapor deposition process, and physical vapor deposition process is used to form the sub-functional layer.

[0013] Optionally, the thickness of the sub-functional layer is 20 Å - 50 Å.

[0014] Optionally, in the second step, by controlling the flow rate of the etching gas, the time duration for etching away the portion of the sub-functional layer on top of the dummy gate is 4 s - 8 s.

[0015] Optionally, the material of the sub-functional layer is silicon nitride, the dummy gate includes a top protection layer at the top, and the material of the top protection layer is silicon oxide. The etching gas used in the second step is a plasma gas mixed with carbon tetrafluoride and fluoromethane.

[0016] Optionally, the material of the functional layer is silicon nitride, the dummy gate includes a top protection layer at the top, and the material of the top protection layer is silicon oxide. Using the photoresist layer as a mask for etching the functional layer includes: dry etching the functional layer with a plasma gas mixed with carbon tetrafluoride and fluoromethane as the etching gas.

[0017] Optionally, the manufacturing method further includes:

[0018] forming a surface protection layer on the dummy gate and on the substrate before forming the functional layer, and the subsequently formed functional layer covers the portions of the surface protection layer on the sidewalls of the dummy gate and on the substrate;

[0019] after using the photoresist layer as a mask for etching the functional layer, using the photoresist layer as a mask for etching the surface protection layer. Among them, the functional layer is etched until the portion of the surface protection layer on the reserved area is exposed, and the surface protection layer is etched until the surface of the reserved area is exposed.

[0020] Optionally, the thickness of the surface protection layer is less than the thickness of the functional layer.

[0021] Optionally, the manufacturing method further includes: widening the preparation trench by etching to form a sigma trench for growing silicon germanide.

[0022] According to a second aspect of the present invention, there is provided a semiconductor structure manufactured by any of the manufacturing methods described in the first aspect.

[0023] The unexpected technical effect of this application is:

[0024] According to the manufacturing method of the semiconductor structure provided by the embodiment of the present application, after forming a functional layer on the sidewalls of the dummy gate and on the substrate, a photoresist layer covering the NMOS device region and having an opening on the PMOS device region is formed. Then, the functional layer is etched using the photoresist layer as a mask until the surface of the reserved region in the PMOS device region is exposed. During this process, there is no functional layer on the top of the dummy gate in the PMOS device region that can be etched, so there is basically no etching phenomenon on the top of the dummy gate in the PMOS device region. After that, after removing the photoresist layer, a preparatory trench is formed in the reserved region of the PMOS device region. The dummy gate in the NMOS device region and the dummy gate in the PMOS device region will be etched in the same way during the formation of the preparatory trench because there is no functional layer on their respective tops. In this way, the dummy gates in the NMOS device region and the PMOS device region can basically achieve the same height. Among them, the functional layer is formed on the sidewalls of the dummy gate and on the substrate by repeatedly executing the first step and the second step. The first step includes: forming a sub-functional layer covering the dummy gate and the substrate. The second step includes: introducing an etching gas downward from above the substrate to etch the sub-functional layer until the part of the sub-functional layer on the top of the dummy gate is etched away. The parts of the sub-functional layer on the sidewalls of the dummy gate and on the substrate have an etching rate lower than that of the part of the sub-functional layer on the top of the dummy gate because the contact angle with the etching gas is smaller than that of the part of the sub-functional layer on the top of the dummy gate. Therefore, when the part of the sub-functional layer on the top of the dummy gate is etched away, the parts of the sub-functional layer on the sidewalls of the dummy gate and on the substrate are partially retained. This process of forming a patterned functional layer does not require the use of a high-cost mask, so the dummy gates of the NMOS device and the PMOS device are basically made to have the same height at a lower cost.

[0025] Further, in the first step, any one of atomic layer deposition process, chemical vapor deposition process, and physical vapor deposition process is used to form the sub-functional layer, so as to ensure that the parts of the formed sub-functional layer on the sidewalls of the dummy gate and on the substrate have the same thickness as the part on the top of the dummy gate. In this way, after the second step is executed, the difference in the contact angles of different parts of the sub-functional layer with the etching gas can be used to preferably etch away the part of the sub-functional layer on the top of the dummy gate while partially retaining the parts of the sub-functional layer on the sidewalls of the dummy gate and on the substrate.

[0026] Further, the thickness of the sub-functional layer is 20 Å - 50 Å. The reason for such a setting is as follows: If the thickness of the sub-functional layer is too small, then in order to form a functional layer with a preset thickness in the reserved area of the defined PMOS device region, the first step and the second step need to be cycled multiple times, thereby increasing the time required for forming the functional layer during the multiple alternating processes between the first step and the second step. On the contrary, if the thickness of the sub-functional layer is too large, then the second step needs to be executed for a long time and / or use a large etching gas flow rate to etch away the part of the sub-functional layer on top of the dummy gate. Executing the second step for a long time and using a large etching gas flow rate will both cause the etching gas to accumulate in the middle of the dummy gate, thereby affecting the etching uniformity of the part of the sub-functional layer on the sidewalls and the substrate of the dummy gate, and further affecting the quality of the formed functional layer.

[0027] Further, in the second step, by controlling the flow rate of the etching gas, the time duration for etching away the part of the sub-functional layer with a thickness of 20 Å - 50 Å on top of the dummy gate is 4 s - 8 s. The reason for such a setting is as follows: If the time duration for executing the second step once is too long, it will increase the time required for forming the functional layer. On the contrary, if the time duration for executing the second step once is too short, for a sub-functional layer with a certain thickness, the flow rate of the etching gas needs to be increased. However, too large a flow rate of the etching gas will cause the etching gas to quickly pass over the top of the dummy gate and accumulate in the middle of the dummy gate, thereby reducing the etching rate of the sub-functional layer on top of the dummy gate, and the etching gas accumulated in the middle of the dummy gate will also cause uneven etching of the part of the sub-functional layer on the sidewalls and the substrate of the dummy gate. BRIEF DESCRIPTION OF THE DRAWINGS

[0028] Through the following description of the embodiments of the present application with reference to the drawings, the above and other objects, features, and advantages of the present application will become clearer. In the drawings:

[0029] Figure 1a A cross-sectional schematic diagram of a substrate and a dummy gate completely covered by a photoresist layer in the prior art is shown;

[0030] Figure 1b A cross-sectional schematic diagram of a substrate and a dummy gate covered by a photoresist layer in the NMOS device region in the prior art is shown;

[0031] Figure 1c A cross-sectional schematic diagram of a substrate and a dummy gate with the surface of the reserved area in the PMOS device region exposed in the prior art is shown;

[0032] Figure 1d A cross-sectional schematic diagram of a substrate and a dummy gate with a preparatory trench etched in the PMOS device region in the prior art is shown;

[0033] Figure 1e A cross-sectional schematic diagram of a substrate and a dummy gate with a sigma trench etched in the PMOS device region in the prior art is shown;

[0034] Figure 1f Shows a cross-sectional schematic diagram of a substrate and a dummy gate after removing a photoresist layer in the prior art;

[0035] Figure 1g Shows a cross-sectional schematic diagram of a substrate and a dummy gate after forming a germanium-silicon trench in a PMOS device region in the prior art;

[0036] Figure 1h Shows a cross-sectional schematic diagram of a substrate and a dummy gate after removing a functional layer in the prior art;

[0037] Figure 2a Shows a schematic diagram of a dummy gate on a PMOS device region in a semiconductor structure manufactured in the prior art;

[0038] Figure 2b Shows a schematic diagram of a dummy gate on an NMOS device region in a semiconductor structure manufactured in the prior art;

[0039] Figure 3a Shows a schematic diagram of a dummy gate on a PMOS device region after performing an etching process to expose the surface of a reserved area during the process of manufacturing a semiconductor structure in the prior art;

[0040] Figure 3b Shows a schematic diagram of a dummy gate on a PMOS device region after performing an etching process to form a preparatory trench during the process of manufacturing a semiconductor structure in the prior art;

[0041] Figure 4 Shows a schematic diagram of an intermediate dielectric layer formed based on a semiconductor structure manufactured in the prior art;

[0042] Figure 5 Shows a flowchart of a manufacturing method of a semiconductor structure according to an embodiment of the present application;

[0043] Figure 6a Shows a cross-sectional schematic diagram of an exemplary substrate and a dummy gate according to an embodiment of the present application;

[0044] Figure 6b Shows a cross-sectional schematic diagram of an exemplary structure formed after first performing a first step according to an embodiment of the present application;

[0045] Figure 6c Shows a cross-sectional schematic diagram of an exemplary structure formed after first performing a second step according to an embodiment of the present application;

[0046] Figure 6d Shows a cross-sectional schematic diagram after forming an exemplary functional layer according to an embodiment of the present application;

[0047] Figure 6eShows a schematic cross-sectional view of a substrate and a dummy gate after an NMOS device region covered by a photoresist layer according to an embodiment of the present application;

[0048] Figure 6f Shows a schematic cross-sectional view of a substrate and a dummy gate after the surface of a reserved region of a PMOS device region according to an embodiment of the present application is exposed;

[0049] Figure 6g Shows a schematic cross-sectional view of a substrate and a dummy gate after the photoresist layer is removed according to an embodiment of the present application;

[0050] Figure 6h Shows a schematic cross-sectional view of a substrate and a dummy gate after a preparation trench is etched in a PMOS device region according to an embodiment of the present application;

[0051] Figure 6i Shows a schematic cross-sectional view of a substrate and a dummy gate after a sigma trench is etched in a PMOS device region according to an embodiment of the present application;

[0052] Figure 6j Shows a schematic cross-sectional view of a substrate and a dummy gate after a germanium-silicon trench is formed in a PMOS device region according to an embodiment of the present application.

[0053] Explanation of reference numerals: 11 - Substrate; 12 - Dummy gate; 12a - Gate conductive layer; 12b - Gate insulating layer; 12c - Top protective layer; 12d - Sidewall; 13 - Functional layer; 13' - Sub-functional layer; 14 - Surface protective layer; 15 - Photoresist layer; 16 - Bottom anti-reflection coating; 17 - Preparation trench; 18 - Sigma trench; 19 - Germanium-silicon trench. Detailed implementation manners

[0054] The present application will be described in more detail below with reference to the accompanying drawings. In each of the drawings, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0055] The present application can be presented in various forms, and some examples will be described below.

[0056] In germanium-silicon epitaxy technology, after the NMOS device is covered by a photoresist layer, germanium-silicon trenches are only formed in the substrate of the PMOS device, so as to increase the compressive stress of the PMOS device and improve the drive current of the PMOS device. Figures 1a to 1h Shows the process of forming germanium-silicon trenches in the prior art. The following will be combined with Figures 1a to 1h Introduce the prior art of forming germanium-silicon trenches in detail.

[0057] As Figure 1aAs shown, the substrate 11 includes an NMOS device region and a PMOS device region. Pseudo-gates 12 are respectively formed on the NMOS device region and the PMOS device region. A functional layer 13 is formed on the substrate 11 and on the pseudo-gates 12. The area of the PMOS device region outside the pseudo-gates 12 and under the sidewall functional layer 13 of the pseudo-gates 12 is a reserved area. Figure 1a In [reference number], the reserved area is framed by a dashed box. In some examples, a surface protection layer 14 is first formed on the substrate 11 and on the pseudo-gates 12, and then the functional layer 13 is formed. The later-formed functional layer 13 covers the previously formed surface protection layer 14. The material used for the functional layer 13 can be silicon nitride, and its function is to control the position of the reserved area in the PMOS device region by adjusting its own thickness. The material used for the surface protection layer 14 can be silicon oxide (SiO2), and its function is to strengthen the protection of the pseudo-gates 12.

[0058] The pseudo-gate 12 includes a stacked structure formed by laminating a gate conductor layer 12a, a gate insulating layer 12b, and a top protection layer 12c, and sidewalls 12d provided on the sidewalls of the stacked structure. The combination of the top protection layer 12c and the sidewalls 12d serves to protect the gate conductor layer 12a and the gate insulating layer 12b. In this way, combined with the protection function of the surface protection layer 14, it is ensured that the gate conductor layer 12a and the gate insulating layer 12b will not be damaged during the formation of the germanium-silicon trench. The material used for the gate conductor layer 12a can be polysilicon, the material used for the gate insulating layer 12b can be silicon nitride, the material used for the top protection layer 12c can be silicon oxide, and the material used for the sidewalls 12d can be silicon nitride.

[0059] During the formation of the germanium-silicon trench, a photoresist layer 15 that only covers the functional layer 13 on the NMOS device region is first formed as shown in Figure 1b . Specifically, a photoresist layer 15 that covers the entire functional layer 13 can be first formed as shown in Figure 1a . Then, through exposure and development, the photoresist layer 15 on the PMOS device region is etched away, thereby forming a photoresist layer 15 that covers the functional layer 13 on the NMOS device region and has an opening on the PMOS device region. In some examples, a bottom anti-reflection coating 16 that covers the entire functional layer 13 is first formed as shown in Figure 1a . The later-formed photoresist layer 15 covers the previously formed bottom anti-reflection coating 16. Therefore, in order to achieve that only the functional layer 13 on the NMOS device region is covered, exposure and development of the photoresist layer 15 are combined with etching of the bottom anti-reflection coating 16.

[0060] Next, using as shown in Figure 1bThe etching of the functional layer 13 and the surface protection layer 14 is performed on the photoresist layer 15 shown and the bottom anti-reflection coating 16 present in some examples. During this etching process, since only the functional layer 13 on the NMOS device region is covered, the functional layer 13 and the surface protection layer 14 on the NMOS device region are not etched, while the functional layer 13 and the surface protection layer 14 on the PMOS device region are etched. Specifically, first, the etching of the functional layer 13 is carried out until a part of the surface protection layer 14 reserved in the PMOS device region is exposed, and then the etching of the surface protection layer 14 is carried out until the surface of the reserved region in the PMOS device region is exposed. It should be understood that during the etching process of the functional layer 13 carried out first, the functional layer 13 on the top of the dummy gate 12 in the PMOS device region will be etched off simultaneously, and during the etching process of the surface protection layer 14 carried out later, the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device region will be etched off simultaneously, so that as Figure 1c shown, the dummy gate 12 on the PMOS device region will be exposed after this process.

[0061] Next, dry etching is carried out through a plasma gas to form a preliminary trench 17 as shown in Figure 1d . It should be noted that Figure 1d only one preliminary trench 17 is shown, and in practice, preliminary trenches 17 can be formed in the reserved regions on both sides of each dummy gate 12 on the PMOS device region. Specifically, the etching rate of the plasma gas for dry etching on silicon is greater than that on silicon nitride and silicon oxide, and since the functional layer 13 on the NMOS device region is covered by the photoresist layer 15, only the functional layer 13 made of silicon nitride material, the surface protection layer 14 made of silicon oxide material, the top protection layer 12c and the reserved region made of silicon material on the PMOS device region can be etched during this dry etching process, and the etched parts of the functional layer 13, the surface protection layer 14 and the top protection layer 12c are less compared with the reserved region.

[0062] After that, wet etching is used to widen the preliminary trench 17 as shown in Figure 1d to form a sigma trench 18 as shown in Figure 1e , and as shown in Figure 1f the photoresist layer 15 as shown in Figure 1e is removed through an ashing process and the bottom anti-reflection coating 16 present in some examples is removed, and silicon germanide is grown in the sigma trench 18 as shown in Figure 1f to form a germanium silicon trench 19 as shown in Figure 1g , thus completing the formation process of the germanium silicon trench 19. Finally, as shown in Figure 1h the functional layer 13 used to define the reserved region on each dummy gate 12 as shown in Figure 1g is removed.

[0063] Based on the above introduction to the formation process of the germanium-silicon trench 19, it can be known that: during the etching process shown in Figure 1c for exposing the surface of the reserved area and during the etching process shown in Figure 1d for forming the preliminary trench 17, since there is no photoresist layer 15 on the PMOS device area, the functional layer 13 on the top of the dummy gate 12 and the surface protection layer 14 existing in some examples on the PMOS device area will be etched away, and then a part of the top protection layer 12c and the sidewall 12d included in the dummy gate 12 will be etched away, so that the dummy gate 12 on the PMOS device area is damaged. For the example with the surface protection layer 14, in the finally formed semiconductor structure shown in Figure 1h , there are a top protection layer 12c and a surface protection layer 14 on the top of the dummy gate 12 in the NMOS device area. Therefore, the damage of the dummy gate 12 on the PMOS device area results in different heights of silicon oxide on the top of the dummy gates 12 in the PMOS device area and the NMOS device area; for the example without the surface protection layer 14, in the finally formed semiconductor structure, there is a complete top protection layer 12c on the top of the dummy gate 12 in the NMOS device area. Therefore, the damage of the dummy gate 12 on the PMOS device area results in a height difference between the dummy gates 12 in the PMOS device area and the NMOS device area.

[0064] Figure 2a And Figure 2b respectively show a schematic diagram of the dummy gate on the PMOS device area and a schematic diagram of the dummy gate on the NMOS device area in a semiconductor structure in an example with the surface protection layer 14 manufactured by the above technology. Among them, Figure 2a indicates that the silicon oxide on the top of the dummy gate on the PMOS device area is 10.2 nm high, Figure 2b indicates that the silicon oxide on the top of the dummy gate on the NMOS device area is 32.1 nm high. It can be seen that the silicon oxide on the top of the dummy gates in the PMOS device area and the NMOS device area has different heights.

[0065] Figure 3a And Figure 3b respectively show schematic diagrams of the dummy gate on the PMOS device area at different stages in another example with the surface protection layer 14 manufactured by the above technology. Among them, Figure 3a shows a schematic diagram of the dummy gate on the PMOS device area after the execution of the etching process for exposing the surface of the reserved area, Figure 3a and the silicon oxide on the top of the dummy gate on the PMOS device area is 32.6 nm high; Figure 3b shows a schematic diagram of the dummy gate on the PMOS device area after the execution of the etching process for forming the preliminary trench, Figure 3bThe silicon oxide on the top of the dummy gate in the PMOS device region is 13.4 nm thick. It can be seen that during the etching process for forming the preliminary trench, the silicon oxide on the top of the dummy gate in the PMOS device region will have a significant reduction in height.

[0066] It should be noted that Figure 1h In the subsequent steps of the semiconductor structure shown, doping ions are to be implanted into the substrate 11 to form source regions and drain regions on both sides of the dummy gate 12. After that, an interlayer dielectric layer is to be formed above the source regions, drain regions, and the dummy gate 12, and the dummy gate 12 is to be removed from the interlayer dielectric layer and replaced with a high-k metal gate structure. Therefore, after the interlayer dielectric layer is formed, it is to be polished to a flat surface to expose the gate insulating layer 12b of the dummy gate 12. In the example where there is a surface protection layer 14, the silicon oxides on the tops of the dummy gates 12 in the PMOS device region and the NMOS device region have different heights, and in the example where there is no surface protection layer 14, the height difference between the dummy gates 12 in the PMOS device region and the NMOS device region will both cause the chemical mechanical polishing loading of the subsequent interlayer dielectric layer. In addition, in the example where there is a surface protection layer 14, the silicon oxide on the top of the dummy gate 12 in the NMOS device region is relatively high, and in the example where there is no surface protection layer 14, the dummy gate 12 in the NMOS device region is relatively high, which are both likely to cause gaps in the interlayer dielectric layer. Figure 4 Shown is that in the example where there is a surface protection layer 14, the relatively high silicon oxide on the top of the dummy gate 12 in the NMOS device region causes gaps framed by the white dotted line in the formed interlayer dielectric layer.

[0067] For the above reasons, the embodiments of the present application provide a manufacturing method for a semiconductor structure. Figure 5 Shown is the flowchart of the manufacturing method for the semiconductor structure provided by the embodiments of the present application. As Figure 5 shown, the manufacturing method includes:

[0068] Step S110: Provide a substrate, where the substrate includes an NMOS device region and a PMOS device region;

[0069] Step S120: Form dummy gates on the NMOS device region and the PMOS device region;

[0070] Step S130: Form a functional layer on the sidewalls of the dummy gates and on the substrate by repeatedly executing a first step and a second step. The area outside the dummy gate and the functional layer on the sidewall of the dummy gate in the PMOS device region is a reserved area. Among them, the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: introducing an etching gas from the upper direction of the substrate to etch the sub-functional layer until the part of the sub-functional layer on the top of the dummy gate is etched away;

[0071] Step S140: After the functional layer is formed, form a photoresist layer covering the NMOS device region and having an opening in the PMOS device region;

[0072] Step S150: Using the photoresist layer as a mask, etch the functional layer until the surface of the reserved area is exposed, and then remove the photoresist layer.

[0073] Step S160: Form a preliminary trench in the reserved area.

[0074] It should be noted that after forming the functional layer in step S130, a reserved area is defined in the PMOS device region. In step S150, etching the functional layer until the surface of the reserved area is exposed is for directly etching the reserved area in step S160 to form a trench for growing silicon germanide in the reserved area. The reserved area is etched in step S160 by using high-selectivity etching, that is, the etching rate for the reserved area is greater than that for the functional layer and the dummy gate, so that although the functional layer and the dummy gate will be etched during the formation of the preliminary trench, the etched part is less compared with the substrate.

[0075] It should be understood that the less part of the dummy gate etched during the formation of the preliminary trench can ensure that the damage degree of the dummy gate is less, thus not affecting the performance of the high-k metal gate structure for replacing the dummy gate later. However, the damage degree of the dummy gate still exists as shown in Figure 3a and Figure 3b shown.

[0076] In the embodiment of the present application, since the functional layer formed by cyclically executing the first step and the second step is only located on the sidewalls of the dummy gate and on the substrate, using the photoresist layer as a mask to etch the functional layer basically will not cause etching on the top of the dummy gate in the PMOS device region. In this way, when the photoresist layer is removed, there is basically no difference between the dummy gates in the NMOS device region and the PMOS device region. After that, during the process of forming the preliminary trench after removing the photoresist layer, since there is no functional layer on the top of the dummy gate in both the NMOS device region and the PMOS device region, the dummy gates in the NMOS device region and the PMOS device region will be etched in the same way, so that the dummy gates in the NMOS device region and the PMOS device region can be basically of the same height. Among them, during the process of cyclically executing the first step and the second step to form the functional layer, there is no need to use a high-cost mask, so the dummy gates of the NMOS device and the PMOS device are basically of the same height at a relatively low cost.

[0077] Figures 6a to 6j are the schematic diagrams of the steps of a manufacturing method of a semiconductor structure provided by the embodiment of the present application. The following will combine Figure 5 and Figures 6a to 6j to describe in detail the manufacturing method of the semiconductor structure provided by the embodiment of the present application.

[0078] The substrate provided in step S110 and the dummy gate formed in step S120 can be as shown in Figure 6a shown. Refer to Figure 6a, the substrate 11 includes an NMOS device region and a PMOS device region. The dummy gate 12 includes a stacked structure formed by laminating a gate conductor layer 12a, a gate insulating layer 12b, and a top protective layer 12c, and sidewalls 12d provided on the sidewalls of the stacked structure.

[0079] The sub-functional layer formed by first performing the first step in step S130 can be as Figure 6b shown. Referring to Figure 6b , the first step can use any one of atomic layer deposition process, chemical vapor deposition process, and physical vapor deposition process to form the sub-functional layer 13', so as to ensure that the part of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11 has the same thickness as the part on the top of the dummy gate 12. In this way, after the second step in step S130 is executed, the part of the sub-functional layer 13' on the top of the dummy gate 12 can be etched away well by using the difference in the contact angles of different parts of the sub-functional layer 13' with the etching gas, while the part of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11 is partially retained.

[0080] The thickness of the sub-functional layer 13' formed by performing the first step once should not be too small or too large. If the thickness of the sub-functional layer 13' is too small, then in order to form the functional layer 13 with a preset thickness that defines the reserved area in the PMOS device region, the first step and the second step need to be cycled many times, thus increasing the formation time of the functional layer 13 during the many alternating processes between the first step and the second step; conversely, if the thickness of the sub-functional layer 13' is too large, then the second step needs to be executed for a long time and / or use a large etching gas flow rate to etch away the part of the sub-functional layer 13' on the top of the dummy gate 12. Executing the second step for a long time and using a large etching gas flow rate will both cause the etching gas to accumulate in the middle of the dummy gate 12, thereby affecting the etching uniformity of the part of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11, and further affecting the quality of the formed functional layer 13. Therefore, in the embodiments of the present application, the sub-functional layer 13' with a thickness of 20 Å - 50 Å is formed by performing the first step once.

[0081] The remaining part of the sub-functional layer 13' after first performing the second step in step S130 can be as Figure 6c shown. Referring to Figure 6c , the parts of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11 are both thinned due to the etching process in the second step, and the part of the sub-functional layer 13' on the top of the dummy gate 12 is removed due to the etching process in the second step.

[0082] The duration of executing the second step once should neither be too small nor too large. If the duration of executing the second step once is too large, it will increase the time consumption for forming the functional layer 13. On the contrary, if the duration of executing the second step once is too small, for a sub-functional layer 13' with a certain thickness, the flow rate of the etching gas needs to be increased. Since too large a flow rate of the etching gas will cause the etching gas to quickly pass over the top of the dummy gate 12 and gather in the middle of the dummy gate 12, thereby reducing the etching rate of the sub-functional layer 13' on the top of the dummy gate 12, and the etching gas gathered in the middle of the dummy gate 12 will also cause uneven etching of part of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and the substrate 11. Therefore, in the embodiment of the present application, when a sub-functional layer 13' with a thickness of 20 Å - 50 Å is formed in the first step, in the second step, by controlling the flow rate of the etching gas, the time duration for etching off the part of the sub-functional layer 13' on the top of the dummy gate 12 is 4 s - 8 s.

[0083] The material of the above-mentioned sub-functional layer 13' can be silicon nitride, and the dummy gate 12 can include a top protection layer 12c at the top as described above, and the material of the top protection layer 12c is silicon oxide. In this way, for the sub-functional layer 13' covering the dummy gate 12 and the substrate 11 formed in the first step, a mixed gas of carbon tetrafluoride (CF4) and fluoromethane (CH3F) can be used as the etching gas for etching in the second step. Since the etching rate of the mixed gas of carbon tetrafluoride and fluoromethane for silicon nitride is much greater than that for silicon oxide, the top protection layer 12c included in the dummy gate 12 can be basically not damaged when the part of the sub-functional layer 13' on the top of the dummy gate 12 is etched off.

[0084] In some examples, in the first step, a sub-functional layer 13' with a thickness of 30 Å is formed by performing a deposition process for 4 - 8 s; in the second step, a mixed gas of carbon tetrafluoride and fluoromethane is used as the etching gas to etch the sub-functional layer 13'. Specifically, since the contact angle between the part of the sub-functional layer 13' on top of the dummy gate 12 and the etching gas is relatively large, the part of the sub-functional layer 13' on top of the dummy gate 12 is more likely to come into contact with the etching gas, so the part of the sub-functional layer 13' on top of the dummy gate 12 is etched faster; while the proportion of the etching gas entering the space between the dummy gates 12 is relatively small, so the parts of the sub-functional layer 13' on the sidewalls of the dummy gate 12 and on the substrate 11 are etched slower. Among them, the part of the sub-functional layer 13' on the substrate 11 is etched even slower because the etching gas is introduced for a short time and thus comes into contact with a smaller amount of etching gas. In some experiments of this example, when the part of the sub-functional layer 13' on top of the dummy gate 12 is etched away, the part of the sub-functional layer 13' on the substrate 11 remains a thickness of about 15 Å, and the part of the sub-functional layer 13' on the sidewalls of the dummy gate 12 remains a thickness greater than 10 Å. When the thickness of the formed functional layer 13 on the sidewalls of the dummy gate 12 needs to be 60 Å, the number of times the first step and the second step need to be cyclically executed is 6 times, that is, after the first step and the second step are successively executed once, the successive execution process of the first step and the second step is repeated until the successive execution process of the first step and the second step is carried out 6 times. Figure 6d Shows the multiple cyclic executions Figure 6b The first step shown Figure 6c And the second step shown Figure 1a After which the formed functional layer 13, compared with Figure 6d The main difference of the functional layer 13 shown

[0085] The material used for the above functional layer 13 can be silicon nitride, and the dummy gate 12 can include a top protective layer 12c at the top as described above, and the material used for the top protective layer 12c is silicon oxide. In step S150, the etching of the functional layer 13 is carried out by dry etching using a plasma gas mixed with carbon tetrafluoride and fluoromethane as the etching gas. Since the etching rate of the mixed gas of carbon tetrafluoride and fluoromethane for silicon nitride is much greater than that for silicon oxide, during the execution of step S150, the top protective layer 12c included in the dummy gate 12 in the PMOS device region is basically not damaged, so that the execution of step S150 basically does not cause a height difference between the dummy gate 12 in the NMOS device region and the dummy gate 12 in the PMOS device region.

[0086] Furthermore, the manufacturing method of the semiconductor structure provided by the embodiments of the present application may further include: before forming the functional layer 13 by executing step S130 as Figure 6aA surface protection layer 14 is formed on the dummy gate 12 and on the substrate 11, so that the dummy gate 12 is protected by the surface protection layer 14. Then, the formed functional layer 13 directly covers the portions of the surface protection layer 14 on the sidewalls of the dummy gate 12 and on the substrate 11, thereby indirectly covering the sidewalls of the dummy gate 12 and the substrate 11. And subsequently, after etching the functional layer 13 using the photoresist layer as a mask in step S150, the surface protection layer 14 is etched using the photoresist layer as a mask. It should be understood that the thickness of the formed surface protection layer 14 should be appropriate so that there is a gap between the surface protection layers 14 on the adjacent sidewalls of the dummy gate 12. Similarly, the thickness of the formed functional layer 13 should also be appropriate so that there is a gap between the functional layers 13 on the adjacent sidewalls of the dummy gate 12, so as not to affect the function of the functional layer 13 in defining the reserved area. Figure 6d The reserved area defined by the functional layer 13 in the figure is outlined by a dashed box.

[0087] In the example of forming the surface protection layer 14, in step S140, a photoresist layer 15 as shown in Figure 6e is formed. The photoresist layer 15 covers the functional layer 13 in the NMOS device area and the portion of the surface protection layer 14 on the top of the dummy gate 12. In step S150, when etching the functional layer 13 using the photoresist layer 15 as a mask, it is until the portion of the surface protection layer 14 on the reserved area is exposed. Then, when etching the surface protection layer 14 using the photoresist layer 15 as a mask, it is as shown in Figure 6f until the surface of the reserved area is exposed, so that the execution of step S160 can directly etch the reserved area to form a trench for growing silicon germanide in the reserved area. Figure 6g The figure shows a schematic diagram after removing the photoresist layer 15 before the execution of step S160.

[0088] It should be noted that the thickness of the surface protection layer 14 formed before the execution of step S130 is basically uniform. Therefore, during the process of etching the surface protection layer 14 using the photoresist layer 15 as a mask, the part of the surface protection layer 14 on the upper surface of the PMOS device area at the top of the dummy gate 12 will be etched off simultaneously, which will affect the filling and polishing of the subsequent interlayer dielectric layer. For this, since the function of the surface protection layer 14 is to protect the dummy gate 12 and the thickness of the surface protection layer 14 can be adjusted, the thickness of the surface protection layer 14 can be made smaller than that of the functional layer 13. In this way, the thickness of the surface protection layer 14 is smaller, and the absence of the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device area while the presence of the surface protection layer 14 on the top of the dummy gate 12 in the NMOS device area will not cause obvious influence on the filling and polishing of the subsequent interlayer dielectric layer. In practice, due to process precision and other reasons, the removal of the photoresist layer 15 will damage the nearby functional layer 13 and even damage the exposed surface protection layer 14 after the functional layer 13 is damaged. The parts of the functional layer 13 and the surface protection layer 14 on the sidewalls of the dummy gate 12 will be damaged to a greater extent especially because the part of the photoresist layer 15 between the dummy gates 12 is difficult to remove. Therefore, the thickness of the functional layer 13 being greater than that of the surface protection layer 14 can also compensate for the lack of protection caused by the thinner surface protection layer 14, ultimately ensuring that the dummy gate 12 will not be damaged and there will be no adverse impact on the subsequent interlayer dielectric layer due to the relatively thick surface protection layer 14.

[0089] The material used for the above-mentioned surface protection layer 14 can be silicon oxide, and the etching of the surface protection layer 14 can be dry etching using a plasma gas of carbon tetrafluoride as the etching gas.

[0090] In some examples, the material of the substrate 11 is silicon, the material of the functional layer 13 is silicon nitride, the material of the surface protection layer 14 is silicon oxide, the material of the top protection layer 12c in the dummy gate 12 is silicon oxide. In step S160, forming a preliminary trench in the reserved area may include: performing dry etching using a plasma gas of hydrogen bromide (HBr) as the etching gas to form a preliminary trench 17 as shown in Figure 6h the figure.

[0091] It should be noted that when performing dry etching using a plasma gas of hydrogen bromide as the etching gas, silicon will be etched at a relatively high etching rate and silicon oxide and silicon nitride will be etched at a relatively low etching rate. Therefore, the plasma gas of hydrogen bromide will Figure 6gEtch the reserved area in the PMOS device region shown. At the same time, etch the top protective layer 12c in the dummy gate 12 on the PMOS device region, and also etch the part of the surface protective layer 14 on the NMOS device region at the top of the dummy gate 12. Even after etching off the part of the surface protective layer 14 on the top of the dummy gate 12, etch the top protective layer 12c in the dummy gate 12. However, during this etching process, since the silicon oxide on the top of the dummy gate 12 on both the PMOS device region and the NMOS device region is etched, there is no etching height difference in the silicon oxide on the top of the dummy gate 12 on the PMOS device region and the NMOS device region. The height difference between the silicon oxides on the top of the dummy gate 12 on the PMOS device region and the NMOS device region is only caused by the process of etching the surface protective layer 14 using the photoresist layer 15 as a mask before, thus Figure 6h the height difference between the silicon oxides on the top of the dummy gate 12 on the PMOS device region and the NMOS device region in is only the thickness of the surface protective layer 14, so it will not have an obvious impact on the filling and polishing of the subsequent interlayer dielectric layer.

[0092] The manufacturing method of the semiconductor structure provided by the embodiment of the present application may further include: after step S160, widen the preparation trench 17 by etching to form a Figure 6i sigma trench 18 for growing silicon germanide as shown. Then grow silicon germanide in the sigma trench 18 to form a Figure 6j silicon germanium trench 19 as shown, thus completing the formation process of the silicon germanium trench 19. It should be noted that Figure 6j only one silicon germanium trench 19 is shown. In practice, a silicon germanium trench 19 can be formed in the reserved areas on both sides of each dummy gate 12 on the PMOS device region.

[0093] The manufacturing method of the semiconductor structure provided by the above embodiments mainly introduces in detail the improvement points compared with the prior art, aiming to illustrate that the improvement points compared with the prior art can make the chemical mechanical polishing load of the interlayer dielectric layer in the manufacturing process of the semiconductor structure small and can make the probability of the existence of gaps in the interlayer dielectric layer included in the semiconductor structure low. For the content other than the improvement points, reference can be made to the relevant descriptions of the prior art.

[0094] Corresponding to the manufacturing method of the semiconductor structure provided by the above embodiments, another embodiment of the present application also provides a semiconductor structure. The semiconductor structure is manufactured by any one of the manufacturing methods provided by the above embodiments. Since the chemical mechanical polishing load of the interlayer dielectric layer in the manufacturing process is small and the probability of the existence of gaps in the included interlayer dielectric layer is low, it has excellent electrical properties and low manufacturing costs. Figure 6j The structure shown can be regarded as an exemplary structure of part of the semiconductor structure provided by the embodiment of the present application. It should be understood that Figures 6a to 6jIt mainly illustrates the formation process of the germanium-silicon trench 19. Therefore, in order for the semiconductor structure provided by the embodiments of the present application to have the complete structures of PMOS devices and NMOS devices, source regions, drain regions, and connection lines also need to be further formed on the Figure 6j structure shown, and an isolation structure between different MOS devices also needs to be formed, etc. In addition Figure 6j the structure shown only exemplarily illustrates the formed germanium-silicon trench 19, and does not impose any limitation on the respective numbers of PMOS devices and NMOS devices in the semiconductor structure provided by the embodiments of the present application.

[0095] As described above in accordance with the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region; forming dummy gates on the NMOS device region and the PMOS device region; Forming a surface protection layer on the dummy gate and the substrate Forming a functional layer on the dummy gate sidewall and the substrate, the functional layer covers the surface protection layer on the dummy gate sidewall and the substrate, and the area of ​​the PMOS device region other than under the dummy gate and the dummy gate sidewall functional layer is a reserved area; After the functional layer is formed, a photoresist layer is formed covering the NMOS device region and having an opening in the PMOS device region; After etching the functional layer using the photoresist layer as a mask, etching the surface protection layer using the photoresist layer as a mask, wherein the functional layer is etched until the portion of the surface protection layer on the reserved area is exposed, the surface protection layer is etched until the surface of the reserved area is exposed, and then the photoresist layer is removed; forming a preliminary groove in the reserved area; Wherein, a functional layer is formed on the side wall of the dummy gate and the substrate by cyclically executing the first step and the second step, wherein the first step includes: forming a sub-functional layer covering the dummy gate and the substrate, and the second step includes: passing an etching gas from above the substrate downward to etch the sub-functional layer until the sub-functional layer on the top of the dummy gate is etched away.

2. The manufacturing method according to claim 1, wherein: The first step forms the sub-functional layer by using any one of an atomic layer deposition process, a chemical vapor deposition process and a physical vapor deposition process.

3. The manufacturing method according to claim 2, wherein: The thickness of the sub-functional layer is 20 angstroms to 50 angstroms.

4. The manufacturing method according to claim 3, wherein: In the second step, the flow rate of the etching gas is controlled so that the portion of the sub-functional layer on the top of the dummy gate is etched away, and the time taken is 4s-8s.

5. The manufacturing method according to claim 1, wherein: The material used for the sub-functional layer is silicon nitride, the pseudo gate includes a top protective layer located on the top and the material used for the top protective layer is silicon oxide, and the etching gas used in the second step is a plasma gas mixed with carbon tetrafluoride and fluoromethane.

6. The manufacturing method according to claim 1, wherein: The material used for the functional layer is silicon nitride, the pseudo gate includes a top protective layer located on the top and the material used for the top protective layer is silicon oxide, and the functional layer is etched using the photoresist layer as a mask, including: dry etching the functional layer using a plasma gas mixed with carbon tetrafluoride and fluoromethane as an etching gas.

7. The manufacturing method according to claim 1, wherein: The thickness of the surface protection layer is smaller than the thickness of the functional layer.

8. The manufacturing method according to claim 1, further comprising: The preliminary trench is widened by etching to form a sigma trench for growing silicon germanium.

9. A semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method according to any one of claims 1 to 8.

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