Semiconductor Structure and Method for Manufacturing the Same

Abstract

The present application discloses a semiconductor structure and a manufacturing method thereof. The manufacturing method includes: providing a substrate, the substrate including an NMOS device region and a PMOS device region; forming dummy gates on the NMOS device region and the PMOS device region; forming a functional layer on the dummy gates and the substrate, a reserved region being an area outside the PMOS device region under the dummy gates and the sidewall functional layers of the dummy gates; forming a photoresist layer covering the functional layer on the NMOS device region and having an opening on the PMOS device region; using the photoresist layer as a mask to etch the functional layer until the surface of the reserved region is exposed, and then removing the photoresist layer; forming a preliminary trench in the reserved region. The present application can reduce the height of the dummy gate of the NMOS device and reduce the height difference between the dummy gates of the NMOS device and the PMOS device.

Description

Technical Field

[0001] This application relates to the field of semiconductor manufacturing technology, and particularly to a semiconductor structure and a manufacturing method thereof. Background Art

[0002] In the process of manufacturing a semiconductor structure, in order to improve the drive current of PMOS (i.e., P-type metal-oxide-semiconductor) devices, the germanium-silicon epitaxial technology is widely used. In the germanium-silicon epitaxial technology, after the NMOS (i.e., N-type metal-oxide-semiconductor) devices are covered by a photoresist layer, germanium-silicon trenches are only formed in the substrate of the PMOS devices. In the existing technology for forming germanium-silicon trenches, the dummy gates of the PMOS devices are damaged, resulting in different heights of the dummy gates of the NMOS devices and the PMOS devices. In this way, the chemical mechanical polishing (CMP) of the interlayer dielectric (ILD) formed subsequently is affected, and the higher dummy gate of the NMOS device is also likely to cause gaps in the interlayer dielectric formed subsequently. Summary of the Invention

[0003] In view of the above problems, this application provides a semiconductor structure and a manufacturing method thereof, aiming to reduce the height of the dummy gate of the NMOS device and reduce the height difference between the dummy gates of the NMOS device and the PMOS device.

[0004] According to a first aspect of the present invention, there is provided a manufacturing method of a semiconductor structure, including:

[0005] Providing a substrate, the substrate including an NMOS device region and a PMOS device region;

[0006] Forming dummy gates on the NMOS device region and the PMOS device region;

[0007] Forming a functional layer on the dummy gates and the substrate, and the region of the PMOS device region outside the lower part of the dummy gate and the sidewall functional layer of the dummy gate is a reserved region;

[0008] Forming a photoresist layer covering the functional layer on the NMOS device region and having an opening on the PMOS device region;

[0009] Using the photoresist layer as a mask to etch the functional layer until the surface of the reserved region is exposed, and then removing the photoresist layer;

[0010] Forming a preliminary trench in the reserved region.

[0011] Optionally, the manufacturing method further includes: after forming the functional layer, etching away the functional layer located on top of the dummy gate, and then the formed photoresist layer covers the functional layer on the NMOS device region and the top of the dummy gate.

[0012] Optionally, there is a gap between the functional layers on the sidewalls of adjacent dummy gates. Etching away the functional layer located on top of the dummy gate includes:

[0013] Filling a masking material in the gap and making the masking material in the gap flush with the functional layer on top of the dummy gate to form a masking layer with an opening on top of the dummy gate;

[0014] Using the masking layer as a mask to etch the functional layer until the functional layer on top of the dummy gate is etched away, and then removing the masking layer.

[0015] Optionally, the masking material is amorphous carbon, and the material used for the functional layer is silicon nitride.

[0016] Optionally, the manufacturing method further includes:

[0017] Forming a surface protection layer on the dummy gate and the substrate before forming the functional layer, and then the formed functional layer covers the surface protection layer;

[0018] After etching the functional layer using the photoresist layer as a mask, etching the surface protection layer using the photoresist layer as a mask, wherein the functional layer is etched until the part of the surface protection layer on the reserved area is exposed, and the surface protection layer is etched until the surface of the reserved area is exposed.

[0019] Optionally, the thickness of the surface protection layer is less than the thickness of the functional layer.

[0020] Optionally, the material of the substrate is silicon, the material of the functional layer is silicon nitride, the material of the surface protection layer is silicon oxide, the dummy gate includes a top protection layer at the top and the material of the top protection layer is silicon oxide. Forming a preliminary trench in the reserved area includes: performing dry etching with a plasma gas of hydrogen bromide as the etching gas to form the preliminary trench in the reserved area.

[0021] Optionally, the material of the functional layer is silicon nitride, and the etching of the functional layer is performed by dry etching with a plasma gas of a mixture of carbon tetrafluoride and fluoromethane as the etching gas.

[0022] Optionally, the manufacturing method further includes: broadening the preliminary trench by etching to form a sigma trench for growing silicon germanide.

[0023] According to a second aspect of the present invention, there is provided a semiconductor structure manufactured by any of the manufacturing methods described in the first aspect.

[0024] The unexpected technical effect of this application is:

[0025] According to the manufacturing method of the semiconductor structure provided by the embodiments of this application, after forming a functional layer on the dummy gate and the substrate, a photoresist layer covering the functional layer on the NMOS device region and having an opening on the PMOS device region is formed. Then, using the photoresist layer as a mask, the functional layer is etched until the surface of the reserved region in the PMOS device region is exposed. During this process, the functional layer on the top of the dummy gate in the PMOS device region will also be etched away, causing the dummy gate to be exposed. After that, the photoresist layer is removed, and a preliminary trench is formed in the reserved region of the PMOS device region. Therefore, during the formation of the preliminary trench, not only the exposed dummy gate in the PMOS device region will be etched, but also the functional layer on the NMOS device region will be etched to expose the dummy gate and cause the exposed dummy gate to be etched. As a result, the height of the dummy gate of the NMOS device will decrease, and the height difference between the dummy gates of the NMOS device and the PMOS device will be reduced.

[0026] Furthermore, the manufacturing method of the semiconductor structure provided by the embodiments of this application further includes etching away the functional layer located on the top of the dummy gate after forming the functional layer. Then, the formed photoresist layer covers the functional layer and the top of the dummy gate on the NMOS device region. In this way, during the process of forming the preliminary trench after removing the photoresist layer, the dummy gate on the NMOS device region and the dummy gate on the PMOS device region will be directly etched simultaneously. As a result, not only the height of the dummy gate on the NMOS device region is further reduced, but also there is no height difference between the dummy gate on the NMOS device region and the dummy gate on the PMOS device region during the formation of the preliminary trench, and the height difference between the dummy gates of the NMOS device and the PMOS device can be controlled to be as small as possible. Description of the Drawings

[0027] Through the following description of the embodiments of this application with reference to the drawings, the above and other objects, features, and advantages of this application will become clearer. In the drawings:

[0028] Figure 1a A cross-sectional schematic diagram of a substrate and a dummy gate completely covered by a photoresist layer in the prior art is shown;

[0029] Figure 1b A cross-sectional schematic diagram of a substrate and a dummy gate with the NMOS device region covered by a photoresist layer in the prior art is shown;

[0030] Figure 1c A cross-sectional schematic diagram of a substrate and a dummy gate with the surface of the reserved region in the PMOS device region exposed in the prior art is shown;

[0031] Figure 1dThe cross-sectional schematic diagram of the substrate and the dummy gate after etching the preparation trench in the PMOS device region in the prior art is shown;

[0032] Figure 1e The cross-sectional schematic diagram of the substrate and the dummy gate after etching the sigma trench in the PMOS device region in the prior art is shown;

[0033] Figure 1f The cross-sectional schematic diagram of the substrate and the dummy gate after removing the photoresist layer in the prior art is shown;

[0034] Figure 1g The cross-sectional schematic diagram of the substrate and the dummy gate after forming the germanium-silicon trench in the PMOS device region in the prior art is shown;

[0035] Figure 1h The cross-sectional schematic diagram of the substrate and the dummy gate after removing the functional layer in the prior art is shown;

[0036] Figure 2a The schematic diagram of the dummy gate on the PMOS device region in the semiconductor structure manufactured in the prior art is shown;

[0037] Figure 2b The schematic diagram of the dummy gate on the NMOS device region in the semiconductor structure manufactured in the prior art is shown;

[0038] Figure 3 The schematic diagram of the intermediate dielectric layer formed based on the semiconductor structure manufactured in the prior art is shown;

[0039] Figure 4 The flowchart of the manufacturing method of the semiconductor structure according to the embodiment of the present application is shown;

[0040] Figure 5a The cross-sectional schematic diagram of an exemplary substrate and dummy gate according to the embodiment of the present application is shown;

[0041] Figure 5b The cross-sectional schematic diagram of an exemplary substrate and dummy gate after forming the mask layer according to the embodiment of the present application is shown;

[0042] Figure 5c The cross-sectional schematic diagram of an exemplary substrate and dummy gate after etching off the functional layer on the top of the dummy gate according to the embodiment of the present application is shown;

[0043] Figure 5d The cross-sectional schematic diagram of an exemplary substrate and dummy gate after removing the mask layer according to the embodiment of the present application is shown;

[0044] Figure 5e The cross-sectional schematic diagram of an exemplary substrate and dummy gate after the NMOS device region is covered with the photoresist layer according to the embodiment of the present application is shown;

[0045] Figure 5fShows a cross-sectional schematic diagram of a substrate and a dummy gate after the surface of the reserved area of the PMOS device region is exposed according to an embodiment of the present application;

[0046] Figure 5g Shows a cross-sectional schematic diagram of a substrate and a dummy gate after removing the photoresist layer according to an embodiment of the present application;

[0047] Figure 5h Shows a cross-sectional schematic diagram of a substrate and a dummy gate after etching a preparation trench in the PMOS device region according to an embodiment of the present application;

[0048] Figure 5i Shows a cross-sectional schematic diagram of a substrate and a dummy gate after etching a sigma trench in the PMOS device region according to an embodiment of the present application;

[0049] Figure 5j Shows a cross-sectional schematic diagram of a substrate and a dummy gate after forming a germanium-silicon trench in the PMOS device region according to an embodiment of the present application.

[0050] Explanation of reference numerals: 11 - substrate; 12 - dummy gate; 12a - gate conductor layer; 12b - gate insulating layer; 12c - top protective layer; 12d - sidewall; 13 - functional layer; 14 - surface protective layer; 15 - photoresist layer; 16 - bottom anti-reflection coating; 17 - preparation trench; 18 - sigma trench; 19 - germanium-silicon trench; 25 - mask layer. Detailed implementation manners

[0051] The present application will be described in more detail below with reference to the drawings. In each drawing, the same elements are denoted by similar reference numerals. For clarity, the various parts in the drawings are not drawn to scale. In addition, some well-known parts may not be shown.

[0052] The present application can be presented in various forms, and some examples will be described below.

[0053] In germanium-silicon epitaxy technology, after the NMOS device is covered by the photoresist layer, a germanium-silicon trench is only formed in the substrate of the PMOS device to increase the compressive stress of the PMOS device and improve the drive current of the PMOS device. Figures 1a to 1h Shows the process of forming a germanium-silicon trench in the prior art. The following will be combined with Figures 1a to 1h introduce the prior art of forming a germanium-silicon trench in detail.

[0054] As Figure 1aAs shown, the substrate 11 includes an NMOS device region and a PMOS device region. Pseudo-gates 12 are respectively formed on the NMOS device region and the PMOS device region. A functional layer 13 is formed on the substrate 11 and on the pseudo-gates 12. The region of the PMOS device region outside the pseudo-gates 12 and the sidewall functional layer 13 of the pseudo-gates 12 is a reserved region. In some examples, a surface protection layer 14 is first formed on the substrate 11 and on the pseudo-gates 12, and then the functional layer 13 is formed. The later-formed functional layer 13 covers the previously-formed surface protection layer 14. The material used for the functional layer 13 is silicon nitride, and its function is to control the position of the reserved region in the PMOS device region by adjusting its own thickness. The material used for the surface protection layer 14 is silicon oxide (SiO2), and its function is to protect the pseudo-gates 12.

[0055] The pseudo-gate 12 includes a stacked structure formed by laminating a gate conductor layer 12a, a gate insulating layer 12b, and a top protection layer 12c, and sidewalls 12d provided on the sidewalls of the stacked structure. The combination of the top protection layer 12c and the sidewalls 12d serves to protect the gate conductor layer 12a and the gate insulating layer 12b. Such a combined protection function with the surface protection layer 14 ensures that the gate conductor layer 12a and the gate insulating layer 12b will not be damaged during the formation of the germanium-silicon trench. The material used for the gate conductor layer 12a is polysilicon, the material used for the gate insulating layer 12b is silicon nitride, the material used for the top protection layer 12c is silicon oxide, and the material used for the sidewalls 12d is silicon nitride.

[0056] During the formation of the germanium-silicon trench, a photoresist layer 15 as shown in Figure 1b is first formed that only covers the functional layer 13 on the NMOS device region. Specifically, a photoresist layer 15 that covers all the functional layer 13 can be first formed as shown in Figure 1a . Then, through exposure and development, the photoresist layer 15 on the PMOS device region is etched away, thereby forming a photoresist layer 15 that covers the functional layer 13 on the NMOS device region and has an opening on the PMOS device region. In some examples, a bottom anti-reflection coating 16 that covers all the functional layer 13 is first formed as shown in Figure 1a . The later-formed photoresist layer 15 covers the previously-formed bottom anti-reflection coating 16. Therefore, in order to achieve that only the functional layer 13 on the NMOS device region is covered, exposure and development of the photoresist layer 15 are combined with etching of the bottom anti-reflection coating 16.

[0057] Next, using as shown in Figure 1bThe etching of the functional layer 13 and the surface protection layer 14 is performed on the photoresist layer 15 shown and the bottom anti-reflection coating 16 present in some examples. During this etching process, since only the functional layer 13 on the NMOS device region is covered, the functional layer 13 and the surface protection layer 14 on the NMOS device region are not etched, while the functional layer 13 and the surface protection layer 14 on the PMOS device region are etched. Specifically, first, the etching of the functional layer 13 is carried out until a part of the surface protection layer 14 on the reserved area in the PMOS device region is exposed, and then the etching of the surface protection layer 14 is carried out until the surface of the reserved area in the PMOS device region is exposed. It should be understood that during the etching process of the functional layer 13 carried out first, the functional layer 13 on the top of the dummy gate 12 in the PMOS device region will be etched away at the same time, and during the etching process of the surface protection layer 14 carried out later, the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device region will be etched away at the same time, so that as Figure 1c shown, the dummy gate 12 on the PMOS device region will be exposed after this process.

[0058] Next, dry etching is carried out through a plasma gas to form a preliminary trench 17 as shown in Figure 1d . Specifically, the etching rate of the plasma gas for dry etching on silicon is greater than that on silicon nitride and silicon oxide, and since the functional layer 13 on the NMOS device region is covered by the photoresist layer 15, only the functional layer 13 made of silicon nitride material, the surface protection layer 14 made of silicon oxide material, the top protection layer 12c, and the reserved area made of silicon material on the PMOS device region can be etched during this dry etching process, and the etched parts of the functional layer 13, the surface protection layer 14, and the top protection layer 12c are less compared to the reserved area.

[0059] After that, wet etching is used to widen the preliminary trench 17 as shown in Figure 1d to form a sigma trench 18 as shown in Figure 1e , and as shown in Figure 1f the photoresist layer 15 as shown in Figure 1e is removed through an ashing process and the bottom anti-reflection coating 16 present in some examples is removed, and silicon germanide is grown in the sigma trench 18 as shown in Figure 1f to form a germanium-silicon trench 19 as shown in Figure 1g , thus completing the formation process of the germanium-silicon trench 19. Finally, as shown in Figure 1h the functional layer 13 used to define the reserved area on each dummy gate 12 as shown in Figure 1g is removed.

[0060] Based on the above introduction to the formation process of the germanium-silicon trench 19, it can be known that: during the etching process shown in Figure 1c for exposing the surface of the reserved area and Figure 1dDuring the etching process of forming the preliminary trench 17 shown, since there is no photoresist layer 15 on the PMOS device region, the functional layer 13 on the top of the dummy gate 12 and the surface protection layer 14 existing in some examples on the PMOS device region will be etched away, and then a part of the top protection layer 12c and the sidewall 12d included in the dummy gate 12 will be etched away, so that the dummy gate 12 on the PMOS device region is damaged. For the example with the surface protection layer 14, finally formed as Figure 1h In the semiconductor structure shown, there are a top protection layer 12c and a surface protection layer 14 on the top of the dummy gate 12 in the NMOS device region. Therefore, the damage of the dummy gate 12 on the PMOS device region makes the silicon oxides on the tops of the dummy gates 12 in the PMOS device region and the NMOS device region have different heights; for the example without the surface protection layer 14, in the finally formed semiconductor structure, there is a complete top protection layer 12c on the top of the dummy gate 12 in the NMOS device region. Therefore, the damage of the dummy gate 12 on the PMOS device region makes there be a height difference between the dummy gates 12 in the PMOS device region and the NMOS device region.

[0061] Figure 2a And Figure 2b respectively show the schematic diagrams of the dummy gates on the PMOS device region and the dummy gates on the NMOS device region in the semiconductor structure of the example with the surface protection layer 14 manufactured by the above technology. Among them, Figure 2a It is indicated that the silicon oxide on the top of the dummy gate on the PMOS device region is 10.2 nm high, Figure 2b It is indicated that the silicon oxide on the top of the dummy gate on the NMOS device region is 32.1 nm high. It can be seen that the silicon oxides on the tops of the dummy gates in the PMOS device region and the NMOS device region have different heights.

[0062] It should be noted that Figure 1h In the subsequent steps of the semiconductor structure shown, doping ions need to be implanted into the substrate 11 to form source regions and drain regions on both sides of the dummy gate 12. After that, an interlayer dielectric layer needs to be formed above the source regions, drain regions and the dummy gate 12, and the dummy gate 12 needs to be removed from the interlayer dielectric layer and replaced with a high-k metal gate structure. Therefore, after the interlayer dielectric layer is formed, it needs to be polished to be flush with the surface and expose the gate insulating layer 12b of the dummy gate 12. The different heights of the silicon oxides on the tops of the dummy gates 12 in the PMOS device region and the NMOS device region in the example with the surface protection layer 14 and the height difference between the dummy gates 12 in the PMOS device region and the NMOS device region in the example without the surface protection layer 14 will both cause the chemical mechanical polishing load (loading) of the subsequent interlayer dielectric layer. In addition, the relatively high silicon oxide on the top of the dummy gate 12 in the NMOS device region in the example with the surface protection layer 14 and the relatively high dummy gate 12 in the NMOS device region in the example without the surface protection layer 14 are both likely to cause gaps in the interlayer dielectric layer. Figure 3Shown is a gap framed by a white dotted line in the interlayer dielectric layer formed due to the relatively high silicon oxide on top of the dummy gate 12 in the NMOS device region in an example where there is a surface protection layer 14.

[0063] For the above reasons, an embodiment of the present application provides a method for manufacturing a semiconductor structure. Figure 4 Shown is a flowchart of the method for manufacturing a semiconductor structure provided by an embodiment of the present application, as Figure 4 shown, the manufacturing method includes:

[0064] Step S110, providing a substrate, the substrate including an NMOS device region and a PMOS device region;

[0065] Step S120, forming dummy gates on the NMOS device region and the PMOS device region;

[0066] Step S130, forming a functional layer on the dummy gates and the substrate, and the region of the PMOS device region outside the lower part of the dummy gate and the sidewall functional layer of the dummy gate is a reserved region;

[0067] Step S140, forming a photoresist layer covering the functional layer on the NMOS device region and having an opening on the PMOS device region;

[0068] Step S150, using the photoresist layer as a mask to etch the functional layer until the surface of the reserved region is exposed, and then removing the photoresist layer;

[0069] Step S160, forming a preliminary trench in the reserved region.

[0070] It should be noted that after forming the functional layer in step S130, a reserved region is defined in the PMOS device region. In step S150, the functional layer is etched until the surface of the reserved region is exposed in order to directly etch the reserved region in step S160 to form a trench for growing silicon germanide in the reserved region. The reserved region is etched in step S160 by using high-selectivity etching, that is, the etching rate for the reserved region is greater than the etching rates of the functional layer and the dummy gate. In addition, since the thickness of the functional layer formed in step S130 is basically uniform, the thickness of the functional layer on top of the dummy gate in the PMOS device region is the same as the thickness of the functional layer on the surface of the reserved region. After step S150 is executed, not only the functional layer on the surface of the reserved region in the PMOS device region is etched away, but also the functional layer on top of the dummy gate in the PMOS device region is etched away simultaneously to expose the dummy gate.

[0071] In the embodiment of the present application, when using the photoresist layer as a mask to etch the functional layer until the surface of the reserved area is exposed and then removing the photoresist layer, during the process of forming the preliminary trench in the reserved area later, not only the dummy gate exposed on the PMOS device area will be etched, but also the functional layer that is no longer covered by the photoresist layer on the NMOS device area will be etched simultaneously, and the dummy gate exposed due to the etching of the functional layer will also be etched. In this way, the height of the dummy gate of the NMOS device will decrease, and the height difference between the dummy gates of the NMOS device and the PMOS device will be reduced.

[0072] Figures 5a to 5j are schematic diagrams of the steps of a manufacturing method of a semiconductor structure provided by an embodiment of the present application. The following will be combined with Figure 4 and Figures 5a to 5j to describe in detail the manufacturing method of the semiconductor structure provided by the embodiment of the present application.

[0073] The substrate provided in step S110, the dummy gate formed in step S120, and the functional layer formed in step S130 can be as Figure 5a shown. Referring to Figure 5a , the substrate 11 includes an NMOS device area and a PMOS device area. The dummy gate 12 includes a stacked structure formed by laminating a gate conductor layer 12a, a gate insulating layer 12b, and a top protection layer 12c, and sidewalls 12d provided on the sidewalls of the stacked structure. The functional layer 13 is formed on the substrate 11 and the dummy gate 12.

[0074] Furthermore, the manufacturing method of the semiconductor structure provided by the embodiment of the present application may further include etching off the functional layer 13 located on the top of the dummy gate 12 after step S130. Correspondingly, the photoresist layer formed in step S140 covers the functional layer 13 on the NMOS device area and the top of the dummy gate 12. In this way, during the execution of step S160 after removing the photoresist layer in step S150, the dummy gate 12 on the NMOS device area and the dummy gate 12 on the PMOS device area will be etched directly at the same time, so that not only the height of the dummy gate 12 on the NMOS device area is further reduced, but also no height difference is generated between the dummy gate 12 on the NMOS device area and the dummy gate 12 on the PMOS device area during the trench formation process.

[0075] Specifically, etching off the functional layer 13 located on the top of the dummy gate 12 may include: depositing a mask material on the functional layer 13 on the reserved area and making the deposited mask material flush with the functional layer 13 on the top of the dummy gate 12 to form a mask layer 25 with an opening on the top of the dummy gate 12 as shown in Figure 5b . Then, as shown in Figure 5c , using the mask layer 25 as a mask to etch the functional layer 13 until the functional layer 13 on the top of the dummy gate 12 is etched off. After that, as shown in Figure 5dThe mask layer 25 is removed as shown, so that a mask plate is not required in the whole process, which is beneficial to saving manufacturing costs. Among them, the mask material can be amorphous carbon, and the material used for the functional layer 13 can be silicon nitride. Therefore, by selectively etching to remove the mask layer 25 and stopping the etching at the functional layer 13, it can be ensured that the functional layer 13 is not damaged during the removal of the mask layer 25.

[0076] Further, the manufacturing method of the semiconductor structure provided by the embodiment of the present application may further include: as Figure 5a shown, a surface protection layer 14 is formed on the dummy gate 12 and the substrate 11 before forming the functional layer 13 by executing step S130, so that the dummy gate 12 is protected by the surface protection layer 14, and the subsequently formed functional layer 13 covers the surface protection layer 14; and subsequently, after etching the functional layer 13 using the photoresist layer as a mask in step S150, the surface protection layer 14 is etched using the photoresist layer as a mask. It should be understood that the thickness of the formed surface protection layer 14 should be appropriate so that there is a gap between the surface protection layers 14 on the side walls of adjacent dummy gates 12, and similarly, the thickness of the formed functional layer 13 should also be appropriate so that there is a gap between the functional layers 13 on the side walls of adjacent dummy gates 12, so as not to affect the function of the functional layer 13 in defining the reserved area.

[0077] Specifically, in this example, after etching off the functional layer 13 located on the top of the dummy gate 12, the photoresist layer 15 as shown is formed by executing step S140. The photoresist layer 15 covers the functional layer 13 on the NMOS device area and the surface protection layer 14 on the top of the dummy gate 12. In step S150, the functional layer 13 is etched using the photoresist layer 15 as a mask until the part of the surface protection layer 14 on the reserved area is exposed, and then the surface protection layer 14 is etched using the photoresist layer 15 as a mask as Figure 5e shown until the surface of the reserved area is exposed, so that the execution of step S160 is to directly etch the reserved area to form a trench for growing silicon germanide in the reserved area. Figure 5f shown in the figure until the surface of the reserved area is exposed, so that the execution of step S160 is to directly etch the reserved area to form a trench for growing silicon germanide in the reserved area. Figure 5g Shown is a schematic diagram after removing the photoresist layer 15 before executing step S160.

[0078] It should be noted that the thickness of the surface protection layer 14 formed before the execution of step S130 is basically uniform, and the thickness of the functional layer 13 formed in step S130 is basically uniform. Therefore, during the process of etching the functional layer 13 using the photoresist layer 15 as a mask, the functional layer 13 on the top of the dummy gate 12 in the PMOS device region will be etched away simultaneously. During the process of etching the surface protection layer 14 using the photoresist layer 15 as a mask, the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device region will be etched away simultaneously. Since the functional layer 13 needs to be removed before the subsequent interlayer dielectric layer is filled, the etching of the functional layer 13 on the top of the dummy gate 12 in the PMOS device region will not affect the filling and polishing of the subsequent interlayer dielectric layer. However, the etching of the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device region will affect the filling and polishing of the subsequent interlayer dielectric layer. For this reason, since the function of the surface protection layer 14 is to protect the dummy gate 12 and the thickness of the surface protection layer 14 can be adjusted, the thickness of the surface protection layer 14 can be made smaller than the thickness of the functional layer 13. In this way, the thickness of the surface protection layer 14 is smaller, and the absence of the surface protection layer 14 on the top of the dummy gate 12 in the PMOS device region while the presence of the surface protection layer 14 on the top of the dummy gate 12 in the NMOS device region will not have an obvious impact on the filling and polishing of the subsequent interlayer dielectric layer. In practice, due to process precision and other reasons, the removal of the mask layer 25 and the removal of the photoresist layer 15 will damage the nearby functional layer 13 and even damage the surface protection layer 14 exposed after the functional layer 13 is damaged. Therefore, the thickness of the functional layer 13 being greater than that of the surface protection layer 14 can also compensate for the lack of protection due to the thinner surface protection layer 14, ultimately ensuring that the dummy gate 12 is not damaged and there is no adverse impact on the subsequent interlayer dielectric layer due to the thicker surface protection layer 14.

[0079] The material used for the above-mentioned functional layer 13 can be silicon nitride, and the etching of the functional layer 13 can be carried out by dry etching using a plasma gas mixture of carbon tetrafluoride (CF4) and fluoromethane (CH3F) as the etching gas. The material used for the above-mentioned surface protection layer 14 can be silicon oxide, and the etching of the surface protection layer 14 can be carried out by dry etching using a plasma gas of carbon tetrafluoride as the etching gas.

[0080] In some examples, the material of the substrate 11 is silicon, the material of the functional layer 13 is silicon nitride, the material of the surface protection layer 14 is silicon oxide, and the material of the top protection layer 12c in the dummy gate 12 is silicon oxide. Step S160, forming a preliminary trench in the reserved area, may include: carrying out dry etching using a plasma gas of hydrogen bromide (HBr) as the etching gas to form a preliminary trench 17 in the reserved area.

[0081] It should be noted that when dry etching is performed using a plasma gas of hydrogen bromide as the etching gas, silicon will be etched at a relatively high etching rate, while silicon oxide and silicon nitride will be etched at a relatively low etching rate. Therefore, in the embodiment where the surface protection layer 14 is formed before the functional layer 13 is formed and the functional layer 13 located on top of the dummy gate 12 is etched in advance, the plasma gas of hydrogen bromide will Figure 5g etch the reserved area in the PMOS device region shown in Figure 5g . At the same time, it will etch the top protection layer 12c in the dummy gate 12 on the PMOS device region, and will also etch the surface protection layer 14 on top of the dummy gate 12 on the NMOS device region. Even after the surface protection layer 14 on top of the dummy gate 12 is etched off, it will etch the top protection layer 12c in the dummy gate 12. However, during this etching process, since the silicon oxide on top of the dummy gate 12 on both the PMOS device region and the NMOS device region is etched, there is no etching height difference in the silicon oxide on top of the dummy gate 12 on the PMOS device region and the NMOS device region. The height difference between the silicon oxide on top of the dummy gate 12 on the PMOS device region and the NMOS device region is only caused by the process of etching the surface protection layer 14 using the photoresist layer 15 as a mask before, thus Figure 5h the height difference between the silicon oxide on top of the dummy gate 12 on the PMOS device region and the NMOS device region in Figure 5h is only the thickness of the surface protection layer 14, so it will not have an obvious impact on the filling and polishing of the subsequent interlayer dielectric layer.

[0082] The manufacturing method of the semiconductor structure provided by the embodiment of the present application may further include: after step S160, etching is performed to widen the preliminary trench 17 to form a sigma trench 18 for growing silicon germanide as shown in Figure 5i Figure 5i . Then, silicon germanide is grown in the sigma trench 18 to form a silicon germanium trench 19 as shown in Figure 5j Figure 5j , thus completing the formation process of the silicon germanium trench 19. It should be noted that Figure 5j only one silicon germanium trench 19 is shown. In practice, a silicon germanium trench 19 can be formed in the reserved areas on both sides of each dummy gate 12 in the PMOS device region.

[0083] The manufacturing method of the semiconductor structure provided by the above embodiments mainly introduces in detail the improvement points compared with the prior art, aiming to illustrate that the improvement points compared with the prior art can make the chemical mechanical polishing load of the interlayer dielectric layer small during the manufacturing process of the semiconductor structure and can make the probability of the existence of gaps in the interlayer dielectric layer included in the semiconductor structure low. For the content other than the improvement points, reference can be made to the relevant descriptions of the prior art.

[0084] Corresponding to the manufacturing method of the semiconductor structure provided in the above embodiments, another embodiment of the present application further provides a semiconductor structure. The semiconductor structure is manufactured by any of the manufacturing methods provided in the above embodiments. Since the chemical mechanical polishing load of the interlayer dielectric layer is small during the manufacturing process and the probability of the existence of gaps in the included interlayer dielectric layer is low, it has excellent electrical properties and low manufacturing costs. Figure 5j The structure shown can be regarded as an exemplary structure of part of the semiconductor structure provided in the embodiments of the present application. It should be understood that Figures 5a to 5j mainly illustrates the formation process of the germanium-silicon trench 19. Therefore, in order for the semiconductor structure provided in the embodiments of the present application to have the complete structures of PMOS devices and NMOS devices, it is also necessary to Figure 5j further form source regions, drain regions, and connection lines on the structure shown, and additionally form isolation structures between different MOS devices, etc. In addition Figure 5j the structure shown only exemplarily illustrates the formed germanium-silicon trench 19, and does not limit the respective numbers of PMOS devices and NMOS devices in the semiconductor structure provided in the embodiments of the present application.

[0085] As described above in accordance with the embodiments of the present application, these embodiments do not describe all the details in detail, nor do they limit the application to only the specific embodiments described. Obviously, many modifications and variations can be made according to the above description. The present specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present application, so that those skilled in the art can make good use of the present application and its modifications based on the present application. The present application is only limited by the claims and their full scope and equivalents.

Claims

1. A method for manufacturing a semiconductor structure, comprising: Providing a substrate, the substrate comprising an NMOS device region and a PMOS device region; forming dummy gates on the NMOS device region and the PMOS device region; forming a surface protection layer on the dummy gate and the substrate; Forming a functional layer on the surface protection layer, the area of ​​the PMOS device region other than under the dummy gate and the dummy gate sidewall functional layer is a reserved area; Etching away the functional layer located on the top of the dummy gate; Forming a photoresist layer covering the functional layer and the top of the dummy gate on the NMOS device region and having an opening on the PMOS device region; Using the photoresist layer as a mask, etching the functional layer and the surface protection layer until the surface of the reserved area is exposed, and then removing the photoresist layer; A preliminary trench is formed in the reserved area.

2. The manufacturing method according to claim 1, wherein: The functional layer located on the top of the dummy gate is etched away, comprising: Depositing a mask material on the functional layer on the reserved area and making the deposited mask material flush with the functional layer on the top of the dummy gate to form a mask layer with an opening on the top of the dummy gate; The functional layer is etched using the mask layer as a mask until the functional layer at the top of the dummy gate is etched away, and then the mask layer is removed.

3. The manufacturing method according to claim 2, wherein: The mask material is amorphous carbon, and the material used for the functional layer is silicon nitride.

4. The manufacturing method according to claim 1, wherein: The thickness of the surface protection layer is smaller than the thickness of the functional layer.

5. The manufacturing method according to claim 1, wherein: The material used for the substrate is silicon, the material used for the functional layer is silicon nitride, the material used for the surface protection layer is silicon oxide, the pseudo gate includes a top protection layer located on the top and the material used for the top protection layer is silicon oxide, and a preparatory groove is formed in the reserved area, including: dry etching using hydrogen bromide plasma gas as etching gas to form the preparatory groove in the reserved area.

6. The manufacturing method according to claim 1, wherein: The material used for the functional layer is silicon nitride, and the functional layer is etched by dry etching using a plasma gas mixed with carbon tetrafluoride and fluoromethane as etching gas.

7. The manufacturing method according to claim 1, further comprising: The preliminary trench is widened by etching to form a sigma trench for growing silicon germanium.

8. A semiconductor structure, wherein the semiconductor structure is manufactured by the manufacturing method according to any one of claims 1 to 7.

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