Silicon-based hetero-device monolithic integration method and silicon-based hetero-device monolithic

Abstract

The application relates to the technical field of semiconductor device preparation, and discloses a silicon-based hetero-device monolithic integration method and a silicon-based hetero-device monolithic, which comprises the following steps: depositing dielectric material on the surface of a silicon substrate, opening an isolation groove above an N well and a P well, and forming an epitaxial stack in the groove; depositing a hard mask layer and performing a patterning process to form a reserved mask layer above the epitaxial stack, and then preparing two different types of vertical devices in the isolation groove; depositing dielectric material in the isolation groove, and exposing the surface of the vertical devices to the external environment by adopting a recess process; performing HKMG deposition and a patterning process on the surface of the vertical devices to form a high-K metal gate, then depositing an interlayer dielectric to form an interlayer dielectric layer, etching a through hole in the interlayer dielectric layer and filling the through hole with conductive metal to form a silicon-based hetero-device monolithic. The above method realizes high-density integration of vertical devices of different types, and significantly improves the performance, reliability and integration of the devices.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor device preparation, in particular to a silicon-based hetero-device monolithic integration method and a silicon-based hetero-device monolith. BACKGROUND

[0002] With the continuous reduction of the size of various electronic devices, the integration density is also increasing, and high integration density leads to increased interconnection delay and power consumption, making the manufacturing process more complex and expensive.

[0003] Specifically, the integration of transistors of multiple different materials faces problems such as poor material compatibility, high process complexity, and difficulty in performance optimization, resulting in interface defects and stress problems, affecting the overall performance and reliability of the device, and further limiting the development of high-performance, high-integration integrated circuits. SUMMARY

[0004] Therefore, the present application provides a silicon-based hetero-device monolithic integration method and a silicon-based hetero-device monolith, which mainly aims to solve the technical problems of poor material compatibility, complex preparation process and low performance of hetero-integration of different devices in the prior art.

[0005] In one aspect, the present application provides a silicon-based hetero-device monolithic integration method, comprising:

[0006] Depositing a dielectric material on the surface of a silicon substrate, opening isolation grooves above the N-well and P-well of the silicon substrate respectively, and forming an epitaxial stack in the isolation grooves;

[0007] Depositing a hard mask layer above the epitaxial stack and performing a patterning process on the hard mask layer to form a reserved mask layer above the epitaxial stack, and based on the epitaxial stack and the reserved mask layer, two different types of vertical devices are prepared in the corresponding isolation grooves of the N-well and P-well of the silicon substrate respectively;

[0008] Depositing a dielectric material in the isolation grooves, using a recess process to make the dielectric material lower than the height of the vertical devices, and exposing the surface of the vertical devices to the external environment;

[0009] Performing HKMG deposition and patterning process on the surface of the two different types of vertical devices to form a high-K metal gate, depositing an interlayer dielectric on the high-K metal gate to form an interlayer dielectric layer, and based on a predetermined layout position, performing via etching on the interlayer dielectric layer and filling it with conductive metal to form a silicon-based hetero-device monolith.

[0010] Optionally, before the step of depositing a dielectric material on the surface of a silicon substrate, the method comprises:

[0011] A well region is formed on a surface of a silicon substrate by an ion implantation process, wherein the well region comprises an N well and a P well.

[0012] Optionally, the method further comprises:

[0013] depositing a first dielectric material on the surface of the silicon substrate, opening a first isolation groove above the N well of the silicon substrate, and forming a first epitaxial layer in the first isolation groove;

[0014] depositing the first dielectric material again on the first epitaxial layer and the first dielectric material, and performing chemical mechanical polishing on the deposited first dielectric material;

[0015] opening a second isolation groove above the P well of the silicon substrate, and forming a second epitaxial layer in the second isolation groove, wherein the first epitaxial layer and the second epitaxial layer are different in material;

[0016] performing chemical mechanical polishing on the first dielectric material to equalize the height of the first epitaxial layer, the second epitaxial layer, and the first dielectric material.

[0017] Optionally, the method further comprises:

[0018] depositing a hard mask layer on the first epitaxial layer and the second epitaxial layer;

[0019] performing photolithography and etching on the hard mask layer in sequence to form a first local mask layer above the first epitaxial layer and a second local mask layer above the second epitaxial layer, respectively;

[0020] performing sidewall deposition and etching on the first local mask layer and the second local mask layer in sequence to form a first reserved mask layer above the first epitaxial layer and a second reserved mask layer above the second epitaxial layer.

[0021] Optionally, the method further comprises:

[0022] depositing a second dielectric material on the surface of the corresponding first dielectric material above the P well of the silicon substrate, so that the second dielectric material covers the second reserved mask layer;

[0023] performing photoetching and developing on the first epitaxial stack, and based on the first epitaxial stack and the first reserved mask layer, preparing a first vertical device in the first isolation groove;

[0024] removing the second dielectric material above the second reserved mask layer, and depositing second dielectric material in the first isolation groove so that the second dielectric material covers the first vertical device;

[0025] performing photoetching and developing on the second epitaxial stack, and based on the second epitaxial stack and the second reserved mask layer, preparing a second vertical device in the second isolation groove, and removing the second dielectric material covering the surface of the first vertical device.

[0026] Optionally, the deposition of the dielectric material in the isolation groove adopts a recess process to make the dielectric material lower than the height of the vertical device, and expose the surface of the vertical device to the external environment, including:

[0027] depositing first dielectric material in the first isolation groove and the second isolation groove, and performing chemical mechanical polishing on the first dielectric material so that the height of the first vertical device, the second vertical device and the first dielectric material is equal;

[0028] adopting a recess process to etch the first dielectric material to be lower than the height of the first vertical device and the second vertical device, and expose the surface of the first vertical device and the second vertical device to the external environment.

[0029] Optionally, the HKMG deposition and patterning process on the surface of the two different types of vertical devices to form a high-K metal gate, including:

[0030] simultaneously performing HKMG deposition on the surface of the first vertical device and the second vertical device so that the surface of the first vertical device and the second vertical device is covered with a high-K layer, and the surface of the high-K layer is covered with a metal gate layer;

[0031] performing photoetching and etching on the metal gate layer based on a preset pattern to form a high-K metal gate.

[0032] Optionally, the interlayer dielectric deposition on the high-K metal gate to form an interlayer dielectric layer, the via etching on the interlayer dielectric layer based on a preset layout position and the filling of conductive metal to form a silicon-based heterojunction device monolithic, including:

[0033] performing interlayer dielectric deposition on the surface of the high-K metal gate to form an interlayer dielectric layer;

[0034] etching a via hole from the top of the interlayer dielectric layer based on the preset layout position, and filling the via hole with conductive metal to form a silicon-based hetero-device monolithic, wherein the bottom of the via hole is in contact with the first vertical device and the second vertical device respectively.

[0035] In another aspect, the application provides a silicon-based hetero-device monolithic prepared by the silicon-based hetero-device monolithic integration method described above, comprising:

[0036] a silicon substrate, a surface of the silicon substrate being provided with an N well and a P well;

[0037] a first vertical device, the first vertical device being arranged above the N well;

[0038] a second vertical device, the second vertical device being arranged above the P well, and a surface of the first vertical device and the second vertical device being covered with a high-K metal gate layer;

[0039] a dielectric material layer, the dielectric material layer being laid on the surface of the silicon substrate and covering the bottom of the first vertical device and the second vertical device;

[0040] an interlayer dielectric layer, the interlayer dielectric layer covering the surface of the first vertical device and the second vertical device;

[0041] a plurality of via holes, the plurality of via holes being opened in the interlayer dielectric layer in a vertical direction until the bottom of the via hole is in contact with the surface of the first vertical device or the second vertical device, and the via hole being filled with conductive metal.

[0042] Optionally, the first vertical device is an NMOS tube, and the second vertical device is a PMOS tube,

[0043] or the first vertical device is an MOS tube, and the second vertical device is a laser or a detector.

[0044] The silicon-based hetero-device monolithic integration method and the silicon-based hetero-device monolithic provided by the application can realize the hetero-integration of different devices, for example, the hetero-integration of vertical devices and optoelectronic devices with matching structural characteristics, thereby significantly improving the integration density; in particular, in the isolation groove opened based on the dielectric material, the device can be subjected to laminated epitaxy, the isolation groove can limit the bulk defects in the thin film hetero-epitaxy, thereby obtaining high-quality device laminated films, and the isolation groove structure can also apply stress to the device, thereby greatly improving the performance of the device; at the same time, the film layer structures of different devices can be independently grown, the preparation process of a single device is flexible, different devices can be independently prepared, and the preparation process of another device is not affected; further, the prepared devices can be continuously integrated in the vertical direction, without occupying more area, which is more conducive to industrial application; through high-K metal gate deposition, interlayer dielectric deposition, via etching and conductive metal filling technologies, the manufacturing process is optimized, the electrical and optical performance of the device is improved, and the consistency and reliability of the device are improved. In summary, the above method realizes the high-density integration of different types of vertical devices, significantly improves the performance, reliability and integration density of the device.

[0045] The above description is only a summary of the technical solutions of the application, in order to more clearly understand the technical means of the application, the application can be implemented according to the content of the specification, and in order to make the above and other purposes, characteristics and advantages of the application more obvious and easy to understand, the following specific embodiments of the application are described. BRIEF DESCRIPTION OF DRAWINGS

[0046] The drawings described herein are used to provide further understanding of the application, constitute a part of the application, the schematic embodiments of the application and the description thereof are used to explain the application, and do not constitute an improper limitation on the application. In the drawings:

[0047] Figure 1 A flowchart of the silicon-based hetero-device monolithic integration method provided by the embodiment of the application is shown;

[0048] Figure 2 A schematic diagram of the well implantation on the silicon substrate in the silicon-based hetero-device monolithic integration method provided by the embodiment of the application is shown;

[0049] Figure 3 A schematic diagram of the dielectric deposition and the opening of the first isolation groove in the silicon-based hetero-device monolithic integration method provided by the embodiment of the application is shown;

[0050] Figure 4 A schematic diagram of the formation of the first epitaxial layer in the silicon-based hetero-device monolithic integration method provided by the embodiment of the application is shown;

[0051] Figure 5A schematic view of medium deposition and second isolation groove opening in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0052] Figure 6 A schematic view of second epitaxial layer formation in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0053] Figure 7 A schematic view of chemical mechanical polishing in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0054] Figure 8 A schematic view of hard mask layer deposition in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0055] Figure 9 A schematic view of hard mask layer photolithography and etching in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0056] Figure 10 A schematic view of local hard mask layer side wall deposition and etching in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0057] Figure 11 A schematic view of medium deposition, photolithography and etching in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0058] Figure 12 A schematic view of first vertical device preparation in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0059] Figure 13 A schematic view of medium deposition, photolithography and development in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0060] Figure 14 A schematic view of second vertical device preparation in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0061] Figure 15 A schematic view of medium material removal in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0062] Figure 16 A schematic view of shallow trench isolation deposition and chemical mechanical polishing in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0063] Figure 17 A schematic view of recess process etching back medium material in the monolithic integration method of the silicon-based heterostructure device provided by the embodiment of the present application is shown;

[0064] Figure 18 A schematic diagram of HKMG deposition in the method for monolithic integration of silicon-based heterostructure devices provided by the embodiment of the present application is shown.

[0065] Figure 19 A schematic diagram of MG lithography and etching in the method for monolithic integration of silicon-based heterostructure devices provided by the embodiment of the present application is shown.

[0066] Figure 20 A schematic diagram of ILD deposition and chemical mechanical polishing in the method for monolithic integration of silicon-based heterostructure devices provided by the embodiment of the present application is shown.

[0067] Figure 21 A schematic diagram of the structure of the monolithic silicon-based heterostructure device provided by the embodiment of the present application is shown.

[0068] In the diagram:

[0069] 1. Silicon substrate; 101. N well; 102. P well;

[0070] 2. First dielectric material;

[0071] 3. First isolation groove;

[0072] 4. First epitaxial layer;

[0073] 5. Second isolation groove;

[0074] 6. Second epitaxial layer;

[0075] 7. Hard mask layer; 701. First local mask layer; 702. Second local mask layer; 703. First reserved mask layer; 704. Second reserved mask layer;

[0076] 8. Second dielectric material;

[0077] 9. First vertical device;

[0078] 10. Second vertical device;

[0079] 11. High-K layer;

[0080] 12. Metal gate layer;

[0081] 13. Interlayer dielectric layer;

[0082] 14. Via hole. DETAILED DESCRIPTION

[0083] Exemplary embodiments of the present application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present application are shown in the drawings, it should be understood that the present application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this application will be thorough and complete, and will fully convey the scope of the present application to those skilled in the art.

[0084] This invention provides a method for monolithic integration of silicon-based heterogeneous devices, such as... Figure 1 As shown, firstly, dielectric material is deposited on the surface of a silicon substrate. Isolation trenches are formed above the N-wells and P-wells of the silicon substrate, and epitaxial stacks are formed within the isolation trenches. Then, a hard mask layer is deposited above the epitaxial stack, and the hard mask layer is patterned to form a retention mask layer above the epitaxial stack. Based on the epitaxial stack and the retention mask layer, two different types of vertical devices are fabricated in the isolation trenches corresponding to the N-wells and P-wells of the silicon substrate, respectively. Next, dielectric material is deposited in the isolation trenches, and a recessed process is used to make the dielectric material lower than the height of the vertical device, exposing the surface of the vertical device to the external environment. Finally, HKMG deposition and patterning processes are performed on the surfaces of the two different types of vertical devices to form high-k metal gates. Interlayer dielectric deposition is performed on the high-k metal gates to form an interlayer dielectric layer. Based on the preset layout positions, via etching is performed on the interlayer dielectric layer and conductive metal is filled to form a silicon-based heterogeneous device monolith.

[0085] The silicon-based heterogeneous device monolithic integration method provided by this invention enables heterogeneous integration of different devices, such as heterogeneous integration of vertical devices with matching structural features and optoelectronic devices, significantly improving integration density. Specifically, device stacking epitaxy can be performed within isolation trenches created based on dielectric materials. The isolation trenches can limit bulk defects in thin film heteroepitaxialization, thereby obtaining high-quality device stacked films. Furthermore, the isolation trench structure can also apply compressive stress to the devices, greatly improving device performance. Simultaneously, the film structures of different devices can be grown independently, and the fabrication process of individual devices is flexible, allowing different devices to be fabricated independently without affecting the fabrication process of other devices. Moreover, the fabricated devices can be continuously stacked and integrated in the vertical direction without occupying more area, which is more conducive to industrial applications. Through high-k metal gate deposition, interlayer dielectric deposition, through-hole etching, and conductive metal filling techniques, the manufacturing process is optimized, improving the electrical and optical performance of the devices and enhancing their consistency and reliability. In summary, the above method achieves high-density integration of different types of vertical devices, significantly improving device performance, reliability, and integration density.

[0086] The specific operation steps of the silicon-based heterogeneous device monolithic integration method provided by this invention are as follows:

[0087] Step 1: Perform well implantation on silicon substrate 1.

[0088] Specifically, a well region is formed on the surface of the silicon substrate 1 by an ion implantation process, wherein the well region includes an N-well 101 and a P-well 102.

[0089] The N-well 101 and the P-well 102 are commonly used doped regions in semiconductor manufacturing, mainly used for forming different types of transistors and isolating different functional regions. The conductivity type of the material is changed by introducing different types of dopants into the silicon substrate 1. The N-well 101 is a region formed by doping n-type dopants in a p-type silicon substrate 1, and the majority carriers in the N-well 101 are electrons. The P-well 102 is a region formed by doping p-type dopants in an n-type silicon substrate 1, and the majority carriers in the P-well 102 are holes.

[0090] In this embodiment, as shown in Figure 2 , the N-well 101 and the P-well 102 are formed on the surface of the silicon substrate 1 by an ion implantation process, providing necessary doped regions for the subsequent preparation of vertical devices and optoelectronic devices. The specific process steps include coating a layer of photoresist on the silicon substrate 1, then using a mask and an exposure light source to irradiate the photoresist, then removing the unexposed photoresist with a developing solution to expose the area that needs to be implanted with ions, then using an ion implanter to implant doped ions into the specific area of the silicon substrate 1 to form the N-well 101 and the P-well 102, and finally removing the remaining photoresist.

[0091] Step 2, deposit a first dielectric material 2 and open a first isolation trench 3.

[0092] Specifically, the first dielectric material 2 is deposited on the surface of the silicon substrate 1, and the first isolation trench 3 is opened above the N-well 101 of the silicon substrate 1.

[0093] The first dielectric material 2 can be silicon oxide or silicon nitride, and the deposition method can use chemical vapor deposition, plasma-enhanced chemical vapor deposition, or high-density plasma chemical vapor deposition.

[0094] In this embodiment, as shown in Figure 3 , a layer of dielectric material is deposited on the surface of the silicon substrate 1 to provide a basis for the subsequent isolation trench opening and epitaxial growth. The isolation trench is opened above the N-well 101 of the silicon substrate 1 to provide a clear boundary for the subsequent epitaxial layer growth and reduce parasitic effects. The opening of the isolation trench can effectively isolate different types of devices, reduce parasitic effects, and improve the performance and reliability of the device. The isolation trench can also limit the bulk defects in the thin film heteroepitaxy, thereby obtaining high-quality epitaxial films. The isolation trench structure can also apply stress to the device, further improving the performance of the device. The first dielectric material 2 has high insulation performance, which can effectively isolate different functional regions and reduce electrical interference.

[0095] Step 3, form a first epitaxial layer 4.

[0096] Specifically, a first epitaxial layer 4 is formed within the first isolation groove 3.

[0097] In this embodiment, such as Figure 4 As shown, an epitaxial stack is grown in the first isolation trench 3 to achieve heterogeneous integration of different materials, providing a high-quality thin film for subsequent device fabrication. The epitaxial stack consists of three layers: the top and bottom layers are Si (silicon), GeSi (germanium-silicon alloy), GaAs (gallium arsenide), and Ge (germanium); the middle layer is Si (silicon), GeSi (germanium-silicon alloy), and InGaAs (indium gallium arsenide). The method for generating the epitaxial stack is RPCVD (remote plasma chemical vapor deposition) technology, which enables the growth of high-quality, low-defect epitaxial thin films through remote activation of plasma, thereby improving the quality of the epitaxial thin film. The epitaxial stack structure formed in this application can optimize the interface quality between layers, reduce interface defects, and improve device performance. The multi-layer structure can optimize stress distribution, reduce stress problems caused by material mismatch, and improve device reliability and performance. Remote plasma chemical vapor deposition technology can select different materials and process parameters according to specific needs to adapt to the fabrication of different types of devices. Furthermore, the formation of epitaxial stacks in isolation trenches can realize the integration of different types of devices in the vertical direction, improve integration density, and the growth of epitaxial stacks can ensure surface planarization, providing a good foundation for subsequent process steps.

[0098] Step 4: Deposit the medium and open the second isolation tank 5.

[0099] Specifically, the first dielectric material 2 is deposited again on top of the first epitaxial stack 4 and the first dielectric material 2, and the deposited first dielectric material 2 is chemically and mechanically polished, and a second isolation trench 5 is opened on top of the P-well 102 of the silicon substrate 1.

[0100] In this embodiment, such as Figure 5 As shown, a dielectric material is deposited again on top of the first epitaxial layer 4 and the first dielectric material 2 to provide protection and support for subsequent isolation trench opening and device fabrication. The first dielectric material 2 after deposition is chemically and mechanically polished to ensure surface planarization, providing a good foundation for subsequent process steps. After chemically and mechanically polishing the first dielectric material 2, a second isolation trench 5 is opened on top of the P-well 102 of the silicon substrate 1 to provide clear boundaries for subsequent epitaxial layer growth and device fabrication, reducing parasitic effects.

[0101] Step 5: Form the second epitaxial layer 6.

[0102] Specifically, a second epitaxial layer 6 is formed within the second isolation groove 5.

[0103] In the embodiment, as shown in Figure 6 The second epitaxial layer 6 is formed in the second isolation groove 5. The forming process of the second epitaxial layer 6 and the forming process of the first epitaxial layer 4 can both adopt remote plasma chemical vapor deposition technology. However, considering that the devices prepared in the first isolation groove 3 and the second isolation groove 5 are different devices, for example, the device in the first isolation groove 3 is an NMOS tube, and the device in the second isolation groove 5 is a PMOS tube; or the device in the first isolation groove 3 is a MOS tube, and the device in the second isolation groove 5 is a laser or a detector, considering that the structures and processes of the two devices are different, the two devices need to be prepared separately in the two isolation grooves.

[0104] Step 6, chemical mechanical polishing.

[0105] Specifically, the first dielectric material 2 is subjected to chemical mechanical polishing, so that the heights of the first epitaxial layer 4, the second epitaxial layer 6, and the first dielectric material 2 are equal.

[0106] In the embodiment, as shown in Figure 7 After the second layer is formed, the first dielectric material 2 is subjected to chemical mechanical polishing, so that the heights of the first epitaxial layer 4, the second epitaxial layer 6, and the first dielectric material 2 are equal, and the surface is planarized, which can reduce defects in subsequent processes, improve the yield and performance of the device, provide a good foundation for subsequent preparation processes, and ensure the reliability and performance of interconnection.

[0107] Step 7, deposition of a hard mask layer 7.

[0108] Specifically, the hard mask layer 7 is deposited above the first epitaxial layer 4 and the second epitaxial layer 6.

[0109] In the embodiment, as shown in Figure 8 The deposition of the hard mask layer 7 provides protection and a mask for subsequent patterning processes and etching steps. The hard mask layer 7 is also a three-layer structure, in which the upper and lower layers can be oxide layers, and the middle layer can be silicon nitride. The hard mask layer 7 protects the epitaxial layer during subsequent etching and process steps, preventing physical or chemical damage to the epitaxial layer and ensuring the integrity of the device structure. The hard mask layer 7 can also reduce the direct effect of the epitaxial layer during etching, reduce the generation of defects, and improve the performance and reliability of the device. Moreover, the hard mask layer 7 generally has a high etching selectivity, that is, the etching rate of the hard mask layer 7 relative to the epitaxial layer is low during etching, which can more accurately control the etching depth and shape. Through photolithography and etching processes, the hard mask layer 7 can be patterned to form a desired mask pattern, providing an accurate mask for subsequent process steps.

[0110] Step 8, patterning and etching of the hard mask layer 7.

[0111] Specifically, the hard mask layer 7 is subjected to patterning and etching processes in sequence to form a first local mask layer 701 above the first epitaxial stack 4 and a second local mask layer 702 above the second epitaxial stack 6, respectively.

[0112] In this embodiment, such as Figure 9 As shown, the desired pattern is formed on the hard mask layer 7 using photolithography, providing a mask for subsequent etching steps. Specifically, a layer of photoresist is uniformly coated on the surface of the hard mask layer 7. The photoresist is then irradiated using a mask and an exposure light source, causing a chemical change in the exposed area. A developer is then used to remove part of the photoresist, exposing a portion of the hard mask layer 7 and forming the desired pattern. Subsequently, an etching process, such as reactive ion etching or other dry etching techniques, is used to remove the portion of the hard mask layer 7 not protected by the photoresist, forming a local mask layer. Dry etching techniques can achieve high-precision etching, ensuring clear edges of the local mask layer and reducing defects during the etching process.

[0113] Step 9: Deposition and etching of the sidewalls of the local hard mask layer 7.

[0114] Specifically, the first local mask layer 701 and the second local mask layer 702 are sequentially subjected to sidewall deposition and etching to form a first reserved mask layer 703 above the first epitaxial stack 4 and a second reserved mask layer 704 above the second epitaxial stack 6.

[0115] In this embodiment, such as Figure 10 As shown, a protective material is deposited on the sidewalls of the first local mask layer 701 and the second local mask layer 702 to form sidewalls. The sidewall material is usually selected from materials with high etching selectivity and good mechanical strength, such as silicon nitride and silicon oxide. The sidewalls are deposited on the sidewalls of the local mask layers, providing additional protection for subsequent etching steps and preventing damage to the epitaxial stack during the etching process. The protective effect of the sidewalls can reduce defects generated during the etching process and improve the performance and reliability of the device. Through sidewall deposition and etching, the pattern and size of the remaining mask layer can be precisely controlled to ensure the consistency and reliability of the device.

[0116] Step 10: Deposition of the first medium material 2.

[0117] Specifically, a second dielectric material 8 is deposited on the surface of the first dielectric material 2 above the P-well 102 of the silicon substrate 1, so that the second dielectric material 8 covers the second retention mask layer 704.

[0118] In this embodiment, such as Figure 11As shown, the second dielectric material 8 can be silicon oxide or silicon nitride in particular, and considering that the devices in the two isolation grooves need to be prepared in sequence respectively, before the preparation of the device in the first isolation groove 3, the second dielectric material 8 is deposited on the second reserved mask layer 704 above the second epitaxial layer 6, that is, the protection of the second reserved mask layer 704 is realized by photoresist.

[0119] Step 11, preparation of the first vertical device 9.

[0120] Specifically, the first epitaxial layer 4 is subjected to photoetching and developing treatment, and based on the first epitaxial layer 4 and the first reserved mask layer 703, the first vertical device 9 is prepared in the first isolation groove 3.

[0121] In the present embodiment, as shown, Figure 12 After the protection of the second epitaxial layer 6 and the second reserved mask layer 704 is formed, the first epitaxial layer 4 is first subjected to photoetching and developing treatment to expose the first epitaxial layer 4, and then the preparation of the first vertical device 9 is performed in the first isolation groove 3. The vertical device can be a vertical gate-all-around (VGAA) device, which is an advanced semiconductor device structure, particularly suitable for future nanoscale integrated circuits. Specifically, by forming nanowires or nanosheets as channels in the vertical direction and wrapping the gate around them, the performance and reliability of the device are significantly improved.

[0122] Step 12, deposition of the second dielectric material 8.

[0123] Specifically, the second dielectric material 8 above the second reserved mask layer 704 is removed, and the second dielectric material 8 is deposited in the first isolation groove 3 so that the second dielectric material 8 covers the first vertical device 9.

[0124] In the present embodiment, as shown, Figure 13 After the preparation of the first vertical device 9 is completed, further preparation of the second vertical device 10 is needed, and at this time the same method can be used to remove the second dielectric material 8 covering the second reserved mask layer 704, deposit the second dielectric material 8 in the first isolation groove 3 so that the second dielectric material 8 covers the first vertical device 9, forming protection for the first vertical device 9, avoiding the preparation of the second vertical device 10 affecting the first vertical device 9.

[0125] Step 13, preparation of the second vertical device 10.

[0126] Specifically, the second epitaxial layer 6 is subjected to photoetching and developing treatment, and based on the second epitaxial layer 6 and the second reserved mask layer 704, the second vertical device 10 is prepared in the second isolation groove 5.

[0127] In the embodiment, as shown in Figure 14 After the first vertical device 9 is formed with the protection of the second medium material 8, the second epitaxial layer 6 is also subjected to the photoetching and developing process to expose the second epitaxial layer 6, and then the second vertical device 10 is prepared in the second isolation groove 5. The first vertical device 9 and the second vertical device 10 are completely different devices, and thus the basis of the silicon-based hetero-device monolithic integration is formed.

[0128] Step 14, medium material removal.

[0129] Specifically, the second medium material 8 covering the surface of the first vertical device 9 is removed.

[0130] In the embodiment, as shown in Figure 15 After the preparation of the second vertical device 10 is completed, the second medium material 8 covering the surface of the first vertical device 9 needs to be removed. The dry etching or wet etching can be used for the removal. At this time, the first vertical device 9 and the second vertical device 10 are respectively prepared in the first isolation groove 3 and the second isolation groove 5.

[0131] Step 15, shallow trench isolation deposition and chemical mechanical polishing.

[0132] Specifically, the first medium material 2 is deposited in the first isolation groove 3 and the second isolation groove 5, and the chemical mechanical polishing is performed on the first medium material 2 to make the height of the first vertical device 9, the second vertical device 10 and the first medium material 2 equal.

[0133] In the embodiment, as shown in Figure 16 The first medium material 2 is deposited in the first isolation groove 3 and the second isolation groove 5 to provide protection and support for the subsequent process steps and realize the isolation between devices. The chemical mechanical polishing is performed on the deposited first medium material 2 to ensure the planarization of the surface, make the height of the first vertical device 9, the second vertical device 10 and the first medium material 2 equal, provide a good foundation for the subsequent process steps, and reduce the defects in the subsequent process and improve the yield and performance of the device.

[0134] Step 16, recess process etching medium material.

[0135] Specifically, the recess process is used to etch the first medium material 2 to be lower than the height of the first vertical device 9 and the second vertical device 10, and expose the surface of the first vertical device 9 and the second vertical device 10 to the external environment.

[0136] In the embodiment, as shown in Figure 17As shown, the first dielectric material 2 is etched to a height lower than that of the first vertical device 9 and the second vertical device 10 by a back-etching process, exposing the surface of the vertical devices to facilitate subsequent process steps, while also ensuring that the height of the first dielectric material 2 after back-etching and the exposure of the surface of the vertical devices meet the requirements.

[0137] Step 17, HKMG deposition.

[0138] Specifically, the surfaces of the first vertical device 9 and the second vertical device 10 are simultaneously subjected to HKMG deposition, so that the surfaces of the first vertical device 9 and the second vertical device 10 are covered with a high-K layer 11, and the surface of the high-K layer 11 is covered with a metal gate layer 12.

[0139] In this embodiment, as shown Figure 18 The High-K Metal Gate (HKMG) technology is an important technology in modern semiconductor devices, aiming to improve the performance and reliability of the devices. High-K materials can reduce gate leakage current, while metal gate materials can improve the operating characteristics and reliability of the gate. By simultaneously depositing HKMG on the surfaces of the first vertical device 9 and the second vertical device 10, the overall optimization of the devices can be achieved.

[0140] The operation steps include cleaning and pretreating the surfaces of the first vertical device 9 and the second vertical device 10 to ensure that the device surfaces are clean and free of contaminants, providing a good foundation for subsequent deposition processes, then depositing high-K materials on the surfaces of the first vertical device 9 and the second vertical device 10 to form a gate insulating layer, and then depositing metal gate materials on the surface of the high-K materials to form a metal gate layer 12.

[0141] Step 18, MG lithography and etching.

[0142] Specifically, the metal gate layer 12 is subjected to lithography and etching based on a predetermined pattern to form a high-K metal gate.

[0143] In this embodiment, as shown Figure 19 After completing the previous steps, the surfaces of the first device and the second device are covered with a high-K layer 11 and a metal gate layer 12. Further, the metal gate layer 12 on the high-K layer 11 needs to be subjected to lithography and etching based on a predetermined pattern, only retaining part of the metal gate layer 12 to form the predetermined pattern, which, together with the underlying high-K layer 11, forms an accurate gate structure, which is crucial for controlling the channel potential, reducing leakage current, and improving device performance.

[0144] Step 19, ILD deposition and chemical mechanical polishing.

[0145] Specifically, interlayer dielectric deposition is performed on the surface of the high-K metal gate to form an interlayer dielectric layer 13.

[0146] In this embodiment, as shown in Figure 20 In semiconductor manufacturing, the deposition of the interlayer dielectric (ILD) layer 13 is to provide insulation and isolation between different levels of metal interconnects, reduce parasitic capacitance, improve device performance and reliability. The deposition of the interlayer dielectric on the surface of the high-K metal gate can ensure good insulation between the gate and other metal layers, and provide a flat surface for subsequent interconnection processes. The specific processing steps include cleaning and pretreatment to ensure that the surface of the high-K metal gate is clean and free of contaminants, providing a good foundation for subsequent deposition processes. Then, the interlayer dielectric material is deposited on the surface of the high-K metal gate to form the interlayer dielectric layer 13, providing insulation and isolation. Finally, the surface of the interlayer dielectric layer 13 is planarized by a chemical mechanical polishing process to provide a good foundation for subsequent interconnection processes.

[0147] Step 20, via hole 14 etching and filling.

[0148] Specifically, based on the preset layout position, the via hole 14 is formed by etching from the top of the interlayer dielectric layer 13, and the conductive metal is filled in the via hole 14 to form a silicon-based hetero-device monolithic, wherein the bottom of the via hole 14 is in contact with the first vertical device 9 and the second vertical device 10, respectively.

[0149] In this embodiment, as shown in Figure 21 In semiconductor manufacturing, the formation of the via hole 14 is a key step to realize different levels of metal interconnection. By etching from the top of the interlayer dielectric layer 13 to form the via hole 14 and filling the conductive metal in the via hole 14, electrical connection between different levels can be achieved, thereby forming a complete silicon-based hetero-device monolithic. The etching process can use dry etching, such as reactive ion etching, to remove the interlayer dielectric material not protected by photoresist to form the via hole 14. The etching time and conditions need to be accurately controlled during the etching process to ensure that the depth and shape of the via hole 14 meet the design requirements. The etching endpoint is detected by optical or electrical methods to ensure that the bottom of the via hole 14 accurately contacts the first vertical device 9 and the second vertical device 10. The remaining photoresist is removed to expose the complete via hole 14 structure. Finally, the inner wall of the via hole 14 is pretreated, such as cleaning and surface modification, to improve the adhesion of the metal. Physical vapor deposition, chemical vapor deposition or electroplating methods are used to deposit conductive metals such as tungsten and copper in the via hole 14 to complete the preparation of the silicon-based hetero-device monolithic.

[0150] In another aspect, the present invention provides a silicon-based heterogeneous device monolith, fabricated based on any of the aforementioned silicon-based heterogeneous device monolithic integration methods, comprising a silicon substrate 1, on the surface of which N-well 101 and P-well 102 are disposed; a first vertical device 9 disposed above the N-well 101; a second vertical device 10 disposed above the P-well 102, the surfaces of both the first vertical device 9 and the second vertical device 10 being covered with a high-k metal gate layer 12; a dielectric material layer disposed on the surface of the silicon substrate 1 and covering the bottom of the first vertical device 9 and the second vertical device 10; an interlayer dielectric layer 13 covering the surfaces of the first vertical device 9 and the second vertical device 10; and a plurality of vias 14 vertically formed within the interlayer dielectric layer 13 until the bottom of the vias 14 contacts the surface of the first vertical device 9 or the second vertical device 10, and the vias 14 being filled with conductive metal.

[0151] Furthermore, the first vertical device 9 is an NMOS transistor and the second vertical device 10 is a PMOS transistor, or the first vertical device 9 is a MOS transistor and the second vertical device 10 is a laser or a detector.

[0152] Among them, such as Figure 21 As shown, a silicon-based heterogeneous device has five vias on a single chip. After being filled with conductive metal, the five vias are named VSS, Vout, Vin, Vout and VDD according to their functions. VSS is the reference potential point in the circuit and is usually connected to the ground of the power supply; Vout is used to represent the output voltage; Vin is used to represent the input voltage; VDD represents the power supply voltage and is usually connected to the positive terminal of the power supply.

[0153] The silicon-based heterojunction device monolithic provided by the application has high integration, by arranging the first vertical device 9 and the second vertical device 10 above the N well 101 and the P well 102 respectively, different types of device integration in the vertical direction can be realized, and the device density in the unit area is greatly improved; the introduction of the interlayer dielectric layer 13 and the via 14 enables different levels of devices and interconnection lines to be efficiently integrated together, further improving the integration; it also has high performance, the use of the high-K metal gate layer 12 can significantly reduce the gate leakage current and improve the electrical performance of the gate, thereby improving the switching speed and driving ability of the device, the use of the interlayer dielectric layer 13 can reduce the parasitic capacitance and resistance between different metal layers, improve the frequency response and switching speed of the device; it also has high reliability, the interlayer dielectric layer 13 provides good insulation and isolation between different levels of metal interconnection lines, reduces parasitic effects, and improves the reliability and stability of the device; and the silicon-based heterojunction device monolithic provided by the application can realize various device combinations, wherein the first vertical device 9 can be an NMOS tube, the second vertical device 10 can be a PMOS tube, or the first vertical device 9 can be an MOS tube, and the second vertical device 10 can be a laser or a detector, so that the monolithic can be applied to various different application scenarios, specifically, by integrating NMOS tubes and PMOS tubes on the same silicon substrate 1, a high-performance logic circuit can be realized, which is suitable for high-performance computing and data center applications, and by integrating MOS tubes and lasers or detectors on the same silicon substrate 1, optoelectronic integration can be realized, which is suitable for high-speed optical communication systems.

Claims

1. A method for monolithic integration of silicon-based heterostructure devices, comprising: The method comprises the following steps: Depositing a medium material on the surface of a silicon substrate, and opening isolation grooves above the N well and the P well of the silicon substrate respectively, and forming epitaxial layers in the isolation grooves; Depositing a hard mask layer above the epitaxial layers, and performing a patterning process on the hard mask layer to form a reserved mask layer above the epitaxial layers, and based on the epitaxial layers and the reserved mask layer, two different types of vertical devices are prepared in the corresponding isolation grooves of the N well and the P well of the silicon substrate respectively; Depositing a medium material in the isolation grooves, and using a recess process to make the medium material lower than the height of the vertical devices, and exposing the surface of the vertical devices to the external environment; Performing HKMG deposition and patterning process on the surface of the two different types of vertical devices to form high-K metal gates, depositing an interlayer dielectric on the high-K metal gates to form an interlayer dielectric layer, and based on a preset layout position, performing via etching on the interlayer dielectric layer and filling a conductive metal to form a silicon-based heterogeneous device monolithic.

2. The method of claim 1, wherein, Before the step of depositing a medium material on the surface of a silicon substrate, the method comprises the following steps: Forming a well region on the surface of a silicon substrate by using an ion implantation process, wherein the well region comprises an N well and a P well.

3. The method of claim 1, wherein, The step of depositing a medium material on the surface of a silicon substrate, and opening isolation grooves above the N well and the P well of the silicon substrate respectively, and forming epitaxial layers in the isolation grooves comprises the following steps: Depositing a first medium material on the surface of a silicon substrate, opening a first isolation groove above the N well of the silicon substrate, and forming a first epitaxial layer in the first isolation groove; Depositing a first medium material again above the first epitaxial layer and the first medium material, and performing chemical mechanical polishing on the deposited first medium material; Opening a second isolation groove above the P well of the silicon substrate, and forming a second epitaxial layer in the second isolation groove, wherein the first epitaxial layer and the second epitaxial layer are different in material; Performing chemical mechanical polishing on the first medium material to make the height of the first epitaxial layer, the second epitaxial layer and the first medium material equal.

4. The method of claim 3, wherein, The step of depositing a hard mask layer above the epitaxial layers, and performing a patterning process on the hard mask layer to form a reserved mask layer above the epitaxial layers comprises the following steps: Depositing a hard mask layer above the first epitaxial layer and the second epitaxial layer; Performing patterning and etching processes on the hard mask layer in sequence to form a first local mask layer above the first epitaxial layer and a second local mask layer above the second epitaxial layer respectively; Performing sidewall deposition and etching processes on the first local mask layer and the second local mask layer in sequence to form a first reserved mask layer above the first epitaxial layer and a second reserved mask layer above the second epitaxial layer.

5. The method of claim 4, wherein, The step of preparing two different types of vertical devices in the corresponding isolation grooves of the N well and the P well of the silicon substrate based on the epitaxial layers and the reserved mask layer comprises the following steps: Depositing a second medium material on the surface of the corresponding first medium material above the P well of the silicon substrate to cover the second reserved mask layer; performing photoetching and developing on the first epitaxial stack, and based on the first epitaxial stack and the first reserved mask layer, preparing a first vertical device in the first isolation groove; removing the second dielectric material above the second reserved mask layer, and depositing the second dielectric material in the first isolation groove, so that the second dielectric material covers the first vertical device; performing photoetching and developing on the second epitaxial stack, and based on the second epitaxial stack and the second reserved mask layer, preparing a second vertical device in the second isolation groove, and removing the second dielectric material covering the surface of the first vertical device.

6. The method of claim 5, wherein, The deposition of the dielectric material in the isolation groove adopts a recess process to make the dielectric material lower than the height of the vertical device, and expose the surface of the vertical device to the external environment, including: depositing a first dielectric material in the first isolation groove and the second isolation groove, and performing chemical mechanical polishing on the first dielectric material, so that the height of the first vertical device, the second vertical device and the first dielectric material is equal; adopting a recess process to etch the first dielectric material to be lower than the height of the first vertical device and the second vertical device, and expose the surface of the first vertical device and the second vertical device to the external environment.

7. The method of claim 6, wherein, The HKMG deposition and patterning process on the surface of the two different types of vertical devices to form a high-K metal gate, including: simultaneously performing HKMG deposition on the surface of the first vertical device and the second vertical device, so that the surface of the first vertical device and the second vertical device is covered with a high-K layer, and the surface of the high-K layer is covered with a metal gate layer; based on a preset pattern, performing photoetching and etching on the metal gate layer to form a high-K metal gate.

8. The method of claim 7, wherein, The interlayer dielectric deposition on the high-K metal gate to form an interlayer dielectric layer, based on a preset layout position, performing via etching on the interlayer dielectric layer and filling it with conductive metal to form a silicon-based heterogeneous device monolithic, including: performing interlayer dielectric deposition on the surface of the high-K metal gate to form an interlayer dielectric layer; based on a preset layout position, performing etching from the top of the interlayer dielectric layer to form a via, and filling the via with conductive metal to form a silicon-based heterogeneous device monolithic, wherein the bottom of the via is in contact with the first vertical device and the second vertical device, respectively.

9. A silicon-based heterojunction device monolith, characterized by, prepared based on the silicon-based heterogeneous device monolithic integration method in any one of claims 1 to 8, including: a silicon substrate (1), the surface of the silicon substrate is provided with an N well (101) and a P well (102); a first vertical device (9), the first vertical device (9) is arranged above the N well (101); a second vertical device (10), the second vertical device (10) is arranged above the P well (102), and the surface of the first vertical device (9) and the second vertical device (10) is covered with a high-K metal gate layer; a dielectric material layer, the dielectric material layer is laid on the surface of the silicon substrate (1), and covers the bottom of the first vertical device and the second vertical device; an interlayer dielectric layer (13) covering the surface of the first vertical device (9) and the second vertical device (10); a plurality of through holes (14) vertically formed in the interlayer dielectric layer (13) until the bottom of the through hole (14) contacts the surface of the first vertical device (9) or the second vertical device (10), and the through hole (14) is filled with a conductive metal.

10. The silicon-based hetero-device monolithic according to claim 9, wherein the first vertical device (9) is an NMOS tube, and the second vertical device (10) is a PMOS tube, or the first vertical device (9) is a MOS tube, and the second vertical device (10) is a laser or a detector. ​ ​

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