Structure with gate over non-aligned semiconductor regions

Abstract

The invention relates to a structure having a gate over non-aligned semiconductor regions. Embodiments of the present disclosure provide structures and related methods for gates over unaligned semiconductor regions. A structure according to the present disclosure includes a first semiconductor region extending within a substrate from a first widthwise end to a second widthwise end. The second semiconductor region is adjacent to the first semiconductor region and extends within the substrate from the first width direction end to the second width direction end. The second width direction end of the second semiconductor region is not aligned with the second width direction end of the first semiconductor region. A gate structure is over the substrate and extends in a width direction over the first semiconductor region and the second semiconductor region.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to integrated circuit (IC) structures. More specifically, embodiments of the present disclosure provide structures and methods for disposing gates over non-aligned semiconductor regions, for example to increase the threshold voltage variation of a physically unclonable function (PUF) array. Background Art

[0002] A physically unclonable function (PUF) is a physical object that is capable of outputting a unique output ("response") based on a repeatable input ("challenge") to the object. The immutable nature of the PUF determines the output for a specific input. PUFs can be implemented in integrated circuits (ICs) in applications with high security requirements, including Internet of Things (IoT) settings, and can prevent chip counterfeiting. In a "PUF array," multiple transistors provide a set of digital bits (similar to random access memory (RAM)), where random variations on the die affect the threshold voltage of each transistor. The threshold voltage, in turn, controls whether each transistor will produce a high or low logic level in response to the input signal. In order for a PUF array to be verifiable, the unique response must be repeatable under various deployment settings and over the life of the device. Summary of the Invention

[0003] All aspects, examples and features mentioned below may be combined in any technically feasible way.

[0004] Some aspects of the present disclosure provide a structure including: a first semiconductor region extending from a first widthwise end to a second widthwise end within a substrate; a second semiconductor region adjacent to the first semiconductor region and extending from the first widthwise end to the second widthwise end within the substrate, wherein the second widthwise end of the second semiconductor region is not aligned with the second widthwise end of the first semiconductor region; and a gate structure located above the substrate and extending in a width direction above the first semiconductor region and the second semiconductor region.

[0005] Other aspects of the present disclosure provide a structure including: a physically unclonable function (PUF) array comprising a plurality of transistors on a substrate, wherein a first transistor of the plurality of transistors comprises: a first semiconductor region extending from a first width-direction end to a second width-direction end within the substrate, a second semiconductor region adjacent to the first semiconductor region and extending from the first width-direction end to the second width-direction end within the substrate, wherein the second width-direction end of the second semiconductor region is not aligned with the second width-direction end of the first semiconductor region, and wherein the first semiconductor region and the second semiconductor region define a source region and a drain region, and a gate structure located above the substrate and extending in a width direction above the first semiconductor region and the second semiconductor region.

[0006] Another aspect of the present disclosure provides a method, comprising: forming a first semiconductor region in a substrate, the first semiconductor region extending from a first width-direction end to a second width-direction end in the substrate; forming a second semiconductor region adjacent to the first semiconductor region in the substrate, the second semiconductor region extending from the first width-direction end to the second width-direction end in the substrate, wherein the second width-direction end of the second semiconductor region is not aligned with the second width-direction end of the first semiconductor region; and forming a gate structure above the substrate, the gate structure extending in the width direction above the first semiconductor region and the second semiconductor region.

[0007] Two or more aspects described in this disclosure, including aspects described in this summary, can be combined to form embodiments not specifically described herein.

[0008] The details of one or more embodiments are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] These and other features of the present disclosure will be more readily understood from the following detailed description of various aspects of the present disclosure taken in conjunction with the accompanying drawings which illustrate various embodiments of the present disclosure, in which:

[0010] Figure 1 A plan view of a structure having non-aligned semiconductor regions according to an embodiment of the present disclosure is shown.

[0011] Figure 2 A plan view of a structure having a curved line segment joining a semiconductor region according to an embodiment of the present disclosure is shown.

[0012] Figure 3 FIG. 4 shows a plan view of a structure in a PUF array according to an embodiment of the present disclosure.

[0013] Figure 4 A schematic diagram of a circuit for challenging and interpreting responses from transistor pairs in a PUF array according to an embodiment of the present disclosure is shown.

[0014] Figure 5 A plan view of a structure having a semiconductor region including a plurality of non-aligned widthwise ends according to another embodiment of the present disclosure is shown.

[0015] Figure 6 A plan view of a structure in a PUF array having a semiconductor region including a plurality of non-aligned widthwise ends according to an embodiment of the present disclosure is shown.

[0016] It should be noted that the drawings of the present disclosure are not necessarily drawn to scale. The drawings are intended to depict only typical aspects of the present disclosure and therefore should not be considered to limit the scope of the present disclosure. In the drawings, the same reference numerals represent the same elements between the drawings. DETAILED DESCRIPTION

[0017] In the following description, reference is made to the accompanying drawings, which form a part thereof, in which are shown by way of illustration certain exemplary embodiments in which the present teachings may be practiced. These embodiments are described in sufficient detail to enable those skilled in the art to practice the present teachings, and it should be understood that other embodiments may be used and changes may be made without departing from the scope of the present teachings. Therefore, the following description is merely illustrative.

[0018] A physically unclonable function (PUF) is a physical object that is capable of outputting a unique output ("response") based on a repeatable input ("challenge") to the object. The immutable nature of the PUF determines the output for a specific input. PUFs can be implemented in integrated circuits (ICs) in applications with high security requirements, including Internet of Things (IoT) settings, and can prevent chip counterfeiting. In a "PUF array," multiple transistors provide a set of digital bits (similar to random access memory (RAM)), where random variations on the die affect the threshold voltage of each transistor. The threshold voltage, in turn, controls whether each transistor will produce a high or low logic level in response to the input signal. In order for a PUF array to be verifiable, the unique response must be repeatable under various deployment settings and over the life of the device.

[0019] Embodiments of the present disclosure provide a structure and related methods for a gate over misaligned semiconductor regions. The term "misaligned" or "non-aligned" means that one semiconductor region is not coaxial or substantially coaxial with an adjacent semiconductor region along its centerline axis. Therefore, at least one sidewall at one end of one semiconductor region does not overlap with the corresponding sidewall at the same end of an adjacent semiconductor region. The structure according to the present disclosure includes a first semiconductor region extending from a first width-direction end to a second width-direction end within a substrate. The second semiconductor region is adjacent to the first semiconductor region and extends from the first width-direction end to the second width-direction end within the substrate. The second width-direction end of the second semiconductor region is not aligned with the second width-direction end of the first semiconductor region. The gate structure is located over the substrate and extends in a width direction over the first semiconductor region and the second semiconductor region. During operation, the misaligned semiconductor regions will increase the threshold voltage variation of each transistor on the substrate, for example, further randomizing the distribution of high voltage outputs and low voltage outputs in the PUF array.

[0020] refer to Figure 1 , embodiments of the present disclosure provide a structure 100 having a substrate 102 and a set of trench isolation (TI) regions of insulating material located on various portions of the substrate 102. Other portions of the substrate 102 may be doped to define a first semiconductor region 104 and a second semiconductor region 106 having non-aligned widthwise ends as discussed herein. The structure 100 represents a portion of a device formed by various transistors and distributed over a two-dimensional area in a plane XY. The structure 100 may be defined in a layout, which may also be referred to as a "map," "design," "floor plan," or other terms indicating the placement of various components (e.g., logic or memory cells and their individual transistors) within a two-dimensional area. The structure 100 may be formed over a substrate 102 of semiconductor material, which may be a base material, on / in which additional materials (e.g., differently doped well regions, transistor structures, insulator regions, and / or other electrical components of the device) are formed.

[0021] The substrate 102 may be formed at least in part of any currently known or later developed semiconductor material, which may include, but is not limited to, silicon, germanium, silicon germanium, and a semiconductor material consisting essentially of a material having the chemical formula Al X1 Ga X2 In X3 As Y1 P Y2 N Y3 Sb Y4A substance composed of one or more III-V compound semiconductors of the defined composition, wherein X1, X2, X3, Y1, Y2, Y3, and Y4 represent relative proportions greater than or equal to zero, and X1+X2+X3+Y1+Y2+Y3+Y4=1 (1 is the total relative molar amount). The substrate 102 can be a bulk semiconductor layer, but in various embodiments can be a semiconductor-on-insulator (SOI) layer, such as a fully depleted semiconductor-on-insulator (FDSOI) layer disposed on a buried insulator layer. In this case, additional insulating and semiconductor materials (not shown) can be disposed below the buried insulator layer, for example, to provide a back gate region as is known in the art. Trench isolations (TIs) 103 may be formed on portions of the substrate 102, each trench isolation comprising one or more dielectric materials (e.g., oxide and / or nitride insulators, and / or other insulating materials, including insulating materials with a low dielectric constant (i.e., any insulating material having a dielectric constant "k" less than approximately 3.9)) and may be located on or within the substrate 102 to cover the respective sets of semiconductor regions 104, 106 and / or to isolate the respective sets of semiconductor regions 104, 106 from each other.

[0022] Various portions of the substrate 102 may be doped to provide semiconductor regions 104, 106 for defining various subcomponents of transistors and / or other device structures formed thereon (e.g., source regions, drain regions, channel regions, etc.). A "dopant" refers to an element introduced into a semiconductor to establish p-type (acceptor) or n-type (donor) conductivity. There are two types of dopants: "donors" and "acceptors." N-type dopants are donors, and P-type dopants are acceptors. In the case of a silicon substrate, common dopants for p-type doping may include, for example, boron (B) and / or indium (In). For n-type doping, doping elements may include, for example, phosphorus (P), arsenic (As) and / or antimony (Sb). Doping is the process of introducing impurities (dopants) into a semiconductor substrate or an element formed on a semiconductor substrate, and is typically performed with a mask (or other previously formed element) in place so that only certain areas of the substrate are doped. An ion implanter is typically used for the actual implantation, but other types of doping may also be implemented. Where applicable, an inert carrier gas such as nitrogen is typically applied to complete the dopant implantation.

[0023] Typically in doping, the dopant, dosage, and energy level are specified, and / or the resulting doping level can be specified. 2 ) atoms and energy level (specified in keV (kiloelectron volts)) to give the dose per cubic centimeter (cm 3) doping level (concentration in the substrate) in terms of the number of atoms. The number of atoms is usually specified in exponential notation, where a number such as "3E15" means 3 times 10 to the 15th power, or "3" followed by 15 zeros (3,000,000,000,000,000). An example of doping is about 1E12 to 1E13 atoms / cm 2 B (boron) is implanted with a dose between 1E17 and 1E18 atoms / cm and an energy of about 40 to 80 keV to produce 1E17 to 1E18 atoms / cm 3 The doping level of the substrate is between 100 and 100. The doped portion of the substrate may be referred to in the art as a "well." A well generally refers to an implantation / diffusion region in a semiconductor wafer required to implement a complementary metal oxide semiconductor (CMOS) cell. Depending on the properties of the structure 100, the well may be n-type or p-type doped.

[0024] Although the semiconductor regions 104, 106 may have a higher dopant concentration than other portions of the substrate 102, the doping type and / or dopant concentration may not be uniform within each semiconductor region 104, 106. For example, as discussed herein, some portions of each semiconductor region 104, 106 (e.g., portions below the gate structure) may have a lighter doping amount to provide a channel region. In other embodiments, the semiconductor regions 104, 106 may be substantially uniformly doped, and a semiconductor material having a higher dopant concentration may be formed thereon.

[0025] The first semiconductor region 104 within the substrate 102 can extend in a width direction, for example, along the Y-axis, as shown in the figure, from a first width-direction end W1A to a second width-direction end W1B. The first semiconductor region 104 within the substrate 102 can also extend in a length direction, for example, along the X-axis, as shown in the figure, from a first length-direction end L1A to a second length-direction end L1B. Although the first semiconductor region 104 is exemplarily shown as having a substantially quadrilateral (e.g., rectangular) shape within the substrate 102, the first semiconductor region 104 can have any conceivable geometric shape in the plane XY while still having a width and a length relative to its outermost end in each direction.

[0026] Similar to the first semiconductor region 104, the second semiconductor region 106 within the substrate 102 can extend in a width direction, such as along the Y-axis, as shown, from a first widthwise end W2A to a second widthwise end W2B. The second semiconductor region 106 within the substrate 102 can also extend in a length direction, such as along the X-axis, as shown, from a first lengthwise end L2A to a second lengthwise end L2B. Although the first semiconductor region 104 is illustratively shown as having a substantially quadrilateral (e.g., rectangular) shape within the substrate 102, the first semiconductor region 104 can have any conceivable geometric shape in the XY plane while still having a width and length relative to its outermost end in each direction. If desired, the first widthwise end W1A of the first semiconductor region 104 can be substantially aligned with, or even coaxial with, the first widthwise end W2A of the second semiconductor region 106. The first semiconductor region 104 and the second semiconductor region 106 can have substantially equal lengths (i.e., spans along the X-axis), but can have different surface areas due to the difference in width.

[0027] The semiconductor regions 104 and 106 may partially abut each other, for example, along most of adjacent ends (e.g., lengthwise ends L2A and L1B as shown). The remaining ends (e.g., ends L1A, W1A, W1B, W2A, W2B, and L2B) of the semiconductor regions 104 and 106 may not abut another semiconductor region, but may abut the TI 103 or otherwise abut less heavily doped semiconductor material of the substrate 102. The semiconductor regions 104 and 106 may have different sizes, for example, Figure 1 As shown, they can have different widths. The width-direction ends W1B and W2B can be misaligned with each other. Since the widths of each semiconductor region 104 and 106 are different, the width-direction end W1B of the first semiconductor region 104 can be offset by a distance S relative to the width-direction end W2B. The distance S can be a width that is less than the majority of the width of the second semiconductor region 106. Therefore, the semiconductor region 104 horizontally abuts the majority of the second semiconductor region 106. The size of the distance S relative to the width of the second semiconductor region 106 can be controlled to affect the threshold voltage of the transistors formed on the regions 104 and 106 as discussed herein. Conversely, the other width-direction ends W1A and W2A of the regions 104 and 106 can optionally be substantially aligned (for example, as shown, along line R) so that the only significant surface area difference between each region 104 and 106 is caused by the relative position of the width-direction ends W1B and W2B.

[0028] Gate structure 110 (at Figure 1 is shown in dashed lines and in Figure 3 、 Figure 6The gate structure 110 may be located above the substrate 102 and extend in the width direction (e.g., along the Y-axis direction) above the first semiconductor region 104 and the second semiconductor region 106 so that it covers the length direction ends L1B and L2A. The gate structure 110 may be located above the channel region defined by the semiconductor regions 104 and 106 or otherwise located within the semiconductor regions 104 and 106. A voltage at least equal to the threshold voltage applied to the gate conductor of the gate structure 110 may cause the source region and the drain region (e.g., Figure 3 、 Figure 5 There is electrical conductivity between the S / D contacts 132 shown and discussed elsewhere herein.

[0029] Thus, in addition to a gate dielectric material (not shown) for separating the conductive material of the gate structure 110 from the semiconductor regions 104, 106, the gate structure 110 may also include, for example, polysilicon, one or more conductive metals, and / or other gate-forming materials therein. The gate structure 110 may include one or more spacers located along its perimeter over the semiconductor regions 104, 106. The spacers of the gate structure 110 may be formed of a dielectric material (e.g., one or more insulating substances suitable for use as insulators, and / or any other currently known or later developed insulating material) to prevent electrical shorting between the gate structure 110 and other electrically active materials formed on the substrate 102. These and other subcomponents of the gate structure 110 are not included in the drawings. Figure 1 , to better illustrate the structural features of the semiconductor regions 104 and 106 in the substrate 102. Therefore, in addition to the portion of the second semiconductor region 106 that does not laterally adjoin the first semiconductor region 104, the gate structure 110 may also cover the portions of the semiconductor regions 104 and 106 that are laterally adjoining to each other.

[0030] Figure 2Another embodiment of structure 100 is shown, for example, in which a curved segment 120 connects the widthwise end W1B of the first semiconductor region to the widthwise end W2B of the second semiconductor region 106. Curved segment 120 can be formed, for example, by changing the doping mask used to form regions 104 and 106. The shape and size of curved segment 120 can also affect the threshold voltage of transistors formed above regions 104 and 106, for example by further increasing or decreasing the amount of semiconductor material below gate structure 110. For example, providing curved segment 120 can reduce the surface area otherwise occupied by the corner segments of each semiconductor region 104 and 106, and thus can slightly reduce the amount of threshold voltage variation between each transistor within structure 100, while maintaining a certain degree of threshold voltage variability. As shown, gate structure 110 can cover the entire curved segment 120. Other features of structure 100 can be the same or identical to other embodiments discussed herein, regardless of whether curved segment 120 is included.

[0031] Figure 3 A plan view of a physical unclonable function (PUF) array 128 is shown having several PUF transistors 130, one or more of which may include the structure 100 discussed herein. Each PUF transistor 130 may include a gate structure 110 extending widthwise over a boundary between semiconductor regions 104, 106 and over an electrically inactive portion of substrate 102 located between adjacent PUF transistors 130. Some gate structures 110 may be conductive, while other gate structures 110 may be non-conductive gate structures (sometimes referred to as "dummy gates") to isolate some PUF transistors 130 from other transistors. As discussed herein, some inactive portions of substrate 102 may include insulating material (e.g., TI 103) formed therein to better isolate each PUF transistor 130 from another. In PUF array 128, semiconductor regions 104, 106 may be substantially aligned at one widthwise end (e.g., along a corresponding axis R) and substantially misaligned at another widthwise end, such that the corresponding widthwise ends are separated by a distance S, as discussed elsewhere herein. Source / drain (S / D) contacts 132, eg, higher conductivity material extending vertically into the underlying semiconductor material, may be located on semiconductor regions 104, 106. The S / D contacts provide vertically extending source and drain coupling to transistor 130 at desired locations.

[0032] Each gate structure 110 may be coupled to a power rail (not shown), which may be a large conductive structure extending vertically (e.g., along the X-axis) for delivering voltage from a power supply to operate each PUF transistor 130 via the gate structure 110 of each PUF transistor 130. Alternatively, the gate structure 110 may be coupled to a power supply and / or similar voltage node via any currently known or later developed structure for delivering voltage to the transistor 130. Portions of each gate structure 110 may additionally include electrically insulating material (i.e., "diffusion breaks") to electrically isolate multiple PUF transistors 130 adjacent to one gate structure 110 from each other.

[0033] Figure 4 A circuit schematic illustrating a portion of a PUF array 128 is shown, in which pairs of PUF transistors 130 (e.g., pairs of N-type transistors, such as N-channel field effect transistors (NFETs) (each pair individually labeled 130 a, 130 b)) may be located in a circuit that generates a unique response to a challenge using a combination of the PUF transistors 130 a, 130 b. It should be understood that in most PUF arrays 128, there will be many more pairs of PUF transistors 130 a, 130 b, and only three pairs of PUF transistors 130 a, 130 b are shown for clarity of illustration.

[0034] Each pair of PUF transistors 130a, 130b may include a gate structure 110 ( Figure 1 、 Figure 2 ). Manufacturing variations combined with the different sizes of each semiconductor region 104, 106 will result in variations in the threshold voltage of each PUF transistor 130a, 130b. Each pair of PUF transistors 130a, 130b in the PUF array 128 can be coupled at their gates to a word line ("WL") for carrying a read signal ("VREADH"). The logic level of the read signal can control whether the PUF transistors 130 of a particular row in the PUF array 128 will receive an input signal ("challenge"), and the threshold voltage of each PUF transistor 130a, 130b controls whether the read signal can cause current to flow between the drain and source. Therefore, the physical structure of each PUF transistor 130a, 130b controls the threshold voltage and, therefore, whether an incoming challenge will output a "1" voltage or a "0" voltage.

[0035] In the configuration shown, for example, VREADH can be set so that it is at or above the threshold voltage of approximately half of the transistors in the array. When VREADH is applied to the word line WL, all PUF transistor pairs 130a, 130b (e.g., NFET pairs) (also referred to herein as bit cells) in the same row are interrogated. The different sizes of the semiconductor regions 104, 106 and other inherent structural differences and variations produced during the manufacturing process will cause some PUF transistors 130a, 130b to have different threshold voltages than other PUF transistors 130, 130b in the same PUF array 128. However, these variations do not necessarily result in each PUF transistor 130a, 130b producing a different response (i.e., logic level) in response to VREADH on the word line WL. More specifically, a source line (“SL”) can be coupled to a voltage source (“VSS”) (e.g., ground) and to a source terminal defined within the semiconductor regions 104, 106 of each PUF transistor 130a, 130b within a pair in the PUF array 128. The semiconductor regions 104, 106 of each PUF transistor 130a, 130b within the pair can be coupled to a complementary bit line (i.e., a “true bit line” (BLT) or a “complement bit line” (BLC)), respectively, for transmitting a pair of binary digits (“bits”) to a multiplexer (“MUX”). During a challenge operation, the BLT and BLC can be precharged. When VREADH on WL goes high, the PUF transistor with the lower threshold voltage will turn on. If the PUF transistor 130a is turned on, the voltage on the BLT will be pulled down to ground; and if the PUF transistor 130b is turned on, the voltage on the BLC will be pulled down to ground. The multiplexer can select a response from one or more pairs of PUF transistors 130a, 130b in the row to transmit to a sense amplifier ("SA") coupled thereto. The sense amplifier can amplify and interpret the input data from the BLT and BLC connected to the PUF transistors 130a, 130b to produce a data output ("Dout") indicating a response to the challenge. For example, if BLT is low and BLC is high, Dout can be a logic 0; while if BLT is high and BLC is low, Dout can be a logic 1, and vice versa. It should be noted that each pair of transistors (i.e., each bit cell) can be repeatedly challenged before the PUF key is generated to ensure that Dout will be consistent (i.e., stable). Typically, Dout will be stable if the absolute value of the threshold voltage difference (delta) between the two transistors in the pair is greater than a predetermined amount (e.g., 35mV), for example. Only bit cells with stable outputs are mapped for use in the PUF key.

[0036] Thus, using a simple, repeatable circuit, each PUF transistor 130a, 130b in the PUF array 128 can be challenged using a signal from the word line WL to generate a unique response. Embodiments of the present disclosure include semiconductor regions 104, 106 of varying sizes to increase the variation in threshold voltage of each PUF transistor 130a, 130b in the PUF array 128. The variation in threshold voltage of each PUF transistor 130a, 130b in the PUF array 128 can partially or completely define the unique response that the PUF array 128 will generate in response to a challenge. Furthermore, the difference in threshold voltage between each PUF transistor 130a, 130b in the PUF array 128 can be significant enough to ensure that the PUF transistor 130 reliably generates a unique response in response to each challenge.

[0037] Figure 5 Another example of structure 100 is shown, in which a pair of adjacent semiconductor regions 104 and 106 are not aligned at opposite widthwise ends. As discussed elsewhere herein, a distance S1 can separate the widthwise end W1B of the first semiconductor region 104 from the widthwise end W2B of the second semiconductor region 106. Optionally, the widthwise end W1A of the first semiconductor region 104 is also not aligned with the widthwise end W2A of the second semiconductor region 106, such that a distance S2 separates the widthwise ends W1A and W2B. The distances S1 and S2 can be different from each other and can be user-defined to increase or decrease the threshold voltage variation of each transistor formed on the semiconductor regions 104 and 106.

[0038] Reference together Figure 5 and Figure 6 , each PUF transistor 130 in the PUF array 128 can have a similar or even identical length (e.g., measured along the X-axis), but can have a different width (e.g., measured along the Y-axis). The transistors 130 of the PUF array 128 can each be located on a pair of semiconductor regions 104, 106 that can have different sizes, and in some cases, each of the semiconductor regions 104, 106 in the PUF array 128 can have a unique surface area. Further varying the size of each semiconductor region 104, 106 in the design of the PUF array 128 can enable each unit of a device produced according to the same design to have a unique electrical response to an incoming challenge. Embodiments of the PUF array 128 in which the semiconductor regions 104, 106 do not have any aligned widthwise ends can optionally be modified with a curved segment 120 ( Figure 2) without otherwise changing the various structural features discussed herein. The presence of curved segment 120 and / or the misalignment of regions 104, 106 at both widthwise ends is not necessarily required to provide an operable PUF array 128, and other embodiments discussed herein (e.g., those in which semiconductor regions 104, 106 have one aligned widthwise end) may be used if desired.

[0039] The present disclosure also provides a method for forming a structure 100 ( Figure 1 、 Figure 2 、 Figure 5 ) and / or PUF array 128 ( Figure 3 、 Figure 4 、 Figure 6 ) method. Reference Figure 1 As an example, the disclosed method may include forming a semiconductor region 104 within the substrate 102, for example, by doping selected portions of the substrate 102 with a doping mask and / or using any currently known or later developed doping technique. At the same or a subsequent stage of doping, the disclosed method may include forming a second semiconductor region 106 adjacent to the first semiconductor region 104 within the substrate 102. In some cases, the designer or manufacturer may rely on a marking layer and / or additional design rule checking (DRC) rules to produce semiconductor regions 104, 106 of different sizes.

[0040] The formation of the semiconductor regions 104, 106 can be controlled such that the widthwise ends of one semiconductor region (e.g., the first semiconductor region 104) are not aligned with the corresponding widthwise ends of the other semiconductor region (e.g., the second semiconductor region 106). A gate structure 110 can be formed over the semiconductor regions 104, 106 (e.g., by forming a gate structure and optionally subsequent metal gate replacement) such that the gate structure 110 extends widthwise over the semiconductor regions 104, 106. The doping mask and / or other techniques used to shape the semiconductor regions 104, 106 can be further modified to produce the curved segment 120 ( Figure 2 ), multiple non-aligned widthwise ends (e.g., Figure 5 ) and / or other structural features discussed herein.

[0041] Embodiments of the present disclosure provide various technical and commercial advantages, examples of which are discussed herein. Embodiments of the structure 100 and / or PUF array 128 and methods of forming the same effectively create threshold voltage mismatches in individual transistors 130 in the PUF array without significantly affecting the current required to operate the transistors 130 and / or the surface area occupied by the transistors 130 on the device. Furthermore, embodiments of the present disclosure can be scalable to larger and smaller surface areas without significantly changing the manufacturing process required to form the PUF array 128. Increasing the threshold voltage variation by varying the size of the semiconductor regions 104, 106 when the transistors 130 are electrically interrogated can contribute to bit stability within the PUF array 128, i.e., embodiments of the present disclosure will prevent the same PUF array from returning different responses when interrogated multiple times.

[0042] Aspects of the present disclosure have been described above with reference to the flowcharts and / or block diagrams of the methods and devices (systems) according to embodiments of the present disclosure. It should be understood that each frame of the flowcharts and / or block diagrams and the combination of frames in the flowcharts and / or block diagrams can be implemented by hardware and / or software (e.g., computer program instructions). In the case of being implemented by means of computer program instructions, these instructions for implementing the method of the present disclosure can be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device to produce a machine, so that when executed by a processor of a computer or other programmable data processing device, these instructions create a device for implementing the function / action specified in the flowchart and / or one or more block diagram frames.

[0043] As used herein, the terms "configured," "configured to," and / or "configured for" may refer to a specific purpose mode of the component. For example, a system or device configured to perform a function may include a computer system or computing device that is programmed or otherwise modified to perform that specific function. In other cases, program code stored on a computer-readable medium (e.g., a storage medium) may be configured to cause the computing device to perform a function when the program code is executed on at least one computing device. In these cases, the arrangement of the program code triggers a specific function in the computing device when executed. In other examples, a device configured to interact with other components and / or act on other components may be specifically shaped and / or designed to effectively interact with and / or act on these components. In some such cases, the device is configured to interact with another component because at least a portion of its shape is complementary to at least a portion of the shape of the other component. In some cases, the size of at least a portion of the device is set to interact with at least a portion of the other component. The physical relationship between the device and the other components (e.g., complementary, sized identically, etc.) can facilitate the performance of functions, such as replacement of one or more of the device or the other components, mating of one or more of the device or the other components, etc.

[0044] The description of the various embodiments of the present disclosure is provided for illustrative purposes and is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those skilled in the art without departing from the scope and spirit of the described embodiments. The terminology used herein is selected to best explain the principles of the embodiments, practical applications, or technical improvements over commercially available technologies, or to enable others skilled in the art to understand the embodiments disclosed herein.

Claims

1. A structure comprising: a first semiconductor region extending from a first widthwise end to a second widthwise end within the substrate; a second semiconductor region adjacent to the first semiconductor region and extending from a first widthwise end to a second widthwise end within the substrate, wherein the second widthwise end of the second semiconductor region is not aligned with the second widthwise end of the first semiconductor region; as well as A gate structure is located above the substrate and extends in a width direction above the first semiconductor region and the second semiconductor region.

2. The structure according to claim 1, wherein: The first width-direction end of the first semiconductor region is substantially aligned with the first width-direction end of the second semiconductor region.

3. The structure according to claim 1, wherein: The first width-direction end of the first semiconductor region is not aligned with the first width-direction end of the second semiconductor region.

4. The structure according to claim 1, wherein: The length of the first semiconductor region is substantially equal to the length of the second semiconductor region.

5. The structure according to claim 1, wherein: The first semiconductor region and the second semiconductor region define respective source and drain regions of a PUF transistor within a Physical Unclonable Function (PUF) transistor array.

6. The structure according to claim 1, wherein: The first semiconductor region horizontally adjoins a majority of the width of the second semiconductor region. 7 . The structure of claim 1 , further comprising a curved segment located below the gate structure and extending from the second width-direction end of the first semiconductor region to the second width-direction end of the second semiconductor region.

8. The structure according to claim 1, wherein: The substrate is one of a bulk semiconductor layer and a semiconductor-on-insulator (SOI) layer.

9. A structure comprising: A physical unclonable function (PUF) array comprising a plurality of transistors on a substrate, wherein a first transistor of the plurality of transistors comprises: a first semiconductor region extending from a first widthwise end to a second widthwise end within the substrate, a second semiconductor region adjacent to the first semiconductor region and extending within the substrate from a first widthwise end to a second widthwise end, wherein the second widthwise end of the second semiconductor region is not aligned with the second widthwise end of the first semiconductor region, and wherein the first semiconductor region and the second semiconductor region define a source region and a drain region, and A gate structure is located above the substrate and extends in a width direction above the first semiconductor region and the second semiconductor region.

10. The structure according to claim 9, wherein: The first width-direction end of the first semiconductor region within the first transistor is substantially aligned with the first width-direction end of the second semiconductor region.

11. The structure according to claim 9, wherein: In the first transistor, the first width-direction end of the first semiconductor region is not aligned with the first width-direction end of the second semiconductor region.

12. The structure according to claim 9, wherein: In the first transistor, a length of the first semiconductor region is substantially equal to a length of the second semiconductor region.

13. The structure according to claim 9, further comprising: A curved segment in the first transistor is located below the gate structure and extends from the second width-direction end of the first semiconductor region to the second width-direction end of the second semiconductor region.

14. The structure according to claim 9, wherein: The substrate is one of a bulk semiconductor layer and a semiconductor-on-insulator (SOI) layer.

15. A method comprising: forming a first semiconductor region in the substrate, the first semiconductor region extending from a first widthwise end to a second widthwise end in the substrate; forming a second semiconductor region adjacent to the first semiconductor region in the substrate, the second semiconductor region extending from a first width direction end to a second width direction end in the substrate, wherein the second width direction end of the second semiconductor region is not aligned with the second width direction end of the first semiconductor region; as well as A gate structure is formed over the substrate, the gate structure extending in a width direction over the first semiconductor region and the second semiconductor region.

16. The method according to claim 15, wherein: Forming the first semiconductor region includes forming the first width-direction end of the first semiconductor region substantially aligned with the first width-direction end of the second semiconductor region.

17. The method according to claim 15, wherein: Forming the first semiconductor region includes forming the first width-direction end of the first semiconductor region not aligned with the first width-direction end of the second semiconductor region.

18. The method according to claim 15, wherein: The second semiconductor region is formed to have a length substantially equal to that of the first semiconductor region.

19. The method of claim 15, further comprising forming a curved segment extending from the second widthwise end of the first semiconductor region to the second widthwise end of the second semiconductor region, wherein: The gate structure is formed over the curved segment.

20. The method according to claim 15, wherein: The substrate is one of a bulk semiconductor layer and a semiconductor-on-insulator (SOI) layer.

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