Semiconductor device layout structure

Abstract

The present invention provides a semiconductor device layout structure, including: a semiconductor substrate, a gate pattern, a drain lightly doped region and a source lightly doped region, wherein the gate pattern is located on the semiconductor substrate, the drain lightly doped region and the source lightly doped region are respectively located in the semiconductor substrate on both sides of the gate pattern, wherein the drain lightly doped region includes a first drain lightly doped region and a plurality of second drain lightly doped regions, a gap is provided between the first drain lightly doped region and the gate pattern, a plurality of second drain lightly doped regions are arranged at intervals along a first direction, and a plurality of second drain lightly doped regions are connected to a side of the first drain lightly doped region close to the gate pattern, and the second drain lightly doped region extends below the edge of the gate pattern. The present invention can achieve the purpose of improving the electrostatic protection capability of semiconductor devices, and can save preparation costs and improve preparation efficiency.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device layout structure. Background Art

[0002] In the semiconductor device manufacturing process, standard MOS devices and ESD devices (ESD devices are MOS devices used for ESD protection) are generally prepared simultaneously. By adjusting the injection energy, injection dose and injection angle of the lightly doped region of the ESD device, the electrostatic protection capability of the ESD device can be improved.

[0003] Figure 1 This is a schematic diagram of an ESD device layout structure in the prior art. Please refer to Figure 1 , Figure 1 FIG. 1 shows a partial structure of an ESD device. A gate pattern 20 is formed on a semiconductor substrate 10. Two lightly doped regions 30 and an active region 40 are formed in the semiconductor substrate 10. The two lightly doped regions 30 are respectively located on both sides of the gate pattern 20 and extend below the edge of the gate pattern 20. Figure 1 The ESD device layout structure in is the same as the standard MOS device layout structure.

[0004] At present, in order to distinguish between standard MOS devices and ESD devices, different masks are usually needed to form different lightly doped regions in standard MOS devices and ESD devices. Using different masks means adding a mask for ESD devices, which leads to high device preparation costs. Moreover, using different masks to form the lightly doped regions of standard MOS devices and ESD devices in steps leads to low device preparation efficiency. Summary of the invention

[0005] The purpose of the present invention is to provide a semiconductor device layout structure to achieve the purpose of improving the electrostatic protection capability of the semiconductor device, and to save preparation costs and improve preparation efficiency.

[0006] In order to achieve the above object, the present invention provides a semiconductor device layout structure, comprising:

[0007] Semiconductor substrate;

[0008] A gate pattern, located on the semiconductor substrate;

[0009] The drain lightly doped region and the source lightly doped region are respectively located in the semiconductor substrate on both sides of the gate pattern, wherein the drain lightly doped region includes a first drain lightly doped region and a plurality of second drain lightly doped regions, a gap is provided between the first drain lightly doped region and the gate pattern, a plurality of the second drain lightly doped regions are arranged at intervals along a first direction, and a plurality of the second drain lightly doped regions are connected to a side of the first drain lightly doped region close to the gate pattern, and the second drain lightly doped region extends below the edge of the gate pattern.

[0010] Optionally, the area of ​​each second drain terminal lightly doped region is the same, the gap between two adjacent second drain terminal lightly doped regions is the same, and along the second direction, the dimension of each second drain terminal lightly doped region extending below the edge of the gate pattern is the same, and the first direction and the second direction intersect perpendicularly.

[0011] Optionally, the shape of the second drain lightly doped region includes a rectangle, an arc and a triangle.

[0012] Optionally, the first drain lightly doped region and the second drain lightly doped region have the same doping type.

[0013] Optionally, an active region is also included, and all of the second drain lightly doped regions are located in the active region.

[0014] Optionally, along the second direction, the size of the gate pattern is L, and the maximum size of the second drain end lightly doped region extending below the edge of the gate pattern is S1, where S1 is to .

[0015] Optionally, along the first direction, the maximum size of the second drain lightly doped region is S2, and the minimum gap between two adjacent second drain lightly doped regions is S3, where S2 is equal to S3.

[0016] Optional, both S2 and S3 are to .

[0017] Optionally, along the second direction, a gap between the first drain lightly doped region and the gate pattern is S4, where S4 is to .

[0018] Optionally, the source lightly doped region extends to below the edge of the gate pattern, and there is a gap between the source lightly doped region and the second drain lightly doped region; along the second direction, the dimension of the source lightly doped region extending to below the edge of the gate pattern is S5, where S5 is .

[0019] In the semiconductor device layout structure provided by the present invention, by changing the morphology of the drain lightly doped region, the drain lightly doped region includes a first drain lightly doped region and a plurality of second drain lightly doped regions, a gap is provided between the first drain lightly doped region and the gate pattern, a plurality of second drain lightly doped regions are arranged at intervals along a first direction, and a plurality of second drain lightly doped regions are connected to a side of the first drain lightly doped region close to the gate pattern, and the second drain lightly doped region extends to below the edge of the gate pattern; while satisfying the electrical performance of the semiconductor device, by reducing the area of ​​the second drain lightly doped region, the area of ​​the drain lightly doped region is reduced, and the total doping amount of the drain lightly doped region can be reduced, thereby achieving the purpose of improving the electrostatic protection capability of the semiconductor device, and no additional mask is required, thereby saving preparation costs and improving preparation efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] Figure 1 The diagram is a schematic diagram of an ESD device layout structure in the prior art.

[0021] Figure 2 A schematic diagram of a semiconductor device layout structure provided by an embodiment of the present invention.

[0022] Figure 3 This is a simulation diagram of an ESD device under a standard light doping dose.

[0023] Figure 4 A simulation diagram of an ESD device with an 80% reduction in standard light doping dose.

[0024] Figure 5 A schematic diagram of a simulation of a semiconductor device provided by an embodiment of the present invention under a standard light doping dose.

[0025] Figure 6 for Figures 3 to 5 The relationship between voltage and leakage current in the expected TLP (Transmission Line Pulse).

[0026] in, Figure 1 The accompanying drawings are:

[0027] 10 - semiconductor substrate; 20 - gate pattern; 30 - lightly doped region; 40 - active region.

[0028] Figure 2~Figure 5 The accompanying drawings are:

[0029] Semiconductor substrate; 200 - gate pattern; 310 - drain lightly doped region; 310A - first drain lightly doped region; 310B - second drain lightly doped region; 320 - source lightly doped region; 400 - active region; 500 - gate oxide layer; 600 - sidewall. DETAILED DESCRIPTION

[0030] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0031] Therefore, the following detailed description of the embodiments of the present application provided in the accompanying drawings is not intended to limit the scope of the present application for which protection is sought, but merely represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0032] In the description of the present application, it should be understood that the terms "center", "up", "down", "left", "right", "vertical", "horizontal", "inside", "outside", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is conventionally placed when in use, or are the orientations or positional relationships conventionally understood by those skilled in the art. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0033] In addition, relational terms such as the terms "first" and "second" are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such articles or equipment. In the absence of further restrictions, the elements defined by the statement "comprise one..." do not exclude the existence of other identical elements in the articles or equipment including the elements. For those of ordinary skill in the art, the specific meanings of the above terms in this application can be understood according to the specific circumstances.

[0034] Figure 2 This is a schematic diagram of the semiconductor device layout structure provided in this embodiment. Please refer to Figure 2, this embodiment provides a semiconductor device layout structure, in which the semiconductor device is an ESD device (the ESD device is a MOS device for ESD protection), including: a semiconductor substrate 100, a gate pattern 200, a drain-side lightly doped region 310 and a source-side lightly doped region 320, wherein the gate pattern 200 is located on the semiconductor substrate 100, and the gate pattern 200 is in a strip shape (specifically a rectangular strip shape), the length direction of the gate pattern 200 is a first direction (D1 direction in the figure), the width direction of the gate pattern 200 is a second direction (D2 direction in the figure), the first direction and the second direction intersect vertically, and in Figure 2 In order to clearly show the doped region under the gate pattern 200, transparency is set for the gate pattern 200. Furthermore, there is a gate oxide layer (not shown in the figure) between the gate pattern 200 and the semiconductor substrate 100, and there are sidewalls (not shown in the figure) on both sides of the gate pattern 200.

[0035] Along the second direction, the drain lightly doped region 310 and the source lightly doped region 320 are respectively located in the semiconductor substrate 100 on both sides of the gate pattern 200, and both the drain lightly doped region 310 and the source lightly doped region 320 extend below the edge of the gate pattern 200, there is a gap between the drain lightly doped region 310 and the source lightly doped region 320, and the size of the drain lightly doped region 310 is larger than the size of the source lightly doped region 320. Along the first direction, the size of the drain lightly doped region 310 and the source lightly doped region 320 is larger than or equal to the size of the gate pattern 200.

[0036] In this embodiment, the drain end lightly doped region 310 includes a first drain end lightly doped region 310A and a plurality of second drain end lightly doped regions 310B ( Figure 2 Two second drain end lightly doped regions 310B are shown schematically, such as Figure 2 As shown in the dashed box, in fact, it is not limited to this number), there is a gap between the first drain lightly doped region 310A and the gate pattern 200, and there is a gap between the source lightly doped region 320 and the second drain lightly doped region 310B, a plurality of second drain lightly doped regions 310B are arranged at intervals along the first direction, and one side of a plurality of second drain lightly doped regions 310B is connected to a side of the first drain lightly doped region 310A close to the gate pattern 200, and the other side of a plurality of second drain lightly doped regions 310B extends to below the edge of the gate pattern 200. Specifically, a side of the second drain lightly doped region 310B away from the first drain lightly doped region 310A extends to below the edge of the gate pattern 200.

[0037] In this embodiment, the shape of the first drain lightly doped region 310A includes a rectangle, and the shape of the second drain lightly doped region 310B includes a rectangle, an arc shape, and a triangle, but is not limited to the above shapes. In the figure, the shape of the second drain lightly doped region 310B is shown as a rectangle. When the shape of the second drain lightly doped region 310B is an arc shape, the arc edge faces the gate pattern 200; when the shape of the second drain lightly doped region 310B is a triangle, a triangle edge is connected to the first drain lightly doped region 310A. In order to facilitate the control of the total doping amount of the drain lightly doped region 310, the area of ​​each second drain lightly doped region 310B is preferably the same, the shape of each second drain lightly doped region 310B is preferably the same, the gap between two adjacent second drain lightly doped regions 310B is preferably the same, and along the second direction, the size of each second drain lightly doped region 310B extending below the edge of the gate pattern 200 is preferably the same. In this embodiment, the first drain lightly doped region 310A and the second drain lightly doped region 310B have the same doping type, and the first drain lightly doped region 310A and the second drain lightly doped region 310B are formed simultaneously in the same preparation step.

[0038] In this embodiment, the gate pattern 200, the first drain lightly doped region 310A, the second drain lightly doped region 310B and the source lightly doped region 320 are all arranged according to the set size rules to ensure the electrical performance of the device, that is, to reduce the impact on the electrical parameters of the device (such as breakdown voltage, leakage current, etc.). Specifically, along the second direction, the size of the gate pattern 200 is L, and the value of L is determined by the device design rules (depending on the actual situation), and the maximum size of the second drain lightly doped region 310B extending below the edge of the gate pattern 200 is S1, where S1 is preferably to , since the shape of the second drain terminal lightly doped region 310B can be a rectangle, an arc, a triangle, etc., it is defined here as the maximum size of the second drain terminal lightly doped region 310B extending below the edge of the gate pattern 200 along the second direction. Along the first direction, the maximum size of the second drain terminal lightly doped region 310B is S2. Since the shape of the second drain terminal lightly doped region 310B can be a rectangle, an arc, a triangle, etc., it is defined here as the maximum size of the second drain terminal lightly doped region 310B along the first direction; the minimum gap between two adjacent second drain terminal lightly doped regions 310B is S3, where S2 is equal to S3, and S2 and S3 are preferably both to Since the shape of the second drain lightly doped region 310B can be rectangular, arc-shaped, triangular, etc., it is defined here as the minimum gap between two adjacent second drain lightly doped regions 310B along the first direction. Along the second direction, the gap between the first drain lightly doped region 310A and the gate pattern 200 is S4, where S4 is preferably to .

[0039] Along the second direction, the source end lightly doped region 320 extends to a size S5 below the edge of the gate pattern 200, where S5 is preferably The source lightly doped region 320 may be rectangular in shape, the source lightly doped region 320 and the drain lightly doped region 310 have the same doping type, and the source lightly doped region 320 and the drain lightly doped region 310 are formed simultaneously in the same preparation step.

[0040] Furthermore, the semiconductor substrate 100 further includes an active region 400. Along the second direction, the active region 400 spans the gate pattern 200, the second drain lightly doped region 310B, part of the first drain lightly doped region 310A and part of the source lightly doped region 320. Along the first direction, the size W of the active region 400 is smaller than the size of the gate pattern 200. The value of W is determined by the device design rule (depending on the actual situation), and all the second drain lightly doped regions 310B are located in the active region 400, that is, all the second drain lightly doped regions 310B are within the size W of the active region 400 along the first direction, and the number of the second drain lightly doped regions 310B is related to the value of W. In this embodiment, according to the values ​​of L and W, the values ​​of S1 to S5 can be obtained, and the values ​​of S1 to S5 are adjusted within the set size rule to control the area of ​​the drain lightly doped region 310 and the positions of several doped regions while ensuring the electrical performance of the device.

[0041] Furthermore, the semiconductor substrate 100 also includes a source region and a drain region (not shown in the figure), the source region is located in the active region 400 corresponding to the source end lightly doped region 320, and the drain region is located in the active region 400 corresponding to the second drain end lightly doped region 310B and the first drain end lightly doped region 310A.

[0042] Figure 3 This is a simulation diagram of an ESD device under standard light doping dosage. Please refer to Figure 3 , Figure 3 The layout structure of ESD devices Figure 1 The layout structure is the same as Figure 3 The gate is not shown. Figure 3 No additional mask is required for light doping. The standard light doping dose is a set doping dose. At the junction of the gate oxide layer 500 and the sidewall 600, the surface of the gate oxide layer 500 ( Figure 3 The maximum electric field strength (shown in the dotted circle) is about 6×e 6 V / cm.

[0043] Figure 4 This is a simulation diagram of an ESD device with 80% reduction in standard light doping dose. Please refer to Figure 4 , Figure 4 The layout structure of ESD devices Figure 1The layout structure is the same as Figure 4 The gate is not shown. Figure 4 An additional mask is needed for light doping. Figure 4 The light doping dose at the middle drain end is relative to the standard light doping dose ( Figure 3 The set doping dose) is reduced by 80%. At the junction of the gate oxide layer 500 and the sidewall 600, the surface of the gate oxide layer 500 ( Figure 4 The maximum electric field strength (shown in the dotted circle) is about 3×e 6 V / cm.

[0044] Figure 5 This is a simulation diagram of the semiconductor device provided in this embodiment under a standard light doping dose. Figure 5 , Figure 4 The layout structure of ESD devices Figure 2 The layout structure is the same as Figure 5 The gate is not shown in the figure. Since the morphology of the drain lightly doped region is changed, the area of ​​the drain lightly doped region is reduced, and the total doping dose of the drain lightly doped region is reduced; no additional mask is required for light doping. At the junction of the gate oxide layer 500 and the sidewall 600, the surface of the gate oxide layer 500 ( Figure 5 The maximum electric field strength (shown in the dotted circle) is about 1×e 6 V / cm. According to the comparison Figures 3 to 5 The maximum electric field strength on the surface of the middle gate oxide layer 500, Figures 3 to 5 The middle red area gradually becomes smaller, indicating that the maximum electric field strength gradually becomes smaller; the smaller the maximum electric field strength, the stronger the electrostatic protection capability; it can be seen that the smaller the total doping dose in the lightly doped region at the drain end, the stronger the electrostatic protection capability.

[0045] Figure 6 for Figures 3 to 5 The relationship between voltage and leakage current in the expected TLP is shown in Figure 2. Figure 6 , learned Figure 5 The leakage current is greater than Figure 3 and Figure 4 The leakage current is greater, and the electrostatic protection capability of the device is stronger. Therefore, it can be known that by changing the morphology of the drain lightly doped region, while satisfying the electrical performance of the semiconductor device, by reducing the area of ​​the second drain lightly doped region, the area of ​​the drain lightly doped region can be reduced. The area of ​​the drain lightly doped region is related to the total doping dose of the drain lightly doped region. Under the same doping concentration, the smaller the area of ​​the drain lightly doped region, the smaller the total doping dose of the drain lightly doped region, thereby reducing the total doping dose of the drain lightly doped region, improving the electrostatic protection capability of the semiconductor device, and achieving the purpose of improving the electrostatic protection capability of the semiconductor device.

[0046] In the present embodiment, since the ESD device is a MOS device used for ESD protection, a standard MOS device will be prepared simultaneously when preparing the ESD device, and generally, lightly doped regions (source lightly doped region and drain lightly doped region) of the standard MOS device and the ESD device will be formed simultaneously; by changing the morphology of the drain lightly doped region in the ESD device, that is, changing the mask for forming the lightly doped regions of the standard MOS device and the ESD device, it is possible to simultaneously form the lightly doped regions of the standard MOS device and the ESD device, without the need for an additional mask of the ESD device to form the lightly doped region of the ESD device, thereby saving preparation costs and improving preparation efficiency.

[0047] In summary, in the semiconductor device layout structure provided by the present invention, by changing the morphology of the drain lightly doped region, the drain lightly doped region includes a first drain lightly doped region and a plurality of second drain lightly doped regions, there is a gap between the first drain lightly doped region and the gate pattern, a plurality of second drain lightly doped regions are arranged at intervals along a first direction, and a plurality of second drain lightly doped regions are connected to a side of the first drain lightly doped region close to the gate pattern, and the second drain lightly doped region extends to below the edge of the gate pattern; while meeting the electrical performance of the semiconductor device, by reducing the area of ​​the second drain lightly doped region, the area of ​​the drain lightly doped region is reduced, the total doping amount of the drain lightly doped region can be reduced, and the purpose of improving the electrostatic protection capability of the semiconductor device is achieved, and no additional photomask is required, which can save preparation costs and improve preparation efficiency.

[0048] The above is only a preferred embodiment of the present invention and does not limit the present invention in any way. Any technician in the relevant technical field, without departing from the scope of the technical solution of the present invention, makes any form of equivalent replacement or modification to the technical solution and technical content disclosed in the present invention, which does not depart from the content of the technical solution of the present invention and still falls within the protection scope of the present invention.

Claims

1. A semiconductor device layout structure, characterized in that: include: Semiconductor substrate; A gate pattern, located on the semiconductor substrate; A drain lightly doped region and a source lightly doped region are respectively located in the semiconductor substrate on both sides of the gate pattern, wherein the drain lightly doped region includes a first drain lightly doped region and a plurality of second drain lightly doped regions, a gap is provided between the first drain lightly doped region and the gate pattern, a plurality of the second drain lightly doped regions are arranged at intervals along a first direction, and a plurality of the second drain lightly doped regions are connected to a side of the first drain lightly doped region close to the gate pattern, and the second drain lightly doped regions extend below the edge of the gate pattern; An active area spans the gate pattern, the second drain lightly doped area, part of the first drain lightly doped area and part of the source lightly doped area along a second direction, all of the second drain lightly doped areas are located in the active area, and the first direction and the second direction intersect vertically.

2. The semiconductor device layout structure according to claim 1, characterized in that: The area of ​​each second drain lightly doped region is the same, the gap between two adjacent second drain lightly doped regions is the same, and along the second direction, the size of each second drain lightly doped region extending below the edge of the gate pattern is the same.

3. The semiconductor device layout structure according to claim 2, characterized in that: The shape of the second drain lightly doped region includes a rectangle, an arc and a triangle.

4. The semiconductor device layout structure according to claim 1, characterized in that: The first drain lightly doped region and the second drain lightly doped region have the same doping type.

5. The semiconductor device layout structure according to claim 2, characterized in that: Along the second direction, the size of the gate pattern is L, and the maximum size of the second drain end lightly doped region extending below the edge of the gate pattern is S1, where S1 is to .

6. The semiconductor device layout structure according to claim 5, characterized in that: Along the first direction, the maximum size of the second drain end lightly doped region is S2, and the minimum gap between two adjacent second drain end lightly doped regions is S3, where S2 is equal to S3.

7. The semiconductor device layout structure according to claim 6, characterized in that: Both S2 and S3 are to .

8. The semiconductor device layout structure according to claim 5, characterized in that: Along the second direction, the gap between the first drain lightly doped region and the gate pattern is S4, where S4 is to .

9. The semiconductor device layout structure according to claim 5, characterized in that: The lightly doped source region extends to below the edge of the gate pattern, and there is a gap between the lightly doped source region and the second lightly doped drain region; along the second direction, the lightly doped source region extends to below the edge of the gate pattern by a size of S5, where S5 is .

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