Display panel and electronic device

Abstract

The invention relates to a display panel and an electronic device. The display panel includes: a circuit board; and an element layer disposed on the circuit board and including: a pixel defining layer having a plurality of openings; and a spacer, which is disposed on the pixel defining layer. The plurality of openings includes a first opening, a second opening, and a third opening adjacent to the spacer. The spacer includes a central portion disposed between the first opening, the second opening, and the third opening, and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively. An end portion of the first extension portion, an end portion of the second extension portion, and an end portion of the third extension portion are disposed in a region defined by an imaginary line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to and the benefit of Korean Patent Application No. 10-2023-0117444 filed in the Korean Intellectual Property Office on September 5, 2023, the entire contents of which are incorporated herein by reference. Technical Field

[0003] Embodiments described herein relate to a display panel having improved manufacturing yield and reliability and an electronic device including the display panel. Background Art

[0004] The display panel may include pixels. Each of the pixels may include an emission layer disposed between electrodes facing each other. The emission layer may be formed by various methods, and one of the methods may be a deposition method using a mask. The display panel may include a spacer supporting the mask. Summary of the invention

[0005] The embodiment provides a display panel capable of improving manufacturing yield and reliability, and an electronic device including the display panel.

[0006] However, the embodiments are not limited to the embodiments described herein. The above and other embodiments will become more apparent to those skilled in the art to which the present disclosure pertains by referring to the detailed description of the present disclosure given below.

[0007] According to an embodiment, a display panel may include: a circuit board including a pixel circuit; and an element layer, which is disposed on the circuit board and includes: a plurality of light emitting elements; a pixel defining layer, which has a plurality of openings respectively overlapping the plurality of light emitting elements; and a spacer, which is disposed on the pixel defining layer. The plurality of openings may include a first opening, a second opening, and a third opening, and each of the first opening, the second opening, and the third opening may be adjacent to the spacer. The spacer may include: a central portion, which is disposed between the first opening, the second opening, and the third opening; a first extension, which extends from the central portion to be disposed between the first opening and the second opening; a second extension, which extends from the central portion to be disposed between the second opening and the third opening; and a third extension, which extends from the central portion to be disposed between the third opening and the first opening. An end of the first extension, an end of the second extension, and an end of the third extension may be disposed within an area defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

[0008] The spacer may include a plurality of layers, and at least one layer among the plurality of layers may include a conductive material.

[0009] The spacer may include a first layer having a first width; and a second layer disposed on the first layer and having a second width smaller than the first width.

[0010] The spacer may include a plurality of spacers, and the plurality of spacers may include a first spacer and a second spacer closest to the first spacer. At least two light emitting elements among the plurality of light emitting elements may be disposed between the first spacer and the second spacer.

[0011] Each of the first opening, the second opening, and the third opening may have a polygonal shape.

[0012] The first opening may include a first side facing the first extension, the second opening may include a second side facing the first extension, and an end of the first extension may be aligned with or spaced apart from a virtual line connecting a center of the first side and a center of the second side.

[0013] The pixel defining layer may include an inorganic material, and the spacer may include an inorganic material.

[0014] The end of the first extension portion, the end of the second extension portion, and the end of the third extension portion may have a rounded shape, an angular shape, or a pointed shape.

[0015] A first angle of a side surface of the pixel defining layer defining the first opening with respect to a bottom surface of the pixel defining layer may be about 40 degrees or less.

[0016] A second angle of the side surface of the spacer with respect to the bottom surface of the spacer may be greater than or equal to the first angle.

[0017] The spacer may be thicker than the pixel defining layer.

[0018] A plurality of valleys recessed from an upper surface of the pixel defining layer may be defined in the pixel defining layer, and the plurality of valleys may respectively surround at least a portion of the first opening, the second opening, and the third opening.

[0019] The spacer may be disposed between the plurality of valleys.

[0020] The display panel may further include a plurality of protrusion patterns disposed on the pixel defining layer and surrounding at least a portion of the first opening, the second opening, and the third opening, respectively.

[0021] The spacer may have a thickness greater than a thickness of the plurality of protrusion patterns.

[0022] According to an embodiment, a display panel may include: a circuit board including a pixel circuit; and an element layer, the element layer is disposed on the circuit board and includes: a light-emitting element including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer, the pixel defining layer having an opening overlapping a portion of the first electrode; and a spacer, the spacer being disposed on the pixel defining layer. The spacer may include a central portion and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively, and the pixel defining layer and the spacer may include an inorganic material.

[0023] A first angle of a side surface of the pixel defining layer defining the opening relative to a bottom surface of the pixel defining layer may be less than or equal to a second angle of a side surface of the spacer relative to a bottom surface of the spacer.

[0024] A first angle of a side surface of the pixel defining layer defining the opening with respect to a bottom surface of the pixel defining layer may be about 40 degrees or less.

[0025] The spacer may be thicker than the pixel defining layer.

[0026] The spacer may include a plurality of layers, and at least one layer among the plurality of layers may include a conductive material.

[0027] The spacer may include a first layer having a first width; and a second layer disposed on the first layer and having a second width smaller than the first width.

[0028] The opening may have a polygonal shape and may include a first side facing the first extension, and an end of the first extension may be aligned with or spaced apart from a normal line extending from a center of the first side.

[0029] The spacer may include a plurality of spacers, and the plurality of spacers may include a first spacer and a second spacer closest to the first spacer. The light emitting element may include a plurality of light emitting elements. At least two of the plurality of light emitting elements may be disposed between the first spacer and the second spacer.

[0030] According to an embodiment, a display panel may include: a circuit board including a pixel circuit; and an element layer, the element layer being disposed on the circuit board and including: a light-emitting element including a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a portion of the first electrode; and a spacer, the spacer being disposed on the pixel defining layer. The spacer may include a central portion and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively. A first angle of a side surface of the pixel defining layer defining the opening relative to a bottom surface of the pixel defining layer is about 40 degrees or less.

[0031] A second angle of the side surface of the spacer with respect to the bottom surface of the spacer may be greater than or equal to the first angle.

[0032] The pixel defining layer and the spacer may each include an inorganic material.

[0033] The spacer may include a plurality of layers, and at least one layer among the plurality of layers may include a conductive material.

[0034] The spacer may include a first layer having a first width and a second layer disposed on the first layer and having a second width smaller than the first width.

[0035] According to an embodiment, an electronic device may include: a display panel that displays an image; and a housing that accommodates the display panel. The display panel may include: a circuit board that includes a pixel circuit; and an element layer that is disposed on the circuit board and includes: a plurality of light-emitting elements; a pixel defining layer that has a plurality of openings that overlap the plurality of light-emitting elements, respectively; and a spacer that is disposed on the pixel defining layer. The plurality of openings may include a first opening, a second opening, and a third opening, each of the first opening, the second opening, and the third opening being adjacent to the spacer. The spacer may include: a central portion that is disposed between the first opening, the second opening, and the third opening; a first extension that extends from the central portion to be disposed between the first opening and the second opening; a second extension that extends from the central portion to be disposed between the second opening and the third opening; and a third extension that extends from the central portion to be disposed between the third opening and the first opening. Ends of the first extension, the second extension, and the third extension may be disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] The above and other objects and features of the present disclosure will become apparent by describing embodiments thereof in detail with reference to the accompanying drawings.

[0037] Figure 1 is a schematic perspective view of an electronic device according to an embodiment.

[0038] Figure 2 is a schematic diagram illustrating the use of an electronic device according to an embodiment.

[0039] Figure 3 is an exploded schematic perspective view showing a part of the electronic device according to the embodiment.

[0040] Figure 4 is an enlarged schematic plan view showing a partial area of ​​a display panel according to the embodiment.

[0041] Figure 5A is a schematic cross-sectional view of a display panel according to an embodiment.

[0042] Figure 5B is a schematic cross-sectional view of a display panel according to an embodiment.

[0043] Figure 5C is a schematic cross-sectional view of a display panel according to an embodiment.

[0044] Fig. 6A is a schematic cross-sectional view of a display panel according to an embodiment.

[0045] Figure 6B is a schematic cross-sectional view of a display panel according to an embodiment.

[0046] Fig. 7A is an enlarged schematic plan view showing a partial area of ​​a display panel according to the embodiment.

[0047] Figure 7B is an enlarged schematic plan view showing a partial area of ​​a display panel according to the embodiment.

[0048] Figure 7C is an enlarged schematic plan view showing a partial area of ​​a display panel according to the embodiment.

[0049] Fig. 8A is a schematic cross-sectional view of a partial region of a display panel according to an embodiment.

[0050] Figure 8B is a schematic cross-sectional view of a partial region of a display panel according to an embodiment.

[0051] Figure 8C is a schematic cross-sectional view of a partial region of a display panel according to an embodiment.

[0052] Fig.8D is a schematic cross-sectional view of a partial region of a display panel according to an embodiment.

[0053] Fig. 8E is a schematic cross-sectional view of a partial region of a display panel according to an embodiment.

[0054] Fig. 9 is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. DETAILED DESCRIPTION

[0055] In the following description, for the purpose of explanation, many specific details are set forth in order to provide a thorough understanding of various embodiments or implementations of the present invention. As used herein, "embodiment" and "implementation" are interchangeable words, which are non-limiting examples of the device or method disclosed herein. However, it is readily understood that various embodiments may be implemented without these specific details or using one or more equivalent arrangements. In this article, various embodiments do not have to be exclusive, nor do they have to limit the present disclosure. For example, the specific shape, configuration and characteristics of an embodiment may be used or implemented in another embodiment.

[0056] Unless otherwise specified, the embodiments shown should be understood to provide features of the present invention. Therefore, unless otherwise specified, the features, components, modules, layers, films, panels, regions and / or aspects of the various embodiments, etc. (hereinafter individually or collectively referred to as "elements") can be further combined, separated, interchanged and / or rearranged without departing from the scope of the present invention.

[0057] The use of cross hatching and / or shading in the accompanying drawings is generally provided to clarify the boundaries between adjacent elements. Thus, unless otherwise specified, the presence or absence of cross hatching or shading does not convey or indicate any preference or requirement for the specific material, material properties, size, ratio, commonality between the elements shown and / or any other characteristics, attributes, performance, etc. of the element. In addition, in the accompanying drawings, the size and relative size of the elements may be enlarged for the purpose of clarity and / or description. When the embodiment can be implemented differently, a specific processing sequence can be performed differently from the described sequence. For example, two consecutively described processes can be performed substantially simultaneously or in an order opposite to the described sequence. In addition, the same reference numerals represent the same elements.

[0058] When an element or layer is referred to as being "on" another element or layer, "connected to" or "coupled to" another element or layer, it may be directly on, connected to or coupled to another element or layer, or there may be intervening elements or layers. However, when an element or layer is referred to as being "directly on" another element or layer, "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers. For this purpose, the term "connected" may refer to a physical connection, an electrical connection and / or a fluid connection with or without an intervening element. In addition, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 are not limited to the three axes of a rectangular coordinate system such as the X, Y, and Z axes, and may be interpreted in a broader sense. For example, the axis of the first direction DR1, the axis of the second direction DR2, and the axis of the third direction DR3 may be perpendicular to each other, or may represent different directions that are not perpendicular to each other. For the purposes of this disclosure, "at least one of A and B" may be understood to mean only A, only B, or any combination of A and B. Furthermore, “at least one of X, Y, and Z” and “at least one selected from the group consisting of X, Y, and Z” may be interpreted as any combination of only X, only Y, only Z, or two or more of X, Y, and Z. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0059] Although the terms "first", "second", etc. may be used herein to describe various types of elements, these elements should not be limited by these terms. These terms are used to distinguish one element from another element. Thus, the first element discussed below may be referred to as a second element without departing from the teachings of the present disclosure.

[0060] Spatially relative terms such as "below," "beneath," "under," "lower," "above," "upper," "above," "higher," and "side" (e.g., as in "sidewall") may be used herein for descriptive purposes, and thereby to describe the relationship of one element to another element shown in the accompanying drawings. Spatially relative terms are intended to encompass different orientations of the device in use, operation, and / or manufacture in addition to the orientations depicted in the accompanying drawings. For example, if the device in the accompanying drawings is flipped, elements described as "below" or "below" other elements or features will be oriented "above" or "above" the other elements or features. Thus, the term "below" may encompass both the "above" and "below" orientations. Furthermore, the device may be otherwise oriented (e.g., rotated 90 degrees or in other orientations), and thus, the spatially relative descriptors used herein should be interpreted accordingly.

[0061] The terms used herein are for the purpose of describing specific embodiments and are not intended to be limiting. As used herein, unless the context clearly indicates otherwise, the singular forms "one", "an" and "said" are also intended to include plural forms. In addition, when used in this specification, the terms "comprises", "comprising", "includes", and / or "including" indicate the presence of the features, integers, steps, operations, elements, components and / or groups thereof, but do not exclude the presence or increase of one or more other features, integers, steps, operations, elements, components and / or groups thereof. It should also be noted that, as used herein, the terms "substantially", "approximately" and other similar terms are used as approximate terms and are not used as terms of degree, and thus, are used to explain the inherent deviations of the measured values, calculated values ​​and / or provided values ​​that will be recognized by those of ordinary skill in the art.

[0062] Various embodiments are described herein with reference to cross-sectional and / or exploded illustrations, which are schematic illustrations of embodiments and / or intervening structures. Thus, variations in the shapes of the illustrations due to, for example, manufacturing techniques and / or tolerances can be expected. Thus, the embodiments disclosed herein should not be interpreted as limited to the shapes of the specific illustrated areas, but rather include deviations in shape due to, for example, manufacturing. In this manner, the areas shown in the drawings may be schematic in nature and the shapes of these areas may not reflect the actual shapes of areas of the device, and thus, are not necessarily intended to be limiting.

[0063] As is customary in the art, some embodiments are described and illustrated in the accompanying drawings according to functional blocks, units and / or modules. It will be understood by those of ordinary skill in the art that these blocks, units and / or modules are physically implemented by electronic (or optical) circuits such as logic circuits, discrete components, microprocessors, hard-wired circuits, memory elements and wiring connections, etc., which can be formed using semiconductor-based manufacturing techniques or other manufacturing techniques. In the case where blocks, units and / or modules are implemented by microprocessors or other similar hardware, they can be programmed and controlled using software (e.g., microcode) to perform the various functions discussed herein and can be selectively driven by firmware and / or software. It is also contemplated that each block, unit and / or module can be implemented by dedicated hardware, or as a combination of dedicated hardware for performing some functions and processors for performing other functions (e.g., one or more programmed microprocessors and related circuits). Moreover, without departing from the scope of the present invention, each block, unit and / or module of some embodiments can be physically divided into two or more interacting and discrete blocks, units and / or modules. Furthermore, the blocks, units and / or modules of some embodiments may be physically combined into more complex blocks, units and / or modules without departing from the scope of the invention.

[0064] Hereinafter, embodiments will be described with reference to the accompanying drawings.

[0065] Figure 1 is a perspective schematic diagram of an electronic device HMD according to an embodiment. Figure 2 is a schematic diagram illustrating the use of the electronic device HMD according to the embodiment. Figure 3 is an exploded schematic perspective view showing a part of the electronic device HMD according to the embodiment.

[0066] refer to Figure 1 , Figure 2 and Figure 3, the electronic device HMD may be a device activated according to an electrical signal. For example, the electronic device HMD may be a mobile phone, a foldable mobile phone, a notebook computer, a television, a tablet computer, a car navigation unit, a game console, or a wearable device, but the embodiment is not limited thereto. The wearable device worn on a part of the user's body may include a head mounted display (HMD) device that implements extended reality (XR). Although Figure 1 An example in which the electronic device HMD is a head mounted display device is shown, but the embodiment is not limited thereto.

[0067] The electronic device HMD may be a display device worn on the head of the user US. The electronic device HMD may provide images and may block the actual peripheral vision of the user US. The user US wearing the electronic device HMD may be more easily immersed in virtual reality.

[0068] The electronic device HMD may include a body HS, a strap STR, a cushion PP, and a display panel DP. For example, the electronic device HMD may include various types of sensors, cameras, and the like.

[0069] The body HS may be worn on the head of the user US. A display panel DP and an acceleration sensor that display images may be housed inside the body HS. The acceleration sensor may sense the movement of the user US and may transmit certain signals to the display panel DP. Therefore, the display panel DP may provide an image corresponding to changes in the gaze of the user US. Thus, the user US may experience a virtual reality similar to actual reality.

[0070] In addition to the above-mentioned components, components with various functions may be accommodated inside the body HS. The body HS may be referred to as a housing or a shell. For example, an operating unit for adjusting the volume or screen brightness, etc. may be additionally provided on the outside of the body HS. The operating unit may be provided as a physical button, or may be provided in the form of a touch sensor. In addition, a proximity sensor for determining whether the user US has turned on the electronic device HMD may be accommodated inside the body HS. For example, an external display panel may be additionally provided on the body HS.

[0071] The body HS can be divided into a body portion HS-1 and a cover portion HS-2. Figure 3 An example is shown in which the body portion HS-1 and the cover portion HS-2 are separated from each other, but the embodiment is not limited thereto. For example, the body portion HS-1 and the cover portion HS-2 may be integrated with each other and may not be separated from each other.

[0072] The display panel DP may be disposed between the body portion HS-1 and the cover portion HS-2. The display panel DP may provide images through the display areas DA, respectively. Figure 3An example in which the left eye image and the right eye image are provided by the display panels DP separated from each other is shown, but the embodiment is not limited thereto. For example, the left eye image and the right eye image may be displayed by a single display panel. The display panel DP may be driven by a separate driver. However, not limited thereto, the display panel DP may be driven by a single driver.

[0073] The display panel DP may generate an image corresponding to the input image data. The display panel DP may be an organic light emitting display panel, an inorganic light emitting display panel, an organic-inorganic light emitting display panel, a quantum dot display panel, a micro light emitting diode (LED) display panel, a nano LED display panel, or a liquid crystal display panel. In this embodiment, the display panel DP is described as an organic light emitting display panel. However, the embodiment is not limited thereto.

[0074] The strap STR may be coupled to the body HS so that the body HS can be easily worn on the head of the user US. The strap STR may include a main strap STR1 and an upper strap STR2.

[0075] The main strap STR1 can be worn around the head of the user US. The main strap STR1 can fix the body HS to the head of the user US so that the body HS is in close contact with the head of the user US. The upper strap STR2 can connect the body HS and the main strap STR1 along the upper part of the head of the user US. The upper strap STR2 can prevent the body HS from slipping. For example, the upper strap STR2 can disperse the weight of the body HS to further improve the wearing comfort of the user US.

[0076] although Figure 1 An example is shown in which the main strap STR1 and the upper strap STR2 are adjustable in length, but the embodiment is not limited thereto. For example, in another example, the main strap STR1 and the upper strap STR2 may be elastic, and the adjustable length portion may be omitted.

[0077] As long as the strap STR can fix the body HS to the head of the user US, the strap STR can be modified to Figure 1 and Figure 2 In another example, the upper strap STR2 may be omitted. In addition, in an embodiment, the strap STR may be modified into various forms (such as a helmet coupled to the body HS or a temple of glasses coupled to the body HS).

[0078] The cushion pad PP may be provided between the body HS and the head of the user US. The cushion pad PP may be formed of a material whose shape is freely deformable. For example, the cushion pad PP may be formed of a polymer resin (e.g., polyurethane, polycarbonate, polypropylene, or polyethylene), or may be formed as a sponge made by foaming liquid rubber, a urethane-based material, or an acrylic-based material. However, the embodiment is not limited thereto.

[0079] The cushion pad PP may bring the body HS into close contact with the head of the user US to improve the wearing comfort of the user US. The cushion pad PP may be detachable from the body HS. In another example, the cushion pad PP may be omitted.

[0080] The optical system OL may be disposed inside the body portion HS-1 of the body HS. The optical system OL may amplify an image provided from the display panel DP. Each of the display panels DP may display an image in a third direction DR3 through a display area DA, which is parallel to the first direction DR1 and a second direction DR2 intersecting the first direction DR1. The optical system OL may be spaced apart from the display panel DP in the third direction DR3. The optical system OL may be disposed between the display panel DP and the eyes of the user US. The optical system OL may include a right-eye optical system OL_R and a left-eye optical system OL_L. The left-eye optical system OL_L may amplify an image and provide the image to the left pupil of the user US, and the right-eye optical system OL_R may amplify the image and provide the image to the right pupil of the user US.

[0081] The left-eye optical system OL_L and the right-eye optical system OL_R may be spaced apart from each other in the first direction DR1. The distance between the right-eye optical system OL_R and the left-eye optical system OL_L may be adjusted to correspond to the distance between the two eyes of the user US. For example, the distance between the optical system OL and the display panel DP may be adjusted according to the vision (or eyesight) of the user US.

[0082] The optical system OL may be a convex aspherical lens. For example, the optical system OL may be a pancake lens, but the embodiment is not limited thereto. In the embodiment, it has been described that each of the left-eye optical system OL_L and the right-eye optical system OL_R is implemented with a single lens. However, the embodiment is not limited thereto. For example, each of the left-eye optical system OL_L and the right-eye optical system OL_R may include a plurality of lenses.

[0083] exist Figures 1 to 3In the above, it has been described that the display panel DP is applied to an electronic device HMD such as a head mounted display device. However, the embodiment is not limited thereto. For example, the display panel DP may also be applied to a bar-shaped electronic device, a foldable electronic device, a rollable electronic device, or a slidable electronic device.

[0084] Figure 4 FIG. 2 is a diagram showing a display panel DP (refer to FIG. 2 ) according to an embodiment. Figure 3 ) is an enlarged schematic plan view of a partial area DA-p.

[0085] Figure 4 The partial area DA-p shown in FIG. 1 (hereinafter referred to as the partial area) may be the display area DA (refer to FIG. 1 ). Figure 3 The emission regions PXA-R, PXA-G, and PXA-B and the spacers SPC included in the partial area DA-p may be repeatedly arranged in the first direction DR1 and the second direction DR2.

[0086] The display area DA of the display panel DP may include emission areas PXA-R, PXA-G, and PXA-B and non-emission areas NPXA surrounding the emission areas PXA-R, PXA-G, and PXA-B. The emission areas PXA-R, PXA-G, and PXA-B may be formed by a pixel defining layer PDL (refer to FIG. 1 ) to be described below. Figure 5A ) are separated from each other. The non-emission area NPXA may be an area between adjacent emission areas PXA-R, PXA-G, and PXA-B and may be an area corresponding to the pixel defining layer PDL. The emission areas PXA-R, PXA-G, and PXA-B may be separated from each other to correspond to the openings OP defined in the pixel defining layer PDL.

[0087] The emission regions PXA-R, PXA-G, and PXA-B may correspond to light emitting elements, respectively. For example, in the light emitting element (eg, a single light emitting element) 100ED (refer to Figure 5A ) defines an emission area (eg, a single emission area) PXA (reference Figure 5A ).

[0088] The emission regions PXA-R, PXA-G, and PXA-B may include a first emission region PXA-R, a second emission region PXA-G, and a third emission region PXA-B. In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may display light having different wavelengths. The first emission region PXA-R may display a first light as light having a red wavelength, the second emission region PXA-G may display a second light as light having a green wavelength, and the third emission region PXA-B may display a third light as light having a blue wavelength.

[0089] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may include an emission layer that outputs the same source light. For example, the source light may be white light or blue light. The source light may be converted into light with different colors by a wavelength conversion layer or a color filter layer included in the display panel DP. Therefore, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may display light with different wavelengths.

[0090] The first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may form a pixel (e.g., a single pixel). For example, the pixel may include a sub-pixel, and the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may correspond to the sub-pixel in a one-to-one manner.

[0091] According to an embodiment, the display panel DP may be applied to an electronic device for realizing extended reality. For example, the display panel DP may be applied to an electronic device for realizing (or realizing) augmented reality or virtual reality. For example, in order to improve the display quality, the display panel DP may be required to have a high resolution. For example, the first emission area PXA-R, the second emission area PXA-G, and the third emission area PXA-B may form a pixel (e.g., a single pixel), and the pixel density of the display panel DP may be 3000 pixels per inch (PPI) or more.

[0092] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have substantially the same area. However, the embodiment is not limited thereto. For example, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have different areas according to the wavelength of the emitted light.

[0093] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a polygonal shape (e.g., in a plan view). For example, each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may have a hexagonal shape, but the embodiment is not limited thereto.

[0094] In an embodiment, a control pattern LLP surrounding the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B and overlapping the non-emission region NPXA may be defined or set in the display panel DP. The control pattern LLP may at least partially surround the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, respectively. For example, the control pattern (e.g., a single control pattern) LLP may surround an emission region (e.g., a single emission region) (e.g., PXA-R). Although Figure 4 An example is shown in which the control pattern LLP completely surrounds the emission region PXA-R, but the embodiment is not limited thereto. For example, the control pattern LLP may surround only a portion of the emission region PXA-R.

[0095] The control pattern LLP can prevent the generation of lateral leakage current between adjacent emission regions PXA-R, PXA-G and PXA-B. In this specification, "lateral leakage current" refers to a current flowing in another direction intersecting with the third direction DR3, rather than a current flowing in the third direction DR3 (for example, in the direction of displaying an image), and the third direction DR3 is the stacking direction of the light emitting element. The lateral leakage current may refer to a current flowing in a plane in a direction parallel to a plane defined by the first direction DR1 and the second direction DR2.

[0096] According to an embodiment, a spacer SPC may be disposed between emission regions PXA-R, PXA-G, and PXA-B. The spacer SPC may include a first spacer SPC1 and a second spacer SPC2 closest to the first spacer SPC1. Among the emission regions PXA-R, PXA-G, and PXA-B, two or more emission regions may be disposed between the first spacer SPC1 and the second spacer SPC2. In addition, since the emission regions are defined to correspond to light emitting elements, respectively, two or more light emitting elements may be disposed between the first spacer SPC1 and the second spacer SPC2.

[0097] Unlike the embodiment, in the case where the spacers SPC are disposed in respective regions adjacent to the three emission regions PXA-R, PXA-G, and PXA-B, the number of the spacers SPC may be increased to correspond to the increase in the resolution of the display panel DP. For example, the amount of organic material accumulated on the upper surface of the spacer SPC may increase, and the organic material may be transferred to the mask. In the process of aligning the mask and the display panel DP being processed, foreign matter transferred to the mask may form punctures on the emission region, which causes a dark spot defect.

[0098] According to the embodiment, the spacer SPC may be disposed only in some areas adjacent to the three emission regions PXA-R, PXA-G, and PXA-B. When compared with the above-mentioned comparative example, because the number of spacers SPC is reduced, the amount of organic material accumulated on the upper surface of the spacer SPC may also be reduced. Therefore, the possibility of dark spot defects may also be reduced. Although Figure 4 An example in which 48 emission areas PXA-R, PXA-G, and PXA-B and two spacers SPC are disposed in the partial area (or single partial area) DA-p is shown, but the embodiment is not limited thereto.

[0099] According to an embodiment, having Figure 4 48 emission regions PXA-R, PXA-G, and PXA-B in the same arrangement relationship of the partial region DA-p shown in FIG. 1 and two spacers SPC may be alternately and repeatedly arranged along the first direction DR1 and the second direction DR2.

[0100] In an embodiment, the arrangement density of the spacers SPC may be lower than the pixel density. For example, Figure 4 The three emission regions PXA-R, PXA-G, and PXA-B in the image may form a pixel (eg, a single pixel). For example, it is understood that in Figure 4 16 pixels are shown in FIG. Therefore, the arrangement density of the spacer SPC may be about 1 / 8 of the pixel density. However, the embodiment is not limited thereto.

[0101] In an embodiment, Figure 4 The partial area DA-p shown in the figure may have a width of about 28.8 μm in the first direction DR1 and a width of about 28.8 μm in the second direction DR2. The emission areas PXA-R, PXA-G, and PXA-B and the spacers SPC included in the partial area DA-p may be repeatedly arranged in the first direction DR1 and the second direction DR2. Therefore, the distance between the spacers SPC closest to each other in the first direction DR1 may be about 28.8 μm or less, and the distance between the spacers SPC closest to each other in the second direction DR2 may be about 28.8 μm or less. Figure 4 The center of the second spacer SPC2 shown in FIG. 1 may be spaced apart from the center of the first spacer SPC1 by about 14.4 μm in the first direction DR1 and by about 14.4 μm in the second direction DR2. In addition, the shortest distance between the center of the first spacer SPC1 and the center of the second spacer SPC2 may be about 20.3 μm. However, the distance and width are not limited to the above values.

[0102] Figure 5A is a schematic cross-sectional view of a display panel DP according to an embodiment. Figure 5A It is along Figure 4 Schematic cross-sectional view of the display panel DP taken along line II'.

[0103] refer to Figure 4 and Figure 5A , the display panel DP may include a circuit board 100 , a component layer 200 , an encapsulation layer 300 , and an optical layer 400 .

[0104] The circuit board 100 may include a base substrate 110 and a pixel circuit 100PC on the base substrate 110. The base substrate 110 may be a silicon substrate, a germanium substrate, or a silicon on insulator (SOI) substrate. For example, the base substrate 110 may be a single crystal silicon substrate, but the embodiment is not limited thereto.

[0105] The pixel circuit 100PC may include a transistor. The transistor may be a metal oxide semiconductor field effect transistor (MOSFET). The pixel circuit 100PC may include a gate electrode E1 above a base substrate 110, a gate dielectric pattern GI between the gate electrode E1 and the base substrate 110, and source / drain regions E2 and E3 on opposite sides of the gate electrode E1. The source / drain regions E2 and E3 may be impurity implantation regions formed in the base substrate 110 on opposite sides of the gate electrode E1.

[0106] The gate electrode E1 may include at least one of a doped semiconductor material, a conductive metal nitride (e.g., titanium nitride or tantalum nitride, etc.), and a metal (e.g., aluminum or tungsten, etc.). The gate dielectric pattern GI may include silicon oxide. The source / drain regions E2 and E3 may have a different conductivity type from the base substrate 110. The source / drain regions E2 and E3 may include N-type impurities (e.g., phosphorus (P) or arsenic (As)) or P-type impurities (e.g., boron (B)).

[0107] The circuit board 100 may further include a lower interlayer insulating layer 120. The lower interlayer insulating layer 120 may be formed on the base substrate 110 and may cover the pixel circuit 100PC. The lower interlayer insulating layer 120 may include an oxide layer, a nitride layer, or an oxidized nitride layer. The lower conductive contact 130 may be formed in the lower interlayer insulating layer 120 and may be connected to the source / drain regions E2 and E3, respectively. The lower conductive contact 130 may include a conductive material.

[0108] The circuit board 100 may further include a wiring pattern layer 140. The wiring pattern layer 140 may be formed on the lower interlayer insulating layer 120. Each of the lower conductive contacts 130 may be connected to a corresponding one of the wiring pattern layers 140. The wiring pattern layer 140 may include, for example, a metal. For example, an additional wiring pattern layer may be formed between the lower interlayer insulating layer 120 and the wiring pattern layer 140. For example, each of the lower conductive contacts 130 may be electrically connected to the corresponding wiring pattern layer 140 through a corresponding one of the additional wiring pattern layers. The additional wiring pattern layer may include, for example, a metal.

[0109] The circuit board 100 may further include an upper interlayer insulating layer 150. The upper interlayer insulating layer 150 may be formed on the lower interlayer insulating layer 120 and may cover the wiring pattern layer 140. The upper interlayer insulating layer 150 may include an oxide layer, a nitride layer, or an oxynitride layer.

[0110] The element layer 200 may be disposed on the circuit board 100. The element layer 200 may include a light emitting element 100ED. Figure 5A , the light emitting element 100ED is representatively shown. The emission area PXA may be defined to correspond to the light emitting element 100ED. The emission area PXA may be defined by an opening OP defined in the pixel defining layer PDL. For example, the pixel circuit 100PC and the light emitting element 100ED may be connected to each other (e.g., electrically connected) and may form a pixel PX.

[0111] The light emitting element 100ED may include a first electrode AE, an intermediate layer CEL, and a second electrode CE. The first electrode AE ​​may be referred to as a pixel electrode or an anode, and the second electrode CE may be referred to as a common electrode or a cathode. The intermediate layer CEL may include a functional layer commonly provided in the emission regions PXA-R, PXA-G, and PXA-B, and an emission layer patterned to correspond to each of the emission regions PXA-R, PXA-G, and PXA-B.

[0112] The first electrode AE ​​may be disposed on the circuit board 100. The first electrode AE ​​may be connected to a corresponding one of the wiring pattern layers 140 by penetrating an upper conductive contact 160 of the upper interlayer insulating layer 150. The first electrode AE ​​may be a transmissive electrode, a semi-transmissive electrode, or a reflective electrode. In an embodiment, the first electrode AE ​​may include a reflective layer formed of silver, magnesium, aluminum, platinum, palladium, gold, nickel, neodymium, iridium, chromium, titanium, titanium nitride, or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include at least one selected from the group consisting of indium tin oxide, indium zinc oxide, indium gallium zinc oxide, zinc oxide, indium oxide, and aluminum-doped zinc oxide. For example, the first electrode AE ​​may include a multilayer structure in which indium tin oxide, silver, and indium tin oxide are stacked one above the other in sequence.

[0113] The pixel defining layer PDL may be disposed on the circuit board 100. An opening OP for exposing a portion of the first electrode AE ​​may be defined in the pixel defining layer PDL. For example, the pixel defining layer PDL may cover the periphery of the first electrode AE. The emission area PXA may be defined by the pixel defining layer PDL. The pixel defining layer PDL may have a single-layer structure or a multi-layer structure. The pixel defining layer PDL may include an inorganic material. For example, the pixel defining layer PDL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0114] In an embodiment, a control pattern LLP overlapping the non-emission area NPXA may be defined in the pixel defining layer PDL. The control pattern LLP may have a shape that is recessed from the upper surface of the pixel defining layer PDL in a third direction DR3 as a thickness direction. Therefore, the control pattern LLP may be referred to as a valley, a valley pattern, a groove, or a groove pattern. The depth of the control pattern LLP may be less than the thickness of the pixel defining layer PDL. Therefore, the side surface and the bottom surface of the control pattern LLP may be defined by the pixel defining layer PDL.

[0115] The intermediate layer CEL may be disposed on the first electrode AE ​​and the pixel defining layer PDL. The second electrode CE may be disposed on the intermediate layer CEL. In an embodiment, the thickness of the intermediate layer CEL may be reduced by the control pattern LLP. For example, some layers included in the intermediate layer CEL may be interrupted. For example, current leakage to a portion where the control pattern LLP is formed may be prevented.

[0116] The element layer 200 may further include a capping layer CPL disposed on the second electrode CE. The capping layer CPL may improve the luminous efficiency through the principle of constructive interference. The capping layer CPL may include, for example, a material having a refractive index of about 1.6 or greater for light having a wavelength of about 589 nm. The capping layer CPL may be an organic capping layer including an organic material, an inorganic capping layer including an inorganic material, or a composite capping layer including an organic material and an inorganic material. For example, the capping layer CPL may include a carbocyclic compound, a heterocyclic compound, an amine-containing compound, a porphyrin derivative, a phthalocyanine derivative, a naphthalocyanine derivative, an alkali metal complex, an alkaline earth metal complex, or a combination thereof. Carbocyclic compounds, heterocyclic compounds, and amine-containing compounds may be selectively substituted with a substituent including oxygen (O), nitrogen (N), sulfur (S), selenium (Se), silicon (Si), fluorine (F), chlorine (Cl), bromine (Br), iodine (I), or a combination thereof.

[0117] The encapsulation layer 300 may be disposed on the element layer 200. The encapsulation layer 300 may include a first inorganic encapsulation layer 310, an organic encapsulation layer 320, and a second inorganic encapsulation layer 330 stacked one above the other in sequence. The first inorganic encapsulation layer 310 and the second inorganic encapsulation layer 330 may protect the element layer 200 from moisture and oxygen, and the organic encapsulation layer 320 may protect the element layer 200 from foreign matter such as dust particles. In an embodiment, the encapsulation layer 300 may be formed as a single layer. For example, the encapsulation layer 300 may include only an inorganic encapsulation layer.

[0118] The optical layer 400 may be disposed on the encapsulation layer 300. The optical layer 400 may include a spacer layer 410, a color filter 420, a cover layer 430, and a lens pattern layer 440.

[0119] The material of the partition layer 410 is not limited as long as it is a material that absorbs light. The partition layer 410 may be a black layer. In an embodiment, the partition layer 410 may include a black colorant. The black colorant may include a black dye or a black pigment. The black colorant may include carbon black, a metal such as chromium, or an oxide thereof.

[0120] The color filter 420 may be disposed to correspond to the opening defined in the partition layer 410. The color filter 420 may transmit light provided from the intermediate layer CEL overlapping the color filter 420. The color filter 420 may improve color reproduction of light provided from the intermediate layer CEL.

[0121] The cover layer 430 may cover the color filter 420. The cover layer 430 may include an organic material, but the embodiment is not limited thereto. The lens pattern layer 440 may be arranged in a region overlapping with the opening OP of the pixel defining layer PDL and may have a convexly protruding shape. However, the shape of the lens pattern layer 440 is not limited thereto. The cover layer 430 and the lens pattern layer 440 may include the same material and may have an integral shape.

[0122] Figure 5B is a schematic cross-sectional view of a display panel DP-1 according to an embodiment. Figure 5B When, with reference Figure 5A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0123] refer to Figure 4 and Figure 5B The display panel DP-1 may further include a control pattern LLPa. The control pattern LLPa of the display panel DP-1 is Figure 5A The control pattern of LLP is different.

[0124] The control pattern LLPa may be disposed on the pixel defining layer PDL. The control pattern LLPa may have a shape protruding from the upper surface of the pixel defining layer PDL. Therefore, the control pattern LLPa may be referred to as a protruding pattern LLPa.

[0125] The control pattern LLPa may include a lower portion and an upper portion having a greater width than the lower portion. The upper portion of the control pattern LLPa may be spaced apart from the pixel defining layer PDL and the lower portion may be between the upper portion of the control pattern LLPa and the pixel defining layer PDL. For example, an end portion may be defined in the control pattern LLPa by having an upper portion and a lower portion having different widths.

[0126] The intermediate layer CEL may be disposed on the first electrode AE, the pixel defining layer PDL, and the control pattern LLPa. In an embodiment, the thickness of the intermediate layer CEL may be reduced by the control pattern LLPa. For example, some layers included in the intermediate layer CEL may be interrupted. For example, current leakage to a portion where the control pattern LLPa is formed may be prevented.

[0127] Figure 5C is a schematic cross-sectional view of a display panel DP-2 according to an embodiment. Figure 5C When, with reference Figure 5A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0128] refer to Figure 4 and Figure 5C The display panel DP-2 may include a circuit board 100, a component layer 200, a packaging layer 300, and an optical layer 400a. Figure 5A The optical layer 400 is different.

[0129] The optical layer 400a may include a base layer MLP-BS and a lens pattern layer MLP. The base layer MLP-BS and the lens pattern layer MLP may include the same material and may have an integral shape. The base layer MLP-BS and the lens pattern layer MLP may include an organic material, but the embodiment is not limited thereto. In another example, the base layer MLP-BS may be omitted. For example, the lens pattern layer MLP may be directly disposed on the encapsulation layer 300.

[0130] In an embodiment, the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B may display light having different wavelengths. Figure 5A For example, the light efficiency of the display panel DP-2 may be further improved, and the display panel DP-2 may display an image with higher brightness.

[0131] Fig. 6Ais a display panel DP according to an embodiment (refer to Figure 5A ) is a schematic cross-sectional view of the .

[0132] refer to Figure 5A and Fig. 6A , a first light emitting element 100ED-R having a first emission area PXA-R defined therein, a second light emitting element 100ED-G having a second emission area PXA-G defined therein, and a third light emitting element 100ED-B having a third emission area PXA-B defined therein are shown as examples.

[0133] The first electrode AE-R of the first light emitting element 100ED-R, the first electrode AE-G of the second light emitting element 100ED-G, and the first electrode AE-B of the third light emitting element 100ED-B may be disposed on the circuit board 100. An intermediate layer CEL covering the first electrodes AE-R, AE-G, and AE-B may be disposed on the circuit board 100.

[0134] The intermediate layer CEL may include a first functional layer HFL, a first auxiliary layer RIL and R', a second auxiliary layer GIL and G', a third auxiliary layer BIL, a first emission layer REML, a second emission layer GEML, a third emission layer BEML, a buffer layer BFL, and a second functional layer EFL. However, this is illustrative, and some components included in the intermediate layer CEL may be omitted. The intermediate layer CEL may also include other components.

[0135] The first functional layer HFL may include a hole transport layer (HTL), may include a hole injection layer (HIL), or may include a hole transport layer and a hole injection layer. The first functional layer HFL may be disposed in the entire display area DA (refer to Figure 3 Therefore, the first functional layer HFL can be aligned with the opening OP of the pixel defining layer PDL and the control pattern LLP of the pixel defining layer PDL (refer to Figure 4 )overlapping.

[0136] The first auxiliary layer RIL and R', the second auxiliary layer GIL and G', and the third auxiliary layer BIL may be disposed on the first functional layer HFL. The first auxiliary layer RIL and R', the second auxiliary layer GIL and G', and the third auxiliary layer BIL may be layers for increasing the luminous efficiency of the dopant and the host, but the embodiment is not limited thereto. In an embodiment, some of the first auxiliary layer RIL and R', the second auxiliary layer GIL and G', and the third auxiliary layer BIL may be omitted, and other auxiliary layers may be additionally disposed.

[0137] The first emission layer REML, the second emission layer GEML and the third emission layer BEML can be respectively arranged on the first auxiliary layer RIL and R', the second auxiliary layer GIL and G' and the third auxiliary layer BIL. The first emission layer REML, the second emission layer GEML and the third emission layer BEML may include an organic material, an inorganic material or an organic-inorganic material that emits light of a certain color. The first auxiliary layer RIL and R', the second auxiliary layer GIL and G' and the third auxiliary layer BIL can be respectively arranged in the first emission region PXA-R, the second emission region PXA-G and the third emission region PXA-B. The first emission layer REML, the second emission layer GEML and the third emission layer BEML can be respectively arranged in the first emission region PXA-R, the second emission region PXA-G and the third emission region PXA-B.

[0138] In an embodiment, the first auxiliary layers RIL and R' and the first emission layer REML may be formed using a first mask (e.g., a fine metal mask). For example, the first mask may include a mask opening, and the deposition material may pass through the opening and may be deposited on the target substrate to form the first auxiliary layers RIL and R' and the first emission layer REML. The second auxiliary layers GIL and G' and the second emission layer GEML may be formed using a second mask, and the third auxiliary layer BIL and the third emission layer BEML may be formed using a third mask. The second mask and the third mask may also be fine metal masks.

[0139] In the case of forming the first emission layer REML, the second emission layer GEML, the third emission layer BEML, the first auxiliary layers RIL and R', the second auxiliary layers GIL and G', and the third auxiliary layer BIL using a mask, the spacer SPC (refer to Figure 4 ) can serve as a supporting mask.

[0140] The buffer layer BFL may be disposed throughout the first emission layer REML, the second emission layer GEML, and the third emission layer BEML. For example, the buffer layer BFL may be disposed throughout the first functional layer HFL and may cover the first emission layer REML, the second emission layer GEML, the third emission layer BEML, the first auxiliary layers RIL and R', the second auxiliary layers GIL and G', and the third auxiliary layer BIL. In another example, the buffer layer BFL may be omitted.

[0141] The second functional layer EFL may be disposed on the buffer layer BFL. The second functional layer EFL may include an electron transport layer (ETL), may include an electron injection layer (EIL), or may include an electron transport layer and an electron injection layer. The second functional layer EFL may be disposed in the entire display area DA (refer to Figure 3Therefore, the second functional layer EFL can be aligned with the opening OP of the pixel defining layer PDL and the control pattern LLP of the pixel defining layer PDL (refer to Figure 4 )overlapping.

[0142] The second electrode CE may be disposed on the second functional layer EFL, and the capping layer CPL may be disposed on the second electrode CE. The microlens arrays MLP-R, MLP-G, and MLP-B may be disposed on the capping layer CPL. Figure 5A and Figure 5B The described components may be disposed between the microlens arrays MLP-R, MLP-G and MLP-B and the capping layer CPL.

[0143] Figure 6B is a display panel DP according to an embodiment (refer to Figure 5A ) is a schematic cross-sectional view of Figure 6B When, with reference Fig. 6A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0144] refer to Figure 5A and Figure 6B The intermediate layer CEL may include a first functional layer HFL-R, HFL-G and HFL-B, a first auxiliary layer RIL and R', a second auxiliary layer GIL and G', a third auxiliary layer BIL, a first emission layer REML, a second emission layer GEML, a third emission layer BEML, a buffer layer BFL and a second functional layer EFL.

[0145] Each of the first functional layers HFL-R, HFL-G, and HFL-B may include a hole transport layer (HTL), may include a hole injection layer (HIL), or may include a hole transport layer and a hole injection layer.

[0146] In an embodiment, the first functional layers HFL-R, HFL-G, and HFL-B may be disposed in the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, respectively. For example, the control pattern LLP (refer to Figure 4 ). However, the embodiment is not limited thereto.

[0147] In an embodiment, a first functional layer HFL-R, first auxiliary layers RIL and R', and a first emission layer REML may be formed using a first mask. A first functional layer HFL-G, second auxiliary layers GIL and G', and a second emission layer GEML may be formed using a second mask, and a first functional layer HFL-B, a third auxiliary layer BIL, and a third emission layer BEML may be formed using a third mask.

[0148] and Fig. 6A and Figure 6B Unlike those shown in FIG. 1 , the intermediate layer CEL may include a common emission layer that generates the same source light. The source light may be white light or blue light. For example, a common emission layer may be provided to replace Fig. 6A and Figure 6B The first auxiliary layer RIL and R', the second auxiliary layer GIL and G', the third auxiliary layer BIL, the first emission layer REML, the second emission layer GEML, and the third emission layer BEML shown in FIG. The common emission layer may be connected to the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B, and may be integrally provided. However, the embodiment is not limited thereto, and the common emission layer may be patterned and formed in each of the first emission region PXA-R, the second emission region PXA-G, and the third emission region PXA-B.

[0149] In an embodiment, the common emission layer may include a first sub-emission layer, a charge generation layer, and a second sub-emission layer stacked one above the other in sequence. The first sub-emission layer and the second sub-emission layer may emit light of different colors. For example, the first sub-emission layer and the second sub-emission layer may emit light of complementary colors, respectively. For example, the first sub-emission layer may emit blue light, and the second sub-emission layer may emit yellow light. Therefore, the emission layer may provide white source light, which is a combination of light provided from the first sub-emission layer and light provided from the second sub-emission layer. The charge generation layer may supply electrons or holes to the first sub-emission layer and the second sub-emission layer to improve the luminous efficiency.

[0150] In an embodiment, the common emission layer may include a first sub-emission layer, a first charge generation layer, a second sub-emission layer, a second charge generation layer, and a third sub-emission layer stacked one above the other. At least one of the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer may emit light having a different color from the light emitted by at least another of the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer. For example, the first sub-emission layer and the third sub-emission layer may emit a first light having the same color, and the second sub-emission layer may emit a second light having a color different from the color of the first light. For example, the first light and the second light may have a complementary color relationship. For example, the first sub-emission layer and the third sub-emission layer may emit blue light, and the second sub-emission layer may emit yellow light. Therefore, the common emission layer may provide white source light, which is a combination of light provided from the first sub-emission layer, the second sub-emission layer, and the third sub-emission layer. The first charge generation layer may supply electrons or holes to the first sub-emission layer and the second sub-emission layer to improve the luminous efficiency. For example, the second charge generation layer may supply electrons or holes to the second sub-emission layer and the third sub-emission layer to improve the luminous efficiency.

[0151] Fig. 7A is an enlarged schematic plan view showing a partial area of ​​a display panel according to the embodiment.

[0152] refer to Fig. 7A , openings OP-R, OP-G, and OP-B defined in the pixel defining layer PDL are shown. The openings OP-R, OP-G, and OP-B may include a first opening OP-R, a second opening OP-G, and a third opening OP-B. The first opening OP-R, the second opening OP-G, and the third opening OP-B may be adjacent to a spacer (e.g., a single spacer) SPC.

[0153] In an embodiment, each of the first opening OP-R, the second opening OP-G, and the third opening OP-B may have a polygonal shape. For example, when viewed from above a plane (e.g., in the third direction DR3), each of the first opening OP-R, the second opening OP-G, and the third opening OP-B may have a hexagonal shape. However, this is illustrative, and embodiments are not limited thereto.

[0154] In an embodiment, the spacer SPC may include a central portion CP, a first extension P1, a second extension P2, and a third extension P3. The central portion CP may correspond to a triangular shape (e.g., in a plan view). The first extension P1 may extend from the central portion CP (e.g., in a plan view) to be disposed between the first opening OP-R and the second opening OP-G. The second extension P2 may extend from the central portion CP (e.g., in a plan view) to be disposed between the second opening OP-G and the third opening OP-B. The third extension P3 may extend from the central portion CP (e.g., in a plan view) to be disposed between the first opening OP-R and the third opening OP-B. Therefore, when viewed from above a plane (or in a plan view), the spacer SPC may have a tripod shape.

[0155] In an embodiment, the first extension portion P1, the second extension portion P2, and the third extension portion P3 may extend from the central portion CP in three different directions, respectively. For example, the first extension portion P1 may extend in a first cross direction CDR1, the third extension portion P3 may extend in a second cross direction CDR2, and the second extension portion P2 may extend in a direction opposite to the second direction DR2. The first cross direction CDR1 may be a direction between the first direction DR1 and the second direction DR2, and the second cross direction CDR2 may be a direction between the second direction DR2 and a direction opposite to the first direction DR1.

[0156] According to an embodiment, the display panel DP (refer to Figure 5A) is used to reduce the area of ​​the region where the spacer SPC is provided by increasing the resolution of the display panel DP. In the case where the spacer SPC has a shape extending in at least three directions with a limited area, the rigidity of the spacer SPC can be improved. During deposition using a mask, the possibility of damaging the spacer SPC due to insufficient rigidity of the spacer SPC can be eliminated or reduced. Therefore, the manufacturing yield and reliability of the display panel DP can be improved.

[0157] In an embodiment, the ends of the first extension portion P1, the second extension portion P2, and the third extension portion P3 may have an arc shape. The ends of the first extension portion P1, the second extension portion P2, and the third extension portion P3 may be arranged in an area AR defined by a virtual line connecting the first center CP-R of the first opening OP-R, the second center CP-G of the second opening OP-G, and the third center CP-B of the third opening OP-B. For example, the length of the first extension portion P1, the second extension portion P2, and the third extension portion P3 may be shorter than the length LT of the side SS of each of the first opening OP-R, the second opening OP-G, and the third opening OP-B.

[0158] The first opening OP-R may include a first side SS1 facing the first extension P1, and the second opening OP-G may include a second side SS2 facing the first extension P1. A virtual line connecting the center of the first side SS1 and the center of the second side SS2 may be the same as a normal line extending from the center of the first side SS1. For example, the line and the normal line may be part of a line defining the area AR. For example, the end of the first extension P1 may be spaced apart from (or may not overlap) the line and the normal line, or may be aligned with the line and the normal line.

[0159] According to an embodiment, the display panel DP may be implemented to have a high resolution. For example, as the resolution increases, the maximum width to which the first extension portion P1, the second extension portion P2, and the third extension portion P3 can be set may be reduced, and the widths of the first extension portion P1, the second extension portion P2, and the third extension portion P3 (e.g., the width in a direction intersecting the extension direction) may be reduced. Therefore, even if the widths of the first extension portion P1, the second extension portion P2 to the third extension portion P3 are reduced, the rigidity of the spacer SPC may be improved by limiting the extension lengths of the first extension portion P2, the second extension portion P2, and the third extension portion P3.

[0160] Figure 7B 1 is an enlarged schematic plan view showing a partial area of ​​a display panel according to an embodiment. Figure 7B When, with reference Fig. 7A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0161] refer to Figure 7B , the spacer SPCa may include a central portion CPa, a first extension P1a, a second extension P2a, and a third extension P3a. The first extension P1a may extend from the central portion CPa to be disposed between the first opening OP-R and the second opening OP-G (for example, in a plan view). The second extension P2a may extend from the central portion CPa to be disposed between the second opening OP-G and the third opening OP-B (for example, in a plan view). The third extension P3a may extend from the central portion CPa to be disposed between the first opening OP-R and the third opening OP-B (for example, in a plan view).

[0162] In an embodiment, the ends of the first extension portion P1a, the second extension portion P2a, and the third extension portion P3a may have an angled shape. For example, the first extension portion P1a, the second extension portion P2a, and the third extension portion P3a may have a quadrilateral shape. The ends of the first extension portion P1a, the second extension portion P2a, and the third extension portion P3a may be disposed within an area AR defined by a virtual line connecting a first center CP-R of the first opening OP-R, a second center CP-G of the second opening OP-G, and a third center CP-B of the third opening OP-B. Therefore, even if the display panel DP (reference Figure 5A ) can be increased by narrowing the first extension portion P1a, the second extension portion P2a and the third extension portion P3a, and the rigidity of the spacer SPCa can be improved by limiting the extension length of the first extension portion P1a, the second extension portion P2a and the third extension portion P3a.

[0163] Figure 7C 1 is an enlarged schematic plan view showing a partial area of ​​a display panel according to an embodiment. Figure 7C When, with reference Fig. 7A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0164] refer to Figure 7C , the spacer SPCb may include a central portion CPb, a first extension P1b, a second extension P2b, and a third extension P3b. The first extension P1b may extend from the central portion CPb (for example, in a plan view) to be disposed between the first opening OP-R and the second opening OP-G. The second extension P2b may extend from the central portion CPb (for example, in a plan view) to be disposed between the second opening OP-G and the third opening OP-B. The third extension P3b may extend from the central portion CPb (for example, in a plan view) to be disposed between the first opening OP-R and the third opening OP-B.

[0165] In an embodiment, the ends of the first extension portion P1b, the second extension portion P2b, and the third extension portion P3b may have a pointed shape. For example, the center portion CPb and the first extension portion P1b, the second extension portion P2b, and the third extension portion P3b may have a triangular shape. The ends of the first extension portion P1b, the second extension portion P2b, and the third extension portion P3b may be disposed within an area AR defined by a virtual line connecting a first center CP-R of the first opening OP-R, a second center CP-G of the second opening OP-G, and a third center CP-B of the third opening OP-B. Therefore, even if the display panel DP (reference Figure 5A ) by narrowing the first extension portion P1b, the second extension portion P2b and the third extension portion P3b, and the rigidity of the spacer SPCb can also be improved by limiting the extension length of the first extension portion P1b, the second extension portion P2b and the third extension portion P3b.

[0166] Fig. 8A is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Fig. 8A It is along Fig. 7A A schematic cross-sectional view of a display panel taken along line II-II'. Fig. 8A Only the reference FIG. 5A to FIG. 5C The circuit board 100 and the element layer 200 are described, and the encapsulation layer 300 and the optical layer 400 or 400a are omitted.

[0167] refer to Figure 4 , Fig. 7A and Fig. 8A , a pixel defining layer PDL may be provided on the circuit board 100. An opening OP for exposing a portion of the first electrode AE ​​may be defined in the pixel defining layer PDL. The opening OP may include a first opening OP-R, a second opening OP-G, and a third opening OP-B. Fig. 8A The area between the second opening OP-G and the third opening OP-B is shown in FIG.

[0168] A control pattern LLP recessed from the upper surface of the pixel defining layer PDL may be defined in the pixel defining layer PDL. The control pattern LLP may be referred to as a valley. The control pattern LLP may surround at least a portion of the first opening OP-R, the second opening OP-G, and the third opening OP-B, respectively. A spacer SPC may be disposed between the control patterns LLP.

[0169] The spacer SPC may be disposed on the pixel defining layer PDL. In an embodiment, the spacer SPC and the pixel defining layer PDL may include an inorganic material. For example, the spacer SPC and the pixel defining layer PDL may include at least one of silicon oxide, silicon nitride, and silicon oxynitride.

[0170] In an embodiment, a first angle AG1 of a side surface of the pixel defining layer PDL relative to a bottom surface of the pixel defining layer PDL may be about 40 degrees or less. For example, an intermediate layer CEL disposed on the pixel defining layer PDL may be stably formed. However, the first angle AG1 is merely an example and is not limited thereto. In an embodiment, a second angle AG2 of a side surface of the spacer SPC relative to a bottom surface of the spacer SPC may be greater than or equal to the first angle AG1 of a side surface of the pixel defining layer PDL relative to a bottom surface of the pixel defining layer PDL. Even if a portion of the intermediate layer CEL or the second electrode CE is disconnected by the spacer SPC, the display panel DP (reference Figure 5A ) can also be limited because the arrangement density of the spacer SPC can be less than or equal to half of the pixel density (e.g., about 1 / 8 of the pixel density). Therefore, the second angle AG2 of the spacer SPC can be designed in various ways without being limited to a specific angle or less.

[0171] In an embodiment, the spacer SPC may include a plurality of layers. For example, the spacer SPC may include a first layer SPL1, a second layer SPL2 disposed on the first layer SPL1, and a third layer SPL3 disposed on the second layer SPL2. The first width SWT1 of the first layer SPL1 may be greater than the second width SWT2 of the second layer SPL2. In the case where the spacer SPC has a stepped structure, when forming the organic encapsulation layer 320 (refer to Figure 5A ) in the case where the monomer can flow smoothly. Therefore, the organic encapsulation layer 320 can be more easily planarized. However, the shape of the spacer SPC is not limited thereto. For example, the first width SWT1 and the second width SWT2 can be substantially the same as each other. The third layer SPL3 can be thinner than the first layer SPL1 and the second layer SPL2.

[0172] In an embodiment, each of the first layer SPL1 and the second layer SPL2 may include at least one of silicon oxide, silicon nitride, and silicon oxynitride. In the case where the first layer SPL1 and the second layer SPL2 are subjected to patterning, the third layer SPL3 may be used as a mask (e.g., a hard mask). For example, the third layer SPL3 may include a metal, a metal alloy, a metal oxide, a metal nitride, or a transparent conductive oxide. For example, the third layer SPL3 may include titanium (Ti), titanium nitride (TiN x ), nickel (Ni), gold (Au), molybdenum (Mo), indium tin oxide (ITO) or indium zinc oxide (IZO).

[0173] The intermediate layer CEL, the second electrode CE and the capping layer CPL may be sequentially arranged on the first electrode AE, the pixel defining layer PDL and the spacer SPC. The intermediate layer CEL may be arranged in a control pattern LLP defined in the upper surface of the pixel defining layer PDL. In an embodiment, the resistance of the intermediate layer CEL (e.g., the first functional layer HFL) may be increased by the control pattern LLP. For example, the first functional layer HFL may be disconnected (or separated) by the control pattern LLP. Therefore, the occurrence of lateral leakage current, color mixing between adjacent pixel regions and brightness degradation may be prevented.

[0174] The first dummy layer DMP1 may be disposed on the first layer SPL1, and the second dummy layer DMP2 may be disposed on the third layer SPL3. Each of the first dummy layer DMP1 and the second dummy layer DMP2 may include the same layer as the first functional layer HFL and the second functional layer EFL. In an embodiment, each of the first dummy layer DMP1 and the second dummy layer DMP2 may further include a layer including the same material as the emission layer EML. In another example, a process of removing the first dummy layer DMP1 and the second dummy layer DMP2 may be added, and the first dummy layer DMP1 and the second dummy layer DMP2 may be omitted.

[0175] In an embodiment, at least one of the first layer SPL1, the second layer SPL2, and the third layer SPL3 may include a conductive material. For example, the second electrode CE may be in contact with at least one layer of the spacer SPC including the conductive material. Therefore, even if the second electrode CE is disconnected by the spacer SPC, the disconnected portion may be connected by the spacer SPC. In another example, even if the resistance of the second electrode CE increases due to the spacer SPC, the increased resistance may be reduced as the spacer SPC and the second electrode CE contact each other.

[0176] In an embodiment, the first thickness TK1 of the pixel defining layer PDL may be approximately to about The second thickness TK2 of the spacer SPC may be greater than or equal to the first thickness TK1 of the pixel defining layer PDL, but the embodiment is not limited thereto.

[0177] In an embodiment, the second thickness TK2 of the spacer SPC may be greater than or equal to the maximum organic material deposition thickness that may occur during deposition using the mask. Fig. 6A , shows a first thickness TK-R of the first auxiliary layer RIL and R' and the first emission layer REML, a second thickness TK-G of the second auxiliary layer GIL and G' and the second emission layer GEML, and a third thickness TK-B of the third auxiliary layer BIL and the third emission layer BEML. For example, referring to Figure 6B, showing a first thickness TK-Ra of the first functional layer HFL-R, the first auxiliary layer RIL and R' and the first emission layer REML, a second thickness TK-Ga of the first functional layer HFL-G, the second auxiliary layer GIL and G' and the second emission layer GEML, and a third thickness TK-Ba of the first functional layer HFL-B, the third auxiliary layer BIL and the third emission layer BEML.

[0178] In an embodiment, the second thickness TK2 of the spacer SPC may be defined as being greater than or equal to the sum of the two maximum thicknesses among the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B. In another example, the second thickness TK2 of the spacer SPC may be defined as being greater than or equal to the sum of the two maximum thicknesses among the first thickness TK-Ra, the second thickness TK-Ga, and the third thickness TK-Ba. For example, the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B may be approximately 0.25 μm, approximately 0.2 μm, and approximately 0.15 μm, respectively. For example, the second thickness TK2 of the spacer SPC may be approximately 0.45 μm or greater. However, these are merely thicknesses determined in consideration of the alignment error of the mask, and embodiments are not limited thereto.

[0179] In an embodiment, the second thickness TK2 of the spacer SPC may be defined as being greater than or equal to the maximum thickness among the first thickness TK-R, the second thickness TK-G, and the third thickness TK-B. In another example, the second thickness TK2 of the spacer SPC may be defined as being greater than or equal to the maximum thickness among the first thickness TK-Ra, the second thickness TK-Ga, and the third thickness TK-Ba. For example, the second thickness TK2 of the spacer SPC may be about 0.25 μm or more or about 0.3 μm or more.

[0180] In an embodiment, the pixel defining layer PDL may have a first width WT1. The first width WT1 may correspond to a distance between openings OP-G and OP-B adjacent to each other among the openings OP-R, OP-G, and OP-B. As the resolution of the display panel DP increases, the first width WT1 may decrease. For example, the first width WT1 may be several μm. For example, the first width WT1 may range from about 2 μm to tens of μm. For example, the first width WT1 may be about 2 μm.

[0181] The width WT2 of the area where the spacer SPC is formed may correspond to a numerical value obtained by subtracting the widths WTa1 and WTa2 of the tapered area, the widths WTb1 and WTb2 of the area where the control pattern LLP is formed, and the width of the process margin from the first width WT1 of the pixel defining layer PDL. The width WT2 may be defined as the second width WT2 of the spacer SPC. For example, in the case where the first width WT1 of the pixel defining layer PDL is about 2 μm or greater, the second width WT2 of the spacer SPC may be about 0.6 μm or greater. However, the numerical value is illustrative, and embodiments are not limited thereto. For example, the process margin may vary depending on the exposure equipment, and the widths WTa1 and WTa2 of the tapered area may vary depending on the material of the pixel defining layer PDL. Therefore, the second width WT2 of the spacer SPC is not limited to a specific numerical value.

[0182] Figure 8B is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Figure 8B When, with reference Fig. 8A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0183] refer to Fig. 7A and Figure 8B , the spacer SPC-1 may be disposed on the pixel defining layer PDL.

[0184] In an embodiment, the spacer SPC-1 may include a plurality of layers. For example, the spacer SPC-1 may include a first layer SPL1a and a second layer SPL2a disposed on the first layer SPL1a. The second layer SPL2a may be thinner than the first layer SPL1a. When the first layer SPL1a is subjected to patterning, the second layer SPL2a may be used as a mask (e.g., a hard mask).

[0185] Figure 8C is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Figure 8C When, with reference Fig. 8A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0186] refer to Fig. 7A and Figure 8C , the spacer SPC-2 may be disposed on the pixel defining layer PDL. The spacer SPC-2 may have a single layer structure or a multi-layer structure. The spacer SPC-2 may include an inorganic material.

[0187] In an embodiment, a second angle AG2a of a side surface of the spacer SPC-2 relative to a bottom surface of the spacer SPC-2 may be greater than or equal to a first angle AG1 of a side surface of the pixel defining layer PDL relative to a bottom surface of the pixel defining layer PDL. The first angle AG1 may be about 40 degrees or less, and the second angle AG2a may be about 90 degrees. However, the values ​​of the first angle AG1 and the second angle AG2a are illustrative, and embodiments are not limited thereto.

[0188] Fig.8D is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Fig.8D When, with reference Fig. 8A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0189] refer to Fig. 7A and Fig.8D , the spacer SPC-3 may be disposed on the pixel defining layer PDL. The spacer SPC-3 may include a first layer SPL1b and a second layer SPL2b. Each of the first layer SPL1b and the second layer SPL2b may have a single layer structure or a multi-layer structure. Each of the first layer SPL1b and the second layer SPL2b may include an inorganic material.

[0190] Fig. 8E is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Fig. 8E When, with reference Fig. 8A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0191] refer to Fig. 7A and Fig. 8E , the spacer SPC-4 may be disposed on the pixel defining layer PDL. The spacer SPC-4 may include a first layer SPL1c, a second layer SPL2c, and a third layer SPL3c. Each of the first layer SPL1c, the second layer SPL2c, and the third layer SPL3c may have a single layer structure or a multilayer structure. Each of the first layer SPL1c, the second layer SPL2c, and the third layer SPL3c may include an inorganic material.

[0192] The first width of the first layer SPL1c may be greater than the second width of the second layer SPL2c, and the second width of the second layer SPL2c may be greater than the third width of the third layer SPL3c. However, the embodiment is not limited thereto.

[0193] refer to FIG. 8A to FIG. 8E The cross-sectional structures of the spacers SPC and SPC-1 to SPC-4 described can be applied to reference 7A to 7CThe planar structures of spacers SPC, SPCa and SPCb are described.

[0194] Fig. 9 is a schematic cross-sectional view of a partial region of a display panel according to an embodiment. Fig. 9 When, with reference Fig. 8A The same components as those described will be given the same reference numerals, and description thereof will be omitted for convenience of description.

[0195] refer to Figure 4 , Fig. 7A and Fig. 9 , the control pattern LLPa may be disposed on the pixel defining layer PDL. The control pattern LLPa may be referred to as a protruding pattern. The second thickness TK2 of the spacer SPC may be greater than or equal to the third thickness TK3 of each of the control patterns LLPa. The spacer SPC may be disposed between the control patterns LLPa.

[0196] The intermediate layer CEL may be disposed on the first electrode AE, the pixel defining layer PDL, and the control pattern LLPa. In an embodiment, the thickness of the intermediate layer CEL (e.g., the first functional layer HFL) may be reduced by the control pattern LLPa. In another example, the first functional layer HFL may be disconnected by the control pattern LLPa. For example, current leakage to a portion where the control pattern LLPa is formed may be prevented.

[0197] According to the above description, the area of ​​the region where the spacer is to be set can be reduced as the resolution of the display panel increases. The spacer can have a shape extending in at least three directions. Therefore, the rigidity of the spacer can be improved. In addition, even if the width of the extension of the spacer is reduced due to the limited area, the rigidity of the spacer can be improved by limiting the extension length of the extension. Therefore, during the deposition using the mask, the possibility of damaging the spacer due to insufficient rigidity can be eliminated or reduced. Thus, the manufacturing yield and reliability of the display panel can be improved.

[0198] In summarizing the detailed description, it will be appreciated by those skilled in the art that many changes and modifications can be made to the embodiments without departing substantially from the principles, spirit and scope of the present disclosure. Therefore, the disclosed embodiments are used in a general and descriptive sense only and not for the purpose of limitation.

Claims

1. A display panel, wherein: The display panel comprises: a circuit board, the circuit board comprising a pixel circuit; and A component layer, the component layer is arranged on the circuit board, and the component layer includes: a plurality of light emitting elements; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light emitting elements; and A spacer, the spacer being disposed on the pixel defining layer, wherein: The plurality of openings include a first opening, a second opening, and a third opening, each of the first opening, the second opening, and the third opening being adjacent to the spacer, The spacer comprises: a central portion disposed between the first opening, the second opening, and the third opening; a first extension extending from the central portion to be disposed between the first opening and the second opening; a second extension extending from the central portion to be disposed between the second opening and the third opening; and a third extension extending from the central portion to be disposed between the third opening and the first opening, and Ends of the first extension portion, the second extension portion, and the third extension portion are disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

2. The display panel according to claim 1, wherein: The spacer comprises a plurality of layers, and At least one layer among the plurality of layers includes a conductive material.

3. The display panel according to claim 1, wherein: The spacer comprises: a first layer having a first width; and A second layer is disposed on the first layer and has a second width that is smaller than the first width of the first layer.

4. The display panel according to claim 1, wherein: The spacer comprises a plurality of spacers, The plurality of spacers include a first spacer and a second spacer closest to the first spacer, and At least two light emitting elements among the plurality of light emitting elements are disposed between the first spacer and the second spacer.

5. The display panel according to claim 1, wherein: Each of the first opening, the second opening, and the third opening has a polygonal shape.

6. The display panel according to claim 5, wherein: The first opening includes a first side facing the first extension, The second opening includes a second side facing the first extension, and The end of the first extension is aligned with or spaced apart from a virtual line connecting a center of the first side and a center of the second side.

7. The display panel according to claim 1, wherein: The pixel defining layer includes an inorganic material, and The spacer includes an inorganic material.

8. The display panel according to claim 1, wherein: The end portion of the first extension portion, the end portion of the second extension portion, and the end portion of the third extension portion have a rounded shape, an angular shape, or a pointed shape.

9. The display panel according to claim 1, wherein: A first angle of a side surface of the pixel defining layer defining the first opening with respect to a bottom surface of the pixel defining layer is about 40 degrees or less.

10. The display panel according to claim 9, wherein: A second angle of the side surface of the spacer relative to the bottom surface of the spacer is greater than or equal to the first angle.

11. The display panel according to claim 1, wherein: The spacer is thicker than the pixel defining layer.

12. The display panel according to claim 1, wherein: A plurality of valleys recessed from an upper surface of the pixel defining layer are provided in the pixel defining layer, and The plurality of valleys surround at least a portion of the first opening, the second opening, and the third opening, respectively.

13. The display panel according to claim 12, wherein: The spacer is disposed between the plurality of valleys.

14. The display panel according to claim 1, wherein: The display panel further includes: A plurality of protrusion patterns are disposed on the pixel defining layer, wherein the plurality of protrusion patterns surround at least a portion of the first opening, the second opening, and the third opening, respectively.

15. The display panel according to claim 14, wherein: The spacer has a thickness greater than a thickness of the plurality of protrusion patterns.

16. A display panel, wherein: The display panel comprises: a circuit board, the circuit board comprising a pixel circuit; and A component layer, the component layer is arranged on the circuit board, and the component layer includes: A light emitting element, the light emitting element comprising a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a portion of the first electrode; and A spacer, the spacer being disposed on the pixel defining layer, wherein: The spacer includes a central portion and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively, and The pixel defining layer and the spacer include an inorganic material.

17. The display panel according to claim 16, wherein: A first angle of a side surface of the pixel defining layer defining the opening relative to a bottom surface of the pixel defining layer is less than or equal to a second angle of a side surface of the spacer relative to a bottom surface of the spacer.

18. The display panel according to claim 16, wherein: A first angle of a side surface of the pixel defining layer defining the opening with respect to a bottom surface of the pixel defining layer is about 40 degrees or less.

19. The display panel according to claim 16, wherein: The spacer is thicker than the pixel defining layer.

20. The display panel according to claim 16, wherein: The spacer comprises a plurality of layers, and At least one layer among the plurality of layers includes a conductive material.

21. The display panel according to claim 16, wherein: The spacer comprises: a first layer having a first width; and A second layer is disposed on the first layer and has a second width that is smaller than the first width.

22. The display panel according to claim 16, wherein: The opening has a polygonal shape and includes a first side facing the first extension, and An end of the first extension is aligned with or spaced apart from a normal line extending from a center of the first side.

23. The display panel according to claim 16, wherein: The spacer comprises a plurality of spacers, The plurality of spacers include a first spacer and a second spacer closest to the first spacer, The light emitting element comprises a plurality of light emitting elements, and At least two light emitting elements among the plurality of light emitting elements are disposed between the first spacer and the second spacer.

24. A display panel, wherein: The display panel comprises: a circuit board, the circuit board comprising a pixel circuit; and A component layer, the component layer is arranged on the circuit board, and the component layer includes: A light emitting element, the light emitting element comprising a first electrode, an intermediate layer, and a second electrode; a pixel defining layer having an opening overlapping a portion of the first electrode; and A spacer, the spacer being disposed on the pixel defining layer, wherein: The spacer includes a central portion and a first extension portion, a second extension portion, and a third extension portion protruding from the central portion in three directions, respectively, and A first angle of a side surface of the pixel defining layer defining the opening with respect to a bottom surface of the pixel defining layer is about 40 degrees or less.

25. The display panel according to claim 24, wherein: A second angle of the side surface of the spacer relative to the bottom surface of the spacer is greater than or equal to the first angle.

26. The display panel according to claim 24, wherein: The pixel defining layer and the spacer each include an inorganic material.

27. The display panel according to claim 24, wherein: The spacer comprises a plurality of layers, and At least one of the plurality of layers includes a conductive material.

28. The display panel according to claim 24, wherein: The spacer comprises: a first layer having a first width; and A second layer is disposed on the first layer and has a second width that is smaller than the first width.

29. An electronic device, wherein: The electronic device comprises: A display panel that displays an image; and A housing accommodating the display panel, wherein: The display panel comprises: a circuit board, the circuit board comprising a pixel circuit; and A component layer, the component layer is arranged on the circuit board, and the component layer includes: a plurality of light emitting elements; a pixel defining layer having a plurality of openings respectively overlapping the plurality of light emitting elements; and a spacer, the spacer being disposed on the pixel defining layer, The plurality of openings include a first opening, a second opening, and a third opening, each of the first opening, the second opening, and the third opening being adjacent to the spacer, and The spacer comprises: a central portion, the central portion being disposed between the first opening, the second opening, and the third opening; a first extension extending from the central portion to be disposed between the first opening and the second opening; a second extension extending from the central portion to be disposed between the second opening and the third opening; and a third extension extending from the central portion to be disposed between the third opening and the first opening, and Ends of the first extension portion, the second extension portion, and the third extension portion are disposed in a region defined by a virtual line connecting a first center of the first opening, a second center of the second opening, and a third center of the third opening.

Images