Time division multiplexing SIMD functional unit

Abstract

A single instruction / multiple data (SIMD) processor uses a functional unit that can perform a single operation on multiple data elements. The functional unit operates at a higher speed than the remainder of the processor, allowing sequential processing of each data element in the SIMD operand, using less computing resources and avoiding any processing throughput loss. The SIMD processor includes an input register that receives N data elements at the beginning of a clock cycle in a slow clock domain. Each data element of the operand is selected and passed to the functional unit over consecutive clock cycles in a fast clock domain. The N results are generated over N consecutive clock cycles in the fast clock domain and combined to provide a plurality of results over a single clock cycle in the slow clock domain.

Description

[0001] Priority application

[0002] This application claims the benefit of priority to U.S. Provisional Application No. 63 / 348,347, filed on June 2, 2022, which is incorporated herein by reference in its entirety.

[0003] Statement on government support

[0004] This invention was made with Government support under Contract No. N00014-21-9-0001. The U.S. Government has certain rights in this invention.

[0005] As used in this Statement of Government Support, "invention" refers to all or part of the subject matter in one or more claims set forth below, or as may be subsequently filed based on the subject matter of this specification. Technical Field

[0006] Embodiments of the present disclosure generally relate to the operation of a processing element using time-division multiplexed single instruction / multiple data (SIMD) functional units to handle SIMD commands. Background Art

[0007] In SIMD processing, a single instruction is received along with multiple data values ​​that will be used to execute the instruction. For example, a single "add" instruction may be received along with four pairs of operands so that four additions are performed. Since the instruction is only sent once, instruction overhead is reduced, making processing more efficient. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] The present disclosure will be more fully understood from the detailed description given below and from the drawings of various embodiments of the present disclosure. However, the drawings should not be construed as limiting the present disclosure to specific embodiments, but are only for explanation and understanding.

[0009] In order to easily identify the discussion of any particular component or act, the most significant digit or digits in a reference number refer to the drawing number in which the component is first introduced.

[0010] Figure 1 An example of a SIMD instruction according to an embodiment is described.

[0011] Figures 2 to 3 An example of a hardware design for implementing a time-division multiplexed SIMD functional unit according to an embodiment is generally described.

[0012] Figures 4 to 7 The invention is generally described according to the embodiment Figures 2 to 3 Timing diagram of the components of a hardware design.

[0013] Figure 8is a flow chart illustrating the operation of a method performed by a circuit in performing a time-division multiplexed SIMD function according to some embodiments of the present disclosure.

[0014] Fig. 9 A block diagram illustrating an example machine in which, in, or by which one or more techniques (eg, methodologies) discussed herein may be implemented. DETAILED DESCRIPTION

[0015] SIMD processors use execution function units that can perform operations on multiple data elements in parallel. This parallelism provides greater data processing throughput than single instruction single data (SISD) processors, but the performance improvement comes at a cost. SIMD function unit resources (such as multipliers and ALUs) are replicated to concurrently process multiple data elements in the function unit input operands. This duplication increases the chip area and design complexity of the processor design.

[0016] As described herein, the functional unit operates at a higher speed than the rest of the processor, allowing each data element in a SIMD operand to be processed sequentially, using fewer computational resources and avoiding any processing throughput loss. The ratio of the functional unit frequency to the processor frequency is greater than or equal to the number of data elements in the operand to maintain the same performance.

[0017] A SIMD processor includes an input register that receives N data elements at the start of a clock cycle in the slow clock domain. Each data element of the operand is selected and passed to the functional unit on successive clock cycles in the fast clock domain. This is achieved using a multiplexer and a modulo-N counter. The functional unit operates in the fast clock domain. The fast clock frequency is N times the slow clock frequency.

[0018] The functional unit comprises X pipeline stages. After a data element is processed by the X pipeline stages, the result is written to an output register. N results are generated over N consecutive clock cycles in the fast clock domain. The results are passed through the Y pipeline stages aligned to the registers one fast clock cycle after another and written to the output register, as enabled by the modulo-N counter and decoder.

[0019] After all N data elements of the result have been received in the output register, the data elements are driven in parallel to the staging register running in the slow clock domain. The multi-element result is passed from the staging register to the SIMD processor.

[0020] By running a local portion of the chip design at a higher frequency than the rest of the design, functional unit resources are saved while maintaining the same performance as a SIMD functional unit with concurrent processing of data elements. Thus, the size of the physical device can be reduced.

[0021] Figure 1 An example of a SIMD instruction according to an embodiment is described. At a first clock cycle, the SIMD processor receives a first single instruction 120 and a first plurality of data 110. The first single instruction 120 is a load instruction that loads the first plurality of data 110 into a register 130. Four data values ​​V1A, V2A, V3A, and V4A of the first plurality of data 110 are loaded into the register 130 according to the single instruction 120.

[0022] On a second clock cycle, the SIMD processor receives a second single instruction 150 and a second plurality of data 140. The second single instruction 150 is an addition instruction that adds the second plurality of data 140 to the value in register 130. Thus, after executing the second single instruction 150, the value in the register is updated, as shown in register 160, which at a later time may be register 130.

[0023] Figures 2 to 3 An example of a hardware design 200 for implementing a time-multiplexed SIMD functional unit according to an embodiment is generally described. The hardware design 200 may be implemented in various devices, such as a field programmable gate array ("FPGA") or an application specific integrated circuit ("ASIC").

[0024] The hardware design 200 includes an input data interface 210, a multiplexer 220, modulo-N counters 230 and 310, a functional unit 240, a decoder 320, an alignment unit 330, latches 340A and 340N, and an output data interface 350. The input data interface 210 and the output data interface 350 operate using a slow clock, and the remaining elements operate using a fast clock. The received SIMD instruction includes N data elements and a single instruction. The fast clock is N times faster than the slow clock. For example, the slow clock may operate at 250 MHz, while the fast clock may operate at 1 GHz, which is the clock frequency of the slow clock multiplied by N.

[0025] Multiplexer 220 receives N input data elements as input data values ​​and outputs one of the input values ​​according to the value of the received control signal. Modulo-N counter 230 provides the control signal to multiplexer 220. Therefore, over N consecutive fast clock cycles, N different input values ​​are selected and output by multiplexer 220.

[0026] Functional unit 240 receives each different input value and processes it to generate an output. Functional unit 240 includes X stages. As a result, X fast clock cycles pass between the time an input value is provided to functional unit 240 and the time a corresponding output is generated. Thus, the first output value is generated X fast clock cycles after processing of the SIMD command begins, and the last output value is generated after N-1 fast clock cycles.

[0027] The output of the functional unit 240 (using the fast clock) can be aligned with the timing of the output data interface 350 (using the slow clock). For example, if X=1 and N=4, then after receiving the SIMD command, the output is generated entirely by four fast clock cycles. In this example, four fast clock cycles are exactly equal to one slow clock cycle. Therefore, the output of the functional unit 240 can be copied to the output data interface 350 without using the alignment unit 330, ready to be read on the next slow clock cycle.

[0028] Alternatively, the outputs of the functional unit 240 may not be aligned with the timing of the output data interface 350. For example, if X=2 and N=4, then the last output is generated on the fifth fast clock cycle. Therefore, some outputs are ready within the first slow clock cycle, while the last output is not ready until the second slow clock cycle. The alignment unit 330 is used to delay the outputs so that they are aligned with the next clock cycle. In this example, three stages of delay will make all four outputs ready on the second slow clock cycle.

[0029] Thus, the outputs of the functional units 240 are provided to the alignment unit 330, which delays each output by a predetermined delay. For example, the alignment unit 330 may include Y stages, each of which delays the output by one fast clock cycle. The aligned outputs are then provided to N latches (two of which are shown: latches 340A and 340N) that store the output data elements. The modulo-N counter 310 is provided as an input to the N output decoder 320. Each of the N outputs of the decoder 320 is provided to a corresponding one of the latches 340A to 340N, thereby enabling the latch and causing the corresponding output data to be copied to the output data interface 350. Thus, over N fast clock cycles (one slow clock cycle), N results are copied to the output data interface 350.

[0030] The assertion of the enable signal by the decoder 320 may be considered to occur on sequential stages of the slow clock (i.e., stage 0 to stage N-1). The number of alignment staging registers (Y) of the alignment unit 330 is selected to allow the first data element to arrive at the output data element 0 register at the end of stage N-1. The number of alignment stages may be derived using the following equation: Y = aN - X - 3, where "a" is the lowest positive integer that avoids negative values ​​for Y. In some examples, the value of "a" may be further increased for more alignment stages to support an architecturally defined pipeline length. This capability may be useful for certain algorithms, such as reduction operations that require the functional unit results to be fed back to the operand inputs after a certain latency.

[0031] Figures 4 to 7 The invention is generally described according to the embodiment Figures 2 to 3 Timing diagram of the components of a hardware design. Figure 4A portion 400 of a timing diagram is illustrated that includes three slow clock cycles and twelve fast clock cycles. Portion 400 includes timelines 410, 420, 430, 440, 450, 460, 470, and 480.

[0032] Time lines 410 and 420 show the oscillations of the slow clock and the fast clock, respectively. Figures 4 to 7 In the example of , the fast clock is four times faster than the slow clock, and the SIMD processor receives four data elements for each instruction. During the first slow clock cycle, data ABCD is received as a 256-bit input data value, as shown in timeline 430. During the second slow clock cycle, the input data ABCD is staged into four separate 64-bit input data values, as shown in timelines 440 to 470. The separate 64-bit input data values ​​are processed using modulo-N counter 230 and multiplexer 220 to provide sequential inputs to functional unit 240 on the fast clock cycle, as shown in timeline 480.

[0033] The process of handling input data is repeated by receiving second 256-bit input values ​​(data EFGH) during the second slow clock cycle and sequentially providing those input values ​​to functional units 240 during the third slow clock cycle.

[0034] Figure 5 A portion 500 of a timing diagram is illustrated that includes approximately three slow clock cycles and eleven fast clock cycles. The first slow clock cycle of portion 500 is the same slow clock cycle as the last slow clock cycle of portion 400. Portion 500 includes timelines 510, 520, 530, 540, 550, 560, 570, 580, and 590. Timelines 510-580 continue their corresponding timelines 410-480 in portion 400 with some overlap. Timeline 590 shows a 64-bit output data element generated by functional unit 240.

[0035] On successive slow clock cycles, data IJKL, MNOP, and QRST are received as 256-bit input data. On each subsequent slow clock cycle, the 256-bit input data is processed as four 64-bit input values, each of which is provided to functional unit 240 successively (on fast clock cycles).

[0036] exist Figures 4 to 7 In the example of FIG. 1 , the first input data (data A) is received by the functional unit 240 during the fifth fast clock cycle, and the corresponding first output data (result A) is generated during the sixteenth fast clock cycle. Therefore, the latency of the functional unit 240 is eleven fast clock cycles. Starting from the sixteenth clock cycle, the functional unit 240 provides another result value on each fast clock cycle.

[0037] Figure 6A portion 600 of a timing diagram is illustrated, which includes Figure 4 The portion 600 includes the same three slow clock cycles and twelve fast clock cycles as the portion 400. The portion 600 includes timelines 610, 620, 630, 640, 650, 660, 670, 680 and 690.

[0038] Timeline 610 to 640 display Figure 3 The decoder 320 of FIG. 6 shows the enabled stages 0 to 3 outputs. Timelines 650 to 680 show the corresponding Figure 3 6. Timeline 690 shows the output data elements 0 through 3 of latches 340A through 340N of FIG. 6. Since no output was generated prior to the time shown in portion 600, the output data elements are zero in portion 600. Timeline 690 shows the output data of output data interface 350, which is also zero in portion 600.

[0039] Figure 7 A portion 700 of a timing diagram is illustrated, which includes Figure 5 The same time period as portion 500. Portion 600 includes timelines 710, 720, 730, 740, 750, 760, 770, 780, and 790, each of which continues Figure 6 One of timelines 610 to 690.

[0040] The enabling stages 0 to 3 timelines 710 to 740 show that on each fast clock cycle, one stage is enabled and on each slow clock cycle (on Figures 4 to 7 Each stage is enabled once on the first (four fast clock cycles in the example of ) phase. After the enable phase signal is raised, the output data element of the stage receives the next value from the alignment unit 330. The output data element of the stage is maintained until the enable phase signal of the stage is raised again. Therefore, after the enable phase 0 signal is raised in the fourth fast clock cycle of the portion 700, the output element 0 [63: 0] value is set to the result A and the value is maintained for four fast clock cycles. After the enable phase 1 signal is raised in the fifth fast clock cycle of the portion 700, the output element 1 [63: 0] value is set to the result B and the value is maintained for four fast clock cycles. The enable phase 2 and enable phase 3 signals are handled similarly. After all four enable phase 0 to 3 signals have been received and all four output data elements 0 to 3 have been latched, the output data [255: 0] contains the complete SIMD result: result ABCD.

[0041] therefore, Figures 4 to 7 The timing diagram of shows the generation of SIMD results from SIMD inputs using a single functional unit 240 and a single alignment unit 330 rather than multiple functional units, one functional unit for each of the multiple data being processed.

[0042] Figure 8 800 is a flowchart illustrating the operations of a method 800 performed by a circuit in performing a time-division multiplexed SIMD function according to some embodiments of the present disclosure. The method 800 includes operations 810, 820, 830, and 840. By way of example and not limitation, the method 800 is described as being performed by a SIMD processor using Figures 2 to 3 The hardware design 200 is used to execute.

[0043] In operation 810, a SIMD processor receives a single instruction and a plurality of data through or using an input interface operating at a first frequency. For example, a SIMD processor operating at a slow clock frequency Figure 2 The input data interface 210 can receive Figure 1 A single instruction 120 or 150 and multiple data 110 or 140.

[0044] In operation 820, the SIMD processor selects from the plurality of data by or using a multiplexer operating at a second clock frequency higher than the first clock frequency. Figure 2 The multiplexer 220 selects from a plurality of data received by the input data interface 210 .

[0045] In operation 830, the SIMD processor performs operations on the selected data by or using the functional units operating at the second clock frequency. For example, the functional units 240 operating at the fast clock frequency perform X operations on each input data element starting from sequential fast clock cycles.

[0046] The SIMD processor provides the result from the functional unit for each of the plurality of data by or using an output interface operating at a first clock frequency (operation 840). Figure 3 The output data interface 350 provides a result for each of the plurality of data elements.

[0047] Fig. 9Block diagram illustrating an example machine 900, which may be used, implemented in or by the machine 900 to implement one or more techniques discussed herein (e.g., methodology). As described herein, an example may include logic or several components or mechanisms in the machine 900 or may be operated by it. A circuit system (e.g., a processing circuit system) is a collection of circuits including hardware (e.g., simple circuits, gates, logic, etc.) implemented in a tangible entity of the machine 900. Over time, the members of the circuit system may be flexible. The circuit system includes members that can perform specific operations individually or in combination when operating. In an example, the hardware of the circuit system may be designed to implement specific operations (e.g., hard-wired) by constant design. In an example, the hardware of the circuit system may include physical components (e.g., execution units, transistors, simple circuits, etc.) that are variably connected, including machine-readable media that are physically modified (e.g., magnetic properties of constant aggregate particles, electrically movable placement, etc.) to encode instructions for the specific operation. When the physical components are connected, the underlying electrical properties of the hardware components are changed, for example, from insulators to conductors or vice versa. The instructions enable embedded hardware (e.g., an execution unit or a loading mechanism) to create a member of a circuit system in hardware via a variable connection to perform a portion of a specific operation when in operation. Thus, in an example, when the device is operating, the machine-readable media element is part of the circuit system or is communicatively coupled to other components of the circuit system. In an example, any of the physical components can be used in more than one member of more than one circuit system. For example, under operation, an execution unit can be used in a first circuit in a first circuit system at one point in time and reused by a second circuit in the first circuit system or a third circuit in the second circuit system at a different time. Additional examples of these components of machine 900.

[0048] In alternative embodiments, the machine 900 may operate as a standalone device or may be connected (e.g., networked) to other machines. In a networked deployment, the machine 900 may operate as a server machine or a client machine or both in a server-client network environment. In an example, the machine 900 may act as a peer machine in a peer-to-peer (P2P) (or other distributed) network environment. The machine 900 may be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a mobile phone, a network appliance, a network router, a switch or a bridge, or any machine capable of (sequentially or otherwise) executing instructions for actions specified by the machine. In addition, although only a single machine is described, the term "machine" should also be deemed to include any collection of machines that individually or jointly execute one (or more) sets of instructions to perform any one or more of the methods discussed herein (e.g., cloud computing, software as a service (SaaS), other computer cluster configurations).

[0049] The machine 900 (e.g., a computer system) may include a hardware processor 902 (e.g., a central processing unit (CPU), a graphics processing unit (GPU), a hardware processor core, or any combination thereof), a main memory 904, a static memory 906 (e.g., memory or storage for firmware, microcode, basic input output (BIOS), unified extensible firmware interface (UEFI), etc.), and a mass storage device 908 (e.g., a hard drive, a tape drive, a flash storage device, or other block device), some or all of which may communicate with each other via an interconnect 930 (e.g., a bus). The machine 900 may further include a display device 910, an alphanumeric input device 912 (e.g., a keyboard), and a user interface (UI) navigation device 914 (e.g., a mouse). In an example, the display device 910, the input device 912, and the UI navigation device 914 may be a touch screen display. The machine 900 may additionally include a signal generating device 918 (e.g., a speaker), a network interface device 920, and one or more sensors 916, such as a global positioning system (GPS) sensor, a compass, an accelerometer, or other sensors. The machine 900 may include an output controller 928, such as for communicating with or controlling a serial (e.g., Universal Serial Bus (USB)), parallel, or other wired or wireless (e.g., infrared (IR), near field communication (NFC), etc.) connection of one or more peripheral devices (e.g., a printer, a card reader, etc.).

[0050] The registers of the hardware processor 902, the main memory 904, the static memory 906, and the mass storage device 908 may be or include a machine-readable medium 922 on which is stored one or more sets of data structures or instructions 924 (e.g., software) embodying or used by any one or more of the techniques or functions described herein. The instructions 924 may also reside, completely or at least partially, within any of the registers of the hardware processor 902, the main memory 904, the static memory 906, or the mass storage device 908 during execution thereof by the machine 900. In an example, one or any combination of the hardware processor 902, the main memory 904, the static memory 906, or the mass storage device 908 may constitute the machine-readable medium 922. Although the machine-readable medium 922 is illustrated as a single medium, the term "machine-readable medium" may include a single medium or multiple media (e.g., a centralized or distributed database or associated caches and servers) configured to store one or more instructions 924.

[0051] The term "machine-readable medium" may include any medium capable of storing, encoding, or carrying instructions executed by the machine 900 and causing the machine 900 to perform any one or more of the techniques of the present disclosure, or capable of storing, encoding, or carrying data structures used by or associated with such instructions. Non-limiting machine-readable medium examples may include solid-state memory, optical media, magnetic media, and signals (e.g., radio frequency signals, other photon-based signals, sound signals, etc.). In an example, a non-transitory machine-readable medium includes a machine-readable medium having a plurality of particles with a constant (e.g., stationary) mass and thus a composition of matter. Thus, a non-transitory machine-readable medium is a machine-readable medium that does not include a transitory propagating signal. Specific examples of non-transitory machine-readable media may include: non-volatile memory, such as semiconductor memory devices (e.g., electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM)) and flash memory devices; magnetic disks, such as internal hard disks and removable magnetic disks; magneto-optical disks; and CD-ROM and DVD-ROM disks.

[0052] In an example, the information stored or otherwise provided on the machine-readable medium 922 may represent instructions 924, such as the instructions 924 themselves or a format from which the instructions 924 may be derived. Such a format from which the instructions 924 may be derived may include source code, encoded instructions (e.g., in compressed or encrypted form), packaged instructions (e.g., divided into multiple packages), or the like. The information representing the instructions 924 in the machine-readable medium 922 may be processed by the processing circuit system into instructions to implement any of the operations discussed herein. For example, deriving the instructions 924 from the information (e.g., processing by the processing circuit system) may include: compiling (e.g., from source code, object code, etc.), interpreting, loading, organizing (e.g., dynamically or statically linking), encoding, decoding, encrypting, not encrypting, packing, unpacking, or otherwise manipulating the information into instructions 924.

[0053] In an example, the export of instructions 924 may include (e.g., by processing circuitry) assembling, compiling, or interpreting information to create instructions 924 from some intermediate or pre-processed format provided by machine-readable media 922. When the information is provided in multiple parts, the information may be combined, unpacked, and modified to create instructions 924. For example, the information may be in multiple compressed source code packages (or object code, or binary executable code, etc.) on one or several remote servers. The source code packages may be encrypted when transmitted over the network, and, if necessary, decrypted, decompressed, assembled (e.g., linked), compiled or interpreted at the local machine (e.g., compiled or interpreted into a library, a stand-alone executable file, etc.) and executed by the local machine.

[0054] The instructions 924 may further be transmitted or received over a communication network 926 using a transmission medium via a network interface device 920 utilizing any of a number of transmission protocols (e.g., frame relay, Internet Protocol, transmission control protocol (TCP), user datagram protocol (UDP), hypertext transfer protocol (HTTP), etc.). Example communication networks may include a local area network (LAN), a wide area network (WAN), a packet data network (e.g., the Internet), a mobile telephone network (e.g., a cellular network), a plain old telephone (POTS) network, and a wireless data network (e.g., the Institute of Electrical and Electronics Engineers (IEEE) 802.11 series of standards (known as ), IEEE 802.16 series of standards (called ), IEEE 802.15.4 family of standards, peer-to-peer (P2P) networks, etc.). In an example, the network interface device 920 may include one or more physical jacks (e.g., Ethernet, coaxial, or telephone jacks) or one or more antennas to connect to the network 926. In an example, the network interface device 920 may include multiple antennas to communicate wirelessly using at least one of single-input multiple-output (SIMO), multiple-input multiple-output (MIMO), or multiple-input single-output (MISO) technology. The term "transmission media" should be taken to include any intangible media capable of storing, encoding, or carrying instructions executed by the machine 900, and includes digital or analog communication signals or other intangible media that facilitate the communication of such software. Transmission media is machine-readable media.

[0055] In order to better illustrate the methods and devices described herein, a set of non-limiting exemplary embodiments are described below as examples of digital recognition.

[0056] Example 1 is a system comprising: an input interface that receives a single instruction and multiple data, the input interface operating at a first clock frequency; a multiplexer that selects from the multiple data, the multiplexer operating at a second clock frequency higher than the first clock frequency; a functional unit that operates on the selected data, the functional unit operating at the second clock frequency; and an output interface that provides a result from the functional unit for each of the multiple data, the output interface operating at the first clock frequency.

[0057] In Example 2, the subject matter of Example 1, wherein: the plurality of data includes N data elements; and the second clock frequency is N times the first clock frequency.

[0058] In Example 3, the subject matter of Example 2 includes a modulo-N counter coupled to the multiplexer and configured to provide a control signal to the multiplexer to control the selection from the plurality of data.

[0059] In Example 4, the subject matter of Examples 1-3 includes an alignment unit that: receives an output of the functional unit; provides the output of the functional unit after a predetermined delay; and operates at the second clock frequency.

[0060] In Example 5, the subject matter of Example 4, wherein: the plurality of data comprises N data elements; the functional unit comprises X stages; the alignment unit comprises Y stages, wherein Y=aN−X−3 and a is the lowest positive integer that avoids negative values ​​of Y.

[0061] In Example 6, the subject matter of Examples 4 to 5, wherein: the plurality of data includes N data elements; the functional unit includes X stages; the alignment unit includes Y stages, wherein Y=aN-X-3 and a is greater than the lowest positive integer that avoids negative values ​​of Y.

[0062] In Example 7, the subject matter of Examples 4-6 includes a plurality of output registers that receive outputs from the alignment unit and provide the outputs to the output interface, the plurality of output registers operating at the second clock frequency.

[0063] In Example 8, the subject matter of Example 7, wherein: the plurality of data includes N data elements; and further includes a modulo-N counter connected to a decoder, the decoder selecting from the plurality of output registers for each output from the alignment unit, the modulo-N counter operating at the second clock frequency.

[0064] In Example 9, the subject matter of Examples 1-8, wherein the system is part of a field programmable gate array (FPGA).

[0065] In Example 10, the subject matter of Examples 1-9, wherein the system is part of an application specific integrated circuit (ASIC).

[0066] Example 11 is a method comprising: receiving a single instruction and multiple data through an input interface operating at a first clock frequency; selecting from the multiple data through a multiplexer operating at a second clock frequency higher than the first clock frequency; performing an operation on the selected data through a functional unit operating at the second clock frequency; and providing a result from the functional unit for each of the multiple data through an output interface operating at the first clock frequency.

[0067] In Example 12, the subject matter of Example 11, wherein: the plurality of data includes N data elements; and the second clock frequency is N times the first clock frequency.

[0068] In Example 13, the subject matter of Example 12 includes controlling the selection of the plurality of data by a modulo-N counter.

[0069] In Example 14, the subject matter of Examples 11-13 includes: receiving, by an alignment unit operating at the second clock frequency, an output of the functional unit; and providing, by the alignment unit, the output of the functional unit after a predetermined delay.

[0070] In Example 15, the subject matter of Example 14, wherein: the plurality of data comprises N data elements; the functional unit comprises X stages; the alignment unit comprises Y stages, wherein Y=aN−X−3 and a is the lowest positive integer that avoids negative values ​​of Y.

[0071] In Example 16, the subject matter of Examples 14-15, wherein: the plurality of data includes N data elements; the functional unit includes X stages; the alignment unit includes Y stages, wherein Y=aN-X-3 and a is greater than the lowest positive integer that avoids negative values ​​of Y.

[0072] In Example 17, the subject matter of Examples 14-16 includes: receiving outputs from the alignment unit through a plurality of output registers operating at the second clock frequency; and providing the outputs to the output interface through the plurality of output registers.

[0073] In Example 18, the subject matter of Example 17, wherein: the plurality of data includes N data elements; and further comprising selecting from the plurality of output registers for each output from the alignment unit by a decoder coupled to a modulo-N counter.

[0074] In Example 19, the subject matter of Examples 11-18, wherein the receiving the single instruction through the input interface comprises receiving the single instruction with a field programmable gate array (FPGA) interface.

[0075] In Example 20, the subject matter of Examples 11-19, wherein the receiving the single instruction through the input interface comprises receiving the single instruction with an application specific integrated circuit (ASIC) interface.

[0076] Example 21 is at least one machine-readable medium comprising instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement any of Examples 1-20.

[0077] Example 22 is an apparatus comprising means for implementing any one of examples 1-20.

[0078] Example 23 is a system for implementing any one of examples 1 to 20.

[0079] Example 24 is a method for implementing any one of examples 1 to 20.

[0080] The above detailed description includes references to the accompanying drawings that form a part of the detailed description. The drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "examples". Such examples may include elements other than the elements shown or described. However, the inventors also contemplate examples in which only those elements shown or described are provided. In addition, the inventors also contemplate examples (or one or more aspects thereof) using any combination or arrangement of those elements shown or described with respect to a specific example (or one or more aspects thereof) or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0081] In this document, the term "a" or "an" is used, as is common in patent literature, to include one or more than one, independent of any other examples or usages of "at least one" or "one or more". In this document, the term "or" is used to refer to a "non-exclusive or", so that "A or B" may include "A but not B", "B but not A", and "A and B", unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the corresponding terms "including" and "wherein". Moreover, in the appended claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements other than those listed after the term in the claim is still considered to fall within the scope of the claim. In addition, in the appended claims, the terms "first", "second", and "third" and the like are used only as labels, and no numerical requirements are intended to be imposed on their objects.

[0082] The above description is intended to be illustrative rather than restrictive. For example, the above examples (or one or more aspects thereof) may be used in combination with each other. After reviewing the above description, for example, a person of ordinary skill in the art may use other embodiments. It should be understood that it will not be used to interpret or limit the scope or meaning of the claims. Moreover, in the above detailed description, various features may be combined together to simplify the present disclosure. This should not be interpreted as wishing that unclaimed public features are indispensable to any claim. Specifically, the subject matter of the invention may have non-all features of a specific disclosed embodiment. Therefore, the attached claims are hereby incorporated into the specific embodiments, wherein each claim itself is a separate embodiment, and it is expected that such embodiments can be combined with each other in various combinations or arrangements. The scope of the present invention should be determined with reference to the attached claims together with the full range of equivalents authorized by such claims.

Claims

1. A system comprising: An input interface, which receives a single instruction and a plurality of data, wherein the input interface operates at a first clock frequency; a multiplexer that selects from the plurality of data, the multiplexer operating at a second clock frequency higher than the first clock frequency; a functional unit that operates on the selected data, the functional unit operating at the second clock frequency; and An output interface provides a result from the functional unit for each of the plurality of data, the output interface operating at the first clock frequency.

2. The system of claim 1, wherein: The plurality of data includes N data elements; and The second clock frequency is N times the first clock frequency.

3. The system according to claim 2, further comprising: A modulo-N counter is coupled to the multiplexer and is configured to provide a control signal to the multiplexer to control the selection from the plurality of data.

4. The system of claim 1, further comprising: An alignment unit which: receiving an output of the functional unit; providing said output of said functional unit after a predetermined delay; and operates at the second clock frequency.

5. The system of claim 4, wherein: The plurality of data includes N data elements; The functional unit includes X stages; The alignment unit includes Y stages, where Y=aN−X−3 and a is the lowest positive integer that avoids negative values ​​of Y.

6. The system of claim 4, wherein: The plurality of data includes N data elements; The functional unit includes X stages; The alignment unit comprises Y stages, where Y=aN−X−3 and a is greater than the lowest positive integer that avoids negative values ​​of Y.

7. The system of claim 4, further comprising: A plurality of output registers receive outputs from the alignment unit and provide the outputs to the output interface, the plurality of output registers operating at the second clock frequency.

8. The system of claim 7, wherein: The plurality of data includes N data elements; and Further included is a modulo-N counter connected to a decoder, the decoder selecting from the plurality of output registers for each output from the alignment unit, the modulo-N counter operating at the second clock frequency.

9. The system of claim 1, wherein the system is part of a field programmable gate array (FPGA).

10. The system of claim 1, wherein the system is part of an application specific integrated circuit (ASIC).

11. A method comprising: receiving a single instruction and a plurality of data via an input interface operating at a first clock frequency; selecting from the plurality of data by a multiplexer operating at a second clock frequency higher than the first clock frequency; performing operations on the selected data by a functional unit operating at the second clock frequency; and Results from the functional unit are provided for each of the plurality of data through an output interface operating at the first clock frequency.

12. The method according to claim 11, wherein: The plurality of data includes N data elements; and The second clock frequency is N times the first clock frequency.

13. The method according to claim 12, further comprising: The selection among the plurality of data is controlled by a modulo-N counter.

14. The method according to claim 11, further comprising: receiving the output of the functional unit via an alignment unit operating at the second clock frequency; and The output of the functional unit is provided through the alignment unit and after a predetermined delay.

15. The method according to claim 14, wherein: The plurality of data includes N data elements; The functional unit includes X stages; The alignment unit includes Y stages, where Y=aN−X−3 and a is the lowest positive integer that avoids negative values ​​of Y.

16. The method of claim 14, wherein: The plurality of data includes N data elements; The functional unit includes X stages; The alignment unit comprises Y stages, where Y=aN−X−3 and a is greater than the lowest positive integer that avoids negative values ​​of Y.

17. The method of claim 14, further comprising: receiving outputs from the alignment unit via a plurality of output registers operating at the second clock frequency; and The output is provided to the output interface through the plurality of output registers.

18. The method of claim 17, wherein: The plurality of data includes N data elements; and Further comprising selecting from the plurality of output registers for each output from the alignment unit via a decoder coupled to a modulo-N counter.

19. The method of claim 11, wherein said receiving the single instruction through the input interface comprises receiving the single instruction using a field programmable gate array (FPGA) interface.

20. The method of claim 11, wherein said receiving the single instruction through the input interface comprises receiving the single instruction using an application specific integrated circuit (ASIC) interface.

Images