Shared column ADC for in-memory computing macros

Abstract

Various embodiments include systems, methods, architectures, mechanisms, devices and improvements thereof for scaling and summing analog signals represented by a plurality of weighted data provided by columns of in-memory compute bit cells within an NxM array of bit cells, the analog accumulation or sum of the analog signals of the weighted data representation is caused to provide a scaling result for further processing.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application is related to U.S. patent application serial number 17 / 221,399 filed on April 2, 2021, which is a continuation of U.S. patent application serial number 17 / 252,521, which claims the benefit of U.S. provisional patent application serial number 62 / 686,296 filed on June 18, 2018, U.S. provisional patent application serial number 62 / 702,629 filed on July 24, 2018, U.S. provisional patent application serial number 62 / 754,805 filed on November 2, 2018, and U.S. provisional patent application serial number 62 / 756,951 filed on November 7, 2018, the entire contents of which are incorporated herein by reference. Technical Field

[0003] The present invention relates to the field of in-memory computing and more particularly to the scaling, summing and conversion to digital data of analog signals representing weighted data such as provided by multiple parallel outputs of an array of in-memory computing units. Background Art

[0004] This section is intended to introduce the reader to various aspects of the technology that may be related to various aspects of the present invention described and / or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Therefore, it should be understood that these statements should be read in this light, and not as admissions of prior art.

[0005] Charge domain in-memory computing (IMC) has recently emerged as a robust and scalable way to perform in-memory computing. Here, computational operations within a memory bit cell provide their results in the form of charge, typically using voltage-to-charge conversion via capacitors. Thus, the bit cell circuit involves appropriate switching of local capacitors in a given bit cell, where the local capacitors are also appropriately coupled to other bit cell capacitors to form an aggregate computational result across the coupled bit cells. In-memory computing is well suited to implementing matrix-vector multiplications, where the matrix elements are stored in a memory array and the vector elements are broadcast over the memory array in a parallel manner.

[0006] Advantageously, the IMC computing architecture does not retrieve a single bit at a time as in conventional memory, but rather retrieves the results of calculations on many bits stored in the memory. This improves system energy efficiency and speed by reducing the number of data acquisition cycles required. Typically, the results of calculations are derived within a memory column, where: parallel input data is provided to the row, the calculation (e.g., multiplication) is performed by the memory bit cell in which the data is stored; and further calculations (e.g., accumulation) are performed on the column bit line to reduce a single output. Relative to a single bit access, the reduced output typically increases the dynamic range (i.e., the number of signal levels) that needs to be resolved. In addition, column calculations typically employ analog operations, which are suitable for calculations within limited memory circuits (e.g., bit cells, bit lines) and enable increased dynamic range. Each column requires an analog-to-digital converter (ADC) to convert the analog output of the column into a digital representation suitable for further processing within the architecture. Summary of the invention

[0007] Various deficiencies in the prior art are addressed by systems, methods, architectures, mechanisms, apparatus, and improvements thereto for performing scaling and summing of analog signals represented by multiple weighted data provided by columns of computational bit cells within a memory within an NxM array of bit cells, such that an analog accumulation or summation of the analog signals represented by the weighted data provides a scaled result for further processing.

[0008] Each bit cell provides a result of an operation at a corresponding output element (e.g., an output capacitor) during a measurement or evaluation phase, the result having a weight associated therewith that is based on the position of the bit cell in the row of bit cells (e.g., binary or other weighting from LSB to MSB of the result) such that each bit cell within a column of bit cells is associated with the same weight.

[0009] The analog signal (e.g., voltage or charge) associated with each column is scaled according to the corresponding column weight during the scaling phase, so that the summation or accumulation of the scaled analog signals (e.g., voltage or charge) provides an accumulated / summed analog signal including an analog domain representation of the calculation result in the memory, and then the accumulated / summed analog signal is analog-to-digital converted (ADC) and further processed.

[0010] The scaling phase may include disconnecting some of the bit cells within a column of bit cells based on their corresponding weighted values ​​so that when the charge levels of the remaining bit cells within each column (e.g., their output capacitors) are accumulated to provide an accumulated / summed analog signal, the charge contributed by each column is proportional to the weighted value of the column.

[0011] The scaling stage may include a signal divider, such as a charge divider or charge divider network, in which the total charge provided by the bit cells within a column of bit cells is divided to provide a charge level or analog signal representative thereof according to the corresponding weighted value of the column. This may be performed prior to the ADC so that the accumulated / summed analog signal presented to the ADC is appropriately scaled, or may be performed in conjunction with the sample and hold (S / H) of the ADC, such as by selective switching of the charge divider elements of the successive approximation ADC.

[0012] Some embodiments provide a device for scaling and summing multiple analog signals represented by weighted data, wherein each analog signal includes a voltage associated with a corresponding multiple coupled bit cell outputs within an in-memory computing (IMC) array of bit cells, the device comprising: a plurality of charge divider circuits, each charge divider circuit being configured to process the analog signals represented by the corresponding weighted data to produce an output signal having a capacitance value scaled according to a corresponding weighting value across a corresponding output capacitor; wherein, during a measurement phase of operation, the output capacitor of the signal divider circuit is coupled to a sample and hold circuit associated with an input of an analog-to-digital converter (ADC), the analog-to-digital converter being configured to generate a digital output representing the sum of the analog signals represented by the weighted data from the input.

[0013] Additional objectives, advantages and novel features of the present invention will be partially described in the following description, and will become partially obvious to those skilled in the art after reading the following, or may be learned through practice of the present invention. The objectives and advantages of the present invention can be realized and achieved by means of the tools and combinations particularly pointed out in the appended claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and, together with the general description of the invention given above and the detailed description of the embodiments given below, serve to explain the principles of the invention.

[0015] Figure 1 The typical structure of the in-memory computing architecture is depicted in a diagrammatic manner;

[0016] Figure 2 depicts a block diagram of a fully row / column parallel (1152 rows x 256 columns) array of multiplication bit cells (M-BC) of an in-memory computation (IMC) macro that enables N-bit (5-bit) input processing;

[0017] Figure 3 Describes the application Figure 2 The circuit architecture of the multiplication bit unit of the M-BC array;

[0018] FIG. 4A to FIG. 4BDiagrammatically depicting mechanisms for scaling and summing outputs of computation result indications illustrating various embodiments;

[0019] FIG. 4C to FIG. 4D Diagrammatically depicting mechanisms for scaling and summing outputs of computation result indications illustrating various embodiments;

[0020] Figure 5 An exemplary IMC column within an array of M-BCs is schematically depicted;

[0021] Figure 6 An example of binary weighted scaling within a bit cell array that aids in understanding the in-memory computing architecture of an embodiment is graphically depicted;

[0022] Figures 7 to 9 A circuit diagram depicting various embodiments of binary weighted scaling near or within an output ADC of an in-memory computing architecture; and

[0023] Fig.10 Circuit diagrams of various embodiments of binary-weighted current divider scaling circuits suitable for use with various embodiments are depicted.

[0024] It should be understood that the drawings are not necessarily drawn to scale, presenting slightly simplified representations of various features that illustrate the basic principles of the invention. Specific design features of the operational sequence as disclosed herein, including, for example, the specific size, orientation, position, and shape of the various illustrated components, will be determined to some extent by the specific intended application and use environment. Certain features of the illustrated embodiments have been enlarged or distorted relative to other features to facilitate visual display and clear understanding. In particular, thin features may be thickened, for example, for clarity or illustration purposes. DETAILED DESCRIPTION

[0025] The following description and drawings illustrate only the principles of the present invention. It will therefore be understood that a person skilled in the art will be able to design various arrangements which, although not explicitly described or shown herein, embody the principles of the present invention and are included within its scope. In addition, all examples described herein are primarily and explicitly intended to be used only for teaching purposes to help the reader understand the principles of the present invention and the concepts contributed by the inventors to the development of technology, and should be interpreted as not being limited to these specifically described examples and conditions. In addition, as used herein, the term "or" refers to a non-exclusive or, unless otherwise specified (e.g., "otherwise" or "or in an alternative"). Furthermore, the various embodiments described herein are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments.

[0026] Many novel teachings of the present application will be described with particular reference to currently preferred exemplary embodiments. However, it should be understood that such embodiments provide only a few examples of many advantageous uses of the novel teachings herein. Overall, the statements made in the specification of the present application do not necessarily limit any of the various claimed inventions. In addition, some statements may apply to some inventive features but not to other inventive features. Those skilled in the art and who have access to the teachings herein will appreciate that the present invention is also applicable to various other technical fields or embodiments.

[0027] Before describing the present invention in more detail, it should be understood that the present invention is not limited to the specific embodiments described, and thus may of course vary. It should also be understood that the terminology used herein is only for the purpose of describing specific embodiments, and is not intended to be restrictive, because the scope of the present invention is limited only by the appended claims.

[0028] Where a range of values ​​is provided, it is to be understood that each intervening value between the upper and lower limits of the range (to one-tenth of the unit of the lower limit, unless the context clearly indicates otherwise) and any other stated value or intermediate value within the stated range are encompassed within the present invention. The upper and lower limits of these smaller ranges may be independently included in smaller ranges and are also encompassed within the present invention, subject to any specifically excluded limitations in the stated ranges. Where the stated range includes one or both of the limitations, ranges excluding either or both of those included limitations are also encompassed within the present invention.

[0029] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the art to which the invention belongs. Although any methods and materials similar or equivalent to those described herein may also be used in the practice and testing of the present invention, a limited number of exemplary methods and materials are described herein. It must be noted that, as used herein and in the appended claims, the singular forms "a / an" and "the" include plural referents unless the context clearly indicates otherwise.

[0030] Various embodiments will be discussed in the context of an IMC computing architecture that obtains computational results stored on many bits in a memory, such as computational results derived within a memory column, wherein: parallel input data is provided to the rows, computations (e.g., multiplications) are performed by the memory bit cells in which the data is stored; and further computations (e.g., accumulations) are performed on the column bit lines to provide a corresponding analog output signal at each column bit line representing the computational result associated with the corresponding bit line, which is illustratively described herein as being provided as a charge level, but in alternative embodiments, the column analog output may include a current level or a voltage level.

[0031] Some of the various embodiments relate to IMC computing architectures, devices, methods, and portions thereof, which are configured to obtain computing results indicative of outputs of multiple parallel columns or bit lines in a manner that avoids using a separate analog-to-digital converter (ADC) for each column or bit line. That is, rather than converting an analog output signal associated with each bit line or column into a corresponding digital representation suitable for further processing within the IMC computing architecture, the various embodiments use the analog output signals associated with the bit lines or columns to perform some of the further processing, so as to reduce the number of ADCs required to implement the functionality of the IMC computing architecture while maintaining the accuracy of the analog output signals (i.e., reducing the effects of ADC quantization errors and other errors).

[0032] Figure 1 The typical structure of the in-memory computing architecture is depicted in a diagrammatic manner. Specifically, as depicted in the figure Figure 1 The in-memory computing architecture 100 consists of a memory array (which may be based on standard bit cells or modified bit cells), and the in-memory computing involves two additional "vertical" signal sets; namely, (1) input lines; and (2) accumulation lines. Figure 1 , it can be seen that a two-dimensional array of bit cells is depicted, wherein each of a plurality of in-memory computing channels 110-1 to 110-N (collectively referred to as in-memory computing channels 110) includes a respective column of bit cells, wherein each of the bit cells in a channel is associated with a common accumulation line and bit line (column) and a respective input line and word line (row). It should be noted that the columns and rows of signals are represented herein as being "perpendicular" relative to each other to simply indicate, e.g. Figure 1 The term "vertical" as used herein is not intended to convey any particular geometric relationship.

[0033] The input / bit and accumulation / bit set of signals may be physically combined with existing signals (e.g., word lines, bit lines) within the memory or may be separate. To implement a matrix-vector multiplication, the matrix elements are first loaded in the memory cells. Then, multiple input vector elements (possibly all) are applied at once via the input lines. This causes a local computation operation, usually in some form of multiplication, to occur at each of the memory bit cells. The result of the computation operation is then driven onto a shared accumulation line. In this way, the accumulation line represents the result of the computation on multiple bit cells activated by the input vector elements. This is in contrast to standard memory access, in which bit cells are accessed one at a time via bit lines activated by a single word line.

[0034] In-memory computation as described has several important properties. First, the computation is typically analog. This is because the constrained structure of memory and bit cells requires a richer computational model than can be achieved with a simple digital switch-based abstraction. Second, local operations on bit cells typically involve performing computations using a 1-b representation stored in the bit cell. This is because the bit cells in a standard memory array are not coupled to each other in any binary-weighted manner; any such coupling must be achieved through methods of accessing / reading out the bit cells from the periphery. In the following, extensions to the in-memory computation proposed in the present invention are described.

[0035] While in-memory computation has the potential to address matrix-vector multiplication in a way that conventional digital acceleration is insufficient, a typical computation pipeline will involve a series of other operations surrounding the matrix-vector multiplication. Typically, such operations can be adequately addressed by conventional digital acceleration; nevertheless, it may be valuable to place this acceleration hardware near the in-memory computation hardware in an appropriate architecture to address the parallel nature, high throughput (and therefore high communication bandwidth required to and from), and general computational patterns associated with in-memory computation. Because many of the surrounding operations will preferably be performed in the digital domain, analog-to-digital conversion via an ADC is included after each of the in-memory computation accumulation lines (which we therefore call in-memory computation channels). The main challenge is to integrate the ADC hardware in the spacing of each in-memory computation channel, but the appropriate layout approach taken in the present invention achieves this goal.

[0036] The introduction of ADC after each computational channel implements an efficient way to expand in-memory computation to support multi-bit matrix and vector elements via bit-parallel / bit-serial (BPBS) computations, respectively. Bit-parallel computations involve loading different matrix element bits into different in-memory computation columns. The ADC outputs from different columns are then appropriately shifted to represent the corresponding bit weights, and digital accumulation on a collection of columns is performed to obtain multi-bit matrix element computation results. On the other hand, bit-serial computations involve applying each bit of the vector element one at a time, storing the ADC output each time, and shifting the stored output appropriately, and then digitally accumulating with the next output corresponding to the subsequent input vector bit. This BPBS method of implementing a mix of analog and digital computations is efficient because it utilizes an efficient low-precision analog hierarchy (1-b) and an efficient high-precision digital hierarchy (multi-bit), while overcoming the access costs associated with conventional memory operations.

[0037] Figure 2 Depicted is a block diagram of a fully row / column parallel (1152 rows x 256 columns) array of multiplication bit cells (M-BC) of an in-memory computation (IMC) macro enabling N-bit (5-bit) input processing, according to an embodiment.

[0038] Figure 2 The exemplary IMC macro may be used to implement a structure such as the compute in memory array (CIMA) structure discussed previously, presented via a 28 nm manufacturing process, and configured to provide fully row / column parallel matrix-vector multiplication (MVM) for utilizing accurate analog computations based on metal edge (line) capacitors, for extending binary input vector elements to 5-bit (5-b) input vector elements, and for improving energy efficiency by approximately 16 times and throughput by 5 times compared to the IMC and CIMA embodiments discussed above.

[0039] It should be noted that Figures 2 to 3 Embodiments of the invention implement MVM operations that dominate compute-intensive and data-intensive AI workloads in a manner that reduces computational energy and data movement by orders of magnitude. This is achieved through efficient analog computation in bit cells, and therefore by accessing computation results (e.g., inner products) from memory instead of individual bits. However, doing so fundamentally creates a tradeoff between energy / throughput and SNR, where analog introduces computational noise and accessing computation results increases dynamic range (i.e., reduces SNR for a given readout architecture).

[0040] Advantageously, metal fringe capacitor based IMCs achieve very low noise from analog non-idealities and thus may have extremely high dynamic range.At least some of the embodiments utilize this precise capacitor based computational mechanism to reliably achieve improved dynamic range such as discussed herein.

[0041] Figure 2 A block diagram of an in-memory computation macro 200 is shown, which includes: a 1152 (row)×256 (column) array 210 of 10T SRAM multiplication bit cells (M-BC); peripheral devices for standard writing / reading therefrom (e.g., a bit line (BL) decoder 240 and 256 BL drivers 242-1 to 242-256, a word line (WL) decoder 250 and 1152 WL drivers 252-1 to 252-1152, and a control block 245 for controlling the decoders 240 / 250); peripheral devices for providing 5-bit input vector elements thereto (e.g., 1152 dynamic range doubling (DRD) DACs 220-1 to 220-1152 and corresponding controllers 225); peripheral devices for digitizing the computation results from each column (e.g., 256 8-bit SAR ADCs); 260-1 to 260-256) and column reset mechanisms 265-1 to 265-256 (e.g., CMOS switches configured to pull the output voltage level of the column computing line CL to the reset voltage V during the reset phase of operation RST, and during the evaluation phase of operation the voltage level of the column calculation line CL is allowed to reflect its corresponding calculation result).

[0042] The array 210 of 10T SRAM multiplication bit cells (M-BC) of the IMC macro 200 operates in a manner similar to that described above with respect to the various figures. In particular, while writes / reads are typically performed row by row, MVM operations are typically performed by applying the input vector elements corresponding to the neural network input activations to all or several rows at once. That is, each DRD-DAC 220 j In response to the corresponding 5-bit input vector element X j [4:0] and generate the corresponding differential output signal (IA j / IAb j ), the differential output signal is connected to each M-BC in the M-BC of the corresponding row j The weights stored at ij / Wb ij ) are multiplied by 1 bit and accumulated by charge redistribution on the M-BC capacitors on the computation line (CL) to form an inner product in each column, which is then digitized via the corresponding ADC 260 of each column. The operation of each 10TSRAM M-BC forming the array 210 will be described below with reference to Figure 3 Discuss in more detail.

[0043] Figure 3 The circuit architecture of a multiplication bit cell (M-BC) according to an embodiment is depicted and is suitable for implementing Figure 2 10T SRAM M-BC and similar array elements as described above with respect to the various figures. Figure 3 The M-BC 300 includes a high density structure for implementing weight storage and multiplication, thereby minimizing data broadcast distance and control signals in the context of an i-row, j-column array (such as a 1152 (row) × 256 (column) array 210 of 10TSRAM multiplication bit cells (M-BC)) implemented using such an M-BC.

[0044] The exemplary M-BC 300 includes a six-transistor bit cell portion 320 , a first switch SW1 , a second switch SW2 , a capacitor C, a word line (WL) 210 , a first bit line (BLj) 312 , a second bit line (BLbj) 314 , and a compute line (CL) 315 .

[0045] The six-transistor bit cell portion 320 is depicted as being located in the middle portion of the M-BC 300 and includes six transistors 304a to 304f. The 6-transistor bit cell portion 320 can be used to store and read and write data. In one example, the 6-transistor bit cell portion 320 stores filter weights. In some examples, data is written to the M-BC 300 via a word line (WL) 310, a first bit line (BL) 312, and a second bit line (BLb) 314.

[0046] The multiplication bit cell 300 includes a first CMOS switch SW1 and a second CMOS switch SW2. The first switch SW1 is depicted as being activated by a first activation signal A (A ij ) such that when closed, SW1 couples one of the received differential output signals (illustrated as IA) provided by the DRD-DAC 220 to the first terminal of the capacitor C. The second switch SW2 is depicted as being activated by a second activation signal Ab (Ab ij ) is controlled so that when closed, SW2 couples the other of the received differential output signals of the corresponding DRD-DAC 220 (illustrated as IAb) to the second terminal of capacitor C. The second terminal of capacitor C is connected to the calculation line (CL). It should be noted that in various other embodiments, the input signals provided to switches SW1 and SW2 may include fixed voltages (e.g., V dd ), ground, or some other voltage level.

[0047] The M-BC 300 including the first SW1 switch and the second SW2 switch can perform calculations on the data stored in the 6-transistor bit cell portion 320. The result of the calculation is driven as a charge on the capacitor C. According to various embodiments, the capacitor C can be positioned above the bit cell 300 and does not utilize additional area on the circuit. In some embodiments, the logic value V is driven on the capacitor C. dd In other embodiments, the voltage driven on capacitor C may include a positive voltage or a negative voltage depending on the operation of switches SW1 and SW2 and the output voltage level generated by the corresponding DRD-DAC 220 .

[0048] Thus, the charge stored on capacitor C (as a function of the drive voltage) is highly stable because the capacitor C value itself is highly stable and the drive voltage is highly stable (e.g., driven to a supply voltage or driven to ground). In some instances, capacitor C is a metal oxide metal (MOM) finger capacitor, and in some instances, capacitor C is a 1.2fF MOM capacitor. MOM capacitors have very well matched temperature and process characteristics and therefore have highly linear and stable computing operations. It should be noted that other types of logic functions can be implemented using the M-BC by changing the connection and / or operation of transistor 304 and / or switches SW1 and SW2 during the reset and evaluation phases of the M-BC operation.

[0049] In various implementations, the 6-transistor bit cell portion 320 is implemented using a different number of transistors and may have a different architecture. In some examples, the bit cell portion 320 may be SRAM, DRAM, MRAM, or RRAM.

[0050] Improved IMC accumulation and scaling of M-BC output

[0051] As mentioned above Figure 2 As depicted, the N=5 (5-bit) input processing in-memory computation (IMC) macro 200 considers a fully row / column parallel (1152 rows x 256 columns) array of multiplication bit cells (M-BC), such as those described above with reference to Figure 3 It should also be noted that the IMC macro 200 is depicted as using one 8-bit analog-to-digital converter (ADC) for each of the columns of connected M-BCs within the array 210. That is, the analog output signals provided by each of the exemplary 256 columns are individually converted by the corresponding 8-bit ADC to a corresponding 8-bit digital representation prior to further processing as discussed above and in the various related patent applications.

[0052] In particular, various embodiments will now be described in the context of an IMC architecture configured to combine the outputs of multiple parallel columns, such as where multiplication with multiple bits of data stored in bit cells is required, but the bit precision cannot be accommodated within a single bit cell. In this case, bit-parallel processing can be employed, where the most significant bit of the data is stored in a bit cell of one column, the next most significant bit of the data is stored in a bit cell of the next column, and so on, all the way to the least significant bit of the data (usually the bits of the stored data elements are all in the same row). In this case, each of the columns represents a component corresponding to a particular bit weighting of the computation output. Due to the linear nature of the multiply-accumulate operation, the total computation output can be derived by scaling each column output with an appropriate binary weighting factor and then summing the different scaled column output components. In general, the bit weightings of the data stored in different columns do not have to be binary; this is easily supported by applying a corresponding scaling factor (not necessarily binary weighted) to each column output.

[0053] The scaling and summing of the calculation results indicating the output of multiple parallel columns or bit lines can be performed before or after the ADC. If performed before the ADC, the scaling and summing operations must be applied to the corresponding analog signals, which can be voltage, current, charge, etc.

[0054] For example, in the context of an in-memory computation (IMC) array of bit cells configured to multiply two vectors (or a vector and a scalar), each element from V1 is multiplied by each element from V2, and the sums are accumulated to obtain a result. Multiple bits of vector V1 stored in memory are mapped to multiple columns, and the input bits of input vector V2 are sequentially provided to each column for iterations of multiplication and bit shifting. Each column (in this example) includes a corresponding total voltage or stored charge associated with a weighted result (e.g., the position of the bit within a multi-bit word), illustratively, a binary weighted result, such as a 4-bit binary word (MSB, MSB-1, MSB-2, LSB) representing the result of multiplying the 4-bit input vector V2 by each of the elements of the storage vector V1.

[0055] Rather than performing a bit shift in the digital domain after A / D conversion of the columns to resolve the multiplication result (e.g., the result of multiplying all input vector elements by all stored vector elements), various embodiments provide an analog domain scaling of the total voltage or stored charge associated with each column according to its column weight or scaling factor (e.g., the position of the bit), accumulation of the scaled voltage / charge of each column to provide an analog representation of the multiplication result (e.g., an analog voltage / charge level representing the result of multiplying each element of the 4-bit input vector V2 by the stored vector V1), which accumulated voltage / charge levels are then A / D converted to provide a digital representation of the final multiplication result. For example, for a 4-bit input vector, rather than performing a 4-cycle bit-parallel bit-serial operation, 4 bits are represented with analog levels and only one cycle is required.

[0056] FIG. 4A to FIG. 4B A mechanism for scaling and summing the outputs of computational result indications illustrating various embodiments is depicted diagrammatically.

[0057] Specifically, each of the mechanisms is described as scaling and summing four calculation result indicating outputs, wherein each output represents a corresponding one of four columns or bit lines, which represent voltage levels associated with charges stored on corresponding columns of connected bit cell output capacitors, the voltage levels representing corresponding weighted portions of the accumulated results, such as binary weighted portions of the accumulated results. As shown, four columns b, b+1, b+2, b+3 represent binary weighted data of the accumulated 4-bit calculation results, wherein the most significant bit (MSB) is represented by column b, and the least significant bit (LSB) is represented by column b+3.

[0058] like FIG. 4A to FIG. 4B As depicted, and as generally described herein, each of the four IMC columns (IMCb through IMCb+3) provides a respective voltage signal or voltage level stored across a respective plurality of bit cell output capacitors forming the column and represents a respective binary-weighted portion of the accumulation result.

[0059] In various embodiments, instead of voltage signals / levels, each of the four IMC columns (IMCb to IMCb+3) may provide a current signal / level or some other type of signal / level to represent a respective binary-weighted portion of the accumulated result of each IMC column (e.g., a signal such as a current or voltage signal provided by a buffer circuit or by a resistor or transistor-based voltage or charge divider circuit instead of an IMC output capacitor and / or a capacitor-based voltage or charge divider circuit, etc.). Furthermore, in addition to using binary weighting and / or scaling, other embodiments may use other types of weighting and / or scaling depending on the application, the components selected for the IMC, and / or other factors. Thus, various embodiments provide a mechanism to selectively attenuate or amplify a weighted signal (or whatever type is used) based on a weighting factor to provide, after summation, a total signal level (voltage level, current level, charge level, etc.) representing the accumulated result. Figure 4A The mechanism envisages scaling and summing of the accumulated weighted parts of the calculation results before ADC processing.

[0060] like Figure 4A As depicted, and as generally described herein, each of the four IMC columns (IMCb to IMCb+3) provides a respective voltage signal or voltage level stored across a respective plurality of bit cell output capacitors forming the column and represents a respective binary weighted portion of the accumulation result. These voltage signals / levels are scaled to reflect their respective binary weights relative to each other. Specifically, the LSB column (b+3) is multiplied by a scaling factor of 2. 0 = 1, multiply the next column (b+2) by the scaling factor 2 1 =2, multiply the next column (b+1) by the scaling factor 2 2 =4, and multiply the last column (b) by a scaling factor of 2 3 = 8. The scaled voltage levels are then added to provide a voltage level representing the accumulation result, which is converted to a digital representation by the ADC converter.

[0061] Figure 4B The mechanism of the invention envisions scaling and summing the accumulated weighted parts of the calculation results in combination with ADC processing. Specifically, the reference is implemented by modifying various operating parameters of the ADC. Figure 4A The scaling and summing functions are discussed in more detail below.

[0062] It should be noted that although FIG. 4A to FIG. 4BThe case of combining four columns before or within the ADC is shown, but any number of columns may be combined in this manner in general. Furthermore, this scaling and summing before / within the ADC may be combined with scaling and summing on any number of outputs after the ADC; this involves applying digital scaling factors (which for binary weighting simplifies to bitwise shifting) and summing in the digital domain. This enables quantization error effects to be optimally managed, in addition to optimizing implementation practicality, as described below.

[0063] FIG. 4C to FIG. 4D The mechanism for scaling and summing the outputs of the calculation result indications for illustrating various embodiments is depicted in a diagrammatic manner. FIG. 4A to FIG. 4B Discussions usually apply to FIG. 4C to FIG. 4D It should be noted that FIG. 4C to FIG. 4D A scaling function is envisioned where the LSB column (b+3) is multiplied by a scaling factor of 1 / 2 0 , multiply the next column (b+2) by the scaling factor 1 / 2 1 , multiply the next column (b+1) by the scaling factor 1 / 2 2 , and multiply the last column (b) by a scaling factor of 1 / 2 3 The scaled voltage levels are then summed to provide a voltage level representing the accumulated result, which is converted to a digital representation by the ADC converter.

[0064] Capacitor-based analog scaling and summing

[0065] Figure 5 An exemplary IMC column within an array of M-BCs is depicted schematically. Figure 5 As shown, each of the columns of M-BC 300 (1 to N) performs input (IA1 / IAb1 to IA N / IAb N ) and weighted value (W b,1 To W b,N ) to provide a corresponding result as an output voltage stored on a corresponding output capacitor, which can be selectively coupled to an output column line CL b In particular, Figure 5The use of switched capacitors is depicted, whereby a column accumulation (reduction) operation is performed via charge redistribution across capacitors in a particular column. In essence, the individual bit cell capacitors form branches of a signal divider circuit (such as a voltage / charge divider circuit), causing the output voltage (i.e., the node coupling all capacitors) to settle to an average value across the voltage / charge divider input (i.e., the driven side of the branch). This average value provides a scaled / normalized version of the accumulation, where the scaling factor is set by the total capacitance of the charge distribution (i.e., V=Q / C). Thus, scaling and summing of column output voltages can be achieved by setting the capacitances involved and then shorting the column capacitances involved across the columns together.

[0066] According to various embodiments, capacitor-based analog scaling and summing may be accomplished via several methods, as will be discussed below; illustratively, (1) setting and shorting the column capacitance, and (2) sampling the column voltage on the auxiliary capacitance and then setting and shorting the auxiliary capacitance (where the auxiliary capacitance may be combined with an ADC sample-and-hold circuit).

[0067] Setting and shorting the column capacitors

[0068] Capacitor-based IMCs typically involve two phases: (1) reset, in which the charge on all capacitors is reset by shorting the coupling nodes of the capacitors to a specific reference voltage; and (2) evaluation, in which the coupling nodes of the capacitors are unshorted from the reference voltage and the input branches of a signal divider circuit, such as a voltage / charge divider circuit, are driven (through a bit cell). Thereafter, the ADC can sample each column output voltage for subsequent digitization.

[0069] For analog scaling and shorting between columns before the ADC, an additional phase can be added, referred to herein as scaling. After the column output voltages are stable, the coupling on all column capacitors can be disconnected to form a proportional amount of remaining capacitance on the columns to be shorted together. The shorting capacitance between columns can then be sampled by the ADC for digitization. As an example, this approach can be used in Figure 6 This is depicted in the case of binary weighted scaling.

[0070] Figure 6 An example of binary weighted scaling within a bit cell array is depicted in a diagrammatic manner to aid in understanding the in-memory computing architecture of an embodiment. Specifically, Figure 6 Depicts eight IMC rows (R1 to R8) of multiplication bit cells multiplied by four IMC columns (CL b To CL b+3 ) of the bit cell output capacitors, each of the IMC columns is connected via a corresponding switch (S b To S b+3) is selectively coupled to the input of the ADC. The array also includes a CL between rows R7 and R8 b+3 , CL between rows R6 and R7 b+2 and CL between rows R4 and R5 b+1 Additional switches S are introduced into the columns at these locations to disconnect / enable coupling of some column capacitors at different points in the column.

[0071] During each of the reset phase of operation and the evaluation phase of operation, the additional switch S is closed, thereby enabling all the capacitances in a column to be coupled. During the scaling phase of operation, the additional switch S is opened, and the remaining column capacitances are coupled by the column switch S b To S b+3 shorted together and the resulting signal is provided to the ADC.

[0072] It should be noted that in the case where the capacitance C of each output capacitor is substantially the same, the use of additional switches S results in a greater charge contribution to the subsequent signal voltage for those columns having more output capacitors. Thus, a column CL having eight bit cell capacitors b is effectively weighted as a column CL with four bit cell capacitors b+1 , a column with four bit cell capacitors is effectively weighted as a column with two bit cell capacitors CL b+2 The column with two bit cell capacitors is effectively weighted as a column with one bit cell capacitor CL b+3 twice as much.

[0073] The resulting voltage signal applied to the ADC represents a proportional cumulative output signal taking into account the charge weighting due to the use of the additional switch S, and may be digitized directly by the ADC to provide a digital representation of the cumulative output signal.

[0074] The inventors have noted that the introduction of switches (whether for disconnecting column-capacitor coupling or for shorting column capacitance) adds parasitic capacitances, and these parasitic capacitances should also be appropriately weighted (binary or otherwise) for accurate scaling and summing across the columns. Thus, in various embodiments, the parasitic bias switch S PO Or other structures are added to the array to balance the total switch-related parasitic capacitance in the column.

[0075] Parasitic bias switch S PO Or other structures may include switches that are either active or inactive. For example, for each additional switch S in a column that is active as described above, a similar active or inactive (e.g., always closed) switch may be included in a substrate (e.g., a VLSI substrate) used to form the bit cell array.

[0076] Thus, in some embodiments using binary weighting, in addition to the additional switches S in one column operating to achieve weighting as described herein, one or more other columns have parasitic bias switches S of similar structure formed at corresponding locations. PO , thereby avoiding capacitance differences between columns. This technique can also be used to implement embodiments with weighting schemes other than binary weighting. PO The number and location of the switches may vary depending on manufacturing technology and other factors; all that matters is the parasitic bias switch S PO It is formed in such a way as to balance or bias the parasitic capacitances imparted to the circuit by the additional switch S, so as to avoid the associated proportional errors as much as possible.

[0077] Sampling, setting and shorting auxiliary capacitors

[0078] In other embodiments, rather than using the same capacitors for column calculations and for scaling operations across columns, the voltage of each set of column capacitors is first sampled via auxiliary sampling capacitors within a signal divider circuit such as a voltage / charge divider circuit (i.e., a capacitor network configured for charge sharing / sampling), where the auxiliary sampling capacitors associated with a column have values ​​selected to produce a scaled output appropriate for that column. The sampling capacitors may include additional capacitors formed for each column, sample-and-hold capacitors of the ADC itself (integrated within the ADC or separate from the ADC), or some other capacitor.

[0079] In these embodiments, a signal associated with a particular column is sampled via an auxiliary capacitor of a charge divider circuit associated with that column, which capacitor may be selectively coupled to the column or the divider circuit.

[0080] Various embodiments contemplate processing the signal associated with each column via a weighted input ADC; that is, an ADC having multiple inputs where each of those inputs may be weighted and the resulting weighted signals summed for ADC processing to provide a digital output signal.

[0081] Figures 7 to 9 Circuit diagrams depicting various embodiments of binary weighted scaling near or within the output ADC of an in-memory computing architecture. It should be noted that while Figures 7 to 9 The embodiments of the present invention are generally depicted and described as processing a voltage signal provided by the charge stored across the bit cell output capacitor as described above, but these embodiments may also be used to process other types of signals (e.g., voltage, current, etc.), such as those described above with reference to FIG. 4A to FIG. 4B discussed.

[0082] Figure 7 Circuit diagrams are depicted to aid in understanding various embodiments. Specifically, Figure 7 Circuit 700 contemplates a plurality of capacitive circuits (e.g., four), each capacitive circuit being operable to share a portion of the charge stored across a corresponding plurality of bit cell output capacitors with a corresponding sampling or auxiliary capacitor to provide a corresponding voltage output signal therein representing a corresponding weighted portion of the accumulated result, wherein the voltage sampled across the sampling or auxiliary capacitor is provided to an ADC for further processing.

[0083] It must be noted that the sampling operation on the auxiliary capacitor is achieved through charge sharing operation. Therefore, sampling causes the sampled voltage to be proportional to C COL / (C COL +C AUX ) is scaled by a factor, where C COL is the total column capacitance, and C AUX is the auxiliary sampling capacitor. This ensures that C COL and C AUX matches well across columns, and C AUX It is important to discharge the C AUX The decomposition into binary-weighted components allows the appropriate binary-weighted components to be subsequently shorted together for accurate scaling and summing.

[0084] In particular, the capacitance of the charge divider circuit (and more generally the signal divider circuit) is important, where in the case of a charge sharing event, the shared capacitance is a scaling mechanism (binary weighted or otherwise), such as sharing the charge stored across multiple bit cell output capacitors with corresponding capacitor voltage / charge divider circuits. In this case, using load balancing capacitors such as Figures 7 to 9 as shown) to ensure that each capacitor charge divider circuit has substantially the same capacitance.

[0085] In addition to charge sharing, in various embodiments, scaling is achieved by other means alone or in combination. For example, in various embodiments, scaling of the analog signals of each weighted data representation may be achieved via charge, voltage, current, or impedance scaling techniques (e.g., using weighted or binary weighted capacitor divider networks, resistor divider networks, etc.), depending on the nature of the analog signals to be scaled. As most generally described herein, various examples provide charge divider circuits based on capacitive charge sharing or redistribution to scale analog signals of charge-based or voltage-based weighted data representations.

[0086] In general, each of a plurality of weighted data representations of analog signals (e.g., column-weighted binary) is scaled so that the ratio of the analog signal contribution (charge, voltage, current, etc.) to the total signal level or cumulative signal level of the analog signals of all the various weighted data representations is proportional to the weight of the analog signal of that data representation (e.g., the weight associated with the column position of the analog signal of that data representation).

[0087] For example, if the bit cell computation output is provided by a resistive / conductive output impedance (rather than a capacitor), the scaling circuit may include a resistive scaling or signal dividing component, a transistor scaling or signal dividing component, or some other scaling or signal dividing component suitable for corresponding weighting / scaling of the charge level or the signal indicating the charge level (e.g., a voltage / charge divider circuit, a charge sharing network, etc.) In this case, there is no need to use a load balancing capacitor because a stable signal does not depend on a capacitive load.

[0088] In this binary weighted example, the b The sampling signal is given to column CL b+1 The weight is twice the weight of CL b+1 Assigned to column CL b+2 The weight is twice the weight of CL b+2 Assigned to column CL b+3 The weight of is twice the weight of . In this way, by observing Figure 7 It can be seen that the various switches are controlled so that the capacitance of the voltage / charge divider circuit of each column is the same (ie, C), but the sampling or auxiliary capacitor of each voltage / charge divider circuit is different. Specifically, column CL b The sampling or auxiliary capacitor is C(C / 2+C / 2), and CL b+1 The sampling or auxiliary capacitor is C / 2, CL b+2 The sampling or auxiliary capacitor is C / 4, and the column CL b+3 The sampling or auxiliary capacitors of the columns are C / 8. The signal present on each of the sampling or auxiliary capacitors represents a corresponding proportional portion of the accumulation result, and by connecting each sampling or auxiliary capacitor of the column together and providing the signal to the ADC, a digital representation of the accumulation result can be generated. As shown, the capacitance of the voltage / charge divider circuit of each column is the same, so that the error from the charge sharing event is balanced across the voltage / charge divider circuit, thereby avoiding any relative error between the voltage / charge divider circuits.

[0089] Figure 8 Circuit diagrams are depicted to aid in understanding various embodiments. Specifically, Figures 8 to 9 Depicted Figure 7A voltage / charge divider circuit is provided in which the voltages sampled across all sampling or auxiliary capacitors are combined into a sample-and-hold (SH) of a successive approximation register (SAR) ADC during a charge sharing event (e.g., during a measurement or evaluation phase of operation) where the SH also serves as a feedback digital-to-analog converter (DAC). This approach enables a compact layout, which is required for an IMC readout ADC.

[0090] It should be noted that Figures 8 to 9 An 8-bit ADC receiving an accumulated input voltage associated with only four weighted input signals is depicted. If the eight weighted input signals are processed by the 8-bit ADC, each of the eight weighted input signals will initially be scaled by a corresponding divider circuit. In the case of using a capacitor divider circuit, the capacitance of each of the additional four (e.g., LSB) voltage / charge divider circuits will also be the same as the initial four (e.g., MSB) voltage / charge divider circuits, and the corresponding sampling or auxiliary capacitors will be scaled accordingly (e.g., C / 16, C / 32, C / 64, and C / 128 assuming that the four columns represent the next four LSB values ​​of the accumulated result).

[0091] exist Figures 8 to 9 In the context of an S / H SAR ADC, the S / H is integrated into the ADC. The SAR ADC includes a feedback circuit in which a digital-to-analog converter (DAC) is adjusted via different digital input signals provided via the SAR logic to ultimately produce a DAC output voltage corresponding to the analog input voltage provided to the ADC, thereby determining a digital word or bit representing the analog input voltage of the ADC.

[0092] The analog input voltage is sampled at the bottom plate of each sampling capacitor of each voltage / charge divider circuit (i.e., the capacitors denoted as C, C / 2, C / 4, and C / 8). A voltage associated with the feedback code of the DAC is then applied successively to the other plate of the capacitor, and in doing so, causes a binary weighted signal to be generated therein for comparison purposes (i.e., for determining the ADC output value).

[0093] For example, Figure 8 The circuit 800 envisions dividing the ADC SH / DAC into four segments for taking inputs from four IMC columns. Each of the four segments has equal capacitance to ensure that relative sampling errors / scaling are not significant. Each of the four segments is then further divided into a portion that is digitized by the ADC and a portion that is not processed. The portion that is further processed corresponds to the binary weighted capacitance across the columns. Each column output is sampled on one side of each segment, and only the portion that is further processed is then coupled together on the other side. The rest remains uncoupled on the other side (kept short at the reference voltage) and is then discharged before future sampling.

[0094] Coupling the segment portions in this manner results in the scaling and summing of the column outputs within the ADC SH / DAC. SAR digitization is then performed in a standard manner to form the final digital output code. As an example, the scaled and summed charge is sampled at one end of the SH / DAC, while the other end is driven by a feedback digital control signal. This causes the feedback digital control signal to form a corresponding negative voltage offset on the signal fed to the comparator. When the negative voltage offset cancels the voltage generated by the sampled charge (i.e., by returning the comparator voltage to a fixed reference), the final digital output code is obtained. Other forms of SAR digitization may also be used, such as separating the DAC from the S / H.

[0095] Fig.10 Depicts a circuit diagram of various embodiments of binary weighted current divider scaling circuits suitable for various embodiments. It can be seen that the MSB column CL b The weighted data represents the analog signal which is effectively weighted as columns CL b+1 Twice, column CL b+1 is effectively weighted as column CL b+2 Twice, column CL b+2 is effectively weighted as column CL b+3 twice as much.

[0096] Benefits and limitations

[0097] The above described embodiments utilize a method of scaling and summing before the ADC, and have the major benefit of sharing the ADC across summing columns in the context of in-memory computing embodiments. This allows the ADC energy and area consumption to be amortized.

[0098] The method based on setting and shorting the column capacitors has the particular advantage that no additional auxiliary capacitors are required. In case the auxiliary capacitors are combined with the ADC SH, the benefit is that the complexity of the ADC is not increased (a standard ADC can be used).

[0099] An approach based on sampling auxiliary capacitors (possibly integrated with the ADC SH and DAC) has the benefit of not requiring an additional scaling stage (after reset and evaluation) and does not increase the complexity of the IMC architecture (e.g. due to the addition of switches to switch on / off the coupling between the groups of bit cell capacitors).

[0100] In general, the limitation of analog scale-and-sum is that the total dynamic range of the signal to be digitized by the ADC is increased. The ADC then quantizes the signal to a specific resolution, so quantization error is introduced. The quantization error is mitigated relative to post-ADC scale-and-sum, where each column output results in quantization (i.e., the analog residual cannot be recovered after each column output is digitized, while pre-ADC scale-and-sum results in one quantization event); however, post-ADC scale-and-sum has a net benefit on quantization error due to the low energy / area cost of digital bit growth. The quantization error of pre-ADC scale-and-sum can be reduced by increasing the ADC resolution, but at the expense of the energy / area overhead of the ADC.

[0101] Although various embodiments are described primarily in the context of binary weighted scaling factors, these embodiments are applicable to any analog scaling of column values. That is, although the present disclosure primarily describes an architecture where columns feeding a shared ADC have binary weighted scaling factors, it should be understood that any scaling factors may be used.

[0102] Furthermore, it should be understood that the scaling factors may be configurable. It should be noted that a major benefit of non-binary weighted scaling factors is that alternative numeric formats (i.e., non-binary integers) may be used for the matrix weights stored in the memory cells. This is valuable because quantized neural networks may utilize alternative numeric formats (e.g., where bit positions represent idempotence of 1.5, 4, rather than 2) to optimize how to manage weight dynamic range tradeoffs.

[0103] Furthermore, the total charge signal can be increased by an equal scaling factor relative to a single column calculation. In this way, mitigation of the effects of different charging noise sources can be achieved.

[0104] Furthermore, the configurability of the scaling factor enables the above two features on a dynamic basis, where, for example, different in-memory calculations scheduled during execution time can be optimized accordingly. This configurability requires setting configurable capacitors between the columns, which can be achieved using capacitive digital-to-analog converters (DACs) coupled to the outputs of the different columns, thereby providing digital configuration control.

[0105] Various embodiments contemplate compensating for capacitance mismatches across columns. Specifically, where column scaling is determined by the relative ratio of capacitance across columns, deviations in the relative ratio due to parasitic capacitance can lead to calculation errors. In various embodiments, this is overcome via any of a variety of practical methods discussed herein.

[0106] For example, in some embodiments, critical capacitance is matched by careful layout and parasitic capacitance estimation. In particular, layout features that affect parasitic capacitance are matched within the array and the array periphery, such as on a substrate or layer of a very large scale integrated (VLSI) circuit during fabrication.

[0107] In the case where the column capacitances are set and shorted, this should include consideration of the column switches used to make / break the coupling connection between the column capacitances. This can be achieved, for example, by introducing virtual MOSFET switches (which can be kept statically on or off) to match the parasitics of the real MOSFET switches in other columns, or by adjusting the geometry of the MOSFET switches so that they remain proportionally scaled across the columns.

[0108] In the case of sampling, setting and shorting the auxiliary capacitors, this can be achieved by matching the layout of the connections from the columns to the auxiliary capacitors (and surrounding features) as well as matching the layout of the auxiliary capacitors themselves.

[0109] Additionally, a capacitance DAC can be coupled to each column output to implement a trimmable capacitive load that introduces a linearly adjustable voltage attenuation to compensate for mismatches in parasitic capacitance.

[0110] As described herein, some of the various embodiments relate to IMC computing architectures, devices, methods, and portions thereof, which are configured to obtain computational results indicative of outputs of multiple parallel columns or bit lines in a manner that avoids using a separate analog-to-digital converter (ADC) for each column or bit line. That is, rather than converting an analog output signal associated with each bit line or column into a corresponding digital representation suitable for further processing within the IMC computing architecture, the various embodiments use the analog output signals associated with the bit lines or columns to perform some of the further processing, so as to reduce the number of ADCs required to implement the functionality of the IMC computing architecture while maintaining the accuracy of the analog output signals (i.e., reducing the effects of ADC quantization errors and other errors).

[0111] Various modifications may be made to the systems, methods, devices, mechanisms, techniques, and portions thereof described herein with respect to the various figures, and such modifications are contemplated to be within the scope of the present invention. For example, although a particular order of steps or arrangement of functional elements is presented in the various embodiments described herein, various other orders / arrangements of steps or functional elements may be utilized within the context of the various embodiments. Furthermore, although modifications to the embodiments may be discussed individually, the various embodiments may use multiple modifications simultaneously or sequentially, combined modifications, etc.

[0112] Although specific systems, devices, methods, mechanisms, etc. have been disclosed as discussed above, it will be appreciated by those skilled in the art that more modifications other than those already described are possible without departing from the inventive concepts herein. Therefore, the subject matter of the present invention is not limited except in the spirit of the present disclosure. In addition, when interpreting the present disclosure, all terms should be interpreted in the broadest possible manner consistent with the context. In particular, the terms "comprises" and "comprising" should be interpreted as referring to elements, components, or steps in a non-exclusive manner, thereby indicating that the mentioned elements, components, or steps may exist, or be used, or be combined with other elements, components, or steps not explicitly mentioned. In addition, the references listed herein are also part of the present application and are incorporated by reference in their entirety as if fully stated herein.

[0113] Although various embodiments incorporating the teachings of the present invention have been shown and described in detail herein, those skilled in the art can easily design many other varied embodiments that still incorporate these teachings. Therefore, although the foregoing is directed to various embodiments of the present invention, other and further embodiments of the present invention can be designed without departing from the basic scope of the present invention.

Claims

1. An apparatus for scaling and summing a plurality of weighted data-representing analog signals, wherein each analog signal comprises voltages associated with a corresponding plurality of coupled bit cell outputs within an in-memory computation (IMC) array of bit cells, the apparatus comprising: a plurality of signal divider circuits, each signal divider circuit configured to process an analog signal represented by a corresponding weighted data to produce an output signal having a value scaled according to a corresponding weighting value; Wherein, during a measurement phase of operation, the signal divider circuit output signal is coupled to an input of an analog-to-digital converter (ADC) configured to generate a digital output from the input representing a sum of analog signals represented by the weighted data.

2. The apparatus of claim 1, wherein the signal divider circuit comprises a voltage divider circuit.

3. The apparatus according to claim 1, wherein: Each bit cell output is provided via a corresponding output capacitor; and The signal divider circuit includes a charge divider circuit.

4. The apparatus according to claim 3, wherein: Each analog signal represents charge stored across a corresponding plurality of coupled bitcell output capacitors within the IMC array of bitcells; and Each of the plurality of signal divider circuits has a substantially similar total capacitance and a corresponding output capacitor having a capacitance selected to provide a corresponding scaled output signal in response to transfer thereto of a portion of charge stored across the corresponding plurality of coupled bitcell output capacitors.

5. The apparatus of claim 2, wherein the signal divider circuit is integrated with a sample and hold circuit within the ADC.

6. The apparatus according to claim 1, wherein the analog signal comprises N analog signals to be binary-weighted, wherein N is an integer greater than 1, the apparatus comprising: The least significant bit (LSB) signal divider circuit has a total capacitance of C and a capacitance of C / 2. N-1 an output capacitor, the LSB signal divider circuit being configured to process an analog signal represented by LSB; as well as A most significant bit (MSB) signal divider circuit having a total capacitance of C and an output capacitor of C, the MSB signal divider circuit being configured to process an analog signal represented by the MSB.

7. The apparatus according to claim 1, comprising: an LSB+1 signal divider circuit having a total capacitance of C and an output capacitor of C / N, the LSB signal divider circuit being configured to process an analog signal represented by LSB+1; as well as A most significant bit (MSB) signal divider circuit has a total capacitance of C and an output capacitor of C / 2, the MSB signal divider circuit being configured to process an analog signal represented by the MSB.

8. The apparatus of claim 3 , wherein corresponding disconnect switches are provided in at least some of the columns of bit cells, the disconnect switches being used to disconnect a first portion of the column of bit cells from the remainder of the column of bit cells such that an analog signal provided by the remainder of the column of bit cells is scaled to a weight associated with the column.

9. The apparatus of claim 8, further comprising a plurality of switches configured to couple the remainder of the columns of bit cells to each other to thereby provide an analog signal representative of a weighted accumulation result.

10. An analog scaling and summing device for capacitor-based in-memory computing (IMC), wherein each bit cell in an NxM array of bit cells provides a voltage level associated with a respective portion of a weight of an IMC operation at a respective output capacitor, wherein columns of bit cell output capacitors storing voltage levels associated with the same weights are coupled together to provide analog signals representative of respective weighted data for the weights, the device comprising: a plurality of signal divider circuits, each signal divider circuit configured to process an analog signal represented by a respective weighted data of a respective column of bit cell output capacitors to produce an output signal across a respective output capacitor having a capacitance value scaled according to the respective weighted value; Wherein, during a measurement phase of operation, the output capacitor of the signal divider circuit is coupled to a sample and hold circuit associated with an input of an analog-to-digital converter (ADC), the analog-to-digital converter (ADC) being configured to generate a digital output from the input representing a sum of analog signals represented by the weighted data.

11. The apparatus of claim 10, wherein each column of the analog signal of the weighted data representation represents a corresponding binary-weighted data bit of a cumulative result of the IMC operation.

12. The apparatus of claim 11, wherein: During a reset phase of operation, the charge stored in each of the columns of bit cell output capacitors is substantially removed; During an evaluation phase of operation, the charge stored in each of the columns of bit cell output capacitors provides a corresponding contribution to the total charge of the respective column; and During the measurement phase of operation, each of the analog signals represented by the weighted data is scaled according to its weighting level to provide a weighted portion of the analog signal representing the cumulative result to be processed by the ADC.

13. An analog scaling and summing device for capacitor-based in-memory computing (IMC), wherein each bit cell in an NxM array of bit cells provides a voltage level associated with a respective portion of a weight of an IMC operation at a respective output capacitor, wherein columns of bit cell output capacitors storing voltage levels associated with the same weights are coupled together to provide analog signals representative of respective weighted data for the weights, the device comprising: a plurality of signal divider circuits, each signal divider circuit configured to process an analog signal represented by a respective weighted data to generate an output signal across a respective output capacitor selectively controlled by a successive approximation register (SAR) analog-to-digital converter (ADC); in During a reset phase of operation, the charge stored in each of the columns of bit cell output capacitors is substantially removed; During an evaluation phase of operation, the charge stored in each of the columns of bit cell output capacitors provides a corresponding contribution to the total charge of the respective column; and During a measurement phase of operation, switches within one or more of the columns of bit cell output capacitors are activated to disconnect at least a portion of the bit cell output capacitors, wherein the remainder of the bit cell output capacitors of each column have a total capacitance that reflects a weighted value of the column, wherein the remaining coupled capacitors in each column are coupled together and to an input of the ADC.

14. An apparatus for scaling and summing a plurality of weighted data-represented analog signals, wherein each weighted data-represented analog signal comprises an electronic voltage, current, or charge provided by a respective column of coupled bit cells within an in-memory computing (IMC) array of bit cells, the apparatus comprising: coupling at least some of the columns of bit cells having respective disconnect switches disposed therein for disconnecting a first portion of the column of bit cells from a remainder of the column of bit cells such that an analog signal provided by the remainder of the column of bit cells is scaled to a weight associated with the column; as well as A switch is configured to couple the remainder of the column of bit cells to each other to thereby provide an analog signal representative of the accumulation result.

15. The apparatus of claim 14, wherein: Each of the bit cells includes an output capacitor for storing a charge indicative of bit cell operation; and Each of the bit cell columns is associated with a corresponding data weight value.

16. The apparatus of claim 15, wherein each column is associated with a remainder of the bit cell output capacitors that is proportional to the weight of the column.

17. The apparatus of claim 15, further comprising a plurality of parasitic bias switches S configured to compensate for weighted parasitic capacitances of the disconnect switches. PO .

18. The apparatus of claim 15, wherein the analog signal comprises N binary-weighted analog signals, wherein N is an integer greater than 1, the apparatus comprising N columns of corresponding coupled bitcell output capacitors within the IMC array.

19. The apparatus of claim 15, wherein the weighted data representation of the analog signal comprises at least a most significant bit (MSB) and a least significant bit (LSB) binary weighted data representation of the analog signal.

20. The apparatus of claim 19, wherein the weighted data-represented analog signal further comprises at least one additional binary weighted data-represented analog signal.

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