Storage device

Abstract

Data held in a volatile memory cell may be stored in a resistance changing element without inserting a transistor of the volatile memory cell. The memory device includes: a volatile memory cell provided with a volatile memory node complementarily holding data and an access transistor connected between the volatile memory node and a bit line; and a non-volatile memory unit provided with a non-volatile memory node complementarily holding data, a first switch connected between the non-volatile memory node and the memory line, and a second switch connected between the non-volatile memory node and the volatile memory node. The first switch may be provided with a storage transistor that stores data held in the volatile storage node in the non-volatile storage node through the storage line, and the second switch may be provided with a recovery transistor that recovers data held in the non-volatile storage node in the volatile storage node.

Description

Technical Field

[0001] The present technology relates to a storage device, and more particularly, to a storage device in which a nonvolatile storage unit is provided in a volatile storage unit. Background Art

[0002] There is a nonvolatile (NV) static random access memory (SRAM) in which data is not lost even if a power failure or power failure occurs. As such an NVSRAM, a technique of inserting an N-channel transistor and a variable resistance element in series between a node and a bit line of the SRAM has been proposed (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2013-125567 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] However, with the above conventional technology, the N-channel transistor and the variable resistance element are inserted in series with the bit line of the SRAM. Therefore, when storing data in the variable resistance element, current flows through the variable resistance element via the transistor of the SRAM, which may increase the size of the transistor of the SRAM.

[0008] The present technology has been made in view of such circumstances, and aims to enable data held in a volatile memory cell to be stored in a variable resistance element without intervention of any transistor of the volatile memory cell.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and its first aspect is a storage device including: a volatile memory cell including a volatile memory node that complementarily holds data and an access transistor connected between the volatile memory node and a bit line; and a nonvolatile memory cell including a nonvolatile memory node that complementarily holds data, a first switch connected between the nonvolatile memory node and a memory line, and a second switch connected between the nonvolatile memory node and the volatile memory node. This brings about the effect of separating a path for storing data held in a volatile memory node to a nonvolatile memory node and a path for restoring data held in a nonvolatile memory node to a volatile memory node.

[0011] Furthermore, in the first aspect, the first switch may include a storage transistor that stores data held in a volatile storage node in a nonvolatile storage node via a storage line, and the second switch may include a recovery transistor that restores data held in the nonvolatile storage node to the volatile storage node. This brings about the effect of storing data held in a volatile storage node in a nonvolatile storage node through the first switch, and restoring data held in a nonvolatile storage node to a volatile storage node through the second switch.

[0012] Furthermore, in the first aspect, the volatile memory cell may be a static random access memory (SRAM), and the nonvolatile memory cell may be a resistive random access memory. This brings about the effect of adding a nonvolatile storage function to the SRAM.

[0013] Furthermore, in the first aspect, the volatile memory cell may include a trigger having a volatile memory node, the nonvolatile memory cell may include a variable resistance element whose resistance changes based on an applied voltage, and one end of a storage transistor and one end of a recovery transistor may be connected to one end of the variable resistance element. This brings about the effect of performing writing and reading of the volatile memory node via a bit line, performing storage to the volatile memory node via a storage line, and performing recovery to the volatile memory node without the intervention of the bit line and the storage line.

[0014] In addition, in the first aspect, the trigger may include an inverter pair, the output terminals of the inverter pair are connected to each other's input terminals, the connection point between the output terminals and the input terminals of the inverter pair is used as a volatile storage node, and the connection point between the variable resistance element, the storage transistor and the recovery transistor is used as a non-volatile storage node. This brings about the effect of storing data held in the volatile storage node to the non-volatile storage node and restoring data stored in the non-volatile storage node to the volatile storage node.

[0015] Furthermore, in the first aspect, data held in a volatile storage node can be sequentially stored in a nonvolatile storage node via a storage line and a storage transistor. This brings about the effect of storing data held in a volatile storage node in a nonvolatile storage node without intervening any bit line.

[0016] Furthermore, in the first aspect, data held in the nonvolatile storage node can be restored to the volatile storage node via the recovery transistor. This brings about the effect of restoring the data held in the nonvolatile storage node to the volatile storage node without intervention of any bit line and any storage line.

[0017] In addition, in the first aspect, the storage device may further include: a word line that turns on and off the access transistor; a restore selection line that turns on and off the restore transistor; a storage selection line that turns on and off the storage transistor; and a non-volatile (NV) control line connected to the variable resistance element. This brings about the effect of separating the volatile storage node and the non-volatile storage node during storage and connecting the volatile storage node and the non-volatile storage node during recovery.

[0018] In addition, in the first aspect, the storage device may further include: a sense amplifier that detects data read from the volatile storage cell; and an NV control unit that controls the potential of the storage line and the potential of the NV control line based on the data detected by the sense amplifier, and stores the data held in the volatile storage node in the nonvolatile storage node via the storage transistor. This brings about the effect of storing the data held in the volatile storage cell in the nonvolatile storage cell in a state where the volatile storage node and the nonvolatile storage node are separated.

[0019] Furthermore, in the first aspect, when the data held in the volatile storage node is stored in the nonvolatile storage node, the NV control unit may complementarily set the potential of the storage line depending on the data detected by the sense amplifier, and make the potential of the control line transition between a high level and a low level. This brings about the effect of complementarily storing data in the nonvolatile storage node according to the current flowing in the opposite direction in the variable resistance element.

[0020] Furthermore, in the first aspect, the NV control unit can drive the nonvolatile memory cell based on a voltage higher than the driving voltage of the volatile memory cell. This brings about the effect of coping with the high voltage driving of the nonvolatile memory cell while coping with the low voltage driving of the volatile memory cell.

[0021] In addition, in the first aspect, the memory device may further include a power gating transistor that performs power gating of the inverter. This brings about the effect of restoring the data held in the nonvolatile memory node to the volatile memory node.

[0022] In addition, in the first aspect, the driving force of the storage transistor can be greater than the driving force of the transistor to be used in the inverter, the driving force of the access transistor, and the driving force of the recovery transistor. This brings about the effect of adding a non-volatile storage function to the volatile memory cell without increasing the size of the volatile memory cell.

[0023] In addition, in the first aspect, the storage device may include a memory cell in which a volatile memory cell and a nonvolatile memory cell are provided, and the memory cells may be arranged in a matrix in the row direction and the column direction. This brings about the effect of adding a nonvolatile storage function to each memory cell having a volatile memory cell.

[0024] In addition, in the first aspect, each of the word line, the restore selection line, and the storage selection line can extend in the row direction, and each of the bit line, the storage line, and the NV control line can extend in the column direction. This brings about the effect of selecting a memory cell for performing reading, writing, storage, and restoration based on the address of the specified memory cell.

[0025] Furthermore, in the first aspect, the volatile memory cell may be a dual-port SRAM. This brings about the effect of enabling two parallel read or write operations of the SRAM in one cycle without changing the configuration of the dual-port SRAM in the memory cell to which the nonvolatile memory function is added.

[0026] Furthermore, in the first aspect, the volatile memory cell may be a two-port SRAM. This brings about an effect that the SRAM can be read and written in one cycle without changing the configuration of the two-port SRAM in the memory cell to which the nonvolatile memory function is added.

[0027] In addition, in the first aspect, the storage device may further include a peripheral recovery circuit that reads the data held in the nonvolatile storage node to the outside of the volatile storage unit. This brings about the effect of reading the data held in the nonvolatile storage unit without intervening in the volatile storage unit.

[0028] In addition, in the first aspect, the data held in the nonvolatile storage node can be restored to the peripheral recovery circuit sequentially via the storage transistor and the storage line. This brings about the effect of restoring the data held in the nonvolatile storage cell to the peripheral recovery circuit without the intervention of the volatile storage cell. BRIEF DESCRIPTION OF THE DRAWINGS

[0029] Figure 1 is a diagram showing an example of the configuration of a memory cell and a peripheral circuit of a storage device according to the first embodiment.

[0030] Figure 2 is a block diagram showing an example configuration of a cell array of a memory device according to the first embodiment.

[0031] Figure 3 is a diagram showing an example of a voltage waveform of each component of a memory cell during a read operation according to the first embodiment.

[0032] Figure 4 is a diagram showing an example of a voltage waveform of each component of a memory cell during a write operation according to the first embodiment.

[0033] Figure 5 is a diagram showing an example of a voltage waveform of each component of the memory cell during a storage operation according to the first embodiment.

[0034] Figure 6 is a diagram showing an example of a voltage waveform of each component of a memory cell during a recovery operation according to the first embodiment.

[0035] Figure 7 is a diagram illustrating an example configuration of a memory cell according to a comparative example.

[0036] Figure 8 is a table showing a size comparison between the memory cell according to the first embodiment and the memory cell according to the comparative example.

[0037] Fig. 9 is a cross-sectional view showing an example layout of wirings in the memory cell array according to the first embodiment.

[0038] Fig.10 is a block diagram showing the overall configuration of a storage device according to the first embodiment.

[0039] Fig.11 is a diagram showing an example configuration of a memory cell of a storage device according to the second embodiment.

[0040] Fig.12 is a diagram showing an example configuration of a memory cell of a storage device according to the third embodiment.

[0041] Fig.13 is a diagram showing an example configuration of a memory cell of a storage device according to a fourth embodiment.

[0042] Fig.14 is a diagram showing an example configuration of a memory cell of a storage device according to a fifth embodiment.

[0043] Fig.15 is a block diagram showing an example configuration of a cell array of a memory device according to a fifth embodiment.

[0044] Fig.16 is a diagram showing an example configuration of a memory cell of a storage device according to a sixth embodiment.

[0045] Fig.17is a diagram showing an example of a voltage waveform of each component of a memory cell during a peripheral recovery operation according to the sixth embodiment.

[0046] Fig.18 is a diagram showing an example of the configuration of a memory cell and a peripheral circuit of a storage device according to a seventh embodiment. DETAILED DESCRIPTION

[0047] In the following description, modes for carrying out the present technology (these modes will be referred to as embodiments hereinafter) will be explained. The explanation will be made in the following order.

[0048] 1. First Embodiment (Example in which a storage transistor for storing data held in a volatile storage node in a nonvolatile storage node and a recovery transistor for recovering data stored in a nonvolatile storage node to a volatile storage node are provided in each memory cell)

[0049] 2. Second Embodiment (Example in which a dual-port SRAM is provided in each memory cell)

[0050] 3. Third Embodiment (Example in which a two-port SRAM is provided in each memory cell)

[0051] 4. Fourth Embodiment (Example of Tail-Type Power Gating Configuration)

[0052] 5. Fifth Embodiment (Example in which a power gate transistor is shared among a plurality of memory cells)

[0053] 6. Sixth Embodiment (Example of Reading Data Stored in a Nonvolatile Memory Cell to the Outside)

[0054] 7. Seventh Embodiment (Example of Driving Nonvolatile Memory Cells Using a Higher Voltage Than a Voltage Used to Drive Volatile Memory Cells)

[0055] <1. First Embodiment>

[0056] Figure 1 is a diagram showing an example of the configuration of a memory cell and a peripheral circuit of a storage device according to the first embodiment.

[0057] In the drawing, a memory device 100 includes a memory cell 101 and a column processing unit 102. The memory cell 101 may be arranged in a matrix in a row direction and a column direction.

[0058] The memory unit 101 includes a volatile memory unit that holds data in a volatile manner and a nonvolatile memory unit that holds data in a nonvolatile manner. At this time, the nonvolatile memory unit can hold the data stored in the volatile memory unit in a nonvolatile manner. In addition, the nonvolatile memory unit can write the data held in a nonvolatile manner by the nonvolatile memory unit back to the volatile memory unit. It should be noted that the term "volatile" as used in this article means that power is required to hold data. In addition, the term "nonvolatile" as used in this article means that no power is required to hold data.

[0059] It should be noted that in this specification, writing data to a volatile memory cell is referred to as "writing", and reading data from a volatile memory cell is referred to as "reading". In addition, a process of causing a nonvolatile memory cell to hold data stored in a volatile memory cell is referred to as "storing", and a process of writing data held in a nonvolatile memory cell back to a volatile memory cell is referred to as "restoring".

[0060] The memory cell 101 includes an SRAM 111 and a resistance random access memory 131. The SRAM 111 includes a flip-flop 121 and access transistors 133 and 143. The flip-flop 121 includes inverters 113 and 123.

[0061] The SRAM 111 includes volatile storage nodes N and NB that hold data in a complementary manner. Each of the volatile storage nodes N and NB holds data in a volatile manner. It should be noted that the term "complementary" used herein refers to a relationship in which when data "0" is held in the volatile storage node N, data "1" is held in the volatile storage node NB, and when data "1" is held in the volatile storage node N, data "0" is held in the volatile storage node NB.

[0062] Each of the inverters 113 and 123 may be formed of a complementary metal oxide semiconductor (CMOS) transistor. For example, each of the inverters 113 and 123 may be formed of a PMOS transistor and an NMOS transistor connected in series.

[0063] The input terminal of the inverter 113 is connected to the output terminal of the inverter 123, and the input terminal of the inverter 123 is connected to the output terminal of the inverter 113. At this time, a volatile storage node N may be set at a connection point between the input of the inverter 113 and the output of the inverter 123, and a volatile storage node NB may be set at a connection point between the input of the inverter 123 and the output of the inverter 113.

[0064] The access transistor 133 is connected between the volatile storage node N and the bit line BL[X]. The access transistor 143 is connected between the volatile storage node NB and the bit line BLB[X]. The on / off of each of the access transistors 133 and 143 is controlled via the word line WL[Y]. Each of the access transistors 133 and 143 can be an NMOS transistor. At this time, the word line WL[Y] can be connected to the gate of each of the access transistors 133 and 143.

[0065] The power gate transistor 141 performs power gating of each of the inverters 113 and 123. At this time, the power gate transistor 141 can extract the charge accumulated in each volatile storage node N and NB into the power supply potential. The opening and closing of the power gate transistor 141 are controlled by the power gate line PG[Y]. The power gate transistor 141 can be a PMOS transistor. At this time, the power gate line PG[Y] can be connected to the gate of the power gate transistor 141.

[0066] The resistive random access memory 131 includes nonvolatile storage nodes M and MB that hold data in a complementary manner. Both the nonvolatile storage nodes M and MB hold data in a nonvolatile manner. It should be noted that the term "complementary" used herein refers to a relationship in which when data "0" is held in the nonvolatile storage node M, data "1" is held in the nonvolatile storage node MB, and when data "1" is held in the nonvolatile storage node M, data "0" is held in the nonvolatile storage node MB.

[0067] The resistance random access memory 131 includes variable resistance elements 135 and 145 , storage transistors 115 and 125 , and recovery transistors 114 and 124 .

[0068] Each of the variable resistance elements 135 and 145 changes resistance based on voltage application, and maintains its resistance state even when voltage application is cut off. At this time, the low resistance state of each of the variable resistance elements 135 and 145 can be made to correspond to data "0", and the high resistance state of each of the variable resistance elements 135 and 145 can be made to correspond to data "1". The variable resistance element 135 is connected between the nonvolatile storage node M and the NV control line CTL[X]. The variable resistance element 145 is connected between the nonvolatile storage node MB and the NV control line CTL[X].

[0069] Each storage transistor 115 and 125 stores the data held in each volatile storage node N and NB in ​​each nonvolatile storage node M and MB via storage lines SL[X] and SLB[X], respectively. The storage transistor 115 is connected between the nonvolatile storage node M and the storage line SL[X]. The storage transistor 125 is connected between the nonvolatile storage node MB and the storage line SLB[X]. The opening and closing of each of the storage transistors 115 and 125 is controlled via the storage selection line ST[Y]. Each of the storage transistors 115 and 125 can be an NMOS transistor. At this time, the storage selection line ST[Y] can be connected to the gate of each of the storage transistors 115 and 125.

[0070] The corresponding recovery transistors 114 and 124 restore the data held in the corresponding non-volatile storage nodes M and MB to the corresponding volatile storage nodes N and NB. The recovery transistor 114 is connected between the volatile storage node N and the non-volatile storage node M. The recovery transistor 124 is connected between the volatile storage node NB and the non-volatile storage node MB. The opening and closing of each of the recovery transistors 114 and 124 is controlled via the recovery selection line SR[Y]. Each of the recovery transistors 114 and 124 can be an NMOS transistor. At this time, the recovery selection line SR[Y] can be connected to the gate of each of the recovery transistors 114 and 124.

[0071] The driving force of each of the storage transistors 115 and 125 may be greater than the driving force of each of the transistors of each of the inverters 113 and 123, each of the access transistors 133 and 143, and each of the restore transistors 114 and 124. At this time, the driving force of each of the storage transistors 115 and 125 may be set based on the current required to change the state of each of the variable resistance elements 135 and 145.

[0072] The RRAM 131 may be a magnetoresistive random access memory (MRAM), a phase change random access memory (PRAM), or a resistive random access memory (ReRAM).

[0073] The column processing unit 102 may be provided for each column. The column processing unit 102 includes a nonvolatile (NV) control unit 112, a precharge circuit 122, a write driver 132, and a sense amplifier 142.

[0074] The NV control unit 112 controls storage and recovery in the resistive random access memory 131 based on the storage control signal SP and the NV control signal CTRL. Here, the NV control unit 112 controls the potentials of the respective storage lines SL[X] and SLB[X] and the potential of the NV control line CTL[X] based on the data detected by the sense amplifier 142 to perform storage in the non-volatile storage nodes M and MB. At this time, the NV control unit 112 can complementarily set the potentials of the respective storage lines SL[X] and SLB[X] according to the data detected by the sense amplifier 142 so that the potential of the NV control line CTL[X] transitions between a high level and a low level.

[0075] The precharge circuit 122 precharges the corresponding bit lines BL[X] and BLB[X] based on the precharge enable signal PRE.

[0076] The write driver 132 sets the potentials of the corresponding bit lines BL[X] and BLB[X] complementarily based on the write enable signal WE. At this time, the write driver 132 can determine the potentials of the corresponding bit lines BL[X] and BLB[X] based on the write data D[X]. For example, when the write data D[X] is 0, the potential of the bit line BL[X] can be set to a low level, and the potential of BLB[X] can be set to a high level. When the write data D[X] is 1, the potential of the bit line BL[X] can be set to a high level, and the potential of BLB[X] can be set to a low level.

[0077] The sense amplifier 142 detects the data read from the SRAM 111 based on the sense enable signal SAE. At this time, when reading data from the SRAM 111, the potentials of the respective bit lines BL[X] and BLB[X] are complementarily set according to the data stored in the SRAM 111. The sense amplifier 142 is then able to determine the data stored in the SRAM 111 based on the potentials of the corresponding bit lines BL[X] and BLB[X]. The sense amplifier 142 outputs the data Q[X] read from the SRAM 111 to the outside, and inputs the read data Q[X] to the NV control unit 112. At this time, the NV control unit 112 can control the potentials of the respective storage lines SL[X] and SLB[X] according to the data Q[X] read from the SRAM 111, and store the data held in the SRAM 111 in the resistive random access memory 131.

[0078] The bit lines BL[X] and BLB[X], the storage lines SL[X] and SLB[X], and the NV control line CTL[X] extend in the column direction. X (X is an integer of 0 or more) may indicate a column position. The column position may be specified based on a column address. The word line WL[Y], the restore selection line SR[Y], the storage selection line ST[Y], and the power gate line PG[Y] extend in the row direction. Y (Y is an integer of 0 or more) may indicate a row position. The row position may be specified based on a row address.

[0079] Note that the SRAM 111 is an example of a volatile memory cell disclosed in the claims. The resistive random access memory 131 is an example of a nonvolatile memory cell disclosed in the claims. Each of the storage transistors 115 and 125 is an example of a first switch disclosed in the claims. Each of the recovery transistors 114 and 124 is an example of a second switch disclosed in the claims.

[0080] Figure 2 is a block diagram showing an example configuration of a cell array of a memory device according to the first embodiment.

[0081] In the drawings, a memory cell array 110 and a peripheral circuit 120 are provided in a memory device 100. In the memory cell array 110, memory cells 101 are arranged in a matrix in the row direction and the column direction. In the peripheral circuit 120, a column processing unit 102 is provided for each column. Note that in the memory cell 101, MC[X][Y] indicates that the column position is X and the row position is Y. In the column processing unit 102, PC[X] indicates that the column position is X.

[0082] Bit lines BL[X] and BLB[X], storage lines SL[X] and SLB[X], and NV control lines CTL[X] may be provided for each column. Word lines WL[Y], storage selection lines ST[Y], restore selection lines SR[Y], and power gate lines PG[Y] may be provided for corresponding rows. Write data D[X] may be input for each column, and read data Q[X] may be output for each column.

[0083] Figure 3 is a diagram showing an example of a voltage waveform of each component of a memory cell during a read operation according to the first embodiment.

[0084] In the drawing, during reading from the SRAM 111, the corresponding recovery transistors 114 and 124 are turned off via the recovery selection line SR[Y], and the SRAM 111 and the resistance random access memory 131 are disconnected from each other. In addition, each of the storage lines SL[X] and SLB[X] enters a floating state (time t1 to t4).

[0085] When the precharge enable signal PRE transitions from a high level to a low level (time t1 ), the precharge circuit 122 then precharges each of the bit lines BL[X] and BLB[X].

[0086] Next, when the precharge start signal PRE changes from a low level to a high level (time t2), the precharge circuit 122 ends the precharge of each of the bit lines BL[X] and BLB[X]. In addition, the corresponding access transistors 133 and 143 are turned on via the word line WL[Y], and the corresponding volatile storage nodes N and NB are connected to the bit lines BL[X] and BLB[X]. At this time, the potential of each bit line BL[X] and BLB[X] changes according to the data held in each volatile storage node N and NB. For example, when "1" is held in the volatile storage node N and "0" is held in the volatile storage node NB, the potential of the bit line BLB[X] becomes lower than the potential of the bit line BL[X].

[0087] Next, when the sense enable signal SAE changes from the low level to the high level (time t3), the sense amplifier 142 determines the data held in the SRAM 111 based on the potentials of the corresponding bit lines BL[X] and BLB[X]. The sense amplifier 142 then outputs read data Q[X] corresponding to the determination result.

[0088] When reading from the SRAM 111 ends, each of the access transistors 133 and 143 is turned off via the word line WL[Y], and the sense enable signal SAE transitions from the high level to the low level (time t4 ).

[0089] Figure 4 is a diagram showing an example of a voltage waveform of each component of a memory cell during a write operation according to the first embodiment.

[0090] In the drawing, when writing into the SRAM 111, the corresponding recovery transistors 114 and 124 are turned off via the recovery selection line SR[Y], and the SRAM 111 and the resistance random access memory 131 are disconnected from each other. In addition, each of the storage lines SL[X] and SLB[X] enters a floating state (time t11 to t13).

[0091] Then, when the precharge enable signal PRE transitions from the high level to the low level (time t11 ), the precharge circuit 122 then precharges each of the bit lines BL[X] and BLB[X].

[0092] Next, when the precharge enable signal PRE changes from a low level to a high level (time t12), the precharge circuit 122 ends the precharge of each of the bit lines BL[X] and BLB[X]. In addition, when the write enable signal WE changes from a low level to a high level, the write driver 132 complementarily sets the potentials of the corresponding bit lines BL[X] and BLB[X] based on the write data D[X]. For example, in the case where "1" is written to the volatile storage node N and a write is performed on the volatile storage node NB, the write data D[X] is set to a high level (from time t11 to time t14). In the case where the write data D[X] is set to a high level, the write driver 132 then sets the bit line BL[X] to a high level and sets BLB[X] to a low level.

[0093] Next, each access transistor 133 and 143 is turned on via the word line WL[Y], and each volatile storage node N and NB is connected to the bit lines BL[X] and BLB[X] (time t13). When each volatile storage node N and NB is connected to the bit lines BL[X] and BLB[X], the potential of each volatile storage node N and NB is set according to the potential of each bit line BL[X] and BLB[X], and data corresponding to the potential is held in each volatile storage node N and NB.

[0094] When writing to the SRAM 111 ends, each of the access transistors 133 and 143 is turned off via the word line WL[Y], and the write enable signal WE transitions from the high level to the low level (time t14 ).

[0095] Figure 5 is a diagram showing an example of a voltage waveform of each component of the memory cell during a storage operation according to the first embodiment.

[0096] In the drawing, when storing in the RRAM 131, the respective recovery transistors 114 and 124 are turned off via the recovery selection line SR[Y], and the SRAM 111 and the RRAM 131 are disconnected from each other (from time t21 to time t25).

[0097] When the precharge enable signal PRE transitions from a high level to a low level (time t21 ), the precharge circuit 122 then precharges each of the bit lines BL[X] and BLB[X].

[0098] Next, when the precharge enable signal PRE changes from a low level to a high level (time t22), the precharge circuit 122 ends the precharge of each of the bit lines BL[X] and BLB[X]. In addition, the corresponding access transistors 133 and 143 are turned on via the word line WL[Y], and the corresponding volatile storage nodes N and NB are connected to the bit lines BL[X] and BLB[X]. At this time, the potential of each bit line BL[X] and BLB[X] changes according to the data held in each volatile storage node N and NB. For example, when "1" is held in the volatile storage node N and "0" is held in the volatile storage node NB, the potential of the bit line BLB[X] becomes lower than the potential of the bit line BL[X].

[0099] Next, when the sense enable signal SAE changes from a low level to a high level (time t23), the sense amplifier 142 determines the data held in the SRAM 111 based on the potentials of the respective bit lines BL[X] and BLB[X]. The sense amplifier 142 then outputs read data Q[X] corresponding to the determination result to the NV control unit 112.

[0100] Next, the respective storage transistors 115 and 125 are turned on via the storage selection line ST[Y], and the respective nonvolatile storage nodes M and MB are connected to the storage lines SL[X] and SLB[X] (time t24).

[0101] In addition, when the storage control signal SP changes from a low level to a high level, the NV control unit 112 changes the potential of the NV control line CTL[X] from a floating state to a high level. In addition, the NV control unit 112 complementarily sets the potentials of the respective storage lines SL[X] and SLB[X] according to the read data Q[X] detected by the sense amplifier 142. For example, when "1" is maintained in the volatile storage node N and "0" is maintained in the volatile storage node NB, the NV control unit 112 sets the potential of the storage line SL[X] to a high level and sets the potential of SLB[X] to a low level. At this time, the potential of the NV control line CTL[X] is a high level. Therefore, no current flows in the variable resistance element 145 connected between the NV control line CTL[X] and the storage line SLB[X] via the storage transistor 125. On the other hand, current flows in the variable resistance element 135 connected between the NV control line CTL[X] and the storage line SL[X] via the storage transistor 115. Therefore, the variable resistance element 135 is set to a high resistance state, and data “1” is stored in the nonvolatile storage node M.

[0102] Next, when the NV control signal CTRL changes from a low level to a high level, the NV control unit 112 changes the potential of the NV control line CTL[X] from a high level to a low level (time t25). At this time, the potential of the storage line SL[X] is at a high level, and the potential of SLB[X] is at a low level. Therefore, no current flows in the variable resistance element 135 connected between the NV control line CTL[X] and the storage line SL[X] through the storage transistor 115. On the other hand, current flows in the variable resistance element 145 connected between the NV control line CTL[X] and the storage line SLB[X] via the storage transistor 125. At this time, the direction in which the current flows in the variable resistance element 145 when the potential of the NV control signal CTRL is at a low level is opposite to the direction in which the current flows in the variable resistance element 135 when the potential of the NV control signal CTRL is at a high level. Therefore, the variable resistance element 145 is set to a low resistance state, and the data "0" is stored in the non-volatile storage node MB.

[0103] When storage in the RRAM 131 is completed, the corresponding storage transistors 115 and 125 are turned off via the storage selection line ST[Y] (time t26). In addition, the sensing enable signal SAE, the storage control signal SP, and the NV control signal CTRL are changed from high level to low level.

[0104] Figure 6 is a diagram showing an example of a voltage waveform of each component of a memory cell during a recovery operation according to the first embodiment.

[0105] In the drawing, when restoring to the SRAM 111, the respective storage transistors 115 and 125 are turned off via the storage selection line ST[Y], and the resistance random access memory 131 is disconnected from the storage lines SL[X] and SLB[X]. In addition, the corresponding bit lines BL[X] and BLB[X] and the corresponding storage lines SL[X] and SLB[X] are placed in a floating state (from time t31 to time t33).

[0106] Then, each recovery transistor 114 and 124 are turned on via the recovery selection line SR[Y], and the SRAM 111 and the resistance random access memory 131 are connected (time t31). In addition, the power gate transistor 141 is turned off via the power gate line PG[Y]. In addition, when the NV control signal CTRL changes from a low level to a high level, the NV control unit 112 changes the potential of the NV control line CTL[X] from a high level to a low level.

[0107] Here, it is assumed that data "1" is maintained at the nonvolatile storage node M, data "0" is maintained at the nonvolatile storage node MB, the variable resistance element 135 is in a high resistance state, and the variable resistance element 145 is in a low resistance state. At this time, a low-level voltage is applied from the NV control line CTL[X] to the volatile storage node NB via the variable resistance element 145, and the data "0" is restored.

[0108] Next, the power gate transistor 141 is turned on via the power gate line PG[Y]. At this time, data is complementarily held in the respective volatile storage nodes N and NB, and data "1" is restored to the volatile storage node N (time t32).

[0109] When restoration to the SRAM 111 is completed, the corresponding restoration transistors 114 and 124 are turned off via the restoration selection line SR[Y], and the NV control signal CTRL transitions from the high level to the low level (time t33 ).

[0110] Figure 7 is a diagram illustrating an example configuration of a memory cell according to a comparative example.

[0111] In the drawings, a memory cell 901 includes an SRAM 911 and a resistive random access memory 931. The SRAM 911 includes NMOS transistors 973 and 983, PMOS transistors 953 and 963, and access transistors 933 and 943. A high power supply voltage VDD and a low power supply voltage VSS are provided to the SRAM 911. A word line WL is connected to the gates of the corresponding access transistors 933 and 943. A bit line BL is connected to a volatile node N of the SRAM 911 via an access transistor 933. A bit line BLB is connected to a volatile node NB of the SRAM 911 via an access transistor 943.

[0112] The resistance random access memory 931 includes variable resistance elements 935 and 945, and resistance drive transistors 915 and 925. The resistance drive transistor 915 is connected in series to the variable resistance element 935. The resistance drive transistor 925 is connected in series to the variable resistance element 945. Moreover, the resistance drive transistor 915 is connected to the volatile node N of the SRAM 911. The resistance drive transistor 925 is connected to the volatile node NB of the SRAM 911. In addition, the variable resistance element 935 is connected to the bit line BL, and the variable resistance element 945 is connected to the bit line BLB. Each of the resistance drive transistors 915 and 925 performs both storage in the resistance random access memory 931 and restoration in the SRAM 911. The storage / restore line WRE is connected to the gates of the respective resistance drive transistors 915 and 925.

[0113] Figure 8is a table showing a size comparison between the memory cell according to the first embodiment and the memory cell according to the comparative example. Note that Figure 8 Element a shows the size of a transistor used in the memory cell 101 according to the first embodiment. Figure 8 b shows that according to Figure 7 The size of the transistor used in the memory cell 901 of the comparative example is shown.

[0114] exist Figure 8 In a, the SRAM 111 according to the first embodiment includes two NMOS transistors and two PMOS transistors for a trigger 121, and two access transistors 133 and 143. In addition, a power gate transistor 141 is added. In the resistance random access memory 131, two storage transistors 115 and 125 and two recovery transistors 114 and 124 are used. Here, the storage transistors 115 and 125 are used to drive the variable resistance elements 135 and 145, and therefore, the gate widths of the storage transistors 115 and 125 are designed to be larger than the gate widths of other transistors.

[0115] exist Figure 8 In b, Figure 7 The SRAM 911 in the embodiment includes two NMOS transistors 973 and 983, two PMOS transistors 953 and 963, and two access transistors 933 and 943. The resistive random access memory 931 includes two resistive drive transistors 915 and 925. Here, the resistive drive transistors 915 and 925 are used to drive the variable resistance elements 935 and 945, and therefore, their gate widths are designed to be larger than the gate widths of other transistors. At this time, the gate width of each of the resistive drive transistors 915 and 925 can be equal to the gate width of the storage transistors 115 and 125. In addition, since the transistor of the SRAM 911 is included in the current path during the driving of each of the variable resistance elements 935 and 945, each transistor of the SRAM 911 needs to be equal to the driving force of each of the resistive drive transistors 915 and 925. Therefore, the gate width of each transistor of the SRAM is increased to match the gate width of each of the resistive drive transistors 915 and 925.

[0116] Therefore, the number of elements in the memory cell 101 according to the first embodiment is greater than Figure 7 The number of elements in the memory cell 911 in the embodiment is less than the sum of the gate widths in the memory cell 101 according to the first embodiment. Figure 7 Therefore, in the memory cell 101 according to the first embodiment, the cell size can be made smaller than Figure 7The cell size of the memory cell 911 in .

[0117] In addition, Figure 7 In the memory cell 901, the resistance driving transistor 915 is connected to the bit line BL via the variable resistance element 935, and the resistance driving transistor 925 is connected to the bit line BLB via the variable resistance element 945. Therefore, the junction capacitance of the corresponding resistance driving transistors 915 and 925 is added to the bit lines BL and BLB, and the turn-off leakage current of the corresponding resistance driving transistors 915 and 925 flows into the bit lines BL and BLB. At this time, the junction capacitance added to the bit line BL is expressed as (the capacitance of the access transistor 933 + the capacitance of the resistance driving transistor 915) × the number of word lines. In addition, the junction capacitance added to the bit line BLB is expressed as (the capacitance of the access transistor 943 + the capacitance of the resistance driving transistor 925) × the number of word lines. The turn-off leakage current flowing in the bit line BL is expressed as (the turn-off leakage current of the access transistor 933 + the turn-off leakage current of the resistance driving transistor 915) × the number of word lines. Furthermore, the off leakage current flowing in the bit line BLB is expressed as (off leakage current of the access transistor 943+off leakage current of the resistance driving transistor 925)×the number of word lines.

[0118] On the other hand, in the memory cell 101 according to the first embodiment, the storage transistors 115 and 125 and the recovery transistors 114 and 124 are not connected to any of the bit lines BL and BLB. Therefore, the junction capacitance of the corresponding storage transistors 115 and 125 and the junction capacitance of the corresponding recovery transistors 114 and 124 are not added to any of the bit lines BL and BLB. Similarly, the off leakage current of each of the storage transistors 115 and 125 and the off leakage current of each of the recovery transistors 114 and 124 do not flow into any of the bit lines BL and BLB. At this time, the junction capacitance added to the bit line BL is expressed as the capacitance of the storage transistor 115 × the number of word lines. Similarly, the junction capacitance added to the bit line BLB is expressed as the capacitance of the storage transistor 125 × the number of word lines. The off leakage current flowing into the bit line BL is expressed as the off leakage current of the storage transistor 115 × the number of word lines. Similarly, the off leakage current flowing into the bit line BLB is expressed as the off leakage current of the storage transistor 125 × the number of word lines.

[0119] Therefore, with Figure 7 Compared with the memory cell 901 in the embodiment, the memory cell 101 according to the first embodiment can reduce power consumption and improve the read and write performance of the SRAM 111.

[0120] Fig. 9 is a cross-sectional view showing an example layout of wiring in the memory cell array according to the first embodiment. Note that Fig. 9 a is a diagram illustrating a first example of a wiring layout of a memory cell array, Fig. 9 b is a diagram illustrating a second example of a wiring layout in a memory cell array, Fig. 9 c is a diagram illustrating a third example of a wiring layout in a memory cell array. In addition, Fig. 9 An example of four-layer wiring is shown.

[0121] In the drawings, gate electrode / via layer 116, wiring layer 126, via layer 136, wiring layer 146, via layer 156, wiring layer 166, via layer 176 and wiring layer 186 are stacked in sequence on semiconductor substrate 106. Device separation layer, impurity diffusion layer and well layer may also be formed on semiconductor substrate 106. The material of semiconductor substrate 106 is, for example, Si, GaAs, SiC or GaN. Gate electrode and contact via are formed in gate electrode / via layer 116. Wiring is formed in each of wiring layers 126, 146, 166 and 186. Vias are formed in each of via layers 136, 156 and 176. The material of wiring and via is, for example, Al or Cu.

[0122] In the wiring layer 146, bit lines BL[X] and BLB[X], storage lines SL[X] and SLB[X], and NV control line CTL[X] are formed. This wiring method is effective in the case of a layout in which the memory cell 101 is long in the row direction. In this case, the wiring layer 186 can be effectively used for other wiring. Note that a signal line can be set in the row direction in the wiring layer 166.

[0123] In b of the accompanying drawings, the bit lines BL[X] and BLB[X] and the NV control line CTL[X] are formed in the wiring layer 146. In the wiring layer 186, the storage lines SL[X] and SLB[X] are formed. At this time, the wiring layer 146 of the bit lines BL[X] and BLB[X] and the wiring layer 186 of the storage lines SL[X] and SLB[X] can be separated from each other. Through this wiring method, the memory cell 101 in the row direction can be miniaturized. This wiring method is effective when the wiring area of ​​the wiring layer 166 in the column direction has a margin.

[0124] In c of the figure, the bit lines BL[X] and BLB[X] and the NV control line CTL[X] are formed in the wiring layer 146. In the wiring layer 186, the storage lines SL[X] and SLB[X] are formed. At this time, the storage lines SL[X] and SLB[X] are arranged to overlap with the bit lines BL[X] and BLB[X]. By this wiring method, the memory cell 101 in the row direction can be miniaturized. This wiring method is effective when the wiring area of ​​the wiring layer 166 in the column direction has a margin.

[0125] Fig.10 is a block diagram showing the overall configuration of a storage device according to the first embodiment.

[0126] In the drawings, the memory device 100 includes a row address decoder 151, a row logic circuit 152, a row driver 153, a column address decoder 154, a memory control unit 155, and a power supply control circuit 156 in addition to the memory cell array 110 and the column processing unit 102. In addition to the NV control unit 112, the precharge circuit 122, the write driver 132, and the sense amplifier 142, the column processing unit 102 also includes a latch circuit 161 and a column selector 162. The row logic circuit 152 and the row driver 153 are provided for the corresponding rows.

[0127] The row address decoder 151 selects a row based on the row address ADR and activates the row logic circuit 152 corresponding to the selected row. The row logic circuit 152 activates the row driver 153 based on the instruction from the row address decoder 151. The row driver 153 drives the memory cell array 110 in row units. At this time, the row driver 153 can drive the power gate line PG[Y], the word line WL[Y], the restore selection line SR[Y], and the storage selection line ST[Y] in row units.

[0128] The column address decoder 154 selects a column based on the column address ADC and activates the column processing unit 102 corresponding to the selected column. The latch circuit 161 latches the write data D[X] and outputs the write data D[X] to the write driver 132. The column selector 162 selects a column of the memory cell array 110. At this time, the column selector 162 can connect the storage lines SL[X] and SLB[X] of the selected column and the NV control line CTL[X] to the NV control unit 112. Moreover, the column selector 162 can connect the bit lines BL[X] and BLB[X] of the selected column to the precharge circuit 122, the write driver 132, and the sense amplifier 142.

[0129] The memory control unit 155 controls the row logic circuit 152 and the column processing unit 102 based on the control signal MCS. The power control circuit 156 controls the power to the row driver 153 and the column processing unit 102. At this time, the power control circuit 156 can control the power to the row driver 153 and the column processing unit 102 so that the resistance random access memory 131 is driven based on a voltage higher than the driving voltage of the SRAM 111.

[0130] In this way, in the above-described first embodiment, the storage transistors 115 and 125 for storing the data held in the SRAM 111 in the resistance random access memory 131 are provided in the memory cell 101. Furthermore, the recovery transistors 114 and 124 for recovering the data stored in the resistance random access memory 131 to the SRAM 111 are provided in the memory cell 101. Therefore, the data held in the SRAM 111 can be stored in the resistance random access memory 131 via the corresponding storage transistors 115 and 125. Moreover, the data held in the resistance random access memory 131 can be recovered to the SRAM 111 via the corresponding recovery transistors 114 and 124. Thus, it is possible to separate the path for storing the data held in the SRAM 111 in the resistance random access memory 131 from the path for recovering the data held in the resistance random access memory 131 to the SRAM 111. As a result, the data held in the SRAM 111 can be stored in the resistance random access memory 131 without intervention of the SRAM 111, and the resistance random access memory 131 does not need to be driven via the SRAM 111 when storing data. Therefore, the size of the SRAM 111 does not need to be increased to store data in the resistance random access memory 131, and a nonvolatile storage function can be added to the SRAM 111 while preventing the size of the memory cell 101 from increasing.

[0131] In addition, in order to allow current to flow into the variable resistance elements 135 and 145 when storing data, the storage lines SL[X] and SLB[X] are set separately from the bit lines BL[X] and BLB[X]. Then, the storage transistor 115 is connected between the storage line SL[X] and the variable resistance element 135, and the storage transistor 125 is connected between the storage line SLB[X] and the variable resistance element 145. Therefore, the junction capacitance of the corresponding storage transistors 115 and 125 can be prevented from being added to the corresponding bit lines BL[X] and BLB[X], and the increase of the parasitic capacitance of each of the bit lines BL[X] and BLB[X] can be prevented. Therefore, the discharge time of each of the bit lines BL[X] and BLB[X] can be prevented from increasing, and the write time and read time of the SRAM 111 can be prevented from increasing. In addition, the charge / discharge amount in each of the bit lines BL[X] and BLB[X] can be prevented from increasing, and the power consumption of the SRAM 111 can be prevented from increasing.

[0132] Furthermore, it is possible to prevent an instantaneous current from flowing into the variable resistance elements 135 and 145 when each of the bit lines BL[X] and BLB[X] is amplified, and it is possible to prevent an increase in noise when reading from and writing to the SRAM 111.

[0133] <2. Second Embodiment>

[0134] In the above-described first embodiment, the SRAM 111 is provided as a volatile memory cell in the memory cell 101. In this second embodiment, a dual-port SRAM is provided as a volatile memory cell in the memory cell.

[0135] Fig.11 is a diagram showing an example configuration of a memory cell of a storage device according to the second embodiment.

[0136] In the drawings, the memory device 200 includes a memory cell 201 instead of the memory cell 101 of the first embodiment described above. The memory device 200 further includes word lines WL1 and WL2 as the word lines WL[Y] of the first embodiment described above. The memory device 200 further includes bit lines BL1, BLB1, BL2, and BLB2 as the bit lines BL[X] and BLB[X] of the first embodiment described above. Other components of the memory device 200 of the second embodiment are similar to those of the memory device 100 of the first embodiment described above.

[0137] The memory cell 201 includes an SRAM 211 instead of the SRAM 111 of the above-described first embodiment. Other components of the memory cell 201 are similar to those of the memory cell 101 of the above-described first embodiment.

[0138] In the SRAM 211, access transistors 233 and 243 are added to the SRAM 111 of the above-described first embodiment. Other components of the SRAM 211 are similar to those of the SRAM 111 of the above-described first embodiment.

[0139] The access transistor 133 is connected between the volatile storage node N and the bit line BL1. The access transistor 143 is connected between the volatile storage node NB and the bit line BLB1. The opening / closing of each of the access transistors 133 and 143 is controlled via the word line WL1. At this time, the word line WL1 may be connected to the gates of the corresponding access transistors 133 and 143.

[0140] The access transistor 233 is connected between the volatile storage node N and the bit line BL2. The access transistor 243 is connected between the volatile storage node NB and the bit line BLB2. The opening / closing of each of the access transistors 233 and 243 is controlled via the word line WL2. Each of the access transistors 233 and 243 may be an NMOS transistor. At this time, the word line WL2 may be connected to the gates of the respective access transistors 233 and 243.

[0141] In this way, in the above-mentioned second embodiment, the dual-port SRAM 211 is set as a volatile storage unit in the memory unit 201. Thus, two parallel read or write operations can be performed on the SRAM in one cycle without changing the configuration of the dual-port SRAM 211, and a non-volatile storage function can be added thereto.

[0142] <3. Third Embodiment>

[0143] In the above-described second embodiment, the dual-port SRAM 211 is provided as a volatile memory cell in each memory cell 201. In this third embodiment, the dual-port SRAM is provided as a volatile memory cell in the memory cell.

[0144] Fig.12 is a diagram showing an example configuration of a memory cell of a storage device according to the third embodiment.

[0145] In the drawings, the memory device 300 includes a memory cell 301 instead of the memory cell 101 of the first embodiment described above. In addition, the memory device 300 includes word lines RWL and WWL as the word lines WL[Y] of the first embodiment described above. In addition, the memory device 300 includes bit lines XWBL, XWBLB, and RBL as the bit lines BL[X] and BLB[X] of the first embodiment described above. Other components of the memory device 300 of the third embodiment are similar to those of the memory device 100 of the first embodiment described above.

[0146] The memory cell 301 includes an SRAM 311 instead of the SRAM 111 of the above-described first embodiment. Other components of the memory cell 301 are similar to those of the memory cell 101 of the above-described first embodiment.

[0147] In the SRAM 311, a read transistor 313, write transistors 333 and 343, and an access transistor 323 are added to the SRAM 111 of the above-described first embodiment. Other components of the SRAM 311 are similar to those of the SRAM 111 of the above-described first embodiment.

[0148] The read transistor 313 and the access transistor 323 are connected in series. In addition, the access transistor 323 is connected to the bit line RBL, and the read transistor 313 is connected to the ground. In addition, the gate of the access transistor 323 is connected to the word line RWL, and the gate of the read transistor 313 is connected to the volatile storage node NB.

[0149] The write transistor 333 and the access transistor 133 are connected in series. Further, the access transistor 133 is connected to the volatile storage node N, and the write transistor 333 is connected to the ground. Further, the gate of the access transistor 133 is connected to the word line WWL, and the gate of the write transistor 333 is connected to the bit line XWBL.

[0150] The write transistor 343 and the access transistor 143 are connected in series. In addition, the access transistor 143 is connected to the volatile storage node NB, and the write transistor 343 is connected to the ground. In addition, the gate of the access transistor 143 is connected to the word line WWL, and the gate of the write transistor 343 is connected to the bit line XWBLB.

[0151] In this way, in the third embodiment described above, a two-port SRAM 311 is provided as a volatile storage unit in each memory cell 301. Thus, read and write operations can be performed on the SRAM in one cycle without changing the configuration of the two-port SRAM 311, and a nonvolatile storage function can be added thereto.

[0152] <4. Fourth Embodiment>

[0153] In the first embodiment described above, the power gate transistor 141 performing header type power gating is connected to each of the inverters 113 and 123. In this fourth embodiment, the power gate transistor performing tail type power gating is connected to each of the inverters 113 and 123.

[0154] Fig.13 is a diagram showing an example configuration of a memory cell of a storage device according to a fourth embodiment.

[0155] In the drawing, the memory device 400 includes a power gate transistor 414 instead of the power gate transistor 141 of the above-described first embodiment. Other components of the memory device 400 of the fourth embodiment are similar to those of the memory device 100 of the above-described first embodiment.

[0156] The power gate transistor 414 performs power gating of each of the inverters 113 and 123. At this time, the power gate transistor 414 can extract the charge accumulated in each of the volatile storage nodes N and NB to the ground line. The gate of the power gate transistor 414 is connected to the power gate line PG.

[0157] As described above, in the fourth embodiment, the power gate transistor 414 is connected to each of the inverters 113 and 123 to form a tail-type power gate configuration. Thus, the charge accumulated in each of the nonvolatile storage nodes N and NB can be extracted, and the data held in the resistance random access memory 131 can be restored to the SRAM 111 via the recovery transistors 114 and 124.

[0158] <5. Fifth embodiment>

[0159] In the above-described first embodiment, the power gate transistor 141 is provided in the corresponding memory cell 101. In this fifth embodiment, one power gate transistor is shared among a plurality of memory cells provided in a memory cell array.

[0160] Fig.14 is a diagram showing an example configuration of a memory cell of a storage device according to a fifth embodiment.

[0161] In the drawing, a memory device 500 includes a memory unit 501 instead of the memory unit 101 of the above-described first embodiment. Other components of the memory device 500 of the fifth embodiment are similar to those of the memory device 100 of the above-described first embodiment.

[0162] In the memory cell 501, the power gate transistor 141 of the above-described first embodiment is omitted. Other components of the memory cell 501 are similar to those of the memory cell 101 of the above-described first embodiment.

[0163] Fig.15 is a block diagram showing an example configuration of a cell array of a memory device according to a fifth embodiment.

[0164] In the drawings, a memory device 500 includes a memory cell array 510 instead of the memory cell array 110 of the first embodiment described above. In addition, in the memory device 500, a power gate transistor 541 is added to the memory device 100 of the first embodiment described above. Other components of the memory device 500 of the fifth embodiment are similar to those of the memory device 100 of the first embodiment described above.

[0165] In the memory cell array 510 , the memory cells 501 are arranged in a matrix form along the row direction and the column direction. The power gate transistor 541 is shared between the plurality of memory cells 501 provided in the memory cell array 510 .

[0166] The power gate transistor 541 performs power gating of each of the inverters 113 and 123 of the plurality of memory cells 501 provided in the memory cell array 510. At this time, the power gate transistor 541 can extract charges accumulated in the corresponding volatile storage nodes N and NB of the plurality of memory cells 501 provided in the memory cell array 510 to the ground line. The gate of the power gate transistor 541 is connected to the power gate line PG.

[0167] As described above, in the fifth embodiment, a single power gate transistor 541 is shared among a plurality of memory cells 501 provided in the memory cell array 500. Therefore, it is not necessary to provide a power gate transistor 541 in each memory cell 501, and the size of the memory cell 501 can be made smaller.

[0168] Note that power gating may be performed on a memory cell basis, a memory cell array basis, a word line basis, a bit line basis, or a power domain basis. At this time, header type power gating may be performed, or trailer type power gating may be performed.

[0169] <6. Sixth Implementation Method>

[0170] In the first embodiment described above, in the case of reading data held in the resistance random access memory 131, the data held in the resistance random access memory 131 is restored to the SRAM 111, and the data is read from the SRAM 111. In the sixth embodiment, in the case of reading data held in the resistance random access memory 131, the data held in the resistance random access memory 131 is not restored to the SRAM 111, but is directly read from the resistance random access memory 131.

[0171] Fig.16 is a diagram showing an example configuration of a memory cell of a storage device according to a sixth embodiment.

[0172] In the drawing, a memory device 600 includes a memory unit 601 instead of the memory unit 101 of the above-described first embodiment. Other components of the memory device 600 of the sixth embodiment are similar to those of the memory device 100 of the above-described first embodiment.

[0173] In the memory cell 601, a peripheral restore circuit 611 is added to the memory cell 101 of the above-described first embodiment. Other components of the memory cell 601 are similar to those of the memory cell 101 of the above-described first embodiment.

[0174] The peripheral recovery circuit 611 includes volatile storage nodes P and PB that complementarily retain data. The peripheral recovery circuit 611 retains data in the nonvolatile storage nodes M and MB of the RRAM 131 in the volatile storage nodes P and PB in a nonvolatile manner, and outputs the data to the outside of the memory cell 601 via the volatile storage node PB.

[0175] The peripheral recovery circuit 611 includes a flip-flop 621, power gate transistors 641 and 642, and inverters 633 and 643. The flip-flop 621 includes inverters 613 and 623.

[0176] The input terminal of the inverter 613 is connected to the output terminal of the inverter 623, and the input terminal of the inverter 623 is connected to the output terminal of the inverter 613. At this time, a volatile storage node P may be provided at a connection point between the input of the inverter 613 and the output of the inverter 623, and a volatile storage node PB may be provided at a connection point between the input of the inverter 623 and the output of the inverter 613. The volatile storage node P is connected to the storage line SL[X], and the volatile storage node PB is connected to the storage line SLB[X].

[0177] The corresponding power gate transistors 641 and 642 perform power gating of the corresponding inverters 613 and 623. At this time, the power gate transistor 641 can extract the charges accumulated in the respective volatile storage nodes P and PB to the power supply potential. The power gate transistor 642 can extract the charges accumulated in the corresponding volatile storage nodes P and PB to the ground. The gate of the power gate transistor 641 is connected to the power gate line PGP[Y]. The gate of the power gate transistor 642 is connected to the power gate line PGP[Y] via the inverter 633. The data held in the volatile storage node PB is output as the recovery data NVQ[X] via the inverter 643.

[0178] Fig.17 is a diagram showing an example of a voltage waveform of each component of a memory cell during a peripheral recovery operation according to the sixth embodiment.

[0179] In the drawing, when the periphery is restored to the peripheral restoration circuit 611, the corresponding restoration transistors 114 and 124 are turned off via the restoration selection line SR[Y], and the SRAM 111 and the resistance random access memory 131 are disconnected from each other. In addition, each of the bit lines BL[X] and BLB[X] enters a floating state (from time t41 to time t43).

[0180] Then, each storage transistor 115 and 125 is turned on via the storage selection line ST[Y], and the storage lines SL[X] and SLB[X] are connected to the resistance random access memory 131 (time t41). In addition, when the NV control signal CTRL changes from a low level to a high level, the NV control unit 112 changes the potential of the NV control line CTL[X] from a high level to a low level.

[0181] Here, it is assumed that data "1" is maintained at the nonvolatile storage node M, data "0" is maintained at the nonvolatile storage node MB, the variable resistance element 135 is in a high resistance state, and the variable resistance element 145 is in a low resistance state. At this time, a low-level voltage is applied from the NV control line CTL[X] to the volatile storage node PB through the variable resistance element 145, the storage transistor 125, and the storage line SLB[X] in sequence, and data "0" is restored thereto.

[0182] Next, the power gate transistors 641 and 642 are turned on via the power gate line PGP[Y] (time t42). At this time, data is complementarily held in the volatile storage nodes P and PB, and data "1" is restored to the volatile storage node P.

[0183] When peripheral recovery in the peripheral recovery circuit 611 is completed, the corresponding storage transistors 115 and 125 are turned off via the storage selection line ST[Y], and the NV control signal CTRL transitions from a high level to a low level (time t43 ).

[0184] As described above, in the sixth embodiment above, the data held in the resistance random access memory 131 is restored to the peripheral restoration circuit 611 via the corresponding storage lines SL[X] and SLB[X], and the restoration data NVQ[X] is read from the peripheral restoration circuit 611. Therefore, it is not necessary to operate the SRAM 111 to read the data held in the resistance random access memory 131, and power consumption can be reduced.

[0185] <7. Seventh Implementation Method>

[0186] In the first embodiment described above, there is no limitation on the driving voltage of the SRAM 111 and the driving voltage of the RRAM 131. In the seventh embodiment, the RRAM 131 is driven based on a voltage higher than the driving voltage of the SRAM 111.

[0187] Fig.18 is a diagram showing an example of the configuration of a memory cell and a peripheral circuit of a storage device according to a seventh embodiment.

[0188] In the drawing, instead of the NV control unit 112 of the above-described first embodiment, the storage device 700 includes an NV control / level shift unit 712. Other components of the storage device 700 of the seventh embodiment are similar to those of the storage device 100 of the above-described first embodiment.

[0189] The NV control / level shift unit 712 controls storage and recovery in the resistive random access memory 131 based on the storage control signal SP and the NV control signal CTRL. The power supply voltage VDDH is supplied to the NV control / level shift unit 712. The power supply voltage VDDH is higher than the power supply voltage for driving the SRAM 111. Here, the NV control / level shift unit 712 controls the potential of each storage line SL[X] and SLB[X] and the potential of the NV control line CTL[X] based on the data detected by the sense amplifier 142 to perform storage in the non-volatile storage nodes M and MB. At this time, the NV control / level shift unit 712 can shift the level of the driving voltage of each of the storage lines SL[X] and SLB[X] and the NV control line CTL[X] to a level higher than the driving voltage of the SRAM 111 based on the power supply voltage VDDH.

[0190] In addition, depending on the characteristics of the corresponding variable resistance elements 135 and 145, only the voltage applied via the storage selection line ST[Y] may be increased. Alternatively, not only the voltage applied via the storage selection line ST[Y] but also the voltages of the power supply voltage VDDH, the storage control signal SP, and the NV control signal CTRL may be made higher depending on the characteristics of the corresponding variable resistance elements 135 and 145. These increases in voltage may be caused by Fig.10 The power control circuit 156 shown in FIG.

[0191] As described above, in the seventh embodiment, the RRAM 131 is driven based on a voltage higher than the driving voltage of the SRAM 111. Therefore, high voltage driving of the RRAM 131 and low voltage driving of the SRAM 111 can be processed.

[0192] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the various contents in the embodiments and the various contents specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the scope of the present technology. In addition, the effects described in this specification are only examples and not restrictive, and some other effects can be achieved.

[0193] It should be noted that the present technology can also have the following configurations.

[0194] (1) A storage device comprising:

[0195] a volatile memory cell including a volatile storage node that complementarily holds data and an access transistor connected between the volatile storage node and a bit line; and

[0196] A nonvolatile memory cell includes a nonvolatile memory node that complementarily holds data, a first switch connected between the nonvolatile memory node and a memory line, and a second switch connected between the nonvolatile memory node and a volatile memory node.

[0197] (2) The storage device according to (1), wherein:

[0198] The first switch includes a storage transistor that stores data held in the volatile storage node into the nonvolatile storage node via the storage line, and

[0199] The second switch includes a recovery transistor that restores data held in the nonvolatile storage node to the volatile storage node.

[0200] (3) The storage device according to (1) or (2), wherein:

[0201] The volatile memory unit includes a static random access memory (SRAM), and

[0202] The non-volatile memory cell includes a resistive random access memory.

[0203] (4) The storage device according to (2), wherein the volatile storage unit comprises:

[0204] Flip-flops, with volatile storage nodes,

[0205] The non-volatile memory cells include:

[0206] A variable resistance element whose resistance changes based on the application of voltage, and

[0207] One terminal of the storage transistor and one terminal of the recovery transistor are connected to one terminal of the variable resistance element.

[0208] (5) The storage device according to (4), wherein:

[0209] The flip-flop includes an inverter pair, output terminals of the inverter pair are connected to input terminals of each other, a connection point between the output and input of the inverter pair is used as a volatile storage node, and

[0210] A connection point between the variable resistance element, the storage transistor, and the recovery transistor is used as a nonvolatile storage node.

[0211] (6) The storage device according to claim 5, wherein data held in the volatile storage node is sequentially stored in the nonvolatile storage node via the storage line and the storage transistor.

[0212] (7) The memory device according to (5), wherein data held in the nonvolatile memory node is restored to the volatile memory node via the restore transistor.

[0213] (8) The storage device according to (5), further comprising:

[0214] word lines, which turn the access transistors on and off;

[0215] a restore select line that turns the restore transistor on and off;

[0216] a memory select line that turns the memory transistor on and off; and

[0217] A non-volatile (NV) control line is connected to the variable resistance element.

[0218] (9) The storage device according to (8), further comprising:

[0219] a sense amplifier to detect data read from the volatile memory cell; and

[0220] The NV control unit controls a potential of the storage line and a potential of the NV control line based on data detected by the sense amplifier, and stores the data held in the volatile storage node in the nonvolatile storage node via the storage transistor.

[0221] (10) The storage device according to (9), wherein:

[0222] When data held in the volatile storage node is stored in the nonvolatile storage node, the NV control unit complementarily sets the potential of the storage line and transitions the potential of the NV control line between a high level and a low level depending on the data detected by the sense amplifier.

[0223] (11) The storage device according to (10), wherein:

[0224] The NV control unit drives the nonvolatile memory cell based on a voltage higher than a driving voltage of the volatile memory cell.

[0225] (12) The storage device according to any one of (5) to (10), further comprising:

[0226] A power gate transistor performs power gating of the inverter.

[0227] (13) The storage device according to any one of (5) to (10), wherein:

[0228] The driving force of the storage transistor is greater than the driving force of a transistor to be used in an inverter, the driving force of an access transistor, and the driving force of a restore transistor.

[0229] (14) The storage device according to (8), further comprising:

[0230] A memory unit, in which a volatile memory unit and a nonvolatile memory unit are arranged, wherein:

[0231] The memory cells are arranged in a matrix in row and column directions.

[0232] (15) The storage device according to (14), wherein:

[0233] Each of the word line, the restore selection line, and the storage selection line extends in a row direction, and

[0234] Each of the bit line, the storage line, and the NV control line extends in the column direction.

[0235] (16) The storage device according to any one of (1) to (15), wherein:

[0236] The volatile memory cell includes a dual-port SRAM.

[0237] (17) The storage device according to any one of (1) to (15), wherein:

[0238] The volatile memory cell includes a two-port SRAM.

[0239] (18) The storage device according to any one of (1) to (17), further comprising:

[0240] The peripheral recovery circuit reads the data held in the nonvolatile storage node to the outside of the volatile storage unit.

[0241] (19) The storage device according to (18), wherein:

[0242] The data held in the nonvolatile storage node is restored to the peripheral recovery circuit sequentially via the storage transistor and the storage line.

[0243] Reference Symbols List

[0244] 100 to 700 storage devices

[0245] 101 Memory Unit

[0246] 102 column processing units

[0247] 111SRAM

[0248] 121 Trigger

[0249] 131 Resistive Random Access Memory

[0250] 112 NV control unit

[0251] 122 Precharge Circuit

[0252] 132 Write drive

[0253] 142 Sense Amplifier

[0254] 113,123 Inverter

[0255] 133,143 Access transistors

[0256] 114,124 Recovery transistor

[0257] 115,125 memory transistors

[0258] 135,145 variable resistance element

[0259] 141 Power Gate Transistor

[0260] BL,BLB bit line

[0261] WL word line

[0262] SL, SLB storage line

[0263] CTL NV control line

[0264] SR Restore Select Line

[0265] ST storage select line

[0266] PG Power Gate Line

[0267] SP storage control signal

[0268] CTRL NV control signal

[0269] PRE Precharge enable signal

[0270] WE Write Enable signal

[0271] SAE sensing enable signal.

Claims

1. A storage device, comprising: A volatile memory cell including a volatile storage node that complementarily holds data and an access transistor connected between the volatile storage node and a bit line; as well as A nonvolatile memory cell includes a nonvolatile memory node that complementarily holds the data, a first switch connected between the nonvolatile memory node and a storage line, and a second switch connected between the nonvolatile memory node and the volatile memory node.

2. The storage device according to claim 1, wherein: The first switch includes a storage transistor that stores data held in the volatile storage node into the nonvolatile storage node via the storage line, and The second switch includes a recovery transistor that restores data held in the nonvolatile storage node to the volatile storage node.

3. The storage device according to claim 1, wherein: The volatile memory unit includes a static random access memory (SRAM), and the nonvolatile memory unit includes a resistive random access memory.

4. The storage device according to claim 2, wherein: The volatile storage unit includes a trigger having the volatile storage node, The non-volatile storage unit comprises: a variable resistance element whose resistance changes based on voltage application, and One end of the storage transistor and one end of the recovery transistor are connected to one end of the variable resistance element.

5. The storage device according to claim 4, wherein: The flip-flop includes an inverter pair whose outputs are connected to each other's inputs, A connection point between the output and the input of the inverter pair is used as the volatile storage node, and A connection point among the variable resistance element, the storage transistor, and the recovery transistor is used as the nonvolatile storage node.

6. The storage device according to claim 5, wherein: The data held in the volatile storage node is sequentially stored in the nonvolatile storage node via the storage line and the storage transistor.

7. The storage device according to claim 5, wherein: The data held in the nonvolatile storage node is restored to the volatile storage node via the recovery transistor.

8. The storage device according to claim 5, further comprising: a word line that turns the access transistor on and off; a restore select line to turn the restore transistor on and off; a storage select line that turns the storage transistor on and off; as well as A non-volatile (NV) control line is connected to the variable resistance element.

9. The storage device according to claim 8, further comprising: a sense amplifier to detect data read from the volatile memory cell; as well as An NV control unit controls a potential of the storage line and a potential of the NV control line based on the data detected by the sense amplifier, and stores the data held in the volatile storage node in the nonvolatile storage node via the storage transistor.

10. The storage device according to claim 9, wherein: When the data held in the volatile storage node is stored in the nonvolatile storage node, the NV control unit complementarily sets the potential of the storage line and transitions the potential of the NV control line between a high level and a low level depending on the data detected by the sense amplifier.

11. The storage device according to claim 10, wherein: The NV control unit drives the nonvolatile memory cell based on a voltage higher than a driving voltage of the volatile memory cell.

12. The storage device according to claim 5, further comprising: A power gate transistor performs power gating of the inverter.

13. The storage device according to claim 5, wherein: The driving force of the storage transistor is larger than the driving force of a transistor to be used in the inverter, the driving force of the access transistor, and the driving force of the recovery transistor.

14. The storage device according to claim 8, further comprising: A memory unit, in which the volatile memory unit and the nonvolatile memory unit are arranged, wherein: The memory cells are arranged in a matrix in row and column directions.

15. The storage device according to claim 14, wherein: Each of the word line, the restore selection line, and the storage selection line extends in the row direction, and Each of the bit line, the storage line, and the NV control line extends in the column direction.

16. The storage device according to claim 1, wherein: The volatile memory unit includes a dual-port SRAM.

17. The storage device according to claim 1, wherein: The volatile memory unit includes a two-port SRAM.

18. The storage device according to claim 1, further comprising: The peripheral recovery circuit reads the data stored in the nonvolatile storage node to the outside of the volatile storage unit.

19. The storage device according to claim 18, wherein: The data held in the nonvolatile storage node is restored to the peripheral recovery circuit sequentially via a storage transistor and the storage line.

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