Tracking sample completion in video coding

Abstract

An apparatus configured to decode video data includes a shared memory and one or more processors configured to execute a plurality of video decoding cores. At least one of the plurality of video decoding cores is in communication with the shared memory, and each of the plurality of video decoding cores is configured to: track completion of decoding samples of one or more regions of a frame of video data; writing information to the shared memory, the information indicating completion of decoding the samples of the one or more regions of the frame of video data; reading the information in the shared memory before decoding a subsequent region of the video data frame; and determining whether to decode the subsequent region of the frame of video data based on the information.

Description

[0001] This application claims the benefit of U.S. patent application No. 17 / 815,486, filed on July 27, 2022, the entire contents of which are incorporated herein by reference. Technical Field

[0002] The present disclosure relates to video encoding and video decoding. Background Art

[0003] Digital video capabilities may be incorporated into a wide variety of devices, including digital televisions, digital live broadcast systems, wireless broadcast systems, personal digital assistants (PDAs), laptop or desktop computers, tablet computers, e-book readers, digital cameras, digital recording devices, digital media players, video game devices, video game consoles, cellular or satellite wireless telephones (so-called "smart phones"), video teleconferencing devices, video streaming devices, etc. Digital video devices implement video coding techniques, such as those described in the standards defined by MPEG-2, MPEG-4, ITU-T H.263, ITU-T H.264 / MPEG-4 (Part 10, Advanced Video Coding (AVC)), ITU-T H.265 / High Efficiency Video Coding (HEVC), and extensions of such standards as well as proprietary video codecs / formats such as AOMedia Video 1 (AV1) developed by the Alliance for Open Media. By implementing such video coding techniques, video devices may more efficiently send, receive, encode, decode, and / or store digital video information.

[0004] Video coding techniques include spatial (intra-picture) prediction and / or temporal (inter-picture) prediction to reduce or remove redundancy inherent in video sequences. For block-based video coding, a video slice or video tile (e.g., a video picture or a portion of a video picture) may be divided into video blocks, which may also be referred to as coding blocks, super blocks, coding tree units (CTUs), coding units (CUs), and / or coding nodes. Video blocks in slices of intra-frame coding (I) of a picture are encoded using spatial prediction relative to reference samples (also referred to as prediction samples) in neighboring blocks in the same picture. Video blocks in slices of inter-frame coding (P or B) of a picture may use spatial prediction relative to reference samples in neighboring blocks in the same picture or temporal prediction relative to reference samples in other reference pictures. Pictures may be referred to as frames, and reference pictures may be referred to as reference frames. Summary of the invention

[0005] In general, this disclosure describes techniques for encoding and decoding video data. Specifically, this disclosure describes techniques for tracking completion of decoding (eg, encoding or decoding) samples and / or pixels of video data in a multi-core video decoding system.

[0006] In some example video decoding systems, when performing a prediction process on a sample of video data in a current frame, the video decoding system may only need to read back samples from a previously decoded frame. In this example, all decoded samples are readily available to the video decoding system. However, in some video decoding systems that implement codecs that support intra-frame block copying or other similar intra-frame decoding techniques, the video decoding system may be configured to perform a prediction process on samples in the current frame using other samples in the same frame. Such samples may not be easily available because there is no guarantee that the portion of the frame required to perform a prediction process on a sample has been completed (e.g., has been encoded and reconstructed or has been decoded). The problem becomes more difficult when a multi-core video decoding system is used to decode multiple areas of a frame in parallel.

[0007] To address this problem, the present disclosure describes techniques and devices in which a video decoding core in a multi-core video decoding system is configured to track the completion of decoding samples / pixels of video data. The video decoding core may write information to a shared memory, wherein the information indicates the completion of decoding samples / pixels in a video data frame. The shared memory may be accessed by each video decoding core of the multi-core video decoding system. In this way, when performing an intra-frame prediction process similar to intra-frame block copying, the video decoding core may access information in the shared memory to determine whether the samples / pixels required for the prediction process have been completed and are available. If so, the video decoding core may continue the prediction process. If the sample / pixel is not available, the video decoding core may wait until information indicating that the sample / pixel is completed and available is written to the shared memory.

[0008] In one example, the present disclosure describes a device configured to decode video data, the device comprising a shared memory and one or more processors configured to execute a plurality of video decoding cores, each of the plurality of video decoding cores communicating with the shared memory. At least one of the plurality of video decoding cores is configured to: track completion of decoding samples of one or more regions of a video data frame; write information to the shared memory indicating completion of decoding samples of one or more regions of the video data frame; read the information in the shared memory before decoding a subsequent region of the video data frame; and determine whether to decode a subsequent region of the video data frame based on the information.

[0009] In another example, the present disclosure describes a method for decoding video data, the method comprising: tracking the completion of decoding samples of one or more regions of a video data frame; writing information to a shared memory, the information indicating the completion of decoding samples of one or more regions of the video data frame; reading the information in the shared memory before decoding a subsequent region of the video data frame; and determining whether to decode the subsequent region of the video data frame based on the information.

[0010] In another example, the present disclosure describes an apparatus configured to decode video data, the apparatus comprising: a component for tracking completion of decoding samples of one or more regions of a video data frame; a component for writing information to a shared memory, the information indicating completion of decoding samples of one or more regions of the video data frame; a component for reading the information in the shared memory before decoding a subsequent region of the video data frame; and a component for determining whether to decode a subsequent region of the video data frame based on the information.

[0011] In another example, the present disclosure describes a non-transitory computer-readable storage medium storing instructions that, when executed, cause one or more processors configured to decode video data to: track completion of decoding samples of one or more regions of a video data frame; write information to a shared memory indicating completion of decoding samples of one or more regions of the video data frame; read the information in the shared memory before decoding a subsequent region of the video data frame; and determine whether to decode the subsequent region of the video data frame based on the information.

[0012] In another example, the present disclosure describes a device configured to encode video data, the device including a shared memory and one or more processors configured to execute a plurality of video encoding cores, each of the plurality of video encoding cores communicating with the shared memory. At least one of the plurality of video encoding cores is configured to: track completion of encoding and reconstructing samples of one or more regions of a video data frame; write information to the shared memory indicating completion of encoding and reconstructing samples of one or more regions of the video data frame; read the information in the shared memory before encoding a subsequent region of the video data frame; and determine whether to encode the subsequent region of the video data frame based on the information.

[0013] The details of one or more examples are set forth in the accompanying drawings and the description below. Other features, objects, and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Figure 1is a block diagram illustrating an example video encoding and decoding system that may perform the techniques of this disclosure.

[0015] Figure 2 is a block diagram illustrating an example video encoder that may perform the techniques of this disclosure.

[0016] Figure 3 is a block diagram illustrating an example video decoder that may perform the techniques of this disclosure.

[0017] Figure 4 is a conceptual diagram illustrating the decoding process of a single processing core.

[0018] Figure 5 is a conceptual diagram illustrating a decoding process of multiple processing cores.

[0019] Figure 6 is a conceptual diagram illustrating a first example of pixel / sample tracking according to the technology of the present disclosure.

[0020] Figure 7 is a conceptual diagram illustrating a sample image tile and raster scanning in a 2D block.

[0021] Figure 8 is a conceptual diagram illustrating a second example of pixel / sample tracking according to the technology of the present disclosure.

[0022] Fig. 9 is a conceptual diagram illustrating a third example of pixel / sample tracking according to the technology of the present disclosure.

[0023] Fig.10 is a conceptual diagram illustrating a third example of pixel / sample tracking in more detail.

[0024] Fig.11 is a conceptual diagram illustrating a fourth example of pixel / sample tracking according to the technology of the present disclosure.

[0025] Fig.12 is a conceptual diagram illustrating a fifth example of pixel / sample tracking according to the technology of the present disclosure.

[0026] Fig.13 is a conceptual diagram illustrating a fifth example of pixel / sample tracking in more detail.

[0027] Fig.14 is a table illustrating example pointer statistics for various example techniques of the present disclosure.

[0028] Fig.15 is a conceptual diagram illustrating an example of partial tile tracking at a tile edge.

[0029] Fig.16 is a conceptual diagram illustrating pixel / sample tracking in conjunction with partial tile tracking according to techniques of this disclosure.

[0030] Fig.17 is a flow chart illustrating an example decoding method according to techniques of this disclosure.

[0031] Fig.18 is a flow chart illustrating another example decoding method according to the techniques of this disclosure. DETAILED DESCRIPTION

[0032] In general, this disclosure describes techniques for encoding and decoding video data. Specifically, this disclosure describes techniques for tracking completion of decoding (eg, encoding or decoding) samples and / or pixels of video data in a multi-core video decoding system.

[0033] In some example video decoding systems, when performing a prediction process on a sample of video data in a current frame, the video decoding system may only need to read back samples from a previously decoded frame. In this example, all decoded samples are readily available to the video decoding system. However, in some video decoding systems that implement codecs that support intra-frame block copying or other similar intra-frame decoding techniques, the video decoding system may be configured to perform a prediction process on samples in the current frame using other samples in the same frame. Such samples may not be easily available because there is no guarantee that the portion of the frame required to perform a prediction process on a sample has been completed (e.g., has been encoded and reconstructed or has been decoded). The problem becomes more difficult when a multi-core video decoding system is used to decode multiple areas of a frame in parallel.

[0034] To address this problem, the present disclosure describes techniques and devices in which a video decoding core in a multi-core video decoding system is configured to track the completion of decoding samples / pixels of video data. The video decoding core may write information to a shared memory, wherein the information indicates the completion of decoding samples / pixels in a frame of video data. The shared memory may be accessed by each video decoding core of the multi-core video decoding system.

[0035] Thus, when performing an intra prediction process similar to intra block copying, the video decoding core can access information in the shared memory to determine whether the samples / pixels required for the prediction process have been completed and are available. If so, the video decoding core can continue the prediction process. If the samples / pixels are not available, the video decoding core can wait until information indicating that the samples / pixels are completed and available is written to the shared memory.

[0036] Figure 1is a block diagram illustrating an example video encoding and decoding system 100 that may perform the techniques of the present disclosure to track pixel completion in a multi-core video encoding and / or video decoding system. The techniques of the present disclosure generally relate to transcoding (encoding and / or decoding) video data. Generally, video data includes any data used to process video. Thus, video data may include unencoded raw video, encoded video, decoded (e.g., reconstructed) video, and video metadata, such as signaling data.

[0037] like Figure 1 As shown, in this example, system 100 includes a source device 102 that provides encoded video data to be decoded and displayed by a destination device 116. Specifically, source device 102 provides video data to destination device 116 via computer-readable medium 110. Source device 102 and destination device 116 may include any of a wide variety of devices, including desktop computers, notebook (i.e., laptop) computers, mobile devices, tablet computers, set-top boxes, handheld phones such as smartphones, televisions, cameras, display devices, digital media players, video game consoles, video streaming devices, broadcast receiver devices, etc. In some cases, source device 102 and destination device 116 may be equipped for wireless communication and may therefore be referred to as wireless communication devices.

[0038] exist Figure 1 In the example of , the source device 102 includes a video source 104, a memory 106, a video encoder 200, and an output interface 108. The destination device 116 includes an input interface 122, a video decoder 300, a memory 120, and a display device 118. According to the present disclosure, the video encoder 200 of the source device 102 and the video decoder 300 of the destination device 116 can be configured to apply a technique for encoding and decoding chroma samples of chroma blocks of video data using chroma predicted from luma. Therefore, the source device 102 represents an example of a video encoding device, and the destination device 116 represents an example of a video decoding device. In other examples, the source device and the destination device may include other components or arrangements. For example, the source device 102 may receive video data from an external video source such as an external camera. Similarly, the destination device 116 may be docked with an external display device instead of including an integrated display device.

[0039] like Figure 1The system 100 shown is only one example. In general, any digital video encoding and / or decoding device can use a multi-core system configured to track pixel completion to perform techniques for encoding and decoding. The source device 102 and the destination device 116 are only examples of such decoding devices, wherein the source device 102 generates decoded video data for sending to the destination device 116. The present disclosure refers to a "decoding" device as a device that performs decoding (e.g., encoding and / or decoding) of data. Therefore, the video encoder 200 and the video decoder 300 represent examples of decoding devices, specifically, video encoders and video decoders, respectively. In some examples, the source device 102 and the destination device 116 can operate in a substantially symmetrical manner, so that each of the source device 102 and the destination device 116 includes video encoding and decoding components. Therefore, the system 100 can support one-way or two-way video transmission between the source device 102 and the destination device 116, for example, for video streaming, video playback, video broadcasting, or video telephony.

[0040] Typically, video source 104 represents the source of video data (i.e., uncoded raw video data), and a series of pictures (also referred to as "frames") of the order of video data are provided to video encoder 200, which encodes the data for pictures. Video source 104 of source device 102 may include a video capture device, such as a camera, a video archive containing previously captured raw video, and / or a video feed interface for receiving video from a video content provider. As another alternative, video source 104 may generate computer graphics-based data as source video, or a combination of real-time video, archived video, and computer-generated video. In each case, video encoder 200 encodes captured, pre-captured, or computer-generated video data. Video encoder 200 may rearrange pictures from the received order (sometimes referred to as "display order") to a decoding order for decoding. Video encoder 200 may generate a bitstream including encoded video data. Source device 102 may then output the encoded video data onto computer-readable medium 110 via output interface 108 to be received and / or retrieved by, for example, input interface 122 of destination device 116 .

[0041] The memory 106 of the source device 102 and the memory 120 of the destination device 116 represent general purpose memories. In some examples, the memories 106, 120 may store raw video data, for example, raw video from the video source 104 and raw decoded video data from the video decoder 300. Additionally or alternatively, the memories 106, 120 may store software instructions that can be executed by, for example, the video encoder 200 and the video decoder 300, respectively. Although the memory 106 and the memory 120 are shown separately from the video encoder 200 and the video decoder 300 in this example, it should be understood that the video encoder 200 and the video decoder 300 may also include internal memories for functionally similar or equivalent purposes. In addition, the memories 106, 120 may store encoded video data, for example, output from the video encoder 200 and input to the video decoder 300. In some examples, portions of the memories 106, 120 may be allocated as one or more video buffers, for example, to store raw decoded and / or encoded video data.

[0042] The computer-readable medium 110 may represent any type of medium or device capable of transmitting encoded video data from the source device 102 to the destination device 116. In one example, the computer-readable medium 110 represents a communication medium that enables the source device 102 to directly transmit the encoded video data to the destination device 116 in real time, for example, via a radio frequency network or a computer-based network. According to a communication standard such as a wireless communication protocol, the output interface 108 may modulate the transmission signal including the encoded video data, and the input interface 122 may demodulate the received transmission signal. The communication medium may include any wireless or wired communication medium, such as a radio frequency (RF) spectrum or one or more physical transmission lines. The communication medium may form part of a packet-based network such as a local area network, a wide area network, or a global network (such as the Internet). The communication medium may include a router, a switch, a base station, or any other equipment that may be useful for facilitating communication from the source device 102 to the destination device 116.

[0043] In some examples, source device 102 may output the encoded data from output interface 108 to storage device 112. Similarly, destination device 116 may access the encoded data from storage device 112 via input interface 122. Storage device 112 may include any of a variety of distributed or locally accessed data storage media, such as a hard drive, a Blu-ray disc, a DVD, a CD-ROM, flash memory, volatile or non-volatile memory, or any other suitable digital storage medium for storing encoded video data.

[0044] In some examples, source device 102 may output the encoded video data to file server 114 or another intermediate storage device that may store the encoded video data generated by source device 102. Destination device 116 may access the stored video data from file server 114 via streaming or downloading.

[0045] The file server 114 may be any type of server device capable of storing encoded video data and sending the encoded video data to the destination device 116. The file server 114 may represent a web server (e.g., for a website), a server configured to provide a file delivery protocol service (such as a file delivery protocol (FTP) or a file delivery over unidirectional transport (FLUTE) protocol), a content delivery network (CDN) device, a hypertext transfer protocol (HTTP) server, a multimedia broadcast multicast service (MBMS) or an enhanced MBMS (eMBMS) server, and / or a network attached storage (NAS) device. The file server 114 may additionally or alternatively implement one or more HTTP streaming protocols, such as dynamic adaptive streaming over HTTP (DASH), HTTP live streaming (HLS), real-time streaming protocol (RTSP), HTTP dynamic streaming, etc.

[0046] The destination device 116 may access the encoded video data from the file server 114 through any standard data connection, including an Internet connection. This may include a wireless channel (e.g., a Wi-Fi connection), a wired connection (e.g., a digital subscriber line (DSL), a cable modem, etc.), or a combination of both, suitable for accessing the encoded video data stored on the file server 114. The input interface 122 may be configured to operate according to any one or more of the various protocols discussed above for retrieving or receiving media data from the file server 114 or other such protocols for retrieving media data.

[0047] Output interface 108 and input interface 122 may represent wireless transmitters / receivers, modems, wired networking components (e.g., Ethernet cards), wireless communication components that operate according to any of the various IEEE 802.11 standards, or other physical components. In examples where output interface 108 and input interface 122 include wireless components, output interface 108 and input interface 122 may be configured to communicate data (such as encoded video data) according to a cellular communication standard (such as 4G, 4G-LTE (Long Term Evolution), Advanced LTE, 5G, etc.). In some examples where output interface 108 includes a wireless transmitter, output interface 108 and input interface 122 may be configured to communicate data (such as encoded video data) according to other wireless standards (such as IEEE 802.11 specifications, IEEE 802.15 specifications (e.g., ZigBee™ ),Bluetooth ™ Standards, etc.) to transfer data (such as encoded video data). In some examples, source device 102 and / or destination device 116 may include corresponding system-on-chip (SoC) devices. For example, source device 102 may include a SoC device for performing functionality belonging to video encoder 200 and / or output interface 108, and destination device 116 may include a SoC device for performing functionality belonging to video decoder 300 and / or input interface 122.

[0048] The techniques of the present disclosure may be applied to video decoding to support any of a variety of multimedia applications, such as over-the-air television broadcasting, cable television transmission, satellite television transmission, Internet streaming video transmission (such as Dynamic Adaptive Streaming over HTTP (DASH)), digital video encoded onto a data storage medium, decoding of digital video stored on a data storage medium, or other applications.

[0049] The input interface 122 of the destination device 116 receives an encoded video bitstream from the computer-readable medium 110 (e.g., a communication medium, a storage device 112, a file server 114, etc.). The encoded video bitstream may include signaling information defined by the video encoder 200 and also used by the video decoder 300, such as syntax elements with values ​​describing characteristics and / or processing of video blocks or other decoding units (e.g., slices, pictures, groups of pictures, sequences, etc.). The display device 118 displays decoded pictures of the decoded video data to a user. The display device 118 may represent any of a variety of display devices, such as a liquid crystal display (LCD), a plasma display, an organic light emitting diode (OLED) display, or another type of display device.

[0050] Despite Figure 1 200 and 300 may be integrated with an audio encoder and / or an audio decoder and may include appropriate MUX-DEMUX units or other hardware and / or software to process a multiplexed stream including both audio and video in a common data stream. If applicable, the MUX-DEMUX unit may follow the ITU H.223 multiplexer protocol or other protocols, such as the User Datagram Protocol (UDP).

[0051] The video encoder 200 and the video decoder 300 may be implemented as any of a variety of suitable encoder and / or decoder circuits, such as one or more microprocessors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field programmable gate arrays (FPGAs), discrete logic, software, hardware, firmware, or any combination thereof. When the technology is partially implemented in software, the device may store instructions for the software in an appropriate non-transitory computer-readable medium and execute the instructions in hardware using one or more processors to perform the technology of the present disclosure. Each of the video encoder 200 and the video decoder 300 may be included in one or more encoders or decoders, any of which may be integrated as part of a combined encoder / decoder (codec) in a corresponding device. A device including the video encoder 200 and / or the video decoder 300 may include an integrated circuit, a microprocessor, and / or a wireless communication device (such as a cellular phone).

[0052] In examples of the present disclosure, the video encoder 200 and the video decoder 300 may be configured as multiple video decoding cores or video encoding cores (e.g., typically video decoding cores). Each of the multiple video decoding cores of the video encoder 200 and the video decoder 300 may be configured to operate on different regions of the video data in parallel. For example, each processing core of the video encoder 200 and / or the video decoder 300 may be configured to operate on predefined rows of video data in parallel. These predefined rows may be rectangular regions of video data (e.g., samples or pixels), such as maximum coding unit (LCU) rows, coding tree unit (CTU) rows, macroblock rows, superblock rows, tile rows, brick rows, or any other type of predefined region of video data of a video compression standard or video decoding format.

[0053] As will be explained in more detail below, the present disclosure describes example techniques and structures including the following operations: tracking completion of pixel and / or sample decoding; and storing data indicating completion of decoding or encoding (e.g., encoding and subsequent encoder-side reconstruction) to a shared memory accessible by all video decoding cores or multi-core video encoders or video decoders. The video decoding cores can be configured to access the data stored to the shared memory to determine whether certain pixels or samples have completed decoding, so that the decoded data can be used by the video decoding cores to perform intra-frame decoding techniques (e.g., intra-frame block copy decoding).

[0054] In the examples described below, the video encoder 200 and the video decoder 300 may be configured to track the completion of encoding and decoding pixels in one or more regions, including blocks, tiles, tile rows, and vertical columns in a video data block. In some examples, such "regions" are divided into continuous (e.g., overlapping) ways for applying decoding techniques to video data frames. Generally speaking, video frames can be divided in one or more tree structures based on a predefined maximum block size (such as LCU, CTU, macroblock, superblock, etc.). Generally speaking, these "maximum block sizes" may be referred to as "codec tiles". Each video decoding core of a multi-core video decoding system can process a codec tile row of video data.

[0055] In other examples of the present disclosure, the area over which the completion of encoding and decoding is tracked is not continuous for the division of the frame. Specifically, the video encoder 200 and the video decoder 300 may be configured to write the values ​​of the decoded samples / pixels out to a memory (e.g., a shared memory) in fixed block sizes. These fixed block sizes for writing data to the memory are referred to as memory tiles or memory blocks. In some examples, the video encoder 200 and the video decoder 300 may be configured to apply a compression scheme to the fixed memory tiles when writing data (e.g., decoded and / or reconstructed sample / pixel values) to the shared memory. One example compression scheme is Universal Bandwidth Compression (UBWC) developed by Qualcomm, Inc., San Diego, CA.

[0056] In some examples of the present disclosure, the video encoder 200 and the video decoder 300 may operate according to a video coding format (such as AOMedia Video 1 (AV1) or an extension thereof) and a successor coding format (e.g., AV2) that may be currently developed or will soon be implemented. In other examples, the video encoder 200 and the video decoder 300 may operate according to other proprietary or industry standards. However, the techniques of the present disclosure are not limited to any particular coding standard and / or video coding format. In general, the video encoder 200 and the video decoder 300 may be configured to perform the techniques of the present disclosure in conjunction with any video coding technique that uses a multi-core encoding system and / or is configured to perform intra-coding techniques such as intra-block copying.

[0057] Typically, the video encoder 200 and the video decoder 300 may perform block-based decoding of a picture. The term "block" generally refers to a structure that includes data to be processed (e.g., to be encoded, decoded, or otherwise used in an encoding and / or decoding process). For example, a block may include a two-dimensional matrix of samples of luminance and / or chrominance data. Typically, the video encoder 200 and the video decoder 300 may decode video data represented in a YUV (e.g., Y, Cb, Cr) format. That is, instead of decoding red, green, and blue (RGB) data for samples of a picture, the video encoder 200 and the video decoder 300 may decode luminance components and chrominance components, wherein the chrominance components may include both red hue chrominance components and blue hue chrominance components. In some examples, the video encoder 200 converts the received RGB format data to a YUV representation before encoding, and the video decoder 300 converts the YUV representation to an RGB format. Alternatively, a pre-processing and post-processing unit (not shown) may perform these conversions.

[0058] The present disclosure may generally relate to the decoding (e.g., encoding and decoding) of a picture to include the process of encoding or decoding data of the picture. Similarly, the present disclosure may relate to the decoding of a block of a picture to include the process of encoding or decoding data for the block (e.g., prediction and / or residual decoding). The encoded video bitstream generally includes a series of values ​​of syntax elements for representing decoding decisions (e.g., decoding modes) and the partitioning of pictures into blocks. Therefore, references to the decoding of a picture or a block should generally be understood as the decoding values ​​of the syntax elements that form the picture or block.

[0059] The present disclosure may use "N×N" and "N by N" interchangeably to refer to the sample size of a block (such as a decoding block, a super block, or other block of video data) in terms of the vertical dimension and the horizontal dimension, for example, 16×16 samples or 16 by 16 samples. Generally, a 16×16 decoding block will have 16 samples in the vertical direction (y=16) and 16 samples in the horizontal direction (x=16). Similarly, an N×N decoding block typically has N samples in the vertical direction and N samples in the horizontal direction, where N represents a non-negative integer value. The samples in the decoding block may be arranged in rows and columns. In addition, the decoding block does not have to have the same number of samples in the horizontal direction as in the vertical direction (i.e., the decoding block may be non-square). For example, a decoding block may include N×M samples, where M is not necessarily equal to N.

[0060] When operating according to the AV1 codec, the video encoder 200 and the video decoder 300 may be configured to decode the video data in blocks. In AV1, the largest decoding block that can be processed is called a super block. In AV1, a super block can be 128×128 luma samples or 64×64 luma samples. However, in subsequent video decoding formats (e.g., AV2), super blocks may be defined by different (e.g., larger) luma sample sizes. In some examples, the super block is the top layer of the block quadtree. The video encoder 200 may further divide the super block into smaller decoding blocks. The video encoder 200 may divide the super block and other decoding blocks into smaller blocks using square or non-square partitions. Non-square blocks may include N / 2×N blocks, N×N / 2 blocks, N / 4×N blocks, and N×N / 4 blocks. The video encoder 200 and the video decoder 300 may perform separate prediction and transform processing on each decoding block.

[0061] AV1 also defines tiles of video data. A tile is a rectangular array of super blocks that can be decoded independently of other tiles. That is, the video encoder 200 and the video decoder 300 can encode and decode coded blocks within a tile, respectively, without using video data from other tiles. However, the video encoder 200 and the video decoder 300 can perform filtering across tile boundaries. The size of the tiles can be uniform or non-uniform. Tile-based decoding enables parallel processing and multi-threading specifically implemented by the encoder and decoder.

[0062] In some examples, the coding block includes one coding block for luma samples and two coding blocks for corresponding chroma samples for a picture having three sample arrays. In other examples, the coding block includes a single coding block of luma samples (e.g., for monochrome pictures). AV1 supports 4:0:0 chroma subsampling (e.g., monochrome), 4:2:0 chroma subsampling, 4:2:2 chroma subsampling, and 4:4:4 chroma subsampling (i.e., no chroma subsampling). AV1 can decode video data in a YUV color space, where Y is the luma component, U is the first chroma component (e.g., blue projection), and V is the second chroma component (e.g., red projection).

[0063] AV1 includes two general techniques for encoding and decoding coded blocks of video data. The two general techniques are intra prediction (e.g., intra prediction or spatial prediction) and inter prediction (e.g., inter prediction or temporal prediction). In the context of AV1, when an intra prediction mode is used to predict a block of a current frame of video data, the video encoder 200 and the video decoder 300 do not use video data from other frames of the video data. For most intra prediction modes, the video encoder 200 encodes a block of the current frame based on the difference between the sample values ​​in the current block and the prediction values ​​generated from the reference samples in the same frame. The video encoder 200 determines the prediction values ​​generated from the reference samples based on the intra prediction mode.

[0064] The difference between the current coded sample and the prediction value generated from the reference sample is called the residual. The video encoder 200 may encode the residual value (e.g., by transforming, quantizing, and entropy coding) in the coded video bitstream. The video decoder 300 may decode the residual value, determine the prediction value generated from the reference sample in the same manner as the video encoder 200, and add the prediction value generated from the reference sample to the residual to reconstruct the coded block. The intra prediction modes of AV1 include directional intra prediction, non-directional smoothing intra prediction, recursive filter intra prediction, luminance to chrominance (CFL) prediction, intra block copy, and color palette mode. The video encoder 200 may encode a syntax element indicating an intra prediction mode for the video decoder 300.

[0065] The video encoder 200 may typically use one of the aforementioned inter-prediction modes or intra-prediction modes (e.g., excluding color palette mode) to form a prediction block for a coded block. In general, the video encoder 200 subtracts the value of the sample of the coded block from the prediction sample determined according to one of the intra-prediction mode or the inter-prediction mode to determine a residual block. The video decoder 300 performs the inverse of this operation. The video decoder 300 determines the prediction sample in the same manner as the video encoder 200, but adds the decoded residual to the prediction sample to reconstruct the coded block.

[0066] To encode a block using directional intra prediction, the video encoder 200 may determine a particular directional intra prediction mode to determine a prediction sample. AV1 provides fifty-six directional intra prediction modes. When encoding a coded block using directional intra prediction, the video encoder 200 uses a directional predictor that projects each sample of the coded block to a prediction sample position. The prediction sample position may be a sub-pixel position (e.g., between samples). In this case, the video encoder may use interpolation (e.g., a 2-tap bilinear filter) to determine the value of the prediction sample.

[0067] In non-directional smooth intra prediction, the video encoder 200 may determine the prediction sample according to the DC prediction mode, the Paeth prediction mode, or by using one of the three smooth predictors. In the DC prediction mode, the video encoder 200 predicts the sample of the block from the average value of the available neighboring reference samples. In the Paeth prediction mode, the video encoder 200 uses one of the top reference sample, the left reference sample, or the upper left edge reference sample with the value closest to (top + left - upper left). The video encoder 200 may determine the three smooth predictors using quadratic interpolation in the horizontal direction, the vertical direction, or the average value of the interpolation in the horizontal and vertical directions.

[0068] The video encoder 200 may determine to use recursive filter intra prediction in the case where there is reduced spatial correlation between samples of a coding block and predicted samples at the edge of the coding block. To perform recursive intra prediction, the video encoder 200 may determine one of five filter intra modes. Each of the five intra modes is defined by a set of 7-tap filters that specify the correlation between samples in a 4×2 sub-block and seven adjacent neighboring samples. The video encoder 200 may determine one of the five types of intra filter modes at a block level and predict samples in a 4×2 sub-block.

[0069] The video encoder 200 may determine to use luma to chroma (CFL) to predict chroma samples from corresponding reconstructed luma samples. Specifically, the video encoder 200 may use the sum of the reconstructed luma samples in a sub-block (e.g., a 2×2 sub-block) of the luma block minus the average luma sample value of the block, and the DC prediction sample of the chroma block to determine the final prediction sample for predicting the chroma sample. The sum of the reconstructed luma samples in the sub-block (e.g., a 2×2 sub-block) of the luma block minus the average luma sample value of the block represents the "AC" contribution from the luma block.

[0070] In intra-block copy mode, the video encoder 200 and the video decoder 300 may predict a coding block using a previously reconstructed and / or decoded coding block as a reference block, where the reference block is in the same frame as the currently decoded coding block. The video encoder 200 may use a displacement vector (e.g., an x ​​and y displacement from the currently decoded coding block) to indicate the location of the previously reconstructed coding block. The intra-block copy mode is similar to the translational inter-frame prediction mode, but the intra-block copy mode uses a reference block from the same frame instead of a reference block in another frame. The intra-block copy mode may be particularly useful for so-called "screen content" video frames (e.g., such as a video showing the contents of a computer screen) that may include text, characters, and / or repeating textures.

[0071] As explained above, implementation of intra block copy decoding may be difficult in a multi-core video decoding system where each video decoding core operates on a different row of a codec tile. For example, if a second video decoding core (e.g., core 1) is instructed to decode a block of video data using intra block copy mode, and the displacement vector points to a block being decoded by a first video decoding core (e.g., core 0), the second video decoding core may not be able to determine whether the first video decoding core has completed decoding such that samples / pixels are available for the intra block copy process.

[0072] The present disclosure solves this problem by having the video decoding core track the completion of decoding samples of one or more regions of a video data frame and write information to a shared memory indicating the completion of decoding samples of one or more regions of the video data frame. The video decoding core can then read the information in the shared memory before decoding a subsequent region of the video data frame and determine whether to decode a subsequent region of the video data frame based on the information. For example, a portion of a subsequent region can be predicted using intra-frame block copying relative to a previous region. Therefore, if the video decoding core determines to use intra-frame block copying to predict a portion of a region of a video data frame relative to a portion of a previous region, the video decoding core can determine whether the previous region has completed decoding using the information in the shared memory.

[0073] In one example, the video decoding core may determine to decode a subsequent region of the video data frame based on information indicating that samples of one or more regions of the video data frame required to decode the subsequent region of the video data frame have been completed. In another example, the video decoding core may determine not to decode the subsequent region based on information indicating that samples of one or more regions of the video data frame required to decode the subsequent region of the video data frame have not been completed. The video decoding core may then wait for a certain period of time, and determine whether to decode the subsequent region of the video data frame based on the information after the period of time. Although described with reference to the intra-frame block copy mode, the technology of the present disclosure may be applicable to any intra-frame coding technology that allows one video decoding core to use decoded samples in the same frame decoded by another video core in a multi-core system.

[0074] In each of the aforementioned intra prediction modes, the video encoder 200 may generate a residual block by subtracting the sample value of the current decoding block from the predicted pixel generated according to one of the intra prediction modes. The color palette mode is considered to be another type of intra prediction mode because the color palette mode does not use the prediction sample generated from the reference sample value. However, the video encoder 200 and the video decoder 300 do not encode and decode the residual values ​​in the color palette mode, respectively. Instead, the video encoder 200 may associate code information indicating an index with a color palette for each sample / pixel of the decoding block. A color palette is a table of color values. The color palette mode may be useful for video data frames with a limited number of unique colors (e.g., screen content).

[0075] When using an inter-frame prediction mode to predict a block of a current frame of video data, the video encoder 200 and the video decoder 300 may use video data from one or more reference frames of the video data. The video encoder 200 may encode sample values ​​based on the difference (e.g., residual) between sample values ​​of the current block to be decoded and a prediction sample in a different frame (e.g., a reference frame). The reference frame may be before or after the current decoded frame in presentation order. The video encoder 200 may determine the prediction sample and the reference frame based on the inter-frame prediction mode.

[0076] As for intra prediction modes (except color palette mode), the video encoder 200 may encode residual values ​​(e.g., by transforming, quantizing, and entropy coding) in an encoded video bitstream. The video decoder 300 may decode the residual values, determine a prediction block in the same manner as the video encoder 200, and add the prediction block to the residual to reconstruct the coded block. The video encoder 200 may determine a specific inter prediction mode that provides the best rate-distortion cost from a plurality of inter prediction modes. The video encoder 200 may encode mode information, residual values ​​(e.g., the difference between the current sample and the predicted sample), and other block characteristics in the encoded video bitstream. The inter prediction modes of AV1 include translational motion compensation, affine motion compensation (e.g., warped motion compensation), overlapped block motion compensation (OBMC), and a composite inter-intra predictor mode.

[0077] For translational motion compensation, the video encoder 200 may use one or more motion vectors to generate a prediction block (e.g., a block including prediction samples). The video encoder 200 may typically perform a motion search to identify a reference block that closely matches a coding block, for example, in terms of the difference between the samples of the coding block and the prediction samples of the reference block. The video encoder 200 may calculate a difference metric using the sum of absolute differences (SAD), the sum of squared differences (SSD), the mean absolute difference (MAD), the mean squared difference (MSD), or other such difference calculations to determine whether the reference block closely matches the current CU. In some examples, the video encoder 200 may use unidirectional prediction or bidirectional prediction to predict the current coding block.

[0078] The video encoder 200 may also encode the motion vector using a prediction method. For example, the video encoder 200 may encode the motion vector with reference to other candidate motion vectors, including spatial motion vectors (e.g., motion vectors of neighboring blocks encoded using inter-frame prediction) or temporal motion vectors (e.g., motion vectors of co-located blocks in other pictures coded using inter-frame prediction). The candidate motion vector may be added to a dynamic motion vector reference list.

[0079] AV1 also provides an affine motion compensation mode. In the affine motion compensation mode, the video encoder 200 may determine a warp parameter to warp a reference block to obtain a prediction using a motion vector of a neighboring candidate. The warp parameter represents a non-translational or affine motion, such as enlargement or reduction, rotation, perspective motion, or other irregular motion types.

[0080] The video encoder 200 can use the OBMC mode to reduce prediction errors near block edges. In the OBMC mode, the video encoder 200 and the video decoder 300 determine prediction samples using prediction samples generated based on motion vectors from top neighboring blocks and / or left neighboring blocks. The video encoder 200 and the video decoder 300 can generate final prediction samples by combining such prediction samples using a smoothing filter.

[0081] In the composite inter-intra predictor mode, the video encoder 200 and the video decoder 300 may use both inter prediction and intra prediction techniques to form prediction samples. The two prediction samples may be combined using weighting coefficients.

[0082] After performing a prediction process (such as intra-frame prediction or inter-frame prediction of a block), the video encoder 200 may calculate residual data for the block. The residual data (such as a residual block) represents the sample-by-sample difference between the prediction samples formed using the corresponding prediction mode of the block and the block. The video encoder 200 may apply one or more transforms to the residual block to generate transformed data in the transform domain rather than in the sample domain. For example, the video encoder 200 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., ADST in reverse order), and an identity transform (IDTX). When an identity transform is used, the transform is skipped in one of the vertical or horizontal directions. In some examples, the transform process may be skipped. The video encoder 200 generates transform coefficients after applying one or more transforms.

[0083] As noted above, after any transforms that produce transform coefficients, the video encoder 200 may perform quantization of the transform coefficients. Quantization generally refers to a process in which transform coefficients are quantized to possibly reduce the amount of data used to represent the transform coefficients, thereby providing further compression. By performing the quantization process, the video encoder 200 may reduce the bit depth associated with some or all transform coefficients. For example, the video encoder 200 may round down an n-bit value to an m-bit value during quantization, where n is greater than m. In some examples, to perform quantization, the video encoder 200 may perform a bit-by-bit right shift of the value to be quantized.

[0084] After quantization, the video encoder 200 may entropy encode syntax elements (including syntax elements indicating the values ​​of the quantized transform coefficients). As another example, the video encoder 200 may entropy encode prediction syntax elements (e.g., motion information for inter-frame prediction or intra-frame mode information for intra-frame prediction). According to AV1, the video encoder 200 may be configured to perform entropy encoding using a symbol-to-symbol adaptive multi-symbol arithmetic decoder. The syntax elements in AV1 include an alphabet of N elements, and the context (e.g., a probability model) includes a set of N probabilities. The video encoder 200 may store the probabilities as a 15-bit cumulative distribution function (CDF). The video encoder 200 may perform recursive scaling with an update factor based on the size of the alphabet to update the context.

[0085] In this way, the video encoder 200 can generate a bitstream including encoded video data, for example, a syntax element describing the partition of a picture into blocks (e.g., super blocks and coding blocks) and prediction modes and / or residual information of the blocks. Finally, the video decoder 300 can receive the bitstream and decode the encoded video data.

[0086] In general, the video decoder 300 performs a process that is the reverse of the process performed by the video encoder 200 to decode the encoded video data of the bitstream. For example, the video decoder 300 may use entropy decoding to decode the values ​​of the syntax elements of the bitstream in a manner substantially similar to, but reverse to, the entropy encoding process of the video encoder 200. The syntax elements may define partitioning information for partitioning a picture into super blocks and coding blocks. The syntax elements may also define prediction and residual information for a block of video data (e.g., a coding block).

[0087] The residual information may be represented by, for example, quantized transform coefficients. The video decoder 300 may inverse quantize and inverse transform the quantized transform coefficients of the block to reproduce a residual block for the block. The video decoder 300 uses the signaled prediction mode (intra-frame or inter-frame prediction mode) and related prediction information (e.g., motion information for inter-frame prediction) to form prediction samples for the block. The video decoder 300 may then combine the prediction samples and corresponding sample values ​​of the residual block (on a sample-by-sample basis) to reproduce the original block. The video decoder 300 may perform additional processing, such as performing a loop filtering process to reduce visual artifacts along the boundaries of the blocks.

[0088] The present disclosure may generally involve "signaling" certain information (such as syntax elements). The term "signaling" may generally refer to the communication of values ​​of syntax elements and / or other data used to decode encoded video data. That is, the video encoder 200 may signal the values ​​of syntax elements in the bitstream. Generally, signaling refers to generating values ​​in the bitstream. As noted above, the source device 102 may transmit the bitstream to the destination device 116 in substantially real time or in non-real time (such as may occur when storing syntax elements to the storage device 112 for later retrieval by the destination device 116).

[0089] Figure 2 is a block diagram illustrating an example video encoder 200 that may perform the techniques of this disclosure. Figure 2 is provided for purposes of explanation and should not be construed as limiting the techniques broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes a video encoder 200 based on techniques in the AV1 coding format. However, the techniques of this disclosure may be performed by a video encoding device configured to encode video data in accordance with other video coding formats and / or various other video coding standards. In particular, the techniques of this disclosure may be applicable for use with any video coding format or standard that includes intra-coding techniques, which allow one video decoding core to use decoded samples in the same frame decoded by another video core in a multi-core system.

[0090] exist Figure 2In the example of , the video encoder 200 includes a video data memory 230, a mode selection unit 202, a residual generation unit 204, a transform processing unit 206, a quantization unit 208, an inverse quantization unit 210, an inverse transform processing unit 212, a reconstruction unit 214, a loop filter unit 216, a decoded picture buffer (DPB) 218, an entropy encoding unit 220, and a shared memory 250. Any or all of the video data memory 230, the mode selection unit 202, the residual generation unit 204, the transform processing unit 206, the quantization unit 208, the inverse quantization unit 210, the inverse transform processing unit 212, the reconstruction unit 214, the loop filter unit 216, the DPB 218, the shared memory 250, and the entropy encoding unit 220 may be implemented in one or more processors or in a processing circuit.

[0091] For example, the units of video encoder 200 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, ASIC, or FPGA. In addition, video encoder 200 may include additional or alternative processors or processing circuits to perform these and other functions.

[0092] In some examples, Figure 2 The structure of the video encoder 200 shown may be a single video encoding core of a multi-core video encoding system. That is, the video encoder 200 may include Figure 2 Multiple instances of the structure shown, wherein each video encoding core of the multi-core system can be configured to encode the codec tiles of the video data in parallel with each other. As explained above, the video frame can be divided in one or more tree structures based on a predefined maximum block size (such as LCU, CTU, macroblock, superblock, etc.). Generally speaking, these "maximum block sizes" can be referred to as "codec tiles". Each video decoding core of the multi-core video encoding system can process a codec tile row of video data. The video data memory 230, DPB 218, and shared memory 250 can be accessed by each video encoding core of the multi-core video encoding system. That is, not every individual video encoding core has a dedicated video data memory, DPB, or shared memory, but there can be a single video data memory 230, DPB 218, and shared memory 250 that can be accessed by each video encoding core.

[0093] Video data memory 230 may store video data to be encoded by components of video encoder 200. Video encoder 200 may receive video data from, for example, video source 104 ( Figure 1) receives video data stored in the video data memory 230. The DPB 218 may act as a reference picture memory that stores reference video data for use when subsequent video data is predicted by the video encoder 200. The video data memory 230 and the DPB 218 may be formed by any of a variety of memory devices, such as a dynamic random access memory (DRAM) (including synchronous DRAM (SDRAM)), a magnetoresistive RAM (MRAM), a resistive RAM (RRAM), or other types of memory devices. The video data memory 230 and the DPB 218 may be provided by the same memory device or by separate memory devices. In various examples, the video data memory 230 may be on-chip with other components of the video encoder 200 (as illustrated), or off-chip relative to those components.

[0094] In the present disclosure, references to the video data memory 230 should not be interpreted as limited to memory inside the video encoder 200 (unless otherwise specified) or memory outside the video encoder 200 (unless otherwise specified). Rather, references to the video data memory 230 should be understood as a reference memory that stores video data received by the video encoder 200 for encoding (e.g., video data for a current block to be encoded). Figure 1 Memory 106 may also provide temporary storage for outputs from various units of video encoder 200 .

[0095] The shared memory 250 may also be implemented as any of a variety of memory devices, such as DRAM (including SDRAM), MRAM, RRAM, or other types of memory devices. In some examples, the shared memory 250 may be part of one or more memory units that are the same as the DPB 218. As will be explained in further detail below, the shared memory 250 may store pixel / sample tracking information 252 that indicates the completion of encoding and reconstructing samples of one or more regions of a frame of video data. The video encoding core of the video encoder 200 may read the pixel / sample tracking information 252 to determine whether a current decoding block of video data (e.g., decoding using an intra-block copy mode) can begin or whether the video encoding core should wait until an indication of the required samples / pixels has been completed.

[0096] Illustrated Figure 2The various units of the video encoder 200 are described to help understand the operations performed by the video encoder 200. The units may be implemented as fixed-function circuits, programmable circuits, or a combination thereof. Fixed-function circuits refer to circuits that provide specific functionality and are pre-set for the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (e.g., to receive parameters or output parameters), but the types of operations performed by fixed-function circuits are generally immutable. In some examples, one or more of the units may be different circuit blocks (fixed-function or programmable), and in some examples, one or more of the units may be integrated circuits.

[0097] The video encoder 200 may include an arithmetic logic unit (ALU), an elementary function unit (EFU), a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example in which the operation of the video encoder 200 is performed using software executed by a programmable circuit, the memory 106 ( Figure 1 ) may store instructions (eg, object code) for software received and executed by the video encoder 200, or another memory (not shown) within the video encoder 200 may store such instructions.

[0098] The video data memory 230 is configured to store the received video data. The video encoder 200 may retrieve the picture / frame of the video data from the video data memory 230 and provide the video data to the residual generation unit 204 and the mode selection unit 202. The video data in the video data memory 230 may be the original video data to be encoded.

[0099] The mode selection unit 202 includes an inter prediction unit 222 and an intra prediction unit 226. The inter prediction unit 222 may be configured to encode a coding block of video data (e.g., both a luma coding block and a chroma coding block) using translational motion compensation, affine motion compensation, OBMC, and / or composite inter-intra prediction, as described above. The intra prediction unit 226 may be configured to encode a coding block of video data (e.g., both a luma coding block and a chroma coding block) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, intra block copy (IBC), and / or color palette mode, as described above. The mode selection unit 202 may include additional functional units that perform video prediction according to other prediction modes.

[0100] The mode selection unit 202 typically coordinates multiple encoding passes to test combinations of encoding parameters and resulting rate-distortion values ​​for such combinations. The encoding parameters may include the partitioning of super blocks into coding blocks, the prediction mode for the coding blocks, the transform type for the residual data of the coding blocks, the quantization parameter for the residual data of the coding blocks, etc. The mode selection unit 202 may ultimately select a coding parameter combination that has a better rate-distortion value than other tested combinations.

[0101] The video encoder 200 may divide the picture retrieved from the video data memory 230 into a series of coding blocks and pack one or more super blocks into tiles. The mode selection unit 202 may divide the super blocks of the picture according to a tree structure.

[0102] In general, the mode selection unit 202 also controls its components (e.g., the inter prediction unit 222 and the intra prediction unit 226) to generate prediction samples for the current decoding block. For example, for translational inter prediction of the current block, the inter prediction unit 222 may perform a motion search to identify one or more closely matching reference blocks in one or more reference pictures (e.g., one or more previously decoded pictures stored in the DPB 218).

[0103] Specifically, the inter prediction unit 222 may calculate values ​​representing how similar a potential reference block will be to the current block, for example, based on a sum of absolute differences (SAD), a sum of squared differences (SSD), a mean absolute difference (MAD), a mean squared difference (MSD), etc. The inter prediction unit 222 may generally perform these calculations using sample-by-sample differences between the current block and the reference block under consideration. The inter prediction unit 222 may identify the reference block having the lowest value resulting from these calculations, thereby indicating the reference block that most closely matches the current block.

[0104] To translate the inter-frame prediction, the inter-frame prediction unit 222 may form one or more motion vectors (MVs) that define the position of the reference block in the reference picture relative to the position of the current block in the current picture. For example, for unidirectional inter-frame prediction, the inter-frame prediction unit 222 may determine a single motion vector, while for bidirectional inter-frame prediction, the inter-frame prediction unit 222 may determine two motion vectors.

[0105] The inter-frame prediction unit 222 may then use the motion vector to generate a prediction block of prediction samples. For example, the inter-frame prediction unit 222 may use the motion vector to retrieve data of a reference block. As another example, if the motion vector has fractional sample accuracy, the inter-frame prediction unit 222 may interpolate the value of the prediction block according to one or more interpolation filters. In addition, for bidirectional inter-frame prediction, the inter-frame prediction unit 222 may retrieve data of two reference blocks identified by corresponding motion vectors and combine the retrieved data, for example, by sample-by-sample averaging or weighted averaging.

[0106] As another example, for intra prediction, the intra prediction unit 226 may generate prediction samples from samples in the same picture as the current block. In some examples, the intra prediction unit 226 may generate prediction samples from reference samples adjacent to the current block. For example, for directional intra prediction modes, the intra prediction unit 226 may generally mathematically combine the values ​​of adjacent samples and use these calculated values ​​as the prediction block in a defined direction across the current block. As another example, for non-directional DC mode, the intra prediction unit 226 may calculate the average of the adjacent samples of the current block to generate the prediction sample.

[0107] For other video coding techniques, such as intra block copy mode, affine motion compensation, recursive filter intra prediction, and other prediction modes, as some examples, inter prediction unit 222 or intra prediction unit 226 generates prediction samples according to the technique of the particular coding mode being used. In some examples, such as color palette mode coding, intra prediction unit 226 may not generate prediction samples, but instead generate syntax elements indicating the manner in which the block is reconstructed based on the selected color palette. In such modes, mode selection unit 202 may provide these syntax elements to entropy encoding unit 220 for encoding.

[0108] Mode selection unit 202 provides the prediction samples to residual generation unit 204. Residual generation unit 204 receives the original uncoded version of the current block from video data memory 230 and the prediction samples from mode selection unit 202. Residual generation unit 204 calculates the sample-by-sample difference between the current block and the prediction samples. The resulting sample-by-sample differences define a residual block for the current block. In some examples, residual generation unit 204 can be formed using one or more subtractor circuits that perform binary subtraction.

[0109] The transform processing unit 206 applies one or more transforms to the residual block to generate a block of transform coefficients (referred to herein as a "transform coefficient block"). The transform processing unit 206 may apply various transforms to the residual block to form a transform coefficient block. For example, the transform processing unit 206 may apply a horizontal / vertical transform combination, which may include a discrete cosine transform (DCT), an asymmetric discrete sine transform (ADST), a flipped ADST (e.g., ADST in reverse order), and an identity transform (IDTX). When the identity transform is used, the transform is skipped in one of the vertical direction or the horizontal direction. In some examples, the transform process may be skipped.

[0110] The quantization unit 208 may quantize the transform coefficients in the transform coefficient block to produce a quantized transform coefficient block. The quantization unit 208 may quantize the transform coefficients of the transform coefficient block according to a quantization parameter (QP) value associated with the current decoding block. The video encoder 200 (e.g., via the mode selection unit 202) may adjust the degree of quantization applied to the transform coefficient block associated with the current block by adjusting the QP value associated with the decoding block. Quantization may cause a loss of information, and therefore, the quantized transform coefficients may have a lower precision than the original transform coefficients generated by the transform processing unit 206.

[0111] The inverse quantization unit 210 and the inverse transform processing unit 212 may apply inverse quantization and inverse transform, respectively, to the quantized transform coefficient block to reconstruct a residual block from the transform coefficient block. The reconstruction unit 214 may generate a reconstructed block corresponding to the current decoding block (although potentially with some degree of distortion) based on the reconstructed residual block and the prediction samples generated by the mode selection unit 202. For example, the reconstruction unit 214 may add samples of the reconstructed residual block to corresponding prediction samples generated by the mode selection unit 202 to generate a reconstructed block.

[0112] The loop filter unit 216 may perform one or more filtering operations on the reconstructed block. For example, the loop filter unit 216 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU. In other examples, the loop filter unit 216 may apply a constrained directional enhancement filter (CDEF) that may be applied after deblocking, and may include the application of a non-separable, nonlinear low-pass directional filter based on the estimated edge direction. The loop filter unit 216 may also include a loop recovery filter applied after CDEF, and may include a separable, symmetric normalized Wiener filter or a dual self-steering filter. In some examples, the operation of the loop filter unit 216 may be skipped.

[0113] The video encoder 200 stores the reconstructed blocks in the DPB 218. For example, in examples where the operation of the loop filter unit 216 is not performed, the reconstruction unit 214 may store the reconstructed blocks to the DPB 218. In examples where the operation of the loop filter unit 216 is performed, the loop filter unit 216 may store the filtered reconstructed blocks to the DPB 218. The inter-prediction unit 222 may retrieve a reference picture formed by the reconstructed (and potentially filtered) blocks from the DPB 218 to perform inter-prediction on blocks of a subsequently encoded picture. In addition, the intra-prediction unit 226 may use the reconstructed blocks of the current picture in the DPB 218 to perform intra-prediction on other blocks in the current picture.

[0114] In general, the entropy coding unit 220 may entropy encode syntax elements received from other functional components of the video encoder 200. For example, the entropy coding unit 220 may entropy encode the quantized transform coefficient blocks from the quantization unit 208. As another example, the entropy coding unit 220 may entropy encode prediction syntax elements (e.g., motion information for inter prediction or intra mode information for intra prediction) from the mode selection unit 202.

[0115] According to AV1, the entropy coding unit 220 may be configured as a symbol-to-symbol adaptive multi-symbol arithmetic decoder. The syntax elements in AV1 include an alphabet of N elements, and the context (e.g., a probability model) includes a set of N probabilities. The entropy coding unit 220 may store the probabilities as a 15-bit cumulative distribution function (CDF). The entropy coding unit 220 may perform recursive scaling using an update factor based on the alphabet size to update the context.

[0116] The video encoder 200 may output an encoded video bitstream that includes entropy encoding syntax elements required to reconstruct blocks of a slice or picture. For example, the entropy encoding unit 220 may output a bitstream.

[0117] According to the techniques of the present disclosure, as will be explained in more detail below, the video encoder 200 may be configured to: track the completion of encoding and reconstructing samples of one or more regions of a video data frame; write information to a shared memory indicating the completion of encoding and reconstructing samples of one or more regions of a video data frame; read the information in the shared memory before encoding a subsequent region of the video data frame; and determine whether to encode a subsequent region of the video data frame based on the information.

[0118] Figure 3 is a block diagram illustrating an example video decoder 300 that may perform the techniques of this disclosure. Figure 3 The foregoing description is provided for purposes of explanation and is not intended to limit the techniques broadly exemplified and described in this disclosure. For purposes of explanation, this disclosure describes a video decoder 300 according to techniques in the AV1 video coding format. However, the techniques of this disclosure may be performed by a video decoding device configured to decode video data according to other video coding formats and / or various other video coding standards.

[0119] exist Figure 3In the example of , the video decoder 300 includes a coded picture buffer (CPB) memory 320, an entropy decoding unit 302, a prediction processing unit 304, an inverse quantization unit 306, an inverse transform processing unit 308, a reconstruction unit 310, a loop filter unit 312, a decoded picture buffer (DPB) 314, and a shared memory 350. Any or all of the CPB memory 320, the entropy decoding unit 302, the prediction processing unit 304, the inverse quantization unit 306, the inverse transform processing unit 308, the reconstruction unit 310, the loop filter unit 312, the shared memory 350, and the DPB 314 may be implemented in one or more processors or in a processing circuit. For example, the units of the video decoder 300 may be implemented as one or more circuits or logic elements as part of a hardware circuit, or as part of a processor, an ASIC, or an FPGA. In addition, the video decoder 300 may include additional or alternative processors or processing circuits to perform these and other functions.

[0120] In some examples, Figure 3 The structure of the video decoder 300 shown may be a single video decoding core of a multi-core video decoding system. That is, the video decoder 300 may include Figure 3 Multiple instances of the structure shown, wherein each video decoding core of the multi-core system can be configured to decode the codec tiles of the video data in parallel with each other. As explained above, the video frame can be divided in one or more tree structures based on a predefined maximum block size (such as LCU, CTU, macroblock, superblock, etc.). Generally speaking, these "maximum block sizes" can be referred to as "codec tiles". Each video decoding core of the multi-core video decoding system can process a codec tile row of video data. CPB memory 320, DPB 314 and shared memory 350 can be accessed by each video decoding core of the multi-core video encoding system. That is, not every individual video encoding core has a dedicated video data memory, DPB or shared memory, but there can be a single video data memory 230, DPB 218 and shared memory 250 that can be accessed by each video decoding core.

[0121] The prediction processing unit 304 includes an inter prediction unit 316 and an intra prediction unit 318. The inter prediction unit 316 may be configured to decode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using translational motion compensation, affine motion compensation, OBMC, and / or composite inter-intra prediction, as described above. As described above, the intra prediction unit 318 may be configured to decode coding blocks of video data (e.g., both luma coding blocks and chroma coding blocks) using directional intra prediction, non-directional intra prediction, recursive filter intra prediction, CFL, intra-block copy (IBC), and / or color palette mode. The prediction processing unit 304 may include additional functional units for performing video prediction according to other prediction modes.

[0122] CPB memory 320 may store video data, such as an encoded video bitstream, to be decoded by components of video decoder 300. For example, the video bitstream may be obtained from computer readable medium 110 ( Figure 1 ) to obtain video data stored in the CPB memory 320. The CPB memory 320 may include a CPB that stores encoded video data (e.g., syntax elements) from an encoded video bitstream. In addition, the CPB memory 320 may store video data other than syntax elements of decoded pictures, such as temporary data representing outputs from various units of the video decoder 300. For example, as will be explained below, the CPB memory 320 may include a first buffer and a second buffer for storing a sum and an average of reconstructed luma sample values ​​predicted by the CFL.

[0123] DPB 314 typically stores decoded pictures, which the video decoder 300 can output and / or use as reference video data when decoding subsequent data or pictures of the encoded video bitstream. CPB memory 320 and DPB 314 can be formed by any of a variety of memory devices, such as DRAM (including SDRAM), MRAM, RRAM, or other types of memory devices. CPB memory 320 and DPB 314 can be provided by the same memory device or a separate memory device. In various examples, CPB memory 320 can be on-chip with other components of the video decoder 300, or off-chip relative to those components.

[0124] Additionally or alternatively, in some examples, video decoder 300 may retrieve the video from memory 120 ( Figure 1 ) to retrieve the decoded video data. That is, memory 120 may utilize CPB memory 320 to store data as discussed above. Likewise, when some or all of the functionality of video decoder 300 is implemented in software to be executed by processing circuitry of video decoder 300, memory 120 may store instructions to be executed by video decoder 300.

[0125] The shared memory 350 may also be implemented as any of a variety of memory devices, such as DRAM (including SDRAM), MRAM, RRAM, or other types of memory devices. In some examples, the shared memory 350 may be part of one or more memory units that are the same as the DPB 314. As will be explained in further detail below, the shared memory 350 may store pixel / sample tracking information 352 that indicates the completion of decoding samples of one or more regions of a frame of video data. The video decoding core of the video decoder 300 may read the pixel / sample tracking information 352 to determine whether a current decoding block of video data (e.g., decoding using an intra-block copy mode) can begin or whether the video decoding core should wait until an indication of the required samples / pixels has been completed.

[0126] Illustrated Figure 3 The various units shown in FIG. 3 are used to help understand the operations performed by the video decoder 300. The units may be implemented as fixed function circuits, programmable circuits, or a combination thereof. Figure 2 , fixed-function circuits refer to circuits that provide specific functionality and are pre-set for the operations that can be performed. Programmable circuits refer to circuits that can be programmed to perform various tasks and provide flexible functionality in the operations that can be performed. For example, a programmable circuit can execute software or firmware that causes the programmable circuit to operate in a manner defined by the instructions of the software or firmware. Fixed-function circuits can execute software instructions (for example, to receive parameters or output parameters), but the type of operations performed by fixed-function circuits is generally immutable. In some examples, one or more of the cells may be different circuit blocks (fixed-function or programmable), and in some examples, one or more of the cells may be integrated circuits.

[0127] The video decoder 300 may include an ALU, an EFU, a digital circuit, an analog circuit, and / or a programmable core formed by a programmable circuit. In an example where the operation of the video decoder 300 is performed by software executed on the programmable circuit, an on-chip or off-chip memory may store instructions (e.g., object code) of the software received and executed by the video decoder 300.

[0128] Entropy decoding unit 302 may receive encoded video data from CPB memory 320 and entropy decode the video data to reproduce syntax elements. Prediction processing unit 304, inverse quantization unit 306, inverse transform processing unit 308, reconstruction unit 310, and loop filter unit 312 may generate decoded video data based on the syntax elements extracted from the bitstream.

[0129] Typically, the video decoder 300 reconstructs a picture block by block. The video decoder 300 may perform a reconstruction operation on each block individually (wherein a block currently being reconstructed (ie, decoded) may be referred to as a "current block").

[0130] The entropy decoding unit 302 may entropy decode syntax elements defining the quantized transform coefficients of the quantized transform coefficient block and transform information, such as a quantization parameter (QP) and / or a transform mode indication. The inverse quantization unit 306 may use the QP associated with the quantized transform coefficient block to determine a degree of quantization and, likewise, a degree of inverse quantization to be applied by the inverse quantization unit 306. The inverse quantization unit 306 may, for example, perform a bitwise left shift operation to inverse quantize the quantized transform coefficients. The inverse quantization unit 306 may thereby form a transform coefficient block including the transform coefficients.

[0131] After the inverse quantization unit 306 forms the transform coefficient block, the inverse transform processing unit 308 may apply one or more inverse transforms to the transform coefficient block to generate a residual block associated with the current decoding block. For example, the inverse transform processing unit 308 may apply an inverse DCT, an inverse ADST, an inverse flip ADST, or a horizontal / vertical combination of an inverse identity transform.

[0132] In addition, prediction processing unit 304 generates prediction samples based on the prediction information syntax elements entropy decoded by entropy decoding unit 302. For example, if the prediction information syntax elements indicate that the current block is inter-predicted, inter-prediction unit 316 may generate prediction samples. In this case, the prediction information syntax elements may indicate a reference picture in DPB 314 from which to retrieve the reference block, and a motion vector identifying the position of the reference block in the reference picture relative to the position of the current block in the current picture. Inter-prediction unit 316 may generally communicate with inter-prediction unit 222 ( Figure 2 ) The inter-frame prediction process is performed in a manner substantially similar to that described in detail herein.

[0133] As another example, if the prediction information syntax element indicates that the current block is intra-predicted, the intra-prediction unit 318 may generate prediction samples according to the intra-prediction mode indicated by the prediction information syntax element. Similarly, the intra-prediction unit 318 may generally communicate with the intra-prediction unit 226 ( Figure 2 The intra prediction process is performed in a manner substantially similar to that described in the foregoing description. The intra prediction unit 318 may retrieve data of neighboring samples of the current block from the DPB 314.

[0134] The reconstruction unit 310 may reconstruct the current block using the prediction block and the residual block. For example, the reconstruction unit 310 may add samples of the residual block to corresponding prediction samples to reconstruct the current block.

[0135] The loop filter unit 312 may perform one or more filtering operations on the reconstructed block. For example, the loop filter unit 312 may perform a deblocking operation to reduce blocking artifacts along the edges of the CU of the reconstructed block. In other examples, the loop filter unit 312 may apply a constrained directional enhancement filter (CDEF) that may be applied after deblocking, and may include the application of a non-separable, nonlinear low-pass directional filter based on the estimated edge direction. The loop filter unit 312 may also include a loop recovery filter applied after CDEF, and may include a separable, symmetric normalized Wiener filter or a dual self-steering filter. The operations of the loop filter unit 312 are not necessarily performed in all examples.

[0136] The video decoder 300 may store the reconstructed block in the DPB 314. For example, in examples where the operation of the loop filter unit 312 is not performed, the reconstruction unit 310 may store the reconstructed block to the DPB 314. In examples where the operation of the loop filter unit 312 is performed, the loop filter unit 312 may store the filtered reconstructed block to the DPB 314. As discussed above, the DPB 314 may provide reference information (such as samples of the current picture for intra-frame prediction and previously decoded pictures for subsequent motion compensation) to the prediction processing unit 304. In addition, the video decoder 300 may output a decoded picture (e.g., a decoded video) from the DPB 314 for use in, for example, Figure 1 18 for subsequent presentation on a display device such as display device 118. As will be described in more detail below, video decoder 300 may be configured to: track completion of decoding samples of one or more regions of a frame of video data; write information to a shared memory indicating completion of decoding samples of one or more regions of a frame of video data; read the information in the shared memory before decoding a subsequent region of the frame of video data; and determine whether to decode the subsequent region of the frame of video data based on the information.

[0137] The following reference will be described based on video decoding Figures 4 to 16 However, it should be understood that the techniques of the present disclosure may also be applied to video encoders. That is, in a video decoding scenario, the video decoding core of a multi-core video decoder may be configured to track the completion of decoding samples and / or pixels. Similarly, in a video encoding scenario, the video encoding core of a multi-core video encoder may be configured to track the completion of encoding and subsequent reconstruction (e.g., for storage in a video encoding processor) of samples and / or pixels. Figure 2 Completion of DPB 218).

[0138] In addition, the techniques described below will be described with reference to tracking the completion of samples. In this context, a sample may refer to a single color component of a pixel value. For example, for a pixel value in the YCrCb format, there are three samples: Y (luminance), Cr (red chrominance), and Cb (blue chrominance). However, the techniques of the present disclosure are equally applicable to tracking the completion of a complete pixel value. For example, the video encoder 200 and the video decoder 300 may be configured to track when each sample value of an entire pixel has completed encoding and reconstruction or decoding.

[0139] Figure 4 is a conceptual diagram illustrating the decoding process of a single processing core. Figure 4 A single video decoding core 400 is shown. The video decoding core 400 may be configured to perform the above-described operations for the video decoder 300 ( Figure 3 ) described in the video decoding techniques. The video decoding core 400 may include a syntax parser and other blocks 402 configured to parse syntax elements and route video data received from a video encoder (e.g., the video encoder 200). A prediction engine (PE) 404 may be configured to perform one or more spatial or temporal prediction processes on blocks of video data, including intra-block copying and other intra-prediction processes. Figure 3 , PE 404 may be configured to perform the techniques of prediction processing unit 304. Filter engine (FE) 406 may be configured to perform filtering operations (eg, post-processing filtering operations) on sample values ​​decoded by PE 404. Figure 3 , FE 406 may be configured to perform the techniques of loop filter unit 312. Direct memory access (DMA) and other blocks 408 may be configured to store the decoded and filtered sample values ​​in DPB memory 410. Figure 3 , DPB memory 410 may be equivalent to DPB 314 .

[0140] like Figure 4 As shown in the top portion of , the video decoding core 400 can be configured to decode blocks of frame 450. Block 458 represents a block of sample values ​​that FE 406 has written to DPB memory 410. Block 460 represents a block of sample values ​​that FE 406 has recently written to DPB memory 410. Block 456 represents a block of sample values ​​that FE 406 has stored in local cache / memory. In this context, local cache / memory is a cache and / or memory that is only accessible to FE 406 and not accessible to PE 404. Block 452 represents a block of sample values ​​that FE 406 is currently processing. Block 454 represents a block of sample values ​​that PE 404 is currently processing. All other blocks in frame 450 have not yet been decoded.

[0141] exist Figure 4In the examples of and the examples described below, it is assumed that blocks of video data are processed in a left-to-right raster scan order. However, the techniques of the present disclosure are applicable to any order in which video data is processed and decoded.

[0142] The "blocks" described in the above paragraphs refer to 2D blocks of fixed-size sample values ​​written to the DPB memory 410. Such blocks may be referred to as "memory blocks" and / or "memory tiles", and do not necessarily and typically do not overlap with any partitioned blocks of the video codec implemented by the video decoding core 400.

[0143] In some example codecs, PE 404 may be configured to read back only the decoded reference samples processed by FE 406 from previously processed frames (labeled as "Feedback"). Therefore, all processed and decoded sample values ​​are readily available to PE 404. However, in some codecs such as AV1 where intra-frame block copy mode is allowed, PE 404 may be configured to read back the decoded reference samples processed by FE 406 from the same frame currently being decoded. Therefore, the sample values ​​required by PE 404 may not be easily available because the required sample values ​​may not have been decoded yet. This situation may occur more frequently in multi-core video decoders, where multiple video decoding cores operate on rows of codec tiles in parallel. Generally speaking, video frames can be divided in one or more tree structures based on a predefined maximum block size (such as LCU, CTU, macroblock, superblock, etc.). Generally speaking, these "maximum block sizes" may be referred to as "codec tiles". Each video decoding core of a multi-core video decoding system can process codec tile rows of video data in parallel.

[0144] Figure 5 is a conceptual diagram illustrating a decoding process of multiple processing cores. Figure 5 A multi-core video decoding system is shown, which includes a video decoding core 400A (core 0), a video decoding core 400B (core 1), a video decoding core 400C (core 2), and a video decoding core 400D (core 3) (labeled 400A-D). Basically, the video decoding cores 400A-D include Figure 4 The example of the present disclosure shows four video decoding cores. The technology of the present disclosure is not limited to this configuration, but can be used with any multi-core video decoding system having at least two video decoding cores.

[0145] Figure 5The DPB memories 410A-D are shown as four distinct memories, but in other examples, the DPB memories 410A-D are a single memory unit accessible by each of the video decoding cores 400A-D. Each of the video decoding cores 400A-D includes a respective parser and other blocks 402A-D, PEs 404A-D, FEs 406A-D, and DMA and other blocks 408A-D.

[0146] like Figure 5 As shown, each of Core 0, Core 1, Core 2, and Core 3 of the video decoding cores 400A-D is configured to process a separate memory and / or codec tile row of a frame 450. When performing an intra prediction process (such as intra block copy) on a block 454 with a label “2”, a PE 404C of the video decoding core 400C (core 2) may need to access samples in a block 458 with a label “1”. Therefore, the processed samples from the FE 406A of the video decoding core 400A (core 0) for the block 458 with a label “1” need to be written to a shared memory (e.g., DPB 410A-D) before being read back and used by the PE 404C of the video decoding core 400C (core 2).

[0147] To facilitate the timing of reading previously decoded samples by another video decoding core, the video decoding cores 400A-D may be configured to track the completion of video decoding and storage in a shared memory (e.g., DPB memory 410A-D) in a manner accessible to each of the video decoding cores. In one example, one or more of the video decoding cores 400A-D may be configured to track the completion of decoding samples of one or more regions of a video data frame. The one or more regions include at least one of the following: a memory block row to a frame edge of a video data frame, a current memory tile of a video data frame, a previous memory tile of a video data frame, a 2D memory block of video data, and / or a vertical column of a 2D memory block of a current memory tile of video data. How the completion of different regions of a video data frame can be tracked will be described in more detail below.

[0148] In the context of the present disclosure, completion of decoding a sample may be defined as storing the decoded sample in a memory accessible to each of the video decoding cores 400A-D (eg, the DPB memories 410A-D). Figure 5 In the example of , such storage to DPB memories 410A-D occurs after filters are applied by FEs 406A-D. However, in other examples, the decoded samples may be stored to shared memory without applying filters.

[0149] The video decoding cores 400A-D may be further configured to write information to the shared memory indicating completion of decoding samples of one or more regions of a frame of video data. Figure 3 , the information may be pixel / sample tracking information 352, and the shared memory may be shared memory 350. Different examples of the types of information that may be written to shared memory 350 and how that information may relate to one or more regions that are being tracked to complete decoding of video samples are described in more detail below.

[0150] The video decoding cores 400A-D may be further configured to read information in the shared memory before decoding a subsequent region of a video data frame. Specifically, the video decoding cores 400A-400D may be configured to read information indicating completion of the decoded samples in the following circumstances: the current block of video data (i.e., the subsequent region) will be decoded using an intra-frame prediction process or other video decoding tool that uses decoded samples processed by another video decoding core in the same video data frame as the current decoded block. As described above, an example intra-frame prediction process is intra-frame block copying. The techniques of the present disclosure may also be applicable to any intra-frame prediction technique that allows the intra-frame prediction technique to use samples of decoded video data that cross boundaries being decoded by other video decoding cores.

[0151] The video decoding core 400A-D may then determine whether to decode a subsequent region of the video data frame based on the information after reading the information. For example, the video decoding core 400A-D may determine to decode the subsequent region based on the information indicating that samples of one or more regions of the video data frame required for decoding the subsequent region of the video data frame have been completed. Conversely, the video decoding core 400A-D determines not to decode the subsequent region based on the information indicating that samples of one or more regions of the video data frame required for decoding the subsequent region of the video data frame have not been completed. Alternatively, the video decoding core 400A-D may wait until the information indicates that the decoding samples are completed. For example, the video decoding core 400A-D may wait for a certain period of time (e.g., a number of clock cycles), and then determine whether to decode the subsequent region of the video data frame based on the information after the period of time.

[0152] The following Figures 6 to 13Different techniques for tracking different regions and / or sets of regions using different types of information written to a shared memory accessible by each of the video decoding cores 400A-B are illustrated. The information written to the shared memory (e.g., shared memory 350) indicating the completion of the decoded sample may include one or more markers and / or pointers that are specific to a particular video decoding core or shared by all video decoding cores. Even if a marker or pointer is specific to a particular video decoding core, such a marker or pointer may be accessed and read by each video decoding core in the multi-core video decoding system.

[0153] As described above, the video decoding cores 400A-D are configured to write markers and / or pointers to the shared memory 350 after the decoded samples are confirmed to be written to the memory accessible to each video decoding core (eg, DPB 314). Figure 3 As described above, shared memory 350 may be part of DPB 314. Figure 5 , the video decoding cores 400A-D may be configured to write markers and / or pointers to the DPB memories 410A-D indicating completion of the decoded samples.

[0154] Figure 6 is a conceptual diagram illustrating a first example of pixel / sample tracking according to the technology of the present disclosure. Figure 6 As shown, each of cores 0 through 3 is configured to decode four rows of memory blocks in frame 600. In summary, rectangular groupings of four rows of memory blocks may form a memory tile. Figure 6 Each of the illustrated memory blocks 610 and 612 represents a fixed size of the smallest unit of sample data written to the DPB memory 410A-D. The memory block 610 is a 2D block of samples to be written to the DPB memory 410A-D. The memory block 612 is a 2D block of samples that have been written to the DPB memory 410A-D by one of the cores 0-3. The memory blocks in the frame 600 may not be contiguous with the partitions of the video data in the frame. That is, the memory block 610 or 612 may include exactly one block of partitioned video data, less than one block of partitioned video data, or more than one block of partitioned video data, depending on how the particular frame of the video data is partitioned.

[0155] The video decoding cores 400A-D (e.g., cores 0-3) are configured to track the completion of decoded samples in each memory block and write a 1-bit flag or pointer to a shared memory accessible to each video decoding core once the decoding of a sample in a memory block is completed and written to the DPB memory 410A-D. Figure 6The 1-bit flag is represented by a "1" in each of the memory blocks 612 of . When a particular video decoding core needs to access a sample value outside of the row that the video decoding core is processing, the video decoding core can access the 1-bit flag associated with the required sample in the shared memory and determine whether the sample is available for reading out from the DPB memory 410A-D based on the value of the flag. For example, a "1" value for the flag indicates that the decoding of such a sample has been completed, while a "0" value for the flag indicates that the decoding of such a sample has not been completed.

[0156] In some examples, when a pointer is used to indicate whether a corresponding region / block of a frame has been decoded, the shared memory may include a pointer array similar to the flag array described above. The pointer array may have a series of entries, each entry representing a corresponding pointer. When the value of a pointer in the pointer array has a null value (e.g., a value of zero), the video decoding core may determine that the corresponding block or region of the video data has not yet completed decoding, and therefore waits to access the block or region. On the other hand, when the corresponding block or region of the video data has completed decoding, the corresponding decoding core may set the value of the corresponding pointer in the array to the memory address of the corresponding block or region.

[0157] In some examples, when pointers are used, a single pointer may be maintained by each core to indicate the last decoded region or block. Thus, different cores may determine the location of the reference block based on intra-block copying, and then determine whether the location of the reference block is less than the location pointed to by the pointer. If the location of the reference block is less than the location pointed to by the pointer, the core may determine that the reference block has been completely decoded and can therefore be accessed as a reference block for intra-block copying. On the other hand, if the location of the reference block is greater than the location pointed to by the pointer, the core may determine that the reference block has not been fully decoded, and therefore may wait until the reference block has been fully decoded before accessing the reference block for intra-block copying (or other video decoding or processing processes).

[0158] Therefore, in Figure 6 In an example of , a video decoding core may be configured to track the completion of decoded samples in each block of a video data frame, and may write data to a corresponding pointer (e.g., a 1-bit flag) indicating the completion of a corresponding block of a video data frame. In this context, a "block" of a video data frame is a memory block of video data. That is, a 2D block of samples that is the smallest unit of data stored to DPB memories 410A-D. In terms of the amount of time a video decoding core may need to wait to determine whether another video decoding core has completed decoding a sample, Figure 6 The technology allows for the lowest latency. This is because Figure 6 The technique of tracks the completion of decoding a sample at a very low level of granularity. As will be seen with other examples of the present disclosure, compared to other techniques, Figure 6Techniques of may achieve this lower latency by using more bits for information written to the shared memory.

[0159] Figure 7 is a conceptual diagram of raster scanning in a sample image tile and a 2D block. Specifically, Figure 7 A raster scan order is shown used between tiles 700 and between blocks 710 within a particular tile in tiles 700. Many video coding formats, such as AV1, use this raster scan order. This means that once the video decoding core has started decoding a particular tile, it knows that the tile to the left of the current tile has been decoded. Likewise, if the video decoding core has started decoding a particular block within a tile, it knows that the block to the left of the current block within the same tile has been decoded. This raster scan order feature of many video codecs is used to define the sample decoding tracked in the following examples.

[0160] Figure 8 is a conceptual diagram illustrating a second example of pixel / sample tracking according to the technology of the present disclosure. Figure 8 As shown, each of cores 0 through 3 (eg, video decoding cores 400A-D) is configured to decode four rows of memory blocks in frame 800. In summary, rectangular groupings of four rows of memory blocks may form a memory tile. Figure 8 Each of the illustrated memory blocks 810 and 812 represents a fixed size of the smallest unit of sample data written to the DPB memory 410A-D. The memory block 810 is a 2D block of samples to be written to the DPB memory 410A-D. The memory block 812 is a 2D block of samples that have been written to the DPB memory 410A-D by one of the cores 0-3. The memory blocks in the frame 800 may not be contiguous with the partitions of the video data in the frame. That is, the memory block 810 or 812 may include exactly one block of partitioned video data, less than one block of partitioned video data, or more than one block of partitioned video data, depending on how the particular frame of the video data is partitioned.

[0161] like Figure 8 As shown, each of the video decoding cores is configured to track the completion of decoding samples in the memory block rows and maintain a corresponding pointer for each memory block row being processed. For example, core 0 (video decoding core 400A) may maintain and update a first pointer (2d_wrptr_0) for memory block row 0, a second pointer (2d_wrptr_1) for memory block row 1, a third pointer (2d_wrptr_2) for memory block row 2, and a fourth pointer (2d_wrptr_3) for memory block row 3. The above pointers may generally be referred to as core row pointers. The term memory block row is used to represent Figure 8The blocks 810 and 812 in are 2D blocks of sample data of a predefined size to be stored to a shared memory (e.g., DPB memory 410A-D). Other places in this disclosure may refer to "block rows". The term block row is intended to be a more general term that can be applied to 2D memory blocks or blocks divided by a video codec (e.g., codec blocks).

[0162] For each memory block row (or more generally, block row), the video decoding core may update the corresponding pointer in the row to indicate the completion of decoding the sample. In one example, the video decoding core may write a value indicating the number of memory blocks that have completed decoding to a pointer (e.g., 2d_wrptr_0). Since the memory blocks have a fixed size, the number of memory blocks completed will indicate which pixels / samples of the video data have been completed. In other examples, the video decoding core may write other information indicating how many memory block rows have been completed to the corresponding pointer. For example, the value written to the pointer may indicate the x and y position in the block in terms of completed samples or pixels.

[0163] In the above examples of the present disclosure, the video decoding core 400A-D may be configured to track the completion of decoding samples in multiple blocks in a block row of a video data frame. The video decoding core 400A-D may then write data to a corresponding core row pointer (e.g., 2d_wrptr_0, 2d_wrptor_1, etc.) indicating the completion of multiple blocks in the block row of the video data frame. Similar to Figure 6 For example, Figure 8 Examples of can achieve sample completion tracking with low latency because the smallest unit of samples written to memory is tracked. In some examples, Figure 8 The technique may require less shared memory to store pointers because the tracking area of ​​frame 800 is proportional to the frame height.

[0164] Fig. 9 is a conceptual diagram illustrating a third example of pixel / sample tracking according to the technology of the present disclosure. Fig. 9 As shown, each of cores 0 through 3 (eg, video decoding cores 400A-D) is configured to decode four rows of memory blocks in frame 900. Also, in total, rectangular groupings of four rows of memory blocks may form a memory tile. Fig. 9Each of the illustrated memory blocks 910 and 912 represents a fixed size of the smallest unit of sample data written to the DPB memory 410A-D. Memory block 910 is a 2D block of samples to be written to the DPB memory 910A-D. Memory block 912 is a 2D block of samples that have been written to the DPB memory 410A-D by one of the cores 0-3. The memory blocks in the frame 900 may not be contiguous with the partitions of the video data in the frame. That is, the memory block 910 or 912 may include exactly one block of partitioned video data, less than one block of partitioned video data, or more than one block of partitioned video data, depending on how the particular frame of the video data is partitioned.

[0165] Fig. 9 The technology used is referenced above Figure 8 The core row pointer of the description. Fig. 9 The technique introduces additional shared pointers that are used to indicate the completion of decoding samples in tile rows, current tile edges, and previous tiles. In this context, a tile can be a codec tile and can include a predefined number of LCUs, CTUs, macroblocks, superblocks, or other coding block partitions. In some examples, the video decoding core can be configured to decode video data within a particular tile before decoding the next tile in raster scan order.

[0166] Shared pointers indicating completion of block rows to frame edges, current tile edges, and previous tiles may be shared by each of the video decoding cores. Tracking completion of tiles in this manner is possible because decoding occurs in raster scan order (e.g., from left to right and from top to bottom of frame 900).

[0167] For each video decoding core that decodes a row of blocks (which can be a row of CTU / LCU / superblock / macroblock blocks), video decoding cores 0-3 can maintain n row pointers per core, which are reused throughout the frame. Fig. 9 In the example of , cores 0-3 maintain four core row pointers (e.g., c1_wrptr_0, c1_wrptr_1, c1_wrptr_2, c1_wrptr_3) because the size of the CTU / LCU / superblock / macroblock being decoded is four times the height of the memory block. More or fewer core row pointers may be maintained based on the size of the CTU / LCU / superblock / macroblock being decoded and the size of the memory block. In general, when decoding a CTU, the number of core row pointers n may be calculated as n=CTU_size / memory_block_size, where CTU_size is the width or height of the CTU in samples, and memory_block_size is the width or height of the memory block in samples.

[0168] Cores 0-3 may maintain and update three additional shared pointers to track progress of a row of blocks to a frame edge of frame 900 (e.g., the F of the F_wrtpr pointer), to track progress of a previous tile (e.g., the Tp or Tp_wrptr pointer), and to track progress of a current tile edge (e.g., the Tc or Tc_wrptr pointer). In this context, tracking completion of a current tile edge may include tracking completion of a row of blocks to a current tile edge.

[0169] Fig. 9 The technique maintains the low latency of the above techniques, with even lower implementation cost for the shared memory storing the pointers, since the shared pointers track the completion of decoding the samples over a larger area. Thus, the total number of bits required to track completion is reduced.

[0170] Fig.10 is a conceptual diagram illustrating a third example of pixel / sample tracking in more detail. Fig.10 In FIG. 1 , a shared pointer indicating completion of decoding samples in a block row to a frame edge 920 is marked as "F". A shared pointer indicating completion of decoding samples is a previous tile to a tile edge 930 is marked as Tp. A shared pointer indicating completion of decoding samples in a block row to an edge of a current tile is marked as Tc. Core row pointers are typically marked as Ri=R0, R1, R2, Rn.

[0171] exist Fig.10 In the example of , the core row pointer Ri is used to track the completion of decoding samples in the block row of the current tile. The value written to the core row pointer Ri can be any of the values ​​discussed above that will indicate the level of completion of decoding, including the X, Y position (e.g., in samples) of the last block where decoding has completed, and / or the number of blocks in the current tile where decoding has completed.

[0172] The video decoding core 400A-D may use a shared pointer "F" to track the completion of decoding samples at the edge of the frame. When the topmost core row pointer Ri being processed by the video decoding core reaches the frame edge 920, the video decoding core may increment the value of the shared pointer F. The value written to the shared pointer "F" may be the X, Y position of the lower right corner of the last block completed in the row of blocks at the edge of the frame.

[0173] The video decoding core 400A-D may use a shared pointer "Tc" to track the completion of decoding samples at the edge of the current tile. When the topmost core row pointer Ri being processed by the video decoding core reaches the current tile edge 930, the video decoding core may increment the value of the shared pointer Tc. The value written to the shared pointer "Tc" may be the X, Y position of the lower right corner of the last block completed in the row of blocks at the edge of the current tile.

[0174] The video decoding core 400A-D may use a shared pointer "Tp" to track the completion of decoding samples of a previous tile. When the bottommost core row pointer Ri being processed by the video decoding core reaches a tile edge 930, the video decoding core may increment the value of the shared pointer Tp. The value written to the shared pointer "Tp" may be the X, Y position of the lower right corner of the last block completed in the row of blocks at the edge of the current tile. Generally speaking, the shared pointer Tp is updated when the entire current codec tile has been decoded and stored to a shared memory (e.g., DPB 410A-D).

[0175] As indicated above, the values ​​written to the shared pointers F, Tc, and Tp may be the X, Y position of the lower right corner of the last block completed in the row of blocks at the edge of the frame. However, other values ​​may be written to the shared pointers to indicate where decoding has been completed. In general, Fig.10 In the example of , the X, Y position values ​​indicate the position of the sample in the inner corner of each memory block, a row of memory blocks at the edge of the current tile, a tile edge, or a row of memory blocks at the edge of a frame.

[0176] In summary, Fig. 9 and Fig.10 In an example of , a video decoding core may be configured to track completion of decoding samples in a block row to a frame edge of a video data frame, a current tile edge of a video data frame, a previous tile of a video data frame, and a plurality of blocks in a block row in a current tile of a video data frame. The video decoding core may write data to a first shared pointer (e.g., F) indicating completion of a block row to a frame edge of a video data frame, write data to a second shared pointer (e.g., Tc) indicating completion of an edge of a current tile of a video data frame, write data to a third shared pointer (e.g., Tp) indicating completion of a previous tile of a video data frame, and write data to a corresponding core row pointer (e.g., Ri) indicating completion of a plurality of blocks in a block row of a current tile of a video data frame.

[0177] Fig.11 is a conceptual diagram illustrating a fourth example of pixel / sample tracking according to the technology of the present disclosure. Fig.11 An example similar to Figure 8 However, instead of using a core row pointer to track the completion of decoding samples in a block of a block row, Fig.11 In the video decoding core, each of the cores may be configured to track the completion of decoding samples in a vertical column of a row of vertical columns. Each vertical column may include multiple 2D blocks of pixels / samples to be written to the memory.

[0178] like Fig.11As shown, each of cores 0 through 3 (eg, video decoding cores 400A-D) is configured to decode four rows of memory blocks in frame 1100. In summary, rectangular groupings of four rows of memory blocks may form a memory tile. Fig.11 Each of the illustrated memory blocks 1110 and 1112 represents a fixed size of the smallest unit of sample data written to the DPB memories 410A-D. Memory block 1110 is a 2D block of samples to be written to the DPB memories 410A-D. Memory block 1112 is a 2D block of samples that have been written to the DPB memories 410A-D by one of the cores 0-3. Vertical column 1114 includes multiple memory blocks 1110 and / or 1112. Fig.11 In the technology, compared with Figure 8 11, the number of pointers maintained by each video decode is reduced by grouping multiple memory blocks into vertical columns 1114. In one example, in a sample, the height of the vertical column 1114 is the same as the codec partition being decoded (e.g., the same as a CTU, LCU, superblock, macroblock, etc.).

[0179] For the example of a CTU, when the video decoding core is decoding a CTU row of samples, memory blocks in the processing area of ​​the video decoding core (e.g., the CTU row to the edge of the frame) are grouped together vertically. Each vertical column 1114 has the same height as the CTU, while the width of the vertical column 1114 may or may not be continuous with the width of the CTU. The video decoding core may track the completion of decoding each vertical column 114. Local tracking of each memory block 1112 is performed in the video decoding core itself (e.g., not stored in shared memory) before determining that a complete vertical column 1114 is to be completed and updating the corresponding core pointer (e.g., 2d_col_wrptr_0 of core 0). Similar to the core row pointer, the corresponding core pointer may be updated with data indicating the number of vertical columns in a row of vertical columns that have been completed, or may indicate the X, Y position of the last vertical column decoded. Although the granularity is smaller than the previous example, it can be implemented with fewer pointers and therefore lower memory requirements. Fig.11 technology.

[0180] In summary, Fig.11 In an example of , the video decoding core may be configured to track completion of decoding samples in multiple vertical columns in a row of vertical columns and write data to corresponding core pointers indicating completion of multiple vertical columns in the row of vertical columns.

[0181] Fig.12 is a conceptual diagram illustrating a fifth example of pixel / sample tracking according to the technology of the present disclosure. Fig.12 The technology is similar to Fig. 9 and Fig.10 The video decoding core is configured to maintain tracking to the frame edge, the current tile edge, and the shared point of completed decoding of the previous tile. However, rather than the lowest level of granularity tracked being a memory block, the video decoding core may track groups of memory blocks (such as described above with respect to Fig.11 completion of the vertical columns of discussion).

[0182] like Fig.12 As shown, each of cores 0 through 3 (eg, video decoding cores 400A-D) is configured to decode codec row (eg, CTU / LCU / superblock / macroblock) rows of memory blocks in frame 1200 . Fig.12 Each of the illustrated memory blocks 1210 and 1212 represents a fixed size of the smallest unit of sample data written to the DPB memory 410A-D. Memory block 1210 is a 2D block of samples to be written to the DPB memory 910A-D. Memory block 1212 is a 2D block of samples that have been written to the DPB memory 410A-D by one of the cores 0-3. The memory blocks in the frame 1200 may not be contiguous with the partitions of the video data in the frame. Vertical column 1214 includes multiple memory blocks 1210 and / or 1212.

[0183] Fig.12 The technology used is referenced above Fig.11 The core pointer described above tracks the completion of the decoded samples in vertical column 1214. Fig.11 , Fig.12 The technique introduces additional shared pointers for indicating the completion of decoding samples of block rows to the frame edge (eg, rows of vertical column 1214), the current tile edge, and the previous tile.

[0184] In the context of a codec that decodes CTUs, the video decoding core may be configured to track the completion of decoding of samples for each ongoing CTU row (per core) with vertical column (e.g., multiple vertical memory blocks) precision using core pointers, and to track completed CTU rows using shared pointers. Fig.12 The technique can further reduce the amount of memory required to store shared pointers.

[0185] When each video decoding core is decoding a CTU row of video samples, all memory blocks in the region being processed by the video decoding core are grouped together vertically. Tracking is performed at the vertical column level. The video decoding core can use local tracking of individual memory blocks in the video decoding core itself before tracking the complete vertical column to complete and write the pointer.

[0186] In a shared location, each core has a set of core pointers (e.g., C1_wrptr) for tracking the video decoding core progress at a vertical column level. The rest of the frame can be tracked using three shared pointers progress at the frame edge, current codec tile edge, and previous codec tile. Fig.13 A more detailed description is given.

[0187] Fig.13 is a conceptual diagram illustrating a fifth example of pixel / sample tracking in more detail. Fig.13 In the example, the shared pointer indicating completion of decoding samples in a vertical column row (e.g., codec CTU row) to a frame edge 1320 is marked as "F". The shared pointer indicating completion of decoding samples is the previous tile to a tile edge 1330 is marked as Tp. The shared pointer indicating completion of decoding samples in a vertical column row to the edge of the current tile is marked as Tc. The core pointers are generally marked Ci=C0, C1, C2, Cn.

[0188] exist Fig.13 In the example of , the core pointer Ci is used to track the completion of decoding samples in the vertical column rows of the current tile. The value written to the core pointer Ci can be any of the values ​​discussed above that will indicate the level of completion of decoding, including the X, Y position (e.g., in samples) of the last vertical column where decoding has completed, and / or the number of vertical columns in the current tile where decoding has completed.

[0189] The video decoding core 400A-D may use a shared pointer "F" to track the completion of decoding samples at the edge of the frame. When the topmost core pointer Ci being processed by the video decoding core reaches the frame edge 1320, the video decoding core may increment the value of the shared pointer F. The value written to the shared pointer "F" may be the X, Y position of the lower right corner of the last vertical column completed in the vertical column row at the frame edge.

[0190] The video decoding core 400A-D may use a shared pointer "Tc" to track the completion of decoding samples at the edge of the current tile. When the topmost core pointer Ci being processed by the video decoding core reaches the current tile edge 930, the video decoding core may increment the value of the shared pointer Tc. The value written to the shared pointer "Tc" may be the X, Y position of the lower right corner of the last vertical column completed in the vertical column row at the edge of the current tile.

[0191] The video decoding core 400A-D may use a shared pointer "Tp" to track the completion of decoding samples of a previous tile. When the bottom-most core pointer Ci being processed by the video decoding core reaches a tile edge 930, the video decoding core may increment the value of the shared pointer Tp. The value written to the shared pointer "Tp" may be the X, Y position of the lower right corner of the last vertical column completed in the vertical column row at the edge of the current tile. Generally speaking, the shared pointer Tp is updated when the entire current codec tile has been decoded and stored to a shared memory (e.g., DPB 410A-D).

[0192] As indicated above, the values ​​written to the shared pointers F, Tc, and Tp may be the X, Y position of the lower right corner of the last vertical column completed in the vertical column row at the edge of the frame. However, other values ​​may be written to the shared pointers to indicate where decoding has been completed. In general, Fig.13 In the example of , the X, Y position values ​​indicate the position of the sample in the inner corner of each memory vertical column, a memory vertical column row at the edge of the current tile, a tile edge, or a memory vertical column row at the edge of the frame.

[0193] In general, the video decoding core may be configured to track completion of decoding samples in a block row to a frame edge of a video data frame, a current tile edge of a video data frame, a previous tile of a video data frame, and multiple vertical columns of a current tile of video data. The video decoding core may be further configured to write data to a first shared pointer (F) indicating completion of a block row to a frame edge of a video data frame, write data to a second shared pointer (Tc) indicating completion of a current tile edge of a video data frame, write data to a third shared pointer (Tp) indicating completion of a previous tile of a video data frame, and write data to a corresponding core row pointer (Ci) indicating completion of multiple vertical columns of a current tile of video data.

[0194] Fig.14 is a table 1400 illustrating example pointer statistics for various example techniques of the present disclosure. The "bitmap" setting corresponds to the above reference Figure 6 The "Lines (Frames)" setting corresponds to the above reference Figure 8 The "Row (core) + Shared" setting corresponds to the above reference Figures 9 and 10 The "CTU row" setting corresponds to the above reference Fig.11 The "core+shared" setup corresponds to the above reference Figure 12 to Figure 13The technique described in the description. Frame width (FW) and frame height (FH) are in samples / pixel. Memory block width (uH) and memory block width (uW) are also in samples / pixel. The variable ctu_H indicates the CTU height (e.g., it can also be LCU, superblock, macroblock, etc.). The variable num_cores indicates the number of video decoding cores. In the above example, num_cores=4. However, other numbers of cores can be used.

[0195] Fig.15 is a conceptual diagram illustrating an example of partial tile tracking at a block edge. Continuing with the previous question, decoded sample data from the video decoding core is written to shared memory (e.g., DPB) in 2D memory blocks. If the codec tile width (e.g., CTU width) is not an integer multiple of these 2D memory blocks, the memory blocks may remain partially filled at the codec tile edges.

[0196] Even if the video decoding core is configured to track the decoding process as described above, if a memory block is written out in a partial manner, the video decoding core may write the same memory block twice to the shared memory before completion. This is because the first write of the memory block may occur on one side of the codec tile edge, while the second write of the memory block may occur on the other side of the codec tile edge once decoding of a new tile has begun.

[0197] Thus, the video decoding core may be further configured to track partial completion of the memory block and write data indicating partial completion or full completion of the memory block to the shared memory before allowing the decoded sample values ​​to be read.

[0198] like Fig.15 As shown, if the memory block is 48 samples wide, but the codec tile 1420 is 64 samples wide, both the memory block marked "1" and the memory block marked "2" overlap the boundary of the codec tile. For the 128 sample wide codec tile 1430, a similar situation occurs for the memory block "2" and the memory block "5".

[0199] Thus, when used with codec tile 1420 (e.g., when only a partial write of memory block 1 has occurred), the sample value in position "A" may be available to other video decoding cores, but the sample value in position "X" may not be available as it has not yet been written to shared memory because it crosses a codec tile boundary and has not yet been decoded.

[0200] In the case where there is a misalignment between the memory block and the codec tile, the video decoding core can be configured to determine whether the requested decoded sample is within a first partial portion of the memory block (marked as A) or within a second partial portion of the memory block (marked as X). If the decoded sample resides in the first partial portion of the memory block (A, XX), the video decoding core can read the decoded sample value from the DPB even if the data written to the shared memory indicates that such memory block is only partially written. Otherwise, if the decoded sample resides in the second partial portion of the memory block (A, XX), the video decoding core can read the decoded sample from the DPB only if the data written to the shared memory indicates that the memory block has been completely written to the DPB (e.g., not partially written).

[0201] Fig.16 is a conceptual diagram illustrating pixel / sample tracking in conjunction with partial tile tracking according to techniques of this disclosure. Fig.16 Illustrated with Fig.13 Same example, but with memory blocks, columns, frame edges, current tile edges, or previous tiles additionally marked as being partially written out. For example, memory column 1610 shows a partially written column of memory blocks at the edge of a codec tile, memory column 1620 shows a fully written column of memory blocks at the edge of a codec tile, and memory column 1630 shows a fully written column of memory blocks that are not at the edge of a codec tile.

[0202] consider Fig.16 Here, the vertical column being written out is partial. Thus, in addition to the pointers described in the above examples, the video decoding core may be configured to track additional information (e.g., additional flags) indicating whether a particular completion of decoding a sample was a partial write.

[0203] Fig.17 is a flow chart illustrating an example decoding method according to techniques of this disclosure. Fig.17 The techniques may be performed by one or more structural units of the video encoder 200.

[0204] In one example of the present disclosure, the video encoder 200 may be configured to track the completion of encoding and reconstructing samples of one or more regions of a video data frame (1700). The video encoder 200 may write information to a shared memory indicating the completion of encoding and reconstructing samples of one or more regions of a video data frame (1710). The video encoder 200 may further read the information in the shared memory before encoding a subsequent region of the video data frame (1720), and determine whether to encode the subsequent region of the video data frame based on the information (1730).

[0205] Fig.18 is a flow chart illustrating another example decoding method according to the techniques of this disclosure. Fig.18 The techniques may be performed by one or more structural units of the video encoder 200.

[0206] In one example of the present disclosure, the video decoder 300 may be configured to track the completion of decoding samples of one or more regions of a video data frame (1800). The video decoder 300 may write information to a shared memory indicating the completion of decoding samples of one or more regions of a video data frame (1810). The video decoder 300 may further read the information in the shared memory before decoding a subsequent region of the video data frame (1820), and determine whether to decode the subsequent region of the video data frame based on the information (1830).

[0207] Other illustrative examples of the disclosure are described below.

[0208] Aspect 1 - A device configured to decode video data, the device comprising: a shared memory; and one or more processors, the one or more processors configured to execute multiple video decoding cores, each of the multiple video decoding cores communicating with the shared memory, and at least one of the multiple video decoding cores configured to: track the completion of decoding samples of one or more regions of a video data frame; write information to the shared memory, the information indicating the completion of decoding the samples of the one or more regions of the video data frame; read the information in the shared memory before decoding a subsequent region of the video data frame; and determine whether to decode the subsequent region of the video data frame based on the information.

[0209] Aspect 2 - An apparatus according to Aspect 1, wherein the one or more regions include at least one of the following: a block row to a frame edge of the video data frame, a current tile edge of the video data frame, a previous tile of the video data frame, and a vertical column of a current tile of the video data.

[0210] Aspect 3 - An apparatus according to Aspect 2, wherein in order to track the completion of decoding the samples of the one or more areas of the video data frame, at least one of the multiple video decoding cores is further configured to: track the completion of decoding the block rows to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame and the samples in multiple vertical columns of the current tile of the video data, and wherein in order to write the information to the shared memory, at least one of the multiple video decoding cores is further configured to: write data to a first shared pointer, the first shared pointer indicating the completion of the block rows to the frame edge of the video data frame; write data to a second shared pointer, the second shared pointer indicating the completion of the current tile edge of the video data frame; write data to a third shared pointer, the third shared pointer indicating the completion of the previous tile of the video data frame; and write data to a corresponding core pointer, the corresponding core pointer indicating the completion of the multiple vertical columns of the current tile of the video data.

[0211] Aspect 4 - An apparatus according to Aspect 1, wherein in order to track the completion of decoding the samples of the one or more regions of the video data frame, at least one of the multiple video decoding cores is further configured to: track the completion of decoding the samples in multiple vertical columns in a row of vertical columns, and wherein in order to write the information to the shared memory, at least one of the multiple video decoding cores is further configured to: write data to a corresponding core pointer, and the corresponding core pointer indicates the completion of the multiple vertical columns in the row of vertical columns.

[0212] Aspect 5 - An apparatus according to Aspect 1, wherein in order to track the completion of decoding the samples of the one or more areas of the video data frame, at least one of the multiple video decoding cores is further configured to: track the completion of decoding the block rows to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame, and the multiple blocks in the block rows in the current tile of the video data frame, and wherein in order to write the information to the shared memory, at least one of the multiple video decoding cores is further configured to: write data to a first shared pointer, the first shared pointer indicating the completion of the block row to the frame edge of the video data frame; write data to a second shared pointer, the second shared pointer indicating the completion of the current tile edge of the video data frame; write data to a third shared pointer, the third shared pointer indicating the completion of the previous tile of the video data frame; and write data to a corresponding core row pointer, the corresponding core row pointer indicating the completion of the multiple blocks in the block row of the current tile of the video data frame.

[0213] Aspect 6 - An apparatus according to Aspect 1, wherein in order to track the completion of decoding the samples of the one or more regions of the video data frame, at least one of the multiple video decoding cores is further configured to: track the completion of decoding the samples in multiple blocks in the block row of the video data frame, and wherein in order to write the information to the shared memory, at least one of the multiple video decoding cores is further configured to: write data to a corresponding core row pointer, and the corresponding core row pointer indicates the completion of the multiple blocks in the block row of the video data frame.

[0214] Aspect 7 - An apparatus according to Aspect 1, wherein in order to track the completion of decoding the samples of the one or more regions of the video data frame, at least one of the multiple video decoding cores is further configured to: track the completion of decoding the samples in each block of the video data frame, and wherein in order to write the information to the shared memory, at least one of the multiple video decoding cores is further configured to: write data to a corresponding pointer, and the corresponding pointer indicates the completion of the corresponding block of the video data frame.

[0215] Aspect 8 - An apparatus according to any one of Aspects 1 to 7, wherein in order to determine whether to decode the subsequent area of ​​the video data frame based on the information, at least one of the multiple video decoding cores is further configured to: determine whether to decode the subsequent area based on the information indicating that the samples of the one or more areas of the video data frame required to decode the subsequent area of ​​the video data frame have been completed.

[0216] Aspect 9 - An apparatus according to any one of Aspects 1 to 8, wherein in order to determine whether to decode the subsequent area of ​​the video data frame based on the information, at least one of the multiple video decoding cores is further configured to: determine not to decode the subsequent area based on the information indicating that the samples of the one or more areas of the video data frame required to decode the subsequent area of ​​the video data frame are not completed; wait for a certain period of time; and after the period of time, determine whether to decode the subsequent area of ​​the video data frame based on the information.

[0217] Aspect 10 - An apparatus according to any one of Aspects 1 to 9, wherein the one or more regions of the video data frame represent a memory map that is not contiguous with a codec map, and wherein at least one of the multiple video decoding cores is further configured to: track partial completion of the memory map; and write additional information indicating partial completion of the memory map to the shared memory.

[0218] Aspect 11 - An apparatus according to Aspect 10, wherein in order to determine whether to decode the subsequent area of ​​the video data frame based on the information, at least one of the multiple video decoding cores is further configured to: determine whether to decode the subsequent area of ​​the video data frame further based on the information and the additional information indicating partial completion of the memory tile.

[0219] Aspect 12 - An apparatus according to any one of aspects 1 to 11, wherein the apparatus is a mobile device, the apparatus further comprising: a receiver configured to receive the video data via a wireless communication standard.

[0220] Aspect 13 - A method for decoding video data, the method comprising: tracking the completion of decoding samples of one or more regions of a video data frame; writing information to a shared memory, the information indicating the completion of decoding the samples of the one or more regions of the video data frame; reading the information in the shared memory before decoding a subsequent region of the video data frame; and determining whether to decode the subsequent region of the video data frame based on the information.

[0221] Aspect 14 - A method according to Aspect 13, wherein the one or more regions include at least one of the following: a block row to a frame edge of the video data frame, a current tile edge of the video data frame, a previous tile of the video data frame, and a vertical column of a current tile of the video data.

[0222] Aspect 15 - A method according to Aspect 14, wherein tracking the completion of decoding the samples of the one or more areas of the video data frame includes: tracking the completion of decoding the block rows to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame and the samples in multiple vertical columns of the current tile of the video data, and wherein writing the information to the shared memory includes: writing data to a first shared pointer, the first shared pointer indicating the completion of the block rows to the frame edge of the video data frame; writing data to a second shared pointer, the second shared pointer indicating the completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating the completion of the previous tile of the video data frame; and writing data to a corresponding core pointer, the corresponding core pointer indicating the completion of the multiple vertical columns of the current tile of the video data.

[0223] Aspect 16 - A method according to Aspect 13, wherein tracking the completion of decoding the samples of the one or more regions of the video data frame includes: tracking the completion of decoding the samples in multiple vertical columns in a row of vertical columns, and wherein writing the information to the shared memory includes: writing data to a corresponding core pointer, the corresponding core pointer indicating the completion of the multiple vertical columns in the row of vertical columns.

[0224] Aspect 17 - A method according to aspect 13, wherein tracking the completion of decoding the samples of the one or more areas of the video data frame includes: tracking the completion of decoding the samples in the block row to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame and the multiple blocks in the block row in the current tile of the video data frame, and wherein writing the information to the shared memory includes: writing data to a first shared pointer, the first shared pointer indicating the completion of the block row to the frame edge of the video data frame; writing data to a second shared pointer, the second shared pointer indicating the completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating the completion of the previous tile of the video data frame; and writing data to a corresponding core row pointer, the corresponding core row pointer indicating the completion of the multiple blocks in the block row of the current tile of the video data frame.

[0225] Aspect 18 - A method according to Aspect 13, wherein tracking the completion of decoding the samples of the one or more regions of the video data frame includes: tracking the completion of decoding the samples in multiple blocks in the block row of the video data frame, and wherein writing the information to the shared memory includes: writing data to a corresponding core row pointer, the corresponding core row pointer indicating the completion of the multiple blocks in the block row of the video data frame.

[0226] Aspect 19 - A method according to aspect 13, wherein tracking the completion of decoding the samples of the one or more regions of the video data frame comprises: tracking the completion of decoding the samples in each block of the video data frame, and

[0227] Wherein writing the information into the shared memory comprises: writing data into a corresponding pointer, wherein the corresponding pointer indicates completion of a corresponding block of the video data frame.

[0228] Aspect 20 - A method according to any one of Aspects 13 to 19, wherein determining whether to decode the subsequent area of ​​the video data frame based on the information includes: determining whether to decode the subsequent area based on the information indicating that the samples of the one or more areas of the video data frame required to decode the subsequent area of ​​the video data frame have been completed.

[0229] Aspect 21 - A method according to any one of Aspects 13 to 20, wherein determining whether to decode the subsequent area of ​​the video data frame based on the information includes: determining not to decode the subsequent area based on the information indicating that the samples of the one or more areas of the video data frame required to decode the subsequent area of ​​the video data frame are not completed; waiting for a certain period of time; and after the period of time, determining whether to decode the subsequent area of ​​the video data frame based on the information.

[0230] Aspect 22 - A method according to any one of Aspects 13 to 21, wherein the one or more regions of the video data frame represent a memory map block that is not contiguous with a codec map block, and the method further includes: tracking partial completion of the memory map block; and writing additional information indicating partial completion of the memory map block to the shared memory.

[0231] Aspect 23 - A method according to Aspect 22, wherein determining whether to decode the subsequent area of ​​the video data frame based on the information includes: further determining whether to decode the subsequent area of ​​the video data frame based on the information and the additional information indicating partial completion of the memory block.

[0232] Aspect 24: The method according to any one of aspects 13 to 23, further comprising: receiving the video data via a wireless communication standard.

[0233] Aspect 25 - A device configured to encode video data, the device comprising: a shared memory; and one or more processors, the one or more processors configured to execute multiple video encoding cores, each of the multiple video encoding cores communicating with the shared memory, and at least one of the multiple video encoding cores configured to: track the completion of encoding and reconstructing samples of one or more regions of a video data frame; write information to the shared memory, the information indicating the completion of encoding and reconstructing the samples of the one or more regions of the video data frame; read the information in the shared memory before encoding a subsequent region of the video data frame; and determine whether to encode the subsequent region of the video data frame based on the information.

[0234] Aspect 26 - A method for encoding video data, the method comprising: tracking the completion of encoding samples of one or more regions of a video data frame; writing information to a shared memory, the information indicating the completion of encoding the samples of the one or more regions of the video data frame; reading the information in the shared memory before encoding a subsequent region of the video data frame; and determining whether to encode the subsequent region of the video data frame based on the information.

[0235] It should be appreciated that, according to examples, certain actions or events of any of the techniques described herein may be performed in a different order, may be added, combined, or omitted entirely (e.g., not all actions or events described are necessary to implement the technique). In addition, in some examples, actions or events may be performed concurrently (e.g., through multithreading, interrupt processing, or multiple processors) rather than sequentially.

[0236] In one or more examples, the described functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, the functionality may be stored as one or more instructions or codes on a computer-readable medium or sent via a computer-readable medium and executed by a hardware-based processing unit. A computer-readable medium may include a computer-readable storage medium (which corresponds to a tangible medium such as a data storage medium) or a communication medium, which includes, for example, any medium that facilitates the transfer of a computer program from one place to another according to a communication protocol. Thus, a computer-readable medium may generally correspond to (1) a non-transitory tangible computer-readable storage medium, or (2) a communication medium such as a signal or carrier wave. A data storage medium may be any available medium that can be accessed by one or more computers or one or more processors to retrieve instructions, codes, and / or data structures for implementing the techniques described in the present disclosure. A computer program product may include a computer-readable medium.

[0237] By way of example and not limitation, such computer-readable storage media may include RAM, ROM, EEPROM, CD-ROM or other optical disk storage devices, magnetic disk storage devices or other magnetic storage devices, flash memory, or any other medium that can be used to store the desired program code in the form of instructions or data structures and can be accessed by a computer. Moreover, any connection is appropriately referred to as a computer-readable medium. For example, if the instruction is sent from a website, server or other remote source using a coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL) or wireless technology (such as infrared, radio and microwave), the coaxial cable, fiber optic cable, twisted pair, DSL or wireless technology (such as infrared, radio and microwave) is included in the definition of the medium. However, it should be understood that computer-readable storage media and data storage media do not include connections, carriers, signals or other transient media, but are instead directed to non-transient tangible storage media. As used herein, disks and optical disks include compact disks (CDs), laser optical disks, optical optical disks, digital versatile disks (DVDs), floppy disks and blue-ray disks, wherein disks generally reproduce data magnetically, while optical disks reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0238] Instructions may be executed by one or more processors, such as one or more DSPs, general-purpose microprocessors, ASICs, FPGAs, or other equivalent integrated or discrete logic circuits. Therefore, the terms "processor" and "processing circuit" as used herein may refer to any of the aforementioned structures or any other structure suitable for implementing the techniques described herein. In addition, in some aspects, the functionality described herein may be provided within dedicated hardware and / or software modules configured for encoding and decoding, or incorporated into a combined codec. In addition, these techniques may be fully implemented in one or more circuits or logic elements.

[0239] The techniques of the present disclosure may be implemented in a variety of devices or apparatuses, including a wireless handset, an integrated circuit (IC), or a set of ICs (e.g., a chipset). Various components, modules, or units are described in the present disclosure to emphasize functional aspects of devices configured to perform the disclosed techniques, but do not necessarily require implementation by different hardware units. Specifically, as described above, the various units may be combined in a codec hardware unit, or the various units may be provided by a collection of interoperable hardware units (including one or more processors as described above) in combination with appropriate software and / or firmware.

[0240] Various examples have been described. These and other examples are within the scope of the following claims.

Claims

1. An apparatus configured to decode video data, the apparatus comprising: Shared memory; and One or more processors configured to execute a plurality of video decoding cores, each of the plurality of video decoding cores in communication with the shared memory, and at least one of the plurality of video decoding cores configured to: Tracking completion of decoding samples of one or more regions of a frame of video data; writing information to the shared memory, the information indicating completion of decoding the samples of the one or more regions of the frame of video data; reading the information in the shared memory before decoding a subsequent region of the video data frame; as well as A determination is made based on the information whether to decode the subsequent region of the video data frame.

2. The apparatus of claim 1, wherein the one or more regions comprise at least one of: a row of blocks to a frame edge of the video data frame, an edge of a current tile of the video data frame, a previous tile of the video data frame, or a vertical column of a current tile of video data.

3. The apparatus of claim 2, wherein to track completion of decoding the samples of the one or more regions of the video data frame, at least one of the plurality of video decoding cores is further configured to: tracking completion of decoding samples in the block row to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame, and a plurality of vertical columns of the current tile of video data, and In order to write the information into the shared memory, at least one of the plurality of video decoding cores is further configured as follows: writing data to a first shared pointer, the first shared pointer indicating completion of the row of blocks to the frame edge of the frame of the video data; writing data to a second shared pointer, the second shared pointer indicating completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating completion of the previous tile of the frame of video data; as well as Data is written to respective core pointers, the respective core pointers indicating completion of the plurality of vertical columns of the current tile of video data.

4. The apparatus of claim 1 , wherein to track completion of decoding the samples of the one or more regions of the video data frame, at least one of the plurality of video decoding cores is further configured to: tracking completion of decoding samples in a plurality of vertical columns in a row of vertical columns, and In order to write the information into the shared memory, at least one of the plurality of video decoding cores is further configured as follows: Data is written to respective core pointers, the respective core pointers indicating completion of the plurality of vertical columns in the row of vertical columns.

5. The apparatus of claim 1 , wherein to track completion of decoding the samples of the one or more regions of the video data frame, at least one of the plurality of video decoding cores is further configured to: tracking completion of decoding samples in a plurality of blocks in a block row to a frame edge of the video data frame, a current tile edge of the video data frame, a previous tile of the video data frame, and a block row in the current tile of the video data frame, and In order to write the information into the shared memory, at least one of the plurality of video decoding cores is further configured as follows: writing data to a first shared pointer, the first shared pointer indicating completion of the row of blocks to the frame edge of the frame of the video data; writing data to a second shared pointer, the second shared pointer indicating completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating completion of the previous tile of the frame of video data; as well as Data is written to respective core row pointers indicating completion of the plurality of blocks in the row of blocks of the current tile of the frame of video data.

6. The apparatus of claim 1 , wherein to track completion of decoding the samples of the one or more regions of the video data frame, at least one of the plurality of video decoding cores is further configured to: tracking completion of decoding samples in a plurality of blocks in a block row of the frame of video data, and In order to write the information into the shared memory, at least one of the plurality of video decoding cores is further configured as follows: Data is written to respective core row pointers, the respective core row pointers indicating completion of the plurality of blocks in the block row of the frame of video data.

7. The apparatus of claim 1 , wherein to track completion of decoding the samples of the one or more regions of the video data frame, at least one of the plurality of video decoding cores is further configured to: tracking completion of decoding samples in each block of the frame of video data, and In order to write the information into the shared memory, at least one of the plurality of video decoding cores is further configured as follows: Data is written to a corresponding pointer, the corresponding pointer indicating completion of a corresponding block of the video data frame.

8. The apparatus of claim 1 , wherein to determine whether to decode the subsequent region of the video data frame based on the information, at least one of the plurality of video decoding cores is further configured to: Determining to decode the subsequent region of the video data frame is performed based on the information indicating that the samples of the one or more regions of the video data frame required for decoding the subsequent region of the video data frame have been completed.

9. The apparatus of claim 1 , wherein to determine whether to decode the subsequent region of the video data frame based on the information, at least one of the plurality of video decoding cores is further configured to: determining not to decode the subsequent region of the frame of video data based on the information indicating that the samples of the one or more regions of the frame of video data required to decode the subsequent region of the frame of video data are not complete; Wait for a certain period of time; as well as After the time period, a determination is made based on the information whether to decode the subsequent region of the video data frame.

10. The apparatus of claim 1 , wherein the one or more regions of the video data frame represent memory tiles that are not contiguous with a codec tile, and wherein at least one of the plurality of video decoding cores is further configured to: Tracking partial completions of the memory tile; and Additional information indicating the partial completion of the memory tile is written to the shared memory.

11. The apparatus of claim 10, wherein in order to determine whether to decode the subsequent region of the video data frame based on the information, at least one of the plurality of video decoding cores is further configured to: Whether to decode the subsequent region of the video data frame is determined further based on the information and the additional information indicating partial completion of the memory tile.

12. The apparatus of claim 1, wherein the apparatus is a mobile device, the apparatus further comprising: A receiver is configured to receive the video data via a wireless communication standard.

13. A method for decoding video data, the method comprising: Tracking completion of decoding samples of one or more regions of a frame of video data; writing information to a shared memory, the information indicating completion of decoding the samples of the one or more regions of the frame of video data; reading the information in the shared memory before decoding a subsequent region of the video data frame; as well as A determination is made based on the information whether to decode the subsequent region of the video data frame.

14. The method of claim 13, wherein the one or more regions include at least one of: a block row to a frame edge of the video data frame, a current tile edge of the video data frame, a previous tile of the video data frame, and a vertical column of a current tile of video data.

15. The method of claim 14, wherein tracking completion of decoding the samples of the one or more regions of the video data frame comprises: tracking completion of decoding samples in the block row to the frame edge of the video data frame, the current tile edge of the video data frame, the previous tile of the video data frame, and a plurality of vertical columns of the current tile of video data, and Wherein writing the information into the shared memory comprises: writing data to a first shared pointer, the first shared pointer indicating completion of the row of blocks to the frame edge of the frame of the video data; writing data to a second shared pointer, the second shared pointer indicating completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating completion of the previous tile of the frame of video data; and Data is written to respective core pointers, the respective core pointers indicating completion of the plurality of vertical columns of the current tile of video data.

16. The method of claim 13, wherein tracking completion of decoding the samples of the one or more regions of the video data frame comprises: tracking completion of decoding samples in a plurality of vertical columns in a row of vertical columns, and Wherein writing the information into the shared memory comprises: writing data into a corresponding core pointer, wherein the corresponding core pointer indicates completion of the plurality of vertical columns in the row of vertical columns.

17. The method of claim 13, wherein tracking completion of decoding the samples of the one or more regions of the video data frame comprises: tracking completion of decoding samples in a plurality of blocks in a block row to a frame edge of the video data frame, a current tile edge of the video data frame, a previous tile of the video data frame, and a block row in the current tile of the video data frame, and Wherein writing the information into the shared memory comprises: writing data to a first shared pointer, the first shared pointer indicating completion of the row of blocks to the frame edge of the frame of the video data; writing data to a second shared pointer, the second shared pointer indicating completion of the current tile edge of the video data frame; writing data to a third shared pointer, the third shared pointer indicating completion of the previous tile of the frame of video data; and Data is written to respective core row pointers indicating completion of the plurality of blocks in the row of blocks of the current tile of the frame of video data.

18. The method of claim 13, wherein tracking completion of decoding the samples of the one or more regions of the video data frame comprises: tracking completion of decoding samples in a plurality of blocks in a block row of the frame of video data, and Wherein writing the information into the shared memory comprises: writing data into a corresponding core row pointer, wherein the corresponding core row pointer indicates completion of the plurality of blocks in the block row of the video data frame.

19. The method of claim 13, wherein tracking completion of decoding the samples of the one or more regions of the video data frame comprises: tracking completion of decoding samples in each block of the frame of video data, and Wherein writing the information into the shared memory comprises: writing data into a corresponding pointer, wherein the corresponding pointer indicates completion of a corresponding block of the video data frame.

20. The method of claim 13, wherein determining whether to decode the subsequent region of the video data frame based on the information comprises: Determining to decode the subsequent region of the video data frame is performed based on the information indicating that the samples of the one or more regions of the video data frame required for decoding the subsequent region of the video data frame have been completed.

21. The method of claim 13, wherein determining whether to decode the subsequent region of the video data frame based on the information comprises: determining not to decode the subsequent region of the frame of video data based on the information indicating that the samples of the one or more regions of the frame of video data required to decode the subsequent region of the frame of video data are not complete; Wait for a certain period of time; as well as After the time period, a determination is made based on the information whether to decode the subsequent region of the video data frame.

22. The method of claim 13, wherein the one or more regions of the video data frame represent memory tiles that are not contiguous with a codec tile, the method further comprising: Tracking partial completion of the memory tile; as well as Additional information indicating the partial completion of the memory tile is written to the shared memory.

23. The method of claim 22, wherein determining whether to decode the subsequent region of the video data frame based on the information comprises: Whether to decode the subsequent region of the video data frame is determined further based on the information and the additional information indicating partial completion of the memory tile.

24. The method according to claim 13, further comprising: The video data is received via a wireless communication standard.

25. An apparatus configured to encode video data, the apparatus comprising: Shared memory; and One or more processors configured to execute a plurality of video encoding cores, each of the plurality of video encoding cores in communication with the shared memory, and at least one of the plurality of video encoding cores configured to: Tracking completion of encoding and reconstructing samples of one or more regions of a frame of video data; writing information to the shared memory, the information indicating completion of encoding and reconstructing the samples of the one or more regions of the frame of video data; reading the information in the shared memory before encoding a subsequent region of the video data frame; as well as A determination is made based on the information whether to encode the subsequent region of the frame of video data.

26. A method for encoding video data, the method comprising: Tracking completion of encoding samples of one or more regions of a frame of video data; writing information to a shared memory, the information indicating completion of encoding the samples of the one or more regions of the frame of video data; reading the information in the shared memory before encoding a subsequent region of the video data frame; as well as A determination is made based on the information whether to encode the subsequent region of the frame of video data.

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