Waveform digitization method and device of blind pulse signal and computer storage medium

Abstract

The invention provides a waveform digitization method and device of a blind pulse signal and a computer storage medium, a system module determines the number of target threshold modules needing to be started according to the estimated voltage amplitude of the blind pulse signal, and the signal input end of each target threshold module accesses the blind pulse signal in parallel. Blind pulse signals and different voltage threshold signals correspondingly output by the voltage unit are connected to the input ends of different threshold comparators respectively, and comparison signals are output to the system module; and the system module determines detection time corresponding to each voltage threshold value of the blind pulse signal according to the comparison signal, and recovers the waveform of the blind pulse signal according to a time sequence. The waveform digitization method provided by the invention can realize rapid and simple parameter adjustment and adaptive output of a coordinate sequence, can adapt to different sampling requirements, has relatively high flexibility, expands the traditional MVT method from only specific pulse signal sampling to arbitrary pulse signal sampling, and can directly restore the pulse waveform through a sampling point.

Description

Technical Field

[0001] The present application relates to the field of signal sampling, and in particular to a waveform digitization method, device and computer storage medium for blind pulse signals. Background Art

[0002] Blind pulse signal refers to any pulse signal, and its main characteristics are as follows: 1. There is the concept of baseline. When a pulse arrives, the voltage will suddenly increase from the baseline, drop back to the baseline after reaching a certain amplitude, and rise from the baseline again when it is triggered next time; 2. The amplitude is 0-5V or 0-3.3V. Although the amplitude of the pulse signal generally has no limited range, due to the limitations of the back-end acquisition circuit, the signal is generally proportionally reduced to the range of 0-5V or 0-3.3V to adapt to the chip operating voltage limit; 3. The pulse width is generally between a few hundred nanoseconds and a few microseconds, which is usually relatively fast and difficult to collect.

[0003] A continuously changing analog signal is composed of an infinite number of continuous sample points that are infinitely close to each other, and each sample point has a certain time and voltage. The core of waveform digitization is to extract a finite number of sample points that can be expressed in digital quantities from the infinite number of signal sample points, and then restore the waveform to approximately describe the original analog signal.

[0004] There are several traditional digitization methods. The first is the direct digitization method of high-speed ADC (analog-to-digital converter), which samples the analog signal at a fixed sampling time interval △t, quantizes and records the voltage value at the sampling moment. The final conversion result is a voltage quantization value sequence V = [V0, V1, ..., V n ], n is a natural number, and the time quantization value of each sample point is expressed as T i =i×△t (i is a natural number) to form a default sequence T=[T0,T1,…,T n ]. Therefore, the core idea is to quantize and record the voltage value of the analog signal at the time i×△t with a predetermined equal time interval △t. This is a way of quantizing and recording when the time is known. For pulse signals, when high-speed ADC is used for direct digitization, the electrical pulse signal needs to be shaped and widened first, and then digitally sampled using a high-speed ADC (above 1GSps). However, because the pulse signal is relatively fast, when digitizing a pulse in engineering practice, in order to obtain more accurate energy information, it is usually necessary to collect at least 20 sampling points, which often places high performance requirements on the chip and is costly. It is impossible to complete digitization in application scenarios such as obtaining the energy spectrum of scintillation crystal pulse signals at high temperatures.

[0005] The second method is to widen and slow down the signal, that is, to widen the flicker pulse using an analog filter circuit and then sample the widened and slowed pulse using a relatively low-speed ADC (sampling rate is usually between 50MSps and 200MSps). The design difficulty will be reduced accordingly, but a large number of analog circuits will make the system more susceptible to interference, with lower measurement accuracy and lower integration. At the same time, due to the widening, there is a recovery process and the waiting time for recovery is very long, usually reaching tens of microseconds. This greatly limits the pulse pass rate of the digital part (the number of pulses processed per unit time) and will lose many pulse signals. Digitalization cannot be completed in application scenarios where the number of pulse events is exploding.

[0006] The third method is the multi-voltage threshold sampling method (Multi-Voltage Threshold, hereinafter referred to as MVT), which is a feasible method for the digitization of fast signals. Compared with the traditional ADC and other time interval sampling methods, MVT digital sampling fixes multiple voltage thresholds and only digitally samples the time when the pulse crosses the voltage threshold, thereby obtaining multiple sampling points in the fast rising edge stage. In specific use, after obtaining a series of time-voltage pair information, the pulse fitting method is used to achieve accurate acquisition of particle energy deposition information based on the prior scintillation pulse shape information in advance.

[0007] The existing MVT digitization scheme has the following problems: it is only applicable to the acquisition of known types of pulses and cannot digitally restore arbitrary pulse signals; it often only has a good fitting effect on pulses in a certain energy band, while it is difficult to converge the fitting parameters of pulse signals in other energy bands; the fitting accuracy is not high enough, and the waveform will be distorted due to noise, temperature and other factors when the signal is sampled, resulting in inaccurate key parameters such as pulse arrival time, which cannot be solved during fitting. Summary of the invention

[0008] In order to solve at least one of the above technical problems, the embodiments of the present application provide a waveform digitization method, device and computer storage medium for a blind pulse signal.

[0009] In the first aspect, the embodiment of the present application provides a waveform digitization device, including a system module and a threshold voltage module; wherein the system module includes a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module includes multiple threshold modules, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and multiple voltage units, in each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; the main chip configures the voltage threshold of each threshold module through each voltage unit. According to a specific embodiment of the present application, the voltage unit includes the voltage unit includes a digital-to-analog converter.

[0010] According to a specific implementation of the present application, the voltage unit includes a digital-to-analog converter and a voltage-dividing resistor connected in series to the digital-to-analog converter.

[0011] According to a specific implementation of the present application, the voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

[0012] According to a specific implementation of the present application, the threshold comparator is a differential comparator.

[0013] According to a specific embodiment of the present application, the chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to an input end of the AND gate circuit via the inversion circuit, the signal input end is connected to another input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

[0014] According to a specific implementation of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory, and the threshold module automatically reads the voltage threshold from the erasable memory each time the power is turned on.

[0015] According to a specific implementation of the present application, the threshold module is connected to the system module in a plug-in manner; and the main chip is connected to each threshold module in a plug-in manner.

[0016] According to a specific implementation of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, where M≥2 and N is a positive integer.

[0017] According to a specific implementation of the present application, voltage thresholds corresponding to adjacent threshold modules gradually increase and are spaced at equal intervals, and voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and are spaced at equal intervals.

[0018] According to a specific implementation of the present application, the system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0019] In the second aspect, an embodiment of the present application provides a waveform digitization method for a blind pulse signal, which can be applied to the waveform digitization device described in the first aspect; the method includes: the system module determines the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, and starts each target threshold module through a start instruction; the blind pulse signal is connected in parallel to the signal input end of each target threshold module, and the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module; the system module determines each voltage threshold and the corresponding detection time of the blind pulse signal according to the comparison signal.

[0020] According to a specific implementation of the present application, before the system module determines the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, and starts each target threshold module through a start instruction, the waveform digitization method also includes: judging whether the voltage threshold of the system module covers the estimated voltage amplitude of the blind pulse signal; if the voltage threshold of the system module covers the estimated voltage amplitude of the blind pulse signal, executing the step of determining the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal; if the voltage threshold of the system module does not cover the estimated voltage amplitude of the blind pulse signal, adjusting the estimated voltage amplitude of the blind pulse signal so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0021] According to a specific implementation of the present application, the step of the system module determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the blind pulse signal includes: determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module; and selecting a threshold module that meets the quantity requirements from all threshold modules as the target threshold module.

[0022] According to a specific implementation of the present application, after the step of starting each target threshold module through a startup instruction, the waveform digitization method also includes: configuring the voltage threshold of each target threshold module; splitting the voltage threshold of each target threshold module into voltage thresholds of corresponding voltage units.

[0023] According to a specific implementation of the present application, the voltage threshold of each target threshold module is split into the voltage threshold of the corresponding voltage unit in the following manner: the number of the threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P = M × N; the voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M; the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0024] According to a specific implementation manner of the present application, the step of starting each target threshold module through a start instruction includes: switching the chip select pin corresponding to each target threshold module to a low level; the signal input end of each target threshold module is connected to the blind pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the blind pulse signal and the voltage threshold signal output by each voltage unit, all chip select pins are high level by default, and the chip select pin corresponding to each target threshold module is low level after being inverted, and is ANDed with the blind pulse signal, and the output clock is low level, and the corresponding target threshold module will not be triggered; when the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the blind pulse signal is valid.

[0025] According to a specific implementation of the present application, the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module, including: the low-level chip select signal connected to the chip select unit is inverted by the inversion circuit of the chip select unit and then input into the AND gate circuit of the chip select unit; the blind pulse signal is input into the AND gate circuit via the signal input end; the output end of the AND gate circuit inputs the blind pulse signal into the signal input end of each threshold comparator.

[0026] According to a specific implementation of the present application, the system module determines the steps of each voltage threshold and the corresponding detection time of the blind pulse signal according to the comparison signal, including: determining the corresponding voltage threshold of the voltage unit connected to the threshold comparator corresponding to the comparison signal; obtaining the signal time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining the noise time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold for the first time; and associating the voltage threshold corresponding to each comparison signal with the signal time and the noise time.

[0027] According to a specific embodiment of the present application, the noise time is determined by acquiring the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0028] According to a specific implementation of the present application, the signal presence time and / or the noise presence time are both achieved by TDC identifying different transition point moments in the comparison signal.

[0029] According to a specific implementation of the present application, the noise time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0030] According to a specific implementation of the present application, the step of obtaining the noise location time when the blind pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold includes: if the blind pulse signal is a single-peak pulse signal, obtaining the trigger time of the front / back trigger point of the rising edge and the trigger time of the front / back trigger point of the falling edge as the noise location time, and setting other times to zero; if the blind pulse signal is a multi-peak pulse signal, obtaining the trigger time of all trigger points and marking the threshold number of each trigger point.

[0031] According to a specific implementation of the present application, after the step of determining the number of target threshold modules that need to be started based on the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module, the waveform digitization method also includes: obtaining predefined global variables, the global variables including the total number of thresholds, the number of valid thresholds and the number of noise thresholds, the total number of thresholds being the sum of the number of valid thresholds and the number of noise thresholds; calculating the actual number of thresholds included in the target threshold module based on the number of threshold modules; if the actual number of thresholds is greater than the valid number of thresholds, determining that the blind pulse signal is a valid signal.

[0032] According to a specific embodiment of the present application, after the system module determines the voltage thresholds and corresponding detection times of the blind pulse signal based on the comparison signal, the waveform digitization method also includes: the system module restores the waveform of the blind pulse signal in a time series based on the integrated information of all detection time-voltage threshold pairs.

[0033] According to a specific implementation of the present application, a method for restoring the waveform of the blind pulse signal includes a scatter plot, a line graph, curve smoothing, and an equal time interval interpolation method.

[0034] According to a specific implementation of the present application, the waveform digitization method further includes performing voltage threshold correction and / or time correction.

[0035] According to a specific implementation of the present application, the voltage threshold correction is performed by any of the following methods: Method 1: setting a fixed horizontal and vertical axis unit scale, collecting and recording the average value as the voltage threshold; Method 2: determining the voltage threshold based on the triggering condition of a square wave signal near a preset amplitude; Method 3: determining the voltage threshold based on the voltage signal of the output trigger point corresponding to a triangle wave as the input signal.

[0036] According to a specific implementation of the present application, the time correction is performed based on the time difference between channels with different voltage thresholds, single-channel TDC, and routing delay factors.

[0037] The waveform digitization method, device, and computing and storage medium of the blind pulse signal provided by the present application above, the system module determines the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, and starts each target threshold module through a startup instruction, connects the blind pulse signal to the signal input end of each target threshold module in parallel, connects the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and sends the comparison signal output by the threshold comparator to the system module; the system module determines each voltage threshold and the corresponding detection time of the blind pulse signal according to the comparison signal. The waveform digitization method provided can realize fast and simple parameter adjustment and adaptive output coordinate sequence, can adapt to different sampling requirements, has greater flexibility, and does not need to digitize the pulse waveform by solving the equation group to obtain the function curve in the process of processing the pulse signal, and expands the traditional MVT method from sampling only specific pulse signals to sampling any pulse signal. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] In order to more clearly illustrate the technical solution of the present application, the following is a brief introduction to the drawings required for use in the embodiments. It should be understood that the following drawings only illustrate certain embodiments of the present application and should not be regarded as limiting the scope of protection of the present application. In each of the drawings, similar components are numbered similarly.

[0039] Figure 1 A schematic diagram showing the structure of a threshold module setting of a waveform digitization device provided in an embodiment of the present application is shown;

[0040] Figure 2 A schematic diagram showing the structure of another threshold module setting of the waveform digitization device provided in an embodiment of the present application is shown;

[0041] Figure 3 A schematic diagram of a process flow of a method for digitizing a waveform of a blind pulse signal provided in an embodiment of the present application is shown;

[0042] Figure 4 A schematic diagram of a differential comparator involved in the waveform digitization method of a blind pulse signal provided in an embodiment of the present application is shown;

[0043] Figure 5 A schematic diagram showing a time interpolation method involved in a waveform digitization method for a blind pulse signal provided in an embodiment of the present application is shown;

[0044] Figure 6 A schematic diagram of a delay chain involved in a waveform digitization method for a blind pulse signal provided in an embodiment of the present application is shown;

[0045] Figure 7 A logical timing diagram of noise time acquisition involved in the waveform digitization method of a blind pulse signal provided in an embodiment of the present application is shown;

[0046] Figure 8 A schematic diagram of the process of acquiring the arrival time involved in the waveform digitization method of the blind pulse signal provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0047] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments.

[0048] The components of the embodiments of the present application generally described and shown in the drawings herein may be arranged and designed in various configurations. Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the application claimed for protection, but merely represents the selected embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those skilled in the art without making creative work belong to the scope of protection of the present application.

[0049] Hereinafter, the terms "including", "having" and their cognates, which may be used in various embodiments of the present application, are intended only to indicate specific features, numbers, steps, operations, elements, components, or combinations of the foregoing items, and should not be understood as first excluding the existence of one or more other features, numbers, steps, operations, elements, components, or combinations of the foregoing items or adding the possibility of one or more features, numbers, steps, operations, elements, components, or combinations of the foregoing items.

[0050] Furthermore, the terms “first”, “second”, “third”, etc. are merely used for distinguishing descriptions and are not to be understood as indicating or implying relative importance.

[0051] Unless otherwise defined, all terms (including technical terms and scientific terms) used herein have the same meanings as those generally understood by those skilled in the art to which the various embodiments of the present application belong. The terms (such as those defined in generally used dictionaries) will be interpreted as having the same meanings as the contextual meanings in the relevant technical field and will not be interpreted as having idealized meanings or overly formal meanings unless clearly defined in the various embodiments of the present application.

[0052] Example 1

[0053] An embodiment of the present application provides a waveform digitization device, including a system module and a threshold voltage module; wherein the system module includes a main chip, and the main chip is provided with a chip select pin and a signal pin; the threshold voltage module includes multiple threshold modules, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip select unit, a threshold comparator and multiple voltage units, in each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip select unit is connected to the chip select pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; the main chip configures the voltage threshold of each threshold module, for example, the main chip can configure the voltage threshold of each threshold module by using a DAC (digital analog converter) or a resistor network voltage divider.

[0054] The waveform digitization device provided in the embodiment of the present application is used to realize the waveform digitization processing of the blind pulse signal. In view of the characteristics of the blind pulse signal, such as the uncertain amplitude, the existence of the baseline, and the small pulse width that is not easy to collect, a method for realizing the output coordinate sequence with fast and simple parameter adjustment and adaptive output is provided. Specifically, the waveform digitization device includes a system module and a threshold voltage module. The system module, such as FPGA firmware, can be used as the main control component, and the chip circuits contained in the threshold voltage module are used as auxiliary components to provide multiple voltage thresholds selected by the system module.

[0055] The waveform digitization device provided can achieve fine sampling of different amplitudes. Therefore, the main factors to be considered in designing the waveform digitization device include threshold setting range, amplitude range adjustment, device selection and implementation, etc. These aspects will be explained in detail below.

[0056] The first aspect is the voltage threshold setting range. The voltage threshold setting range is determined according to the amplitude range of the blind pulse signal to be sampled. It is necessary to make the set voltage threshold setting range completely cover the amplitude range of the blind pulse signal. The amplitudes of pulse signals in different detection scenarios vary greatly. For example, in the particle detection scenario, the pulse signal fluctuates between 2 and 2.5V depending on the corresponding particle energy. In this case, the minimum voltage threshold can be set to 0V, and the maximum voltage threshold can be set to greater than 2.5V to ensure that the set voltage threshold completely covers the pulse signal to be sampled.

[0057] The second aspect is the amplitude range adjustment. The amplitude of the pulse signal is usually between 0 and 5V to adapt it to the signal processing circuit of common weak current readout electronics. If it is not within this amplitude range, it can be adjusted to be within this amplitude range by adjusting the sensitivity. The ways to adjust the sensitivity include: adjusting the supply voltage of the front-end devices such as photoelectric conversion to adjust the gain, adjusting the resistance value of the back-end signal amplification circuit to adjust the gain, etc.

[0058] Third, select devices based on the range. After determining the amplitude range of the signal to be sampled, select the voltage unit and threshold comparator according to the amplitude range, considering the output voltage range of the voltage unit such as DAC and the allowable input voltage range of the threshold comparator to meet the amplitude requirements of the pulse signal. For example, the threshold comparator can be a differential comparator, and the input voltage range of the differential comparator is set.

[0059] Fourth, the number of voltage threshold settings. In theory, the more voltage threshold settings there are, the more precisely the pulse waveform can be depicted and the better the digitization effect. However, due to the limitations of voltage threshold setting accuracy, the number of differential pins of FPGA chips, PCB layout area and power consumption, the number of voltage threshold settings cannot be infinite.

[0060] It is worth noting that there are accuracy issues in setting the voltage threshold, and the voltage noise may become larger as the voltage threshold becomes higher, so the interval between the set voltage thresholds must be greater than the peak-to-peak value of the voltage noise.

[0061] There is also a limit on the number of differential pins of FPGA chips. For a voltage threshold, the differential signal output of the pulse signal to be sampled and the voltage threshold after passing through the threshold comparator requires a pair of FPGA differential pins to process it. For example, if 64 voltage thresholds are set, the FPGA chip is required to have 64 pairs of differential pins. There are limitations on PCB layout area and power consumption. When it comes to system integration, the size and power consumption of a single detector readout electronics are particularly important. The more voltage threshold settings there are, the more differential pins are required for the FPGA chip, and the larger the PCB layout area, the more cumbersome the entire system will be. Therefore, it is necessary to comprehensively consider many factors to finally determine the number of voltage threshold settings.

[0062] Based on this, the waveform digitization device provided in this embodiment includes a main control system module and a voltage threshold module, and the voltage threshold module includes multiple threshold modules, and each threshold module is provided with multiple voltage units. The main chip configures the voltage threshold of each threshold module. Through the combination of the voltage thresholds of multiple voltage units and the combination of the voltage thresholds of the threshold module, a pulse sampling scheme with selectable multiple voltage thresholds is provided.

[0063] Specifically, each threshold module is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip selection unit, a plurality of voltage units and a threshold comparator. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip selection unit is connected to the chip selection pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal. Optionally, the threshold comparator is a differential comparator.

[0064] According to a specific implementation of the present application, the voltage unit includes a digital-to-analog converter (DAC) for setting different voltage thresholds.

[0065] According to another specific implementation of the present application, the voltage unit includes a digital-to-analog converter and a voltage-dividing resistor connected in series to the digital-to-analog converter.

[0066] Furthermore, the voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

[0067] The multiple voltage thresholds in the threshold module can be realized by means of a digital-to-analog converter (DAC) or a resistor network voltage divider or a combination of the two. The method of using DAC to directly give the voltage threshold has the advantage of flexible settings. The voltage threshold output by the DAC can be modified directly through serial communication, and the voltage threshold setting is stored in the E2PROM (also known as EEPROM, the abbreviation of electrically erasable programmable read-only memory), which can be automatically read each time the power is turned on. At the same time, the DAC method can also be used for more flexible calibration. The resistor network voltage divider method has the advantages of higher accuracy and lower cost. Using the principle of resistor series voltage divider, each voltage threshold can be derived from one end of a high-precision resistor.

[0068] The combination of DAC and resistor network can make better use of the advantages of both and realize the setting of multiple voltage thresholds. The many voltage thresholds to be set are divided into several voltage intervals. The maximum value of each interval, i.e., the voltage threshold, is provided by DAC, and the unit voltage threshold subdivision within the interval is realized by the resistor network. For example, for the voltage threshold setting range of 0-3V, 3 DACs provide 1V, 2V, and 3V respectively, and the voltage subdivision between 0-1V, 1-2V, and 2-3V is realized by the resistor network.

[0069] like Figure 1 As shown in FIG. 1 , it is a schematic diagram of the structure of a threshold module 100 of an 8-way voltage unit. The number of thresholds is not limited to 8, but can be 12, 16, 24, 32, etc. Figure 2 Another schematic diagram of a structure with DAC and 16 thresholds is shown. The number of pins of threshold modules with different threshold numbers will be different.

[0070] Figure 1 and Figure 2 In the example, the pin types are mainly divided into three categories, namely power pins, input pins and output pins. The power pins include VCC, VEE, and GND, which are used to power DAC102 and threshold comparator 101. The input pin Signal_in is used to input blind pulse signals, SDA, SCL, and V ref Indicates the driving and reference voltage pins under the DAC solution, V max / V min Indicates the maximum / minimum voltage under the resistor network solution, CS indicates the chip select pin, and the output pin V out1 、V out2 、V out3 、V out4 、V out5 、V out6 、V out7 、V out8 , used as the differential signal output after threshold comparison.

[0071] According to a specific embodiment of the present application, the chip select unit 103 includes an AND gate circuit 1031 and an inversion circuit 1032. The chip select unit 103 is connected to an input end of the AND gate circuit 1031 via the inversion circuit 1032, the signal input end is connected to another input end of the AND gate circuit 1031, and the output end of the AND gate circuit 1031 is connected to the signal input end of each threshold comparator 101.

[0072] The chip select signal is used to select whether to connect to the module. It is high by default and low after being inverted. When ANDed with the blind pulse signal, the output clock is low and will not trigger the threshold comparator. When the threshold module is needed, the chip select signal is pulled low and the blind pulse signal is valid.

[0073] According to a specific implementation of the present application, the threshold module is connected to the system module in a plug-in manner; and the main chip is connected to each threshold module in a plug-in manner.

[0074] In this embodiment, plug-in connection can be used to meet different application requirements. In the prior art, such as the high-speed ADC direct digitization method, the high-speed ADC is a whole, which is not convenient for plug-in connection. However, the waveform digitization device provided by this application realizes the plug-in connection between the threshold module and the system module due to the modular setting. The plug-in connection between the main chip and each threshold module is convenient for flexible organization, updating and upgrading, and adaptation to different application requirements according to actual needs, and adapting to different accuracy requirements.

[0075] According to a specific implementation of the present application, the main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory, and the threshold module automatically reads the voltage threshold from the erasable memory each time the power is turned on.

[0076] In this embodiment, the threshold module and the system module are plug-in connected to meet the needs of different precisions. The system module can lead out all LVDS differential IO ports as needed, freely combine a specified number of threshold modules, and the system module recognizes the number of threshold modules started, and adaptively changes the size interval of each voltage threshold corresponding to each threshold module to adapt the corresponding number of thresholds. Freely combine multiple threshold modules according to the precision requirements to maximize the use of FPGA resources.

[0077] According to a specific implementation of the present application, the number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, wherein M and N are both positive integers.

[0078] According to a specific implementation of the present application, the voltage thresholds of adjacent threshold modules gradually increase and the intervals are equal, and the voltage thresholds of adjacent voltage units in the threshold module gradually increase and the intervals are equal.

[0079] Taking the total number of thresholds as 512 and the number of threshold modules as 64 as an example, the FPGA part sets an 8-way DAC, that is, 8-way voltage thresholds, which are equally spaced. The threshold size can be freely modified. Assume that it is set to V 64 、V 128 、V 192 ,…,V 512 , 8 external threshold modules are connected, and the 64 thresholds in each threshold module are equally spaced. Taking the first threshold module as an example, it is V0, V1, ..., V 63 , other threshold modules are analogous in turn, and their DAC and resistor network solutions can be freely selected according to requirements.

[0080] When the accuracy requirement is 512 thresholds, the 3.3V voltage is divided into 512 equal parts (9 bits), the chip select signals of the 8 threshold modules are all pulled low, and each threshold is set in turn.

[0081] According to a specific implementation of the present application, the system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

[0082] For example, the number of threshold modules for identification startup can be determined according to the accuracy requirements. If the accuracy requirements are not so high, such as 256 thresholds, the chip select signals of the first four threshold modules can be pulled low, and the thresholds can be read at intervals. Furthermore, if the traditional MVT solution is used, a threshold module with 8 thresholds can be selected, and only the chip select signal of the first threshold module can be pulled low. The threshold is modified accordingly, and it can be used as a traditional 8-threshold MVT solution.

[0083] The waveform digitization device provided can perform waveform digitization processing on blind pulse signals to achieve fast and simple parameter adjustment and adaptive output coordinate sequence. It can adapt to different sampling requirements and has greater flexibility. In the process of processing pulse signals, there is no need to digitize the pulse waveform by solving a group of equations to obtain a function curve. The traditional MVT method is extended from sampling only specific pulse signals to sampling any pulse signal, and the pulse waveform can be directly restored through the sampling points.

[0084] Example 2

[0085] See also Figure 3 , is a flow chart of a method for digitizing a waveform of a blind pulse signal provided in an embodiment of the present application, which method can be applied to the waveform digitizing device provided in the above embodiment 1. Figure 3As shown, the method mainly comprises the following steps:

[0086] In step S301, the system module determines the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, and starts each target threshold module through a start instruction.

[0087] The system module is connected to multiple threshold modules, first obtains the estimated voltage amplitude of the blind pulse signal to be sampled, and determines the number of threshold modules required according to the estimated voltage amplitude of the blind pulse signal, which is defined as the target threshold module. The chip select pin sends a start instruction to the chip select unit of each target threshold module to start the target threshold module.

[0088] According to a specific implementation of the present application, the system module determines the target threshold module to be started according to the estimated voltage amplitude of the blind pulse signal, and before the step of sending a start instruction to the chip select unit of each target threshold module through the chip select pin, the method also includes:

[0089] Determining whether the voltage threshold of the system module covers the estimated voltage amplitude of the blind pulse signal;

[0090] If the voltage threshold of the system module covers the estimated voltage amplitude of the blind pulse signal, executing the step of determining a target threshold module to be activated according to the estimated voltage amplitude of the blind pulse signal;

[0091] If the voltage threshold of the system module does not cover the estimated voltage amplitude of the blind pulse signal, adjust the estimated voltage amplitude of the blind pulse signal so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0092] For example, the sensitivity can be adjusted so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module. It should be noted that the sensitivity adjustment method includes: adjusting the power supply voltage of the front-end device such as the photoelectric conversion to adjust the gain, adjusting the resistance value of the back-end signal amplification circuit to adjust the gain, etc., so as to achieve that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

[0093] According to a specific implementation of the present application, the step of the system module determining the target threshold module to be activated according to the estimated voltage amplitude of the blind pulse signal includes:

[0094] Determine the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module;

[0095] A threshold module that meets the quantity requirement is selected from all threshold modules as a target threshold module.

[0096] According to a specific implementation of the present application, after the step of starting each target threshold module through a start instruction, the method further includes:

[0097] Configure the voltage threshold of each target threshold module;

[0098] The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

[0099] According to a specific implementation of the present application, the voltage threshold of each target threshold module is split into the voltage threshold of the corresponding voltage unit in the following manner:

[0100] The number of the target threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N;

[0101] The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M;

[0102] Set the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

[0103] For example, according to a specific implementation of the present application, the number of threshold modules M is 8, and the number of voltage units in the threshold module is 64; if the voltage quantity accuracy required for detection is 512, the number of modules of the target threshold module is 8, and the voltage thresholds of each target threshold module are V 64 、V 128 、V 192 ,…,V 512 , where the voltage threshold is V 64 The voltage thresholds of the 64 voltage units in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V 512 The voltage thresholds of the 64 voltage units in the target threshold module are V 448 、V 449 ,…,V 511 .

[0104] If the voltage number accuracy required for detection is 256, the number of target threshold modules is 4, and the voltage thresholds of each target threshold module are V 64 、V 128 、V 192 ,…,V 256 , where the voltage threshold is V64 The cell voltage thresholds of each voltage unit in the target threshold module are V0, V1, ..., V 63 , the voltage threshold is V256 The cell voltage threshold of each voltage cell in the target threshold module is V 192 、V 193 ,…,V 255 .

[0105] According to a specific implementation of the present application, the step of sending a start instruction to a chip select unit of each target threshold module through a chip select pin includes:

[0106] Switch the chip select pin corresponding to each target threshold module to a low level;

[0107] The signal input end of each target threshold module is connected to the blind pulse signal in parallel, and the input end of the threshold comparator is connected to the blind pulse signal and the voltage threshold signal output by each voltage unit respectively. The chip select pin is high by default, and the chip select pin corresponding to each target threshold module is low after being inverted, and is ANDed with the blind pulse signal. The output clock is low and will not trigger the threshold module. When the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the blind pulse signal is valid.

[0108] Step S302, connecting the blind pulse signal to the signal input end of each target threshold module in parallel, connecting the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and sending the comparison signal output by the threshold comparator to the system module.

[0109] Exemplarily, the target threshold module started by the blind pulse signal is input in parallel and connected to one input end of each threshold comparator, and the different voltage thresholds corresponding to each voltage unit are input to the other input end of the corresponding threshold comparator. Each threshold comparator generates a comparison signal according to the amplitude of the blind pulse signal and the size of the corresponding voltage threshold, and outputs it to the system module.

[0110] According to a specific implementation of the present application, the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit are respectively connected to the input end of the threshold comparator, and the comparison signal output by the threshold comparator is sent to the system module, including:

[0111] The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit;

[0112] The blind pulse signal is input into the AND gate circuit via the signal input terminal;

[0113] The output end of the AND gate circuit inputs the blind pulse signal into the signal input end of each threshold comparator.

[0114] The chip selection unit includes an AND gate circuit and an inversion circuit, the chip selection pin of the system module is preset to a high level, and the step of outputting a comparison signal to the system module includes:

[0115] The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit and then input into the AND gate circuit;

[0116] The blind pulse signal is input into the AND gate circuit via the signal input terminal;

[0117] The output end of the AND gate circuit inputs the blind pulse signal into the signal input end of each threshold comparator. If the amplitude of the blind pulse signal is greater than the corresponding voltage threshold received by the threshold comparator, the threshold comparator outputs a jump signal to the system module and records the time when the jump occurs through the system module; if the amplitude of the blind pulse signal is less than the corresponding voltage threshold received by the threshold comparator, the threshold comparator does not jump.

[0118] The chip select pin is high by default, and low after inversion. When ANDed with the blind pulse signal, the output clock is low and will not trigger the comparator threshold. When the threshold module is needed, the chip select signal is pulled low and the blind pulse signal is valid.

[0119] Step S303: the system module determines each voltage threshold and corresponding detection time of the blind pulse signal according to the comparison signal.

[0120] According to a specific implementation of the present application, step S303 includes:

[0121] Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal;

[0122] Obtaining the signal point time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining the noise point time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold for the first time;

[0123] The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

[0124] In this embodiment, the noise time is determined by acquiring the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

[0125] In this embodiment, the signal presence time and / or the noise presence time are both realized by TDC identifying different transition point moments in the comparison signal.

[0126] In this embodiment, the noise presence time is acquired through a timing logic implemented by a threshold comparator and a TDC.

[0127] In this embodiment, waveform digitization processing is mainly performed by detecting blind pulse signals through voltage thresholds, obtaining the time when the blind pulse signals trigger each voltage threshold, and then restoring the waveform based on the voltage value-time information.

[0128] According to a specific implementation of the present application, the step of the system module determining each voltage threshold and detection time of the blind pulse signal according to the comparison signal includes:

[0129] Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal;

[0130] Obtaining the signal point time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining the noise point time when the blind pulse signal corresponding to the comparison signal first crosses the noise voltage threshold;

[0131] The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

[0132] The time information of the blind pulse signal can be divided into two aspects: the time acquisition method at the signal over noise and the time acquisition method at the noise. The signal time acquisition method can be obtained by the existing MVT method, such as recording the flip time of the high and low levels in the comparison signal output by the comparator through TDC to obtain the time corresponding to the rising edge or falling edge of the blind pulse signal crossing different thresholds. However, when the threshold is set to be equivalent to the noise baseline, it is more difficult to obtain the time corresponding to the signal below the noise voltage threshold. The noise time acquisition method provided in this embodiment is based on FPGA to directly obtain the first time point after the pulse exceeds the baseline and does not return to the baseline in a short time, and this time point is used as the start time of the pulse.

[0133] Those skilled in the art should understand that "short time" in the present application is a relative concept, which may vary according to the type, amplitude or detection accuracy requirements of the blind pulse signal. For example, for some signals with relatively regular waveforms, short time may refer to no more than 100ns or no more than 50ns. For some applications with higher detection accuracy requirements, short time may refer to no more than 20ns or no more than 10ns.

[0134] The above process mainly uses the threshold comparator and TDC. TDC is used to obtain time, and the threshold comparator is used to compare the signal (including blind pulse signal and noise signal) with the voltage threshold. When the signal crosses the voltage threshold, a corresponding edge trigger signal is generated (such as the edge time corresponding to the high and low level flip). The threshold comparator uses a differential comparator, such as Figure 4 The threshold comparator based on LVDS input interface is shown. The high and low levels in differential signal communication are identified by the relative size of the voltages at the positive input terminal and the negative input terminal in the differential interface, that is, when the voltage at the positive input terminal is higher than the voltage at the negative input terminal, the input signal is considered to be logic '1'; when the voltage at the positive input terminal is lower than the voltage at the negative input terminal, the input signal is considered to be logic '0'. Connect the blind pulse signal to the positive input terminal and connect the voltage threshold to the negative input terminal. When the pulse signal voltage amplitude is higher than the threshold, the differential comparator considers the input signal to be logic '1'; when the pulse signal voltage amplitude is lower than the threshold, the differential comparator considers the input signal to be logic '0'. The moment when the analog pulse signal crosses the voltage threshold corresponds to the moment when the rising edge jump or falling edge jump of the logic signal identified by the LVDS receiver occurs.

[0135] Use TDC to calculate the transition time, that is, the time to reach the threshold. The time obtained by TDC is realized by time interpolation using the internal resources of FPGA. Figure 5 The figure shows a schematic diagram of the time interpolation method. The measurement of the edge signal arrival time consists of two parts: coarse time measurement and fine time measurement. Coarse time measurement refers to a long-range, low-precision measurement of the signal occurrence time, which is usually achieved by using a counter to count the number of flips of the periodic clock signal. c It is the coarse time of the rising edge jump time of the measured signal Hit under the interpolation TDC measurement. The coarse time measurement can be completed by recording the number of periodic clock signal flips when the measured signal jumps to a high level, that is, T c =n×T, where n is also called the coarse count; T is the cycle time of the clock signal. Fine time measurement refers to a high-precision measurement of the interval time between the signal occurrence moment and the moment corresponding to the coarse time count, usually using a delay chain for measurement. f is the fine time measurement result, which is the time when the rising edge jump of the measured signal Hit occurs and T c The time interval between moments. The pulse occurrence time is measured by time interpolation method, and the measurement result includes two parts, namely the rough time T in the figure. c and fine time T f The time of pulse occurrence is recorded as T c -T f .

[0136] like Figure 6The figure shows a schematic diagram of a delay chain, which is composed of a plurality of delay units cascaded in series, and the delay time of each delay unit is ΔT. The signal to be measured Hit is connected to the first-stage delay unit, which records the level state of the current Hit signal. After ΔT time, the signal state recorded by the first-stage delay unit will be transmitted to the second-stage delay unit and the current signal level state will be re-recorded; at the same time, the second-stage delay unit will pass its previously recorded level state to the next-stage delay unit and re-record the level state passed by the first-stage delay unit. The working method of subsequent delay units is similar. At time t, the level state recorded by the nth-stage delay unit is the level state of the signal to be measured Hit before time n×ΔT. Therefore, the time for the rising edge jump of the signal to be measured Hit is measured by time interpolation method, and it is only necessary to measure the time at T f By constantly recording the level state recorded by each delay unit in the delay chain and finding the first delay unit with a low level state from the first level to the last level, fine time measurement can be achieved. In this way, the signal processing time can be obtained.

[0137] The acquisition of the noise time is based on FPGA, using threshold comparator and TDC to implement a timing logic, so as to obtain effective time information of the noise. If the voltage threshold of the threshold comparator is set below the noise amplitude, when there is a voltage greater than the set threshold, the level will flip. Figure 7 The figure shows a simple schematic diagram. The timing above is the clock cycle, and the level flipping of the threshold comparator output is shown below. When the pulse does not come, there will be a baseline noise, which will also continuously trigger the threshold comparator, forming a result between A and B. The level keeps flipping, and the time at this time is not the real start time of the pulse, so some timing judgment needs to be added.

[0138] like Figure 8The figure shows the sequential logic process of the time acquisition at the noise provided by the present embodiment. clk is the clock signal, signal is the level signal output by the threshold comparator, time is the continuously changing time information, cnt is the counter output signal, reg, reg_timeup, reg_timedown are all registers, and flag_up, flag_reg, flag_down are flag signals. When there is no pulse input, signal will continue to jump like the previous part of the figure. At this time, the signal jump position of multiple TDCs in one clock cycle needs to be judged. If the signal is high at this time, cnt starts counting; if the signal is low at this time, cnt is cleared. When the pulse level data enters, cnt will continue to accumulate according to the clock signal until the pulse ends and returns to the state when there is no pulse input. When cnt=1, reg triggers the latch to store the current time information; when cnt reaches a certain count N, the flag_up signal will be pulled high; and when the flag_up signal is high, the reg data will be assigned to reg_timeup, which is the real time triggered by the rising edge.

[0139] The flag_reg signal will be pulled high when it recognizes that the flag_up signal is high, and will be pulled low when it recognizes that cnt is 1 again; based on the above flag_reg signal, the pull-up condition of the flag_down signal is that the flag_reg signal is high and cnt is 0; and when the flag_down signal is high, the time data will be assigned to reg_timeup, which is the real time of the falling edge trigger. In this way, the real rising and falling edge trigger time of the pulse can be obtained.

[0140] This method requires knowing the approximate pulse width in advance and setting an N to make a judgment. This N is used to roughly estimate the pulse width. When the pulse width is large, the value of N will be very large. At this time, due to the limited number of cnt digits, certain settings are required. When cnt reaches the maximum number of digits, the next step is to assign cnt to N+1 and continue to accumulate the count until the maximum value is reached.

[0141] Furthermore, with a 64 threshold (TH_ALL), a reference voltage of 3.3V (V ref ), taking the noise amplitude of 80mv as an example, the thresholds are evenly distributed from 0 to 3.3V, that is, the interval is 3.3V / (64–1)=52.4mv. The lowest 2 thresholds (TH_Trigger, 0mv, 52.4mv) adopt the noise time acquisition method, and the other thresholds adopt the signal time acquisition method. In this way, the time information of the trigger point under any threshold can be obtained, and the parameters can be quickly adjusted and modified.

[0142] Exemplarily, the system module restores the waveform of the blind pulse signal in a time sequence according to the integrated information of all time-voltage pairs.

[0143] After the system module obtains the data pair information composed of each voltage threshold and detection time, it restores and displays the waveform to realize waveform digitization. The specific methods of restoring the waveform may include: 1. scatter plot; 2. line graph; 3. curve smoothing; 4. equal time interval interpolation method (V-T transformation).

[0144] In addition, according to a specific embodiment of the present application, after the step of determining the number of target threshold modules to be started according to the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy, and the number of voltage units in each threshold module, the method further includes:

[0145] Acquire predefined global variables, wherein the global variables include a total threshold number, an effective threshold number, and a noise threshold number, wherein the total threshold number is the sum of the effective threshold number and the noise threshold number;

[0146] Calculate the actual number of thresholds included in the target threshold module according to the number of threshold modules;

[0147] If the actual threshold quantity is greater than the effective threshold quantity, the blind pulse signal is determined to be a effective signal.

[0148] Three global variables are defined in the hardware description language (Verilog). The first one is used to describe the total number of thresholds TH_ALL, that is, the number of voltage thresholds set within the voltage threshold range; the second one is used to describe the number of effective thresholds TH_MVT. Only when the number of thresholds triggered by the signal to be sampled is greater than the effective threshold number, it is considered a valid signal, which can be used to filter out low-amplitude signals that are not within the energy window range; the third one is used to describe the noise voltage threshold TH_Trigger. Only when a voltage threshold higher than the noise voltage threshold is triggered, it is considered a valid signal, not a noise signal or a signal buried in the noise. Global variables can be flexibly set and quickly modified, and can be adaptively adjusted to meet the needs of different application scenarios.

[0149] TH_ALL=TH_MVT+TH_Trigger; Generally, the noise threshold does not need to be modified, so only TH_ALL needs to be modified.

[0150] After obtaining the horizontal axis time information of the waveform according to the above steps, it is also necessary to obtain the coordinate point information. When multiple threshold modules are used in free combination, each threshold processing is a separate processing channel, and the thresholds are in parallel. Each threshold has a flag signal, which can be regarded as a synchronous processing of the comparator output signal. When the rising edge of the pulse is recognized, it is pulled high. When the falling edge is recognized, it is delayed by one clock cycle to write the data into the cache, and then pulled low. When the rising edge is recognized again, this operation is repeated.

[0151] In the case where a blind pulse signal has a baseline, the pulse signal segment from the pulse arrival time to the pulse end time, or the time period when the minimum noise threshold is triggered by the pulse falling edge is considered a group of pulses. After a group of pulses is identified, the pulse information is packaged and sent to the PC, or for needs such as area calculation, time calculation, etc.

[0152] Further, the step of obtaining the noise location time when the blind pulse signal corresponding to the comparison signal first crosses the noise threshold includes:

[0153] If the blind pulse signal is a single-peak pulse signal, obtain the trigger time of the front / rear trigger point of the rising edge and the trigger time of the front / rear trigger point of the falling edge as the noise time, and set the other times to zero;

[0154] If the blind pulse signal is a multi-peak pulse signal, the trigger time of all trigger points is obtained and the threshold number of each trigger point is marked.

[0155] This embodiment provides five ways to output time information, which can be selected through the FPGA firmware implementation method: 1. Take the rising edge before and the falling edge before; 2. Take the rising edge before and the falling edge after; 3. Take the rising edge after and the falling edge before; 4. Take the rising edge after and the falling edge after; 5. Output all points. Among them, methods 1 to 4 are suitable for single-peak pulse signals, and method 5 is suitable for multi-peak pulse signals.

[0156] For the output method of the front and back points of the single-peak pulse signal, the coordinate point obtained by "taking the front" is the first value of the trigger. For the rising edge, when the flag signal is pulled high, the time information is latched immediately; the same is true for the falling edge, when the flag signal is pulled low, the time information is latched immediately. The coordinate point obtained by "taking the back" is the last value of the trigger. For the rising edge, when the flag signal is pulled high, the time information is not latched, and it will continue to change according to the pulse triggering situation; the same is true for the falling edge, when the flag signal is pulled low, the time information is also not latched. When the end of the pulse is recognized (the pulse end time or the minimum threshold of over-noise is triggered by the falling edge of the pulse), the time information of the threshold is output.

[0157] For the full-point output mode of multi-peak pulse signals, the present invention will add a "threshold number" as a frame header in each threshold output information, and write the time information into the cache whenever the falling edge of the flag signal is identified. Similarly, when the end of the pulse is identified (the pulse end time or the minimum threshold of over-noise is triggered by the falling edge of the pulse), the time information of the threshold is output. This method will have a dead time of 1 clock cycle, but considering comprehensively, it has no effect on the reproduction of the waveform. Those skilled in the art should note that the dead time is for a single threshold, and there is no dead time between thresholds. Assuming a system clock of 200M, the dead time is 5ns. If a single threshold fluctuation occurs within 5ns, it can be approximately regarded as the superposition of noise signals, and there is no visible effect on the final waveform recovery.

[0158] In the specific implementation, if method 1 to method 4 are selected, the time information corresponding to the untriggered threshold will be assigned a value of zero. For method 5, since the output information contains the threshold number, this problem does not need to be considered. Regardless of the above methods, the length of the output information can be calculated, so the size of the data packet can be expressed as a parameter to achieve an adaptive output coordinate sequence.

[0159] On the basis of the above embodiment, an error correction process may be further provided, including correction of the vertical axis-voltage error and correction of the horizontal axis-time error.

[0160] The vertical axis - voltage error correction mainly considers the influencing factors such as DAC threshold / resistance network, comparator trigger voltage, etc.

[0161] According to a specific embodiment of the present application, the voltage threshold correction is performed by any of the following methods: Method 1: setting a fixed horizontal and vertical axis unit scale, collecting and recording the average value as the voltage threshold; Method 2: determining the voltage threshold based on the triggering condition of a square wave signal near a preset amplitude; Method 3: determining the voltage threshold based on the voltage signal of the output trigger point corresponding to a triangle wave as an input signal.

[0162] Method 1: Use an oscilloscope to read the threshold output pin, set fixed horizontal and vertical axis unit scales, avoid factors such as quantization errors, collect and record the average value multiple times, which can be considered as the actual threshold.

[0163] Method 2: Set the threshold at a fixed voltage interval, use a square wave as the input signal, and use the debugging tool SignalTap to capture the test multiple times; assuming that the threshold is set to 500mv, the signal generator generates a square wave signal with an amplitude of about 500mv, and the debugging tool SignalTap is used to observe the triggering of the threshold. There are two situations: ① The amplitude is V min When the trigger is successful, very few cases occur; ② The amplitude is V maxIn rare cases, the trigger is not successful. The average value can be considered as the actual threshold.

[0164] Method 2 additionally considers the influence of comparator trigger voltage on it based on method 1. Using the above method, different thresholds are set and tested multiple times to obtain two coordinate vectors, namely the theoretical threshold and the actual threshold. Fitting them completes the vertical axis correction.

[0165] Method 3: Set the threshold at equal intervals with a fixed voltage, use a triangle wave as the input signal, and read the coordinate information of the output trigger point; because the horizontal axis TDC accuracy system error is small, this solution is equivalent to further correction of the vertical axis voltage threshold.

[0166] The horizontal axis-time error correction mainly considers and corrects the horizontal axis influencing factors such as the time difference between channels, single-channel TDC, and routing delay.

[0167] Method 1: All DAC outputs are set to the same voltage value, a square wave is used as the test signal, and the time information of each channel is read. The time information of threshold number 1 is used as the reference, and the difference between the time information corresponding to other thresholds and the reference is calculated. The average value is obtained after multiple measurements.

[0168] Method 2: All thresholds are provided by a fixed voltage reference, and the rest are the same as method 1.

[0169] Method 2 optimizes the influence of the vertical axis on the horizontal axis based on method 1. By subtracting the offset from the waveform presentation part of the FPGA or host computer in the above method, the horizontal axis correction is completed.

[0170] Horizontal-vertical axis error correction: Explore the combined error impact of the horizontal-vertical axis, establish an error model and propose a normalized correction method for the system error.

[0171] Compared with the traditional MVT method, the waveform digitization method of the blind pulse signal provided by the present application does not need to restore the pulse waveform by solving the equation group to obtain the function curve in the process of processing the pulse signal, and the traditional MVT method is extended from sampling only for known pulse shape signals to sampling any pulse signal. Since the number of thresholds can be freely modified, the parameter adjustment can be fast, simple and adaptive output coordinate sequence, which can adapt to different sampling requirements and has greater flexibility. Its sampling effect can be equivalent to an analog-to-digital converter with a sampling rate of 100KSps to 100GSps. In this embodiment, the signal sampling point is obtained only when the threshold is triggered, and the result will be output, which is non-continuous sampling and reduces power consumption. The position of the acquired sampling point is closely related to the measured signal. The signal changes frequently → rich information → many samples, and the signal changes slowly → less information → fewer samples, and almost no redundant data is generated; in application scenarios such as spectrum acquisition, the points generated are all useful information, and there is no need to accumulate a large number of points (with redundant data) like a high-speed ADC. There is huge potential for development. The TDC accuracy is affected by the performance of the device and can theoretically reach the picosecond level. If the storage medium / transmission rate is sufficient, it can be comparable to a sampling rate of about 500GSps+.

[0172] The embodiments of the present application also relate to electronic devices capable of implementing the methods of the embodiments of the present application.

[0173] In some embodiments, an electronic device is provided, which may include a processor and a memory storing a computer program, wherein the processor is configured to execute the waveform digitization method of any embodiment of the present application when running the computer program.

[0174] In some embodiments, the waveform digitization method described in the present application can be implemented using a single or multiple electronic devices. In some embodiments, it can be implemented using cloud or distributed electronic devices.

[0175] In some embodiments, the electronic device includes a processor, which can perform various appropriate operations and processes according to the program and / or data stored in the read-only memory (ROM) or the program and / or data loaded from the storage portion into the random access memory (RAM). The processor can be a single-core or multi-core processor, or it can include multiple processors. In some embodiments, the processor may include a general-purpose main processor (such as a CPU) and one or more special coprocessors, such as a graphics processing unit (GPU), a neural network processor (NPU), a digital signal processor (DSP) or other general or application-specific integrated circuits. In RAM, various programs and data required for the operation of the electronic device are also stored. The processor, ROM, and RAM are connected to each other via a bus.

[0176] The processor and the memory are used together to execute the program stored in the memory. When the program is executed by the computer, the steps or functions of the methods described in the above embodiments can be implemented.

[0177] In some embodiments, the electronic device may be combined with various components to obtain a method, device, and system having the advantages of the present invention.

[0178] Although not shown, in some embodiments, a computer-readable storage medium is also provided, storing a computer program, which is configured to execute any method of the present application embodiment when it is run. The computer program includes various program modules / units constituting the device according to the embodiment of the present application, and the computer program composed of various program modules / units can realize the functions corresponding to the various steps in the method described in the above embodiment when it is executed. The computer program can also be run on an electronic device as described in the embodiment of the present application.

[0179] The storage medium of the embodiment of the present application includes non-volatile and / or volatile articles that can be used to store information by any method or technology. Non-volatile memory may include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory may include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in various forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0180] The embodiments of the present application are described above in conjunction with the accompanying drawings, but the present application is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present application, ordinary technicians in this field can also make many forms without departing from the purpose of the present application and the scope of protection of the claims, all of which are within the protection of the present application.

Claims

1. A waveform digitizing device, characterized in that: It includes a system module and a threshold voltage module; wherein, The system module comprises a main chip, and the main chip is provided with a chip selection pin and a signal pin; The threshold voltage module includes a plurality of threshold modules, each of which is provided with a signal input terminal, a voltage input terminal, a signal output terminal, a chip selection unit, a threshold comparator and a plurality of voltage units. In each threshold module, the voltage input terminal is connected to the main chip, the output terminal of the voltage unit and the signal input terminal are respectively connected to the input terminal of the threshold comparator, the chip selection unit is connected to the chip selection pin of the main chip, and the output terminal of the threshold comparator is connected to the signal pin of the main chip via the signal output terminal; The main chip configures the voltage threshold of each threshold module through each voltage unit.

2. The waveform digitizing device according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter.

3. The waveform digitizing device according to claim 1, characterized in that: The voltage unit includes a digital-to-analog converter and a voltage dividing resistor connected in series to the digital-to-analog converter.

4. The waveform digitizing device according to claim 3, characterized in that: The voltage-dividing resistors in each voltage unit in the threshold module are equivalent circuits.

5. The waveform digitizing device according to claim 1, characterized in that: The threshold comparator is a differential comparator.

6. The waveform digitizing device according to any one of claims 1 to 5, characterized in that: The chip select unit includes an AND gate circuit and an inversion circuit. The chip select unit is connected to one input end of the AND gate circuit via the inversion circuit, the signal input end is connected to the other input end of the AND gate circuit, and the output end of the AND gate circuit is connected to the signal input end of each threshold comparator.

7. The waveform digitizing device according to claim 1, characterized in that: The main chip configures the voltage threshold of each threshold module through serial communication, and stores the voltage threshold setting in an erasable memory. The threshold module automatically reads the voltage threshold from the erasable memory each time it is powered on.

8. The waveform digitizing device according to claim 1, characterized in that: The threshold module is connected to the system module in a plug-in manner; the main chip is connected to each threshold module in a plug-in manner.

9. The waveform digitizing device according to claim 1, characterized in that: The number of the threshold modules is M, the number of voltage units in each threshold module is N, and the number of voltage thresholds of the system module is M×N, wherein M≥2 and N is a positive integer.

10. The waveform digitizing device according to claim 9, characterized in that: The voltage thresholds corresponding to adjacent threshold modules gradually increase and the intervals are equal, and the voltage thresholds corresponding to adjacent voltage units in the same threshold module gradually increase and the intervals are equal.

11. The waveform digitizing device according to claim 1, characterized in that: The system module is configured to identify the number of threshold modules that are enabled, and adaptively change the size interval of the corresponding voltage threshold in each threshold module to adapt to the corresponding number of thresholds.

12. A method for digitizing the waveform of a blind pulse signal, characterized in that: The waveform digitization method comprises: The system module determines the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, and starts each target threshold module through a start instruction; Connecting the blind pulse signal to the signal input end of each target threshold module in parallel, connecting the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator respectively, and sending the comparison signal output by the threshold comparator to the system module; The system module determines each voltage threshold and corresponding detection time of the blind pulse signal according to the comparison signal.

13. The waveform digitization method according to claim 12, characterized in that: Before the step of the system module determining the number of target threshold modules to be started according to the estimated voltage amplitude of the blind pulse signal and starting each target threshold module through a start instruction, the waveform digitization method further includes: Determining whether the voltage threshold range of the system module covers the estimated voltage amplitude of the blind pulse signal; If the voltage threshold range of the system module covers the estimated voltage amplitude of the blind pulse signal, performing the step of determining the number of target threshold modules that need to be activated according to the estimated voltage amplitude of the blind pulse signal; If the voltage threshold range of the system module does not cover the estimated voltage amplitude of the blind pulse signal, adjust the estimated voltage amplitude of the blind pulse signal so that the estimated voltage amplitude of the blind pulse signal after adjustment is within the coverage range of the voltage threshold of the system module.

14. The waveform digitization method according to claim 12, characterized in that: The step of the system module determining the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal includes: Determine the number of target threshold modules that need to be started according to the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module; A threshold module that meets the quantity requirement is selected from all threshold modules as a target threshold module.

15. The waveform digitization method according to claim 14, characterized in that: After the step of starting each target threshold module by a start instruction, the waveform digitization method further includes: Configure the voltage threshold of each target threshold module; The voltage threshold of each target threshold module is split into voltage thresholds of corresponding voltage units.

16. The waveform digitization method according to claim 15, characterized in that: The voltage threshold of each target threshold module is split into the voltage thresholds of the corresponding voltage units in the following manner: The number of the target threshold modules is M, the number of the voltage units is N, M and N are both positive integers, and the number accuracy of the voltage threshold required for detection is P=M×N; The voltage threshold of the i-th target threshold module is recorded as V i×N , where 1≤i≤M; Set the voltage threshold V of the i-th target threshold module i×N The voltage threshold of each voltage unit in the corresponding N voltage units is split.

17. The waveform digitization method according to claim 12, characterized in that: The step of starting each target threshold module through a start instruction includes: Switch the chip select pin corresponding to each target threshold module to a low level; The signal input end of each target threshold module is connected to the blind pulse signal in parallel, and the input end of the threshold comparator is respectively connected to the blind pulse signal and the voltage threshold signal output by each voltage unit. The chip select pin is high level by default, and the chip select pin corresponding to each target threshold module is low level after being inverted, and is ANDed with the blind pulse signal. The output clock is low level and will not trigger the corresponding target threshold module; when the corresponding target threshold module needs to be triggered, the chip select signal of the corresponding target threshold module is pulled low, and the blind pulse signal is valid.

18. The waveform digitization method according to claim 12, characterized in that: The step of respectively connecting the blind pulse signal and the corresponding voltage threshold signal output by the voltage unit to the input end of the threshold comparator, and sending the comparison signal output by the threshold comparator to the system module includes: The low-level chip selection signal connected to the chip selection unit is inverted by the inversion circuit of the chip selection unit and then input into the AND gate circuit of the chip selection unit; The blind pulse signal is input into the AND gate circuit via the signal input terminal; The output end of the AND gate circuit inputs the blind pulse signal into the signal input end of each threshold comparator.

19. The waveform digitization method according to any one of claims 12 to 18, characterized in that: The step of the system module determining each voltage threshold and the corresponding detection time of the blind pulse signal according to the comparison signal includes: Determine a voltage threshold corresponding to a voltage unit connected to a threshold comparator corresponding to the comparison signal; Obtaining the signal point time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold, and obtaining the noise point time when the blind pulse signal corresponding to the comparison signal crosses the corresponding voltage threshold for the first time; The voltage threshold corresponding to each comparison signal is associated with the signal time and the noise time.

20. The waveform digitization method according to claim 19, characterized in that: The noise time is determined by obtaining the first time point after the signal crosses the baseline and does not return to the baseline within a preset time.

21. The waveform digitization method according to claim 19, characterized in that: The signal time and / or the noise time are both achieved by TDC identifying different jump point moments in the comparison signal.

22. The waveform digitization method according to claim 19, characterized in that: The noise time is obtained through a threshold comparator and a timing logic implemented by a TDC.

23. The waveform digitization method according to claim 19, characterized in that: The step of obtaining the noise time when the blind pulse signal corresponding to the comparison signal first crosses the corresponding voltage threshold comprises: If the blind pulse signal is a single-peak pulse signal, obtain the trigger time of the front / rear trigger point of the rising edge and the trigger time of the front / rear trigger point of the falling edge as the noise time, and set the other times to zero; If the blind pulse signal is a multi-peak pulse signal, the trigger time of all trigger points is obtained and the threshold number of each trigger point is marked.

24. The waveform digitization method according to claim 14, characterized in that: After the step of determining the number of target threshold modules to be started according to the estimated voltage amplitude of the blind pulse signal, the detection voltage accuracy and the number of voltage units in each threshold module, the waveform digitization method further includes: Acquire predefined global variables, wherein the global variables include a total threshold number, an effective threshold number, and a noise threshold number, wherein the total threshold number is the sum of the effective threshold number and the noise threshold number; Calculate the actual number of thresholds included in the target threshold module according to the number of threshold modules; If the actual threshold number is greater than the effective threshold number, it is determined that the blind pulse signal is a valid signal.

25. The waveform digitization method according to claim 12, characterized in that: After the step of the system module determining each voltage threshold and the corresponding detection time of the blind pulse signal according to the comparison signal, the waveform digitization method further includes: The system module restores the waveform of the blind pulse signal in a time sequence according to the integrated information of all detection time-voltage threshold pairs.

26. The waveform digitization method according to claim 25, characterized in that: Methods for restoring the waveform of the blind pulse signal include scatter plot, line graph, curve smoothing and equal time interval interpolation.

27. The waveform digitization method according to claim 12, characterized in that: The waveform digitization method further includes performing voltage threshold correction and / or time correction.

28. The waveform digitization method according to claim 27, characterized in that: The voltage threshold correction is performed by any of the following methods: Method 1: setting fixed horizontal and vertical axis unit scales, collecting and recording the average value as the voltage threshold; Method 2: determining the voltage threshold based on the triggering condition of a square wave signal near a preset amplitude; Method 3: determining the voltage threshold based on the voltage signal of the output trigger point corresponding to a triangle wave as the input signal.

29. The waveform digitization method according to claim 27, characterized in that: The time correction is performed based on the time difference between channels with different voltage thresholds, single-channel TDC, and wiring delay factors.

30. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, which is configured to perform the waveform digitization method according to any one of claims 12 to 29 when executed.

31. An electronic device, characterized in that: include: A processor and a memory storing a computer program, wherein the processor is configured to perform the waveform digitization method according to any one of claims 12 to 29 when running the computer program.

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