Memory management method and memory controller

Abstract

The invention discloses a memory management method and a memory controller. The memory management method is used for a rewritable nonvolatile memory module. The method comprises the steps that a plurality of first storage groups are identified, each first storage group comprises a plurality of first entity units, and the first storage groups belong to a second storage group; counting a first reading frequency of each first storage group; obtaining a target first storage group according to the plurality of first reading times; counting a target first reading frequency of the target first storage group and a second reading frequency of the second storage group; obtaining an expected block reading number of times based on at least one of the target first reading number of times and the second reading number of times; and if the expected block reading frequency exceeds a preset reading frequency threshold, executing a read verification operation on the second storage group. According to the method, through a multi-level statistics and prediction mechanism, the evaluation precision of the read verification triggering operation is improved while the storage space occupation is reduced, and the storage efficiency and the data reliability are effectively balanced.

Description

Technical Field

[0001] The present invention relates to a memory management technology, and in particular to a memory management method for triggering a storage device to perform a read verification operation and a memory controller using the method. Background Art

[0002] Non-volatile memory refers to computer memory in which the stored data does not disappear when the current is cut off. It has the advantages of non-volatility, power saving, small size and no mechanical structure, and is widely used in various electronic devices.

[0003] Common non-volatile memory is a memory configured with flash memory (such as a solid-state drive), which has the characteristics of high read and write speed and does not require a mechanical structure to access data.

[0004] In NAND Flash storage devices, frequent read operations on NAND will cause crosstalk to other word lines (WL). Therefore, when the number of reads of a storage block reaches a certain threshold, that is, the read interference threshold is reached, a read verification operation needs to be performed on the storage block. The read verification operation refers to rescanning the data on the storage block. If uncorrectable erroneous data is found, error handling is required to recover the data.

[0005] At present, the method for judging whether to perform a read verification operation is mainly based on the evaluation of the storage block as the basic unit. This method needs to count the number of reads of each storage block, so it takes up more storage space. As the capacity of storage devices continues to increase, the storage overhead of this method also increases, affecting the overall performance and cost-effectiveness of storage devices. Summary of the invention

[0006] The purpose of the present invention is to provide a method for triggering a storage device to perform read verification, aiming to overcome the problems existing in the prior art. The present invention adopts an organizational structure at a higher level than a physical unit as a basic statistical unit, and realizes a more efficient and accurate read verification trigger mechanism through prediction and dynamic adjustment.

[0007] One or more embodiments of the present invention provide a memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units, and the method includes: identifying a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; counting a first read count of each first storage group, wherein the first read count reflects the sum of the read counts of each first physical unit belonging to the corresponding first storage group; acquiring a target first storage group among the plurality of first storage groups according to the plurality of first read counts of the plurality of first storage groups; after acquiring the target first storage group, counting a target first read count of the target first storage group and a second read count of the second storage group, wherein the second read count reflects the sum of the read counts of all first physical units belonging to the second storage group; acquiring an expected block read count based on at least one of the target first read count and the second read count; and performing a read verification operation on the second storage group if the expected block read count exceeds a preset read count threshold.

[0008] In one or more embodiments of the present invention, the method also includes: during the period of counting the first number of reads of each first storage group, dividing the predetermined storage space into multiple first counting spaces, wherein the multiple storage bits of the multiple first counting spaces are used to respectively record the first number of reads of each first storage group, wherein the first quantity of the multiple storage bits of the multiple first counting spaces reflects the maximum number of reads that can be recorded; when the target first number of reads recorded by the target first counting space among the multiple first counting spaces reaches the maximum number of reads, determining the target first storage group corresponding to the target first counting space.

[0009] In one or more embodiments of the present invention, the step of counting the target first read count of the target first storage group and the second read count of the second storage group includes: after obtaining the target first storage group, re-dividing the predetermined storage space into a second counting space and a third counting space, wherein the second counting space is used to record the second read count, and the third counting space is used to record the target first read count, wherein the second number of multiple storage bits in the second counting space and the third number of multiple storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

[0010] In one or more embodiments of the present invention, the method also includes: during the period of counting the first read times of each first storage group, each time a read operation is performed on any first physical unit belonging to a first storage group, the first read times recorded in the corresponding first counting space are increased; during the period of counting the target first read times of the target first storage group and the second read times of the second storage group: each time a read operation is performed on any first physical unit belonging to the target first storage group, the target first read times recorded in the third counting space are increased; and each time a read operation is performed on any first physical unit belonging to the second storage group, the second read times recorded in the second counting space are increased.

[0011] In one or more embodiments of the present invention, the step of obtaining the expected block read number based on at least one of the target first read number and the second read number includes: obtaining the first expected block read number based on the target first read number; obtaining the second expected block read number based on the second read number; obtaining the expected block read number according to the first expected block read number and the second expected block read number, the expected block read number being the one with the largest value between the first expected block read number and the second expected block read number; or obtaining the expected block read number based on the target first read number and the second read number.

[0012] In one or more embodiments of the present invention, the step of obtaining the first expected block read number based on the target first read number includes: obtaining a first average block read number according to the target first read number and the number of first physical units corresponding to the target first storage group, wherein the first number of physical units is the total number of the multiple first physical units belonging to the target first storage group; and using the first average block read number as the first expected block read number.

[0013] In one or more embodiments of the present invention, the step of obtaining the second expected block read number based on the second read number includes: obtaining a second average block read number according to the second read number and a second physical unit number corresponding to the second storage group, wherein the second physical unit number is the total number of all first physical units belonging to the second storage group; and using the second average block read number as the second expected block read number.

[0014] In one or more embodiments of the present invention, the step of obtaining the expected block read number based on the target first read number and the second read number includes: obtaining a first average block read number according to the target first read number and the number of first physical units corresponding to the target first storage group, wherein the first physical unit number is the total number of the multiple first physical units belonging to the target first storage group; obtaining a second average block read number according to the second read number and the number of second physical units corresponding to the second storage group, wherein the second physical unit number is the total number of all first physical units belonging to the second storage group; and obtaining the expected block read number according to the first average block read number and the second average block read number.

[0015] In one or more embodiments of the present invention, the step of obtaining the expected block read number according to the first average block read number and the second average block read number includes: obtaining the larger value of the first average block read number and the second average block read number; obtaining the absolute difference between the first average block read number and the second average block read number; and taking the sum of the larger value and the absolute difference as the expected block read number.

[0016] In one or more embodiments of the present invention, the step of obtaining the expected block read count based on the target first read count and the second read count includes:

[0017] Acquire an imbalance coefficient, where the imbalance coefficient reflects the imbalance degree of the number of reads of each first physical unit in the second storage group;

[0018] The unbalance coefficient is multiplied by an average number of reads of the first physical unit in the second storage group to obtain the expected number of block reads.

[0019] In one or more embodiments of the present invention, the step of obtaining the imbalance coefficient includes:

[0020] Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group;

[0021] Obtaining a second average block read count according to the second read count and the number of second physical units corresponding to the second storage group;

[0022] Calculating a maximum expected number of reads, wherein the maximum expected number of reads is the sum of a larger value of the first average block read number and the second average block read number and an absolute value of a difference between the two;

[0023] Divide the maximum expected number of reads by the second average number of block reads to obtain a current imbalance coefficient;

[0024] The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

[0025] One or more embodiments of the present invention provide a memory controller for controlling a storage device equipped with a rewritable non-volatile memory module. The memory controller includes: a memory interface control circuit electrically connected to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units; and a processor electrically connected to the memory interface control circuit. Wherein, the processor is configured to: identify multiple first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes multiple first physical units, wherein the multiple first storage groups belong to the second storage group; count the first read times of each first storage group, wherein the first read times reflect the sum of the read times of each first physical unit belonging to the corresponding first storage group; obtain a target first storage group among the multiple first storage groups according to the multiple first read times of the multiple first storage groups; after obtaining the target first storage group, count the target first read times of the target first storage group and the second read times of the second storage group, wherein the second read times reflect the sum of the read times of all first physical units belonging to the second storage group; obtain an expected block read times based on at least one of the target first read times and the second read times; if the expected block read times exceeds a preset read times threshold, perform a read verification operation on the second storage group.

[0026] Based on the above, the memory management method and memory controller provided by the embodiments of the present invention can significantly save the storage space and computing resources used to record the number of read times of each block through multi-level storage group statistics and dynamic prediction mechanisms, and also maintain the execution of necessary read verification operations, thereby realizing the precise triggering of read verification operations and enhancing system adaptability and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] The accompanying drawings are included to provide a further understanding of the present invention and are incorporated in and constitute a part of this specification. The drawings illustrate embodiments of the present invention and together with the description serve to explain the principles of the present invention.

[0028] Figure 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention;

[0029] Figure 2is a flowchart of a memory management method according to an embodiment of the present invention;

[0030] Figure 3 is a schematic diagram of the architecture of a rewritable non-volatile memory module according to an embodiment of the present invention;

[0031] Figure 4 A schematic diagram of dividing a predetermined storage space into a plurality of first counting spaces according to an embodiment of the present invention;

[0032] Figure 5 It is a schematic diagram showing re-dividing a predetermined storage space into a second counting space and a third counting space according to an embodiment of the present invention.

[0033] Description of Figure Numbers

[0034] 10: Host system

[0035] 20: Storage device

[0036] 211: First processor

[0037] 110: Second processor

[0038] 120: Host memory

[0039] 130: Data transmission interface circuit

[0040] 210: Memory controller

[0041] 212: Data management circuit

[0042] 213: Memory interface control circuit

[0043] 214: Buffer memory

[0044] 220: Rewritable non-volatile memory module

[0045] 230: Connecting interface circuit

[0046] S210-S260: Process steps of the memory management method

[0047] BM: Reserved storage space

[0048] BM1: Initially allocated reserved storage space

[0049] BM2: Reserved storage space after redivision

[0050] CS1(1)~CS1(4): First counting space

[0051] CS2: Second Counting Space

[0052] CS3: Third Counting Space

[0053] 221(1) to 221(4): First storage group

[0054] 222(1)~222(M): Second storage group

[0055] 220(1)~220(4): Physical architecture (channel, CE, chip or plane)

[0056] BK1, BK2, BKN: Solid elements

[0057] A41~A42、A51~A53:arrow DETAILED DESCRIPTION

[0058] Reference will now be made in detail to exemplary embodiments of the present invention, examples of which are illustrated in the accompanying drawings. Whenever possible, the same reference numerals are used in the drawings and the description to refer to the same or like parts.

[0059] Figure 1 FIG. 1 is a block diagram of a host system and a storage device according to an embodiment of the present invention. Figure 1 , the host system 10 is, for example, a personal computer, a notebook computer, or a server. The host system 10 includes a processor 110 (also referred to as a second processor), a host memory 120, and a data transfer interface circuit 130. In the present embodiment, the processor 110 is coupled (also referred to as electrically connected) to the host memory 120 and the data transfer interface circuit 130. In another embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 are electrically connected to each other using a system bus. In the present embodiment, the processor 110, the host memory 120, and the data transfer interface circuit 130 may be disposed on a motherboard of the host system 10.

[0060] The storage device 20 includes a storage controller 210, a rewritable non-volatile memory module 220, and a connection interface circuit 230. The storage controller 210 includes a processor 211 (also called a first processor), a data management circuit 212, and a memory interface control circuit 213.

[0061] In this embodiment, the host system 10 is electrically connected to the storage device 20 through the data transmission interface circuit 130 and the connection interface circuit 230 of the storage device 20 to perform data access operations. For example, the host system 10 can store data to the storage device 20 or read data from the storage device 20 via the data transmission interface circuit 130.

[0062] In this embodiment, the number of the data transmission interface circuit 130 can be one or more. Through the data transmission interface circuit 130, the motherboard can be electrically connected to the storage device 20 via a wired or wireless manner. The storage device 20 can be, for example, a USB flash drive, a memory card, a solid state drive (SSD) or a wireless memory storage device. The wireless memory storage device can be, for example, a near field communication (NFC) memory storage device, a wireless fax (WiFi) memory storage device, a Bluetooth memory storage device or a low power consumption Bluetooth memory storage device (e.g., iBeacon) and other memory storage devices based on various wireless communication technologies. In addition, the motherboard can also be electrically connected to various I / O devices such as a global positioning system (GPS) module, a network interface card, a wireless transmission device, a keyboard, a screen, a speaker, etc. through a system bus.

[0063] In this embodiment, the data transmission interface circuit 130 and the connection interface circuit 230 are interface circuits compatible with the high-speed peripheral component interconnect interface (Peripheral Component Interconnect Express, PCI Express) standard. In addition, the data transmission interface circuit 130 and the connection interface circuit 230 use the fast non-volatile memory interface standard (Non-Volatile Memory express, NVMe) communication protocol to transmit data.

[0064] Furthermore, in another embodiment, the connection interface circuit 230 and the memory controller 210 may be packaged in one chip, or the connection interface circuit 230 may be disposed outside a chip including the memory controller 210 .

[0065] In the present embodiment, the host memory 120 is used to temporarily store instructions or data executed by the processor 110. For example, in the present embodiment, the host memory 120 may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. However, it should be understood that the present invention is not limited thereto, and the host memory 120 may also be other suitable memories.

[0066] The memory controller 210 is used to execute a plurality of logic gates or control instructions implemented in hardware or firmware and to perform operations such as writing, reading and erasing data in the rewritable non-volatile memory module 220 according to instructions of the host system 10 .

[0067] In more detail, the processor 211 in the memory controller 210 is hardware with computing capabilities, which is used to control the overall operation of the memory controller 210. Specifically, the processor 211 is programmed by a plurality of control instructions / program codes, and when the storage device 20 operates, these control instructions / program codes are executed to perform operations such as writing, reading and erasing data. In addition, in this embodiment, the control instructions / program codes can be further executed to implement the memory management method provided by the present invention. The control instructions / program codes corresponding to the memory management method can be further implemented as a circuit unit in the form of hardware to implement the memory management method provided by the present invention.

[0068] It is worth mentioning that in the present embodiment, the processor 110 and the processor 211 are, for example, a central processing unit (CPU), a microprocessor, or other programmable processing units (Microprocessor), a digital signal processor (DSP), a programmable controller, an application specific integrated circuit (ASIC), a programmable logic device (PLD) or other similar circuit components, but the present invention is not limited thereto.

[0069] In this embodiment, as described above, the memory controller 210 further includes a data management circuit 212 and a memory interface control circuit 213. It should be noted that the operations performed by the various components of the memory controller 210 can also be regarded as the operations performed by the memory controller 210.

[0070] The data management circuit 212 is electrically connected to the processor 211, the memory interface control circuit 213 and the connection interface circuit 230. The data management circuit 212 is used to receive instructions from the processor 211 to transmit data. For example, data is read from the host system 10 (e.g., the host memory 120) via the connection interface circuit 230, and the read data is written to the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (e.g., the write operation is performed according to the write instruction from the host system 10). For another example, data is read from one or more physical units of the rewritable non-volatile memory module 220 via the memory interface control circuit 213 (the data can be read from one or more storage units in the one or more physical units), and the read data is written to the host system 10 (e.g., the host memory 120) via the connection interface circuit 230 (e.g., the read operation is performed according to the read instruction from the host system 10). In another embodiment, the data management circuit 212 can also be integrated into the processor 211.

[0071] The memory interface control circuit 213 is used to receive instructions from the processor 211 and cooperate with the data management circuit 212 to perform a write (also called programming) operation, a read operation or an erase operation on the rewritable non-volatile memory module 220 .

[0072] In addition, the data to be written to the rewritable non-volatile memory module 220 will be converted into a format acceptable to the rewritable non-volatile memory module 220 via the memory interface control circuit 213. Specifically, if the processor 211 wants to access the rewritable non-volatile memory module 220, the processor 211 will transmit a corresponding instruction sequence to the memory interface control circuit 213 to instruct the memory interface control circuit 213 to perform a corresponding operation. For example, these instruction sequences may include a write instruction sequence indicating writing data, a read instruction sequence indicating reading data, an erase instruction sequence indicating erasing data, and corresponding instruction sequences for indicating various memory operations. These instruction sequences may include one or more signals, or data on the bus. These signals or data may include instruction codes or program codes. For example, in a read instruction sequence, information such as a read identification code, a memory address, and a physical address may be included.

[0073] In addition, the memory controller 210 establishes a logical to physical address mapping table and a physical to logical address mapping table to record the mapping relationship between the logical address of the logical unit (e.g., logical block, logical page or logical column) configured for the rewritable non-volatile memory module 220 and the physical address (physical address) of the physical unit (e.g., physical erase unit / physical block, physical page, physical column). In other words, the memory controller 210 can search for the physical unit mapped by a logical unit (e.g., search for the physical page mapped by a logical page; search for the physical address mapped by a logical address) through the logical to physical address mapping table (also called the logical to physical mapping table), and the memory controller 210 can search for the logical unit mapped by a physical unit (e.g., search for the logical page mapped by a physical page; search for the logical address mapped by a physical address) through the physical to logical address mapping table (also called the physical to logical mapping table).

[0074] In one embodiment, the memory controller 210 further includes a buffer memory 214. The buffer memory is electrically connected to the processor 211 and is used to temporarily store data and instructions from the host system 10, data from the rewritable non-volatile memory module 220, or other system data for managing the storage device 20 (e.g., various mapping tables, index tables, address lists, storage group mapping tables, various read times, and other information associated with the present method), so that the processor 211 can quickly access the data, instructions, or system data from the buffer memory 214.

[0075] The rewritable non-volatile memory module 220 is electrically connected to the memory controller 210 (memory interface control circuit 213 ) and is used to store data written by the host system 10 .

[0076] In the present embodiment, the rewritable non-volatile memory module 220 has a plurality of word lines, wherein each of the plurality of word lines is electrically connected to a plurality of storage cells, also known as columns (also known as physical columns). A plurality of columns on the same word line constitute a physical programming unit (also known as a physical page). Each physical page corresponds to a physical address for recording the location of the data stored in the physical page. In addition, a plurality of physical pages may constitute a physical block (also known as a physical erase unit). Each memory grain (chip) of the plurality of memory grains of the rewritable non-volatile memory module has a plurality of planes, and each plane has a plurality of physical blocks. It should be noted that the present invention is not limited to the size of each physical page and logical page.

[0077] Channel (CH) pins (also called physical channels) are a group of physical pins in the rewritable non-volatile memory module 220, which are responsible for receiving and transmitting data and commands.

[0078] The chip enable (CE) pin is used to select or deselect the memory chip. Each CE pin corresponds to a physical chip (memory chip). If a chip enable pin is in a valid state, the corresponding physical chip is selected.

[0079] In one embodiment, for the rewritable non-volatile memory module 220, the read verification operation is an important step to ensure data integrity. Generally speaking, the process of the read verification operation is as follows: First, the memory controller 210 sends a read verification command to the target memory chip through the channel (Channel), and selects the corresponding physical chip through the chip enable (CE) pin. Then, the controller specifies the physical block and physical page to be verified. The memory reads the data on each word line in the specified physical page in turn and compares it with the original data. If an error is found during the read verification process, the controller will try to correct it using an error correction code (ECC). If the error cannot be corrected by ECC, it is determined that the page has not passed the read verification operation. At this time, the controller will start a data recovery program, which usually includes the following steps: first, try to reread the data of the error page; if it still fails, mark the data of the page as unreliable, and if possible, restore the data from other backup sources (such as redundant data or checksum); finally, rewrite the recovered data into a new physical page or physical block, and update the corresponding mapping table. If the data cannot be recovered, the controller will mark the area as a bad block to prevent it from being used in future programs. These measures ensure the reliability and data integrity of the storage system.

[0080] Figure 2 The figure is a flowchart of a memory management method according to an embodiment of the present invention.

[0081] like Figure 2 As shown, the memory management method of the present invention comprises the following steps:

[0082] Step S210: Identify multiple first storage groups of the rewritable non-volatile memory module 220. Each of the first storage groups includes multiple first physical units (e.g., physical blocks), and the multiple first storage groups belong to the second storage group. This step lays the foundation for the subsequent reading count and management. For the convenience of explanation, the following embodiments will be described using physical blocks as physical units. However, the present invention is not limited to this. For example, the physical unit of the memory management method applied in the present invention may also be a physical page.

[0083] Figure 3 FIG. 1 is a schematic diagram of the architecture of a rewritable non-volatile memory module according to an embodiment of the present invention. Figure 3 A schematic diagram of the architecture of the rewritable non-volatile memory module 220 is shown to illustrate the architecture details of the first storage group and the second storage group defined in step S210 .

[0084] like Figure 3 As shown, the rewritable non-volatile memory module 220 includes a plurality of second storage groups, which are represented by 222(1) to 222(M). Each second storage group further includes a plurality of first storage groups, which are illustrated by 221(1), 221(2), 221(3) and 221(4) as examples. Each first storage group further includes a plurality of physical blocks, which are represented by BK1, BK2 to BKN.

[0085] In this embodiment, 220(1) to 220(4) belong to the same physical architecture, which can be any one of a channel, a CE (Chip Enable), a chip, or a plane. For example, if 220(1) to 220(4) represent different CEs, then several physical blocks in each CE can constitute a first storage group (e.g., two physical blocks BK1 and BK2 of CE 220(1) belong to a first storage group). In this case, the first storage groups 221(1), 221(2), 221(3), and 221(4) correspond to different CEs, respectively, and the number of physical blocks in each first storage group 221 is the same.

[0086] The second storage groups 222(1) to 222(M) may be higher-level physical or logical organizational units. For example, if 220(1) to 220(4) represent CEs, a second storage group may include a portion of each of the plurality of CEs (i.e., the first storage group of each of the plurality of CEs corresponding to the second storage group). For example, the second storage group 222(1) includes first storage groups 221(1) to 221(4) corresponding to the plurality of CEs 220(1) to 220(4), respectively.

[0087] Each physical block (such as BK1, BK2, BKN) is the smallest unit that can be erased independently. In the memory management method of the present invention, we implement an efficient read verification operation trigger mechanism by tracking and counting the read times of the first storage group and the second storage group at the upper level, thereby avoiding the resource consumption caused by the read times counting operation at the physical block level.

[0088] Through this multi-level storage organization structure, the present invention can manage and monitor read operations at different granularity levels. This flexible architecture allows the memory management method of the present invention to adapt to storage devices of various sizes and types, thereby maximizing the performance and life of the storage system while ensuring data integrity.

[0089] Please go back Figure 2 Step S220: Count the first read times of each first storage group. The first read times reflect the total number of times each first physical block belonging to the corresponding first storage group is read. This step can effectively track the usage of each first storage group.

[0090] Step S230: According to the first read times of the first storage groups, a target first storage group in the first storage groups is obtained. This step can identify the most frequently read target first storage group, which may also include physical blocks that have been disturbed by read.

[0091] Figure 4 FIG. 1 is a schematic diagram showing a plurality of first counting spaces divided according to an embodiment of the present invention. Figure 4 , continued Figure 3 For example, according to the number of first storage groups in each second storage group, the predetermined storage space BM is set to a predetermined storage space BM1 (as shown by arrow A41), wherein the predetermined storage space BM1 is divided into a plurality of first counting spaces CS1(1) to CS1(4). The predetermined storage spaces BM and BM1 can be configured via the buffer memory 214 and / or the rewritable non-volatile memory module 220, and their sizes are limited to preset fixed values.

[0092] The first counting space BM1 is further divided into a plurality of first counting spaces CS1(1), CS1(2), CS1(3) and CS1(4), each of which corresponds to a first storage group 221(1), 221(2), 221(3) and 221(4) and is used to record the first reading times of the corresponding first storage group (as indicated by arrow A42).

[0093] Specifically, the plurality of storage bits in the first counting spaces CS1(1), CS1(2), CS1(3), and CS1(4) are used to record the first read counts of the corresponding first storage groups 221(1), 221(2), 221(3), and 221(4), respectively. The number of the plurality of storage bits in each first counting space (also referred to as the first number) determines the maximum number of read counts that can be recorded. For example, if each first counting space uses 12 bits, the maximum number of read counts that can be recorded is 4095 (i.e., 2 12 -1) times.

[0094] In one embodiment, for example, when any physical block (such as BK1 or BK2) in the first storage group 221 (1) is read, the processor 211 increases the first reading count recorded in the corresponding first counting space (such as CS1 (1)). This method allows the system to track the reading status of each first storage group in real time.

[0095] Next, when the target first reading number recorded in a target first counting space among the plurality of first counting spaces (CS1(1) to CS1(4)) reaches the maximum reading number, the processor 211 determines that the corresponding first storage group is the target first storage group.

[0096] For example, assuming that the first reading count recorded in the first counting space CS1(4) reaches the maximum reading count 4095 first, the processor 211 will determine the corresponding first storage group 221(4) as the target first storage group. In addition, the processor 211 will also accumulate the four first reading counts recorded in the first counting spaces CS1(1) to CS1(4) as the second reading count of the corresponding second storage group. When the predetermined storage space is re-divided into the second counting space and the third counting space, this second reading count can be used to set the second counting space as the initial value of the second reading count recorded in the second counting space. On the other hand, the first reading count (target first reading count) recorded in the first counting space CS1(4) can be used to set the third counting space as the initial value of the target first reading count recorded in the third counting space.

[0097] This mechanism allows the system to quickly identify the most frequently used storage area, providing an accurate target for subsequent read verification operations. In other words, since the maximum number of reads is reached first, the target first storage group will be determined by the system as the first storage group that may have read interference, and in subsequent management operations, the statistics of the number of reads of the target first storage group will be the main focus.

[0098] Through the division and management method of the predetermined storage space, the present invention can efficiently track the reading conditions of a large number of storage units within limited storage resources, and efficiently determine the first storage group to which the physical block that may cause read interference belongs.

[0099] Please go back Figure 2In step S240, after acquiring the target first storage group, the target first read count of the target first storage group and the second read count of the second storage group are counted. The second read count reflects the sum of the read counts of all first entity blocks belonging to the second storage group. This step emphasizes that the statistics of the read counts are performed for the target first storage group and the entire second storage group, further narrowing the statistical scope of the read counts and omitting the statistical operation of the first read counts of other first storage groups other than the target first storage group. Since only the statistics of the read counts of the target first storage group and the entire second storage group are focused on, the limited scheduled storage space can also be replanned.

[0100] Figure 5 It is a schematic diagram showing re-dividing a predetermined storage space into a second counting space and a third counting space according to an embodiment of the present invention.

[0101] like Figure 5 As shown, after acquiring the target first storage group, as shown by arrow A51, the processor 211 re-divides the predetermined storage space BM into a predetermined storage space BM2, which includes a second counting space CS2 and a third counting space CS3.

[0102] Continue Figure 3 For example, as shown by arrow A52, the second counting space CS2 is used to record the second reading number of the second storage group 222 (1). The third counting space CS3 is specifically used to record the target first reading number of the target first storage group (for example, the first storage group 221 (4) in the second storage group 222 (1)).

[0103] It is worth noting that the second number of the plurality of storage bits of the second counting space CS2 and the third number of the plurality of storage bits of the third counting space CS3 are both greater than the first number of the first counting space. The purpose of this design is to be able to record a wider range of read times. In addition, the number of bits of the second counting space CS2 is greater than the number of bits of the third counting space CS3 because the second storage group usually contains more physical blocks and requires a larger counting range.

[0104] It should be noted that, in one embodiment, the difference between the number of bits of the second counting space CS2 and the number of bits of the third counting space CS3 can be set according to the total number of the first storage groups of each second storage group. For example, if the total number of the first storage groups of the second storage group is 4, the difference can be set to 2, so that the difference between the second reading number and the target first reading number can be at least 4 (2 2 =4) times.

[0105] In the process of counting the target first read count of the target first storage group and the second read count of the second storage group, the present invention adopts the following strategy:

[0106] Whenever a read operation is performed on any first physical block (such as BK1 or BK2) belonging to the target first storage group 221 (4), as indicated by arrow A53, the processor 211 increases the target first read count recorded in the third counting space CS3.

[0107] At the same time, as indicated by arrow A52, whenever a read operation is performed on any first physical block belonging to the second storage group 222(1), the processor 211 increases the second read count recorded in the second counting space CS2.

[0108] This method allows the system to track the read status of the target first storage group and the entire second storage group at the same time, providing a more accurate trigger basis for subsequent read verification operations. By recording the read times of these two levels separately, the present invention can more comprehensively evaluate the usage mode of the storage device.

[0109] For example, in one embodiment, the processor 211 divides the 48-bit predetermined storage space BM into four equal first counting spaces (eg Figure 4 Each first counting space contains 12 bits, which correspond to the reading times of the four CEs (first storage groups). This initial state can be understood as Figure 4 It is worth mentioning that the counting space of this method can also be implemented as a counter.

[0110] As the storage device 20 is used, the system continuously records the number of reads of each CE. When the number of reads of a CE reaches the maximum value of 4095 that can be recorded by 12 bits, the system predicts that CE will be the target CE with the most reads in the future. After identifying the target CE, the system will re-divide the 48-bit space. Specifically:

[0111] The processor 211 first adds the original four 12-bit values ​​(which may be called CE_count1, CE_count2, CE_count3 and CE_count4) to obtain the total number of reads (Unit_cnt) of the entire second storage group.

[0112] Next, the processor 211 divides 26 bits (corresponding to Figure 5 CS2 in Figure 5 A second counting space CS2 in the storage unit is used to record the second reading number (Unit_cnt) of the second storage group.

[0113] The remaining 22 bits (corresponding to Figure 5CS3 in ), which is used to record the read count (target first read count) (CE_Cnt) of the target CE (target first storage group) predicted to have the largest number of reads in the future.

[0114] For example, assuming that re-division is triggered when CE_count4 corresponding to CE4 reaches 4095, the processor 211 will add the values ​​of CE_count1, CE_count2, CE_count3 and CE_count4 to obtain Unit_count (stored in the second counting space CS2), and determine CE4 as the target CE, and its subsequent reading times will be recorded in the third counting space CS3.

[0115] This rezoning approach brings several significant advantages:

[0116] Precise Tracking: With CS3 (22 bits), the system can continue to accurately track the number of times the target CE is read without losing information due to bit overflow in the counting space.

[0117] Overall monitoring: Through CS2 (26 bits), the system can monitor the overall read status of the entire second storage group (Unit), providing a basis for global read verification decisions.

[0118] Space efficiency: The 26-bit and 22-bit designs cleverly balance the counting requirements of the Unit level and the CE level. The difference between the two is 4 bits, and the actual maximum value that can be recorded differs by 16 (2 4 =16) times, which is sufficient to cope with the situation of up to 16 CEs, while avoiding premature overflow of the second counting space corresponding to the second storage group.

[0119] Strong adaptability: This dynamic partitioning method can adaptively identify and track high-frequency storage areas, allowing system resources to be more focused on potential problem areas.

[0120] Please go back Figure 2 In step S250, based on at least one of the target first read count and the second read count, an expected block read count is obtained. This step predicts possible block read counts by comprehensively considering read statistics at different levels.

[0121] Step S260: If the expected block read count exceeds a preset read count threshold (also called a read disturbance threshold), a read verification operation is performed on the second storage group. This step determines whether a read verification operation needs to be performed by comparing the expected block read count with the preset threshold, thereby ensuring data integrity and reliability.

[0122] In one embodiment, the present invention provides a flexible and comprehensive method to obtain the expected block read count, which is a further refinement of step S250. This method takes into account storage organization structures at different levels to achieve a more accurate read verification trigger mechanism.

[0123] The present invention provides three methods for obtaining the expected block read times (eg, method 1 to method 3), which are respectively based on different statistical data.

[0124] [Method 1] Get the first expected block read count based on the target first read count:

[0125] In this way, the system uses Figure 5 The first expected block read count is calculated based on the read count of the target first storage group 221 (4) recorded in the third counting space CS3. This method pays special attention to the storage area identified as being used frequently, and can respond to local read pressure more quickly.

[0126] In more detail, method 1 includes the following steps:

[0127] (1) Obtaining the target first reading number: The processor 211 reads the accumulated target first reading number of the target first storage group 221 (4) from the third counting space CS3. This value reflects the overall reading situation of the area predicted to be used frequently.

[0128] (2) Determine the number of first physical blocks of the target first storage group: The processor 211 calculates the total number of all first physical blocks (such as BK1, BK2, etc.) belonging to the target first storage group 221 (4). This number may be determined when the system is initialized or obtained through dynamic scanning.

[0129] (3) Calculating the first average block read count: The processor 211 divides the target first read count by the number of first physical blocks to obtain the first average block read count, which reflects the average read frequency of each physical block in the target first storage group.

[0130] (4) Setting the first expected block read count: The processor 211 directly uses the calculated first average block read count as the first expected block read count.

[0131] The advantage of this approach is that it considers the overall read pressure distribution of the target first storage group, providing a more balanced and representative expected read count.

[0132] The following is a specific numerical example to illustrate this calculation process:

[0133] Assume the following situation: the target first storage group 221 (4) includes 1000 first physical blocks; the target first read count recorded in the third counting space CS3 is 5,000,000 times.

[0134] The calculation process is as follows:

[0135] Target first read count = 5,000,000

[0136] First physical block quantity = 1,000

[0137] First average block read count = target first read count / first physical block number

[0138] =5,000,000 / 1,000

[0139] =5,000

[0140] Therefore, the first expected number of block reads is set to 5,000.

[0141] This result means that, in the target first storage group, each physical block was read 5,000 times on average. The system can use this value to determine whether to trigger a read verification operation. For example, if the preset read count threshold is 10,000 times, then in this case, the system will not trigger a read verification operation, but will continue to closely monitor the read activity of this area.

[0142] Through this method, the present invention can accurately reflect the reading pressure of high-frequency use areas and provide a reliable basis for read verification triggering decisions, thereby achieving a balance between protecting data integrity and maintaining system performance.

[0143] [Method 2] Obtain the second expected block read count based on the second read count:

[0144] This method uses Figure 5 The second expected block read count is calculated based on the read count of the second storage group 222(1) recorded in the second counting space CS2. This method provides a more global perspective, taking into account the usage of the entire second storage group, and helps to balance the overall read load.

[0145] In more detail, method 2 includes the following steps:

[0146] (1) Obtaining the second reading number: The processor 211 obtains Figure 5 The second counting space CS2 in the second memory group 222 (1) reads the accumulated reading times of the second memory group 222 (1). This value reflects the overall reading situation of the entire second memory group 222 (1).

[0147] (2) Determine the number of second physical blocks in the second storage group: The processor 211 calculates the total number of all first physical blocks belonging to the second storage group 222(1). This number includes all physical blocks in all first storage groups (such as 221(1), 221(2), 221(3), 221(4), etc.) in the second storage group (e.g., each first storage group has 2 physical blocks, for a total of 8 physical blocks).

[0148] (3) Calculating the second average block read times: The processor 211 divides the second read times by the number of second physical blocks to obtain the second average block read times, which reflects the average read frequency of each physical block in the second storage group.

[0149] (4) Setting the second expected block read number: the processor 211 directly uses the calculated second average block read number as the second expected block read number.

[0150] The advantage of this method is that it provides a more macroscopic perspective, taking into account the read pressure distribution of the entire second storage group, and is suitable for evaluating the status of the overall storage system.

[0151] The following is a specific numerical example to illustrate this calculation process:

[0152] Assume the following situation: the second storage group 222 (1) includes 4 first storage groups, each of which has 500 physical blocks; the second reading number recorded in the second counting space CS2 is 20,000,000 times.

[0153] The calculation process is as follows:

[0154] Second read count = 20,000,000

[0155] Number of second physical blocks = 4*500 = 2,000

[0156] Second average block read count = second read count / second physical block number

[0157] =20,000,000 / 2,000

[0158] =10,000

[0159] Therefore, the second expected block read count is set to 10,000.

[0160] This result shows that in the entire second storage group, each physical block is read 10,000 times on average. The system can use this value to evaluate the read pressure of the overall storage system and decide whether to trigger a read verification operation.

[0161] For example, if the preset read count threshold is 7,000 times, then in this case, the system triggers a read verification operation.

[0162] Through this method, the present invention can comprehensively evaluate the read pressure of the storage system and provide a macro reference basis for the read verification trigger decision to avoid the predicted target first storage group not being the storage group where read interference occurs. This method is particularly suitable for scenarios where the overall storage system status needs to be considered, and helps to optimize the read verification strategy at the system level and balance data protection and system performance.

[0163] [Method 1 + Method 2] Consider the read status of the first and second target storage groups at the same time

[0164] In one embodiment, the present invention provides a comprehensive method for obtaining the expected block read count, by simultaneously considering the read conditions of the target first storage group and the second storage group, selecting the most conservative expected block read count (the expected block read count is the largest one between the first expected block read count and the second expected block read count) to ensure data reliability.

[0165] The following is a specific numerical example to illustrate the calculation process of this comprehensive method:

[0166] Assume that the current state of the system is as follows: the target first storage group 221 (4) includes 1000 first physical blocks, and the target first read count recorded in the third counting space CS3 is 5,000,000 times. The second storage group 222 (1) includes 4 first storage groups, each of which has 1000 physical blocks, and the second read count recorded in the second counting space CS2 is 32,000,000 times.

[0167] First, the processor 211 calculates the first expected block read count using method 1:

[0168] Target first read count = 5,000,000

[0169] Number of first physical blocks = 1,000

[0170] First expected block read count = 5,000,000 / 1,000 = 5,000

[0171] Then, the processor 211 calculates the second expected block read number using method 2:

[0172] Second read count = 32,000,000

[0173] Second physical block quantity = 4*1,000 = 4,000

[0174] Second expected block read count = 32,000,000 / 4,000 = 8,000

[0175] Finally, processor 211 compares the two expected block read times:

[0176] First expected block read count: 5,000

[0177] Second expected block read count: 8,000

[0178] According to the comparison result, processor 211 selects the larger value of 8,000 as the final expected block read count. This selection method reflects the system's conservative strategy for data security, because a larger expected block read count means that the system may trigger a read verification operation earlier, thereby better protecting data integrity.

[0179] For example, if the preset read count threshold is 7,000 times, in this case, since the expected block read count (8,000) finally selected exceeds the threshold, the system will trigger a read verification operation on the second storage group even if the read pressure of the target first storage group has not yet reached the trigger condition.

[0180] The advantage of this comprehensive method is that it considers both local (target first storage group) and global (second storage group) read pressures. By selecting a larger value as the final result, it reflects the system's conservative attitude towards data security, can detect potential read interference problems earlier, improve the reliability of data protection, and avoid the judgment bias that may be caused by a single evaluation method.

[0181] [Method 3] Get the expected block read count based on the target first read count and second read count:

[0182] This is a comprehensive approach that takes into account both the CS3 and CS2 recorded read counts. By combining local (target first storage group) and global (second storage group) read statistics, this approach provides the most comprehensive estimate of expected block read counts.

[0183] Specifically, method 3 includes the following steps:

[0184] (1) Calculate the first average block read count: Figure 5 The third counting space CS3 in the target first reading number is obtained; the first physical block number of the target first storage group 221 (4) is determined; and the first average block reading number is calculated = the target first reading number / the first physical block number.

[0185] (2) Calculate the second average block read times: Figure 5The second counting space CS2 in the memory obtains the second read count; determines the second physical block quantity (the total number of all first physical blocks) of the second storage group 222 (1); and calculates the second average block read count = the second read count / the second physical block quantity.

[0186] (3) Obtaining the expected number of block reads: Find the larger value between the first average number of block reads and the second average number of block reads; Calculate the absolute difference between the first average number of block reads and the second average number of block reads; Add the larger value and the absolute difference to obtain the expected number of block reads.

[0187] The advantage of this method is that it not only considers the read pressure of the high-frequency usage area (the target first storage group), but also considers the state of the overall storage system (the second storage group), and reflects the imbalance of the read pressure by calculating the difference.

[0188] The following is a specific numerical example to illustrate this calculation process:

[0189] Assume the following situation:

[0190] The target first storage group 221 (4) includes 1000 first physical blocks, and the cumulative number of reads is 6,000,000 times.

[0191] The second storage group 222 ( 1 ) includes four first storage groups, a total of 4000 physical blocks, and a cumulative read count of 20,000,000 times.

[0192] The calculation process is as follows:

[0193] First average block read count = 6,000,000 / 1,000 = 6,000

[0194] Second average block read count = 20,000,000 / 4,000 = 5,000

[0195] Larger value = max(6,000,5,000) = 6,000

[0196] Absolute difference = |6,000-5,000| = 1,000

[0197] Third expected block read count = larger value + absolute difference = 6,000 + 1,000 = 7,000

[0198] Therefore, the third expected number of block reads is set to 7,000.

[0199] This result reflects the following:

[0200] The average read pressure of the target first storage group (6,000) is higher than the overall average (5,000).

[0201] There is a 1,000-times difference in read pressure, indicating that the read load is somewhat unbalanced.

[0202] The final expected block read count (7,000) takes into account the high-stress area and the overall imbalance. The system can use this value to determine whether a read verification operation needs to be triggered. For example, if the preset read count threshold is 6,500, then in this case, the third expected block read count (7000) obtained using method 3 will trigger a read verification operation. On the other hand, the first expected block read count (6000) and the second expected block read count (5000) obtained using methods 1 and 2 respectively will not trigger a read verification operation.

[0203] Through this method, the present invention can more comprehensively evaluate the read pressure status of the storage system and provide a more accurate basis for read verification triggering decisions. This method is particularly suitable for scenarios where both local high pressure areas and overall system status need to be considered at the same time, helping to achieve a better balance between protecting data integrity and optimizing system performance.

[0204] [Method 4] Calculation method of expected block read times based on imbalance coefficient

[0205] In one embodiment, by introducing a dynamically adjusted imbalance coefficient, the imbalance condition of the read load can be captured more sensitively, thereby providing a more accurate read verification trigger mechanism.

[0206] Specifically, method 4 includes the following steps:

[0207] (1) Calculate the first average block read count:

[0208] from Figure 5 The third counting space CS3 in obtains the target first reading number;

[0209] Determine the number of first physical blocks of the target first storage group 221(4);

[0210] Calculate the first average block read count=target first read count / first physical block quantity.

[0211] (2) Calculate the second average block read times:

[0212] from Figure 5 The second counting space CS2 in obtains the second reading number;

[0213] Determining the number of second physical blocks of the second storage group 222(1);

[0214] The second average block read count=the second read count / the second physical block quantity is calculated.

[0215] (3) Calculate the maximum expected number of reads (PB_max):

[0216] Find the larger value of the first average block read count and the second average block read count;

[0217] Calculate the absolute difference between the two;

[0218] Add the larger value to the absolute difference to get the maximum expected number of reads.

[0219] (4) Calculate the current imbalance coefficient (Current_Ec):

[0220] Current_Ec = maximum expected number of reads / second average number of block reads;

[0221] (5) Update the maximum imbalance coefficient (max_Ec):

[0222] Compare the current imbalance coefficient with the historical maximum imbalance coefficient;

[0223] The larger value of the two is taken as the new maximum imbalance coefficient.

[0224] (6) Calculate the expected number of block reads:

[0225] Expected block read count=second average block read count×maximum imbalance coefficient.

[0226] The following is a specific numerical example to illustrate this calculation process, assuming the following situation: the target first storage group 221 (4) contains 1000 first physical blocks, and the cumulative number of reads is 6,000,000 times; the second storage group 222 (1) contains 4 first storage groups, a total of 4000 physical blocks, and the cumulative number of reads is 20,000,000 times; the historical maximum imbalance coefficient is 1.6.

[0227] The calculation process is as follows:

[0228] First average block read count = 6,000,000 / 1,000 = 6,000

[0229] Second average block read count = 20,000,000 / 4,000 = 5,000

[0230] PB_max=max(6,000,5,000)+|6,000-5,000|=6,000+1,000=7,000

[0231] Current_Ec=7,000 / 5,000=1.4

[0232] max_Ec=max(1.4,1.6)=1.6

[0233] Expected number of block reads = 5,000 x 1.6 = 8,000

[0234] Therefore, the final expected number of block reads is set to 8,000.

[0235] This result reflects the following:

[0236] The current imbalance coefficient (1.4) is lower than the historical maximum (1.6), so the system retains the historical maximum imbalance coefficient. By multiplying the second average block read count (5,000) by the historical maximum imbalance coefficient (1.6), the system obtains a more conservative expected block read count (8,000). Even though the current read pattern shows a lower imbalance, the system still adopts a more conservative strategy based on historical experience, allowing the system to trigger the read verification operation earlier.

[0237] For example, if the preset read count threshold is 7,500, then in this case, the system will trigger a read verification operation because the expected block read count (8,000) calculated using the historical maximum imbalance coefficient exceeds the threshold (the expected block read count (7,000) calculated using the current maximum imbalance coefficient does not exceed the threshold). This shows that the system will refer to historical experience to protect data security, even if the current read pattern seems relatively balanced.

[0238] It is worth mentioning that the processor 211 can choose to use one or more of the above five methods according to actual needs. For example, in some cases, the system may calculate all expected block read times and then select the maximum value as the final expected block read time to ensure that the most conservative data protection strategy is adopted. Alternatively, as long as any expected block read time exceeds the preset read time threshold, the processor 211 will perform a read verification operation on the second storage group.

[0239] like Figure 5 The system can update the second read count and the target first read count in real time, thereby dynamically updating the expected block read count. This dynamic update mechanism enables the present invention to adapt to the usage mode changes of the storage device at different times and provide a more accurate read verification triggering time.

[0240] This flexible method for obtaining the expected block read count takes into account the special needs of local high-frequency usage areas while not neglecting the status of the overall storage system, thereby achieving a good balance between data protection and system performance.

[0241] In one embodiment, the specific process of the read verification operation on the second storage group is as follows:

[0242] (1) Triggering a read verification operation

[0243] When the expected block read count exceeds the preset read count threshold, the processor 211 triggers a read verification operation on the second storage group 222 (1). This trigger may be based on any one or a combination of the following three methods:

[0244] (1a) First expected block read count (based on target first read count)

[0245] (1b) Second expected block read count (based on second read count)

[0246] (1c) Third expected block read count (based on a comprehensive consideration of the target first read count and the second read count)

[0247] (2) Read data from the target area

[0248] Once the read verification operation is triggered, the processor 211 will instruct the memory interface control circuit 213 to read the data in the second storage group 222 (1). This process involves the following steps:

[0249] (2a) The processor 211 generates a read command sequence.

[0250] (2b) The memory interface control circuit 213 converts the command sequence into a format recognizable by the rewritable non-volatile memory module 220 .

[0251] (2c) The memory interface control circuit 213 sends a read command to the target memory chip through the corresponding channel.

[0252] (2d) The corresponding physical chip is selected through the chip enable (CE) pin.

[0253] (2e) Read the data on each word line in the specified physical page in sequence.

[0254] (3) Perform ECC check

[0255] The data management circuit 212 performs an error correction code (ECC) check on the read data. This process includes:

[0256] (3a) Calculate the ECC value of the read data.

[0257] (3b) Compare the calculated ECC value with the stored ECC value.

[0258] (3c) If the two are consistent, the data is considered correct.

[0259] (3d) If there is a difference, error correction is attempted using ECC.

[0260] (4) If the ECC check passes, continue monitoring. If the ECC check passes, it means that the current data is not affected by read interference. In this case:

[0261] (4a) The processor 211 updates relevant reading statistics, such as the target first reading number and the target second reading number.

[0262] (4b) Continue to monitor the read activity of the area (second storage group) using the method of the present invention.

[0263] (4c) The read verification timer of the second storage group or the related counting space may be reset (for example, the predetermined storage space corresponding to the second storage group is reset to the initial stage).

[0264] (5) If the ECC check fails, attempt data recovery. If the ECC check fails and the error cannot be corrected by ECC, the processor 211 will start the data recovery procedure:

[0265] (5a) Try to re-read the data of the failed page, possibly using different read voltage or other read parameters.

[0266] (5b) If the re-read fails, the processor 211 will search for other possible data sources, such as redundant data or checksums.

[0267] (5c) Use this additional information to try to reconstruct the original data.

[0268] (6) Move data to a new storage area when necessary

[0269] If the data recovery is successful or partially successful: (6a) the processor 211 will instruct the data management circuit 212 to write the recovered data to a new, reliable storage location; (6b) this new location may be another physical block within the same second storage group 222 (1), or another second storage group; (6c) during the writing process, the memory interface control circuit 213 will generate new ECC data.

[0270] If the data cannot be recovered: (6a) the processor 211 will mark the corresponding area as a bad block; (6b) the bad block management table will be updated to ensure that the area will not be used in the future.

[0271] (7) Update relevant mapping tables and management information

[0272] After completing the above operations, the processor 211 will update various management information in the system:

[0273] (7a) If the data is moved, update the logical to physical address mapping table and map the relevant logical address to the new physical address.

[0274] (7b) Update the physical to logical address mapping table to reflect the new correspondence between the physical address and the logical address.

[0275] (7c) If a bad block is generated, update the bad block management table.

[0276] (7d) Reset or update the read count statistics associated with the second storage group.

[0277] (7e) Update the storage group mapping table if the data is moved to a different storage group.

[0278] By executing this detailed read verification operation process, the present invention can effectively identify and handle data errors caused by frequent read operations, thereby improving the reliability and life of the rewritable non-volatile memory module 220. This method can not only detect potential data integrity problems in a timely manner, but also minimize the risk of data loss through intelligent data management strategies, while optimizing the overall performance of the storage system.

[0279] This embodiment also provides a computer program product, including a computer readable code, or a non-volatile computer readable storage medium carrying the computer readable code, when the computer readable code runs in the processor of the host system, the processor executes the steps of the above-mentioned memory simulator and storage device testing method. The computer program product can be implemented in hardware, firmware, software or a combination thereof. In an optional embodiment, the computer program product is specifically embodied as a computer storage medium, and in another optional embodiment, the computer program product is specifically embodied as a software product, such as a software development kit (Software Development Kit, SDK) and the like.

[0280] Based on the above, the memory management method and memory controller provided by the embodiments of the present invention can achieve the following effects:

[0281] Storage space saving: Compared with traditional methods, the present invention only requires a small amount of additional storage space to manage the read statistics of a large number of storage blocks, which significantly reduces storage overhead.

[0282] Improved management efficiency: The concept of multi-level storage groups and dynamic prediction mechanism simplifies the management process and improves system efficiency.

[0283] Accurate read verification triggering: Comprehensively considers the reading modes of storage groups at different levels to improve the accuracy of read verification triggering and reduce unnecessary read verification operations.

[0284] Enhanced adaptability: Storage groups can be flexibly defined according to the actual storage structure, suitable for storage devices of various sizes and types.

[0285] Improved reliability: Through more accurate read verification management, the risk of data errors caused by read interference is effectively reduced, and the overall reliability of the storage system is improved.

[0286] Performance optimization: Reduces unnecessary read verification operations, reduces the impact on normal read and write operations, and helps improve the overall performance of the storage system.

[0287] Extended life: Through more accurate read verification management, unnecessary data migration and erase operations are reduced, helping to extend the life of storage devices.

[0288] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A memory management method for a rewritable non-volatile memory module, wherein the rewritable non-volatile memory module comprises a plurality of physical units, characterized in that: include: Identifying a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; Counting the first reading times of each first storage group, wherein the first reading times reflects the sum of the reading times of each first physical unit belonging to the corresponding first storage group; According to a plurality of first read times of the plurality of first storage groups, acquiring a target first storage group among the plurality of first storage groups; After acquiring the target first storage group, counting a target first read count of the target first storage group and a second read count of the second storage group, wherein the second read count reflects the sum of read counts of all first physical units belonging to the second storage group; Based on at least one of the target first read count and the second read count, obtaining an expected block read count; as well as If the expected block read count exceeds a preset read count threshold, a read verification operation is performed on the second storage group.

2. The memory management method according to claim 1, characterized in that , the method further comprises: During counting the first number of reads of each first storage group, dividing a predetermined storage space into a plurality of first counting spaces, wherein a plurality of storage bits of the plurality of first counting spaces are used to respectively record the first number of reads of each first storage group, wherein a first number of the plurality of storage bits of the plurality of first counting spaces reflects a maximum number of reads that can be recorded; When the target first reading number recorded in a target first counting space among the plurality of first counting spaces reaches the maximum reading number, the target first storage group corresponding to the target first counting space is determined.

3. The memory management method according to claim 2, characterized in that: The step of counting the target first reading number of the target first storage group and the second reading number of the second storage group comprises: After acquiring the target first storage group, re-dividing the predetermined storage space into a second counting space and a third counting space, wherein the second counting space is used to record the second reading number, and the third counting space is used to record the target first reading number, A second number of the plurality of storage bits in the second counting space and a third number of the plurality of storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

4. The memory management method according to claim 3, characterized in that: The method further comprises: During counting of the first reading times of each first storage group, whenever a reading operation is performed on any first physical unit belonging to a first storage group, the first reading times recorded in the corresponding first counting space are increased; During counting of the target first reading number of the target first storage group and the second reading number of the second storage group: Whenever a read operation is performed on any first physical unit belonging to the target first storage group, the target first read count recorded in the third counting space is increased; and Whenever a read operation is performed on any first physical unit belonging to the second storage group, the second read count recorded in the second counting space is increased.

5. The memory management method according to claim 1, characterized in that: Based on at least one of the target first read count and the second read count, the step of obtaining the expected block read count comprises: Based on the target first read count, obtaining a first expected block read count; Based on the second read count, obtaining a second expected block read count; According to the first expected block reading number and the second expected block reading number, the expected block reading number is obtained, wherein the expected block reading number is the largest one of the first expected block reading number and the second expected block reading number; or The expected block read number is obtained based on the target first read number and the second read number.

6. The memory management method according to claim 5, characterized in that: Based on the target first read count, the step of obtaining the first expected block read count includes: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group, wherein the number of first physical units is the total number of the plurality of first physical units belonging to the target first storage group; and The first average block read count is used as the first expected block read count.

7. The memory management method according to claim 5, characterized in that: Based on the second read count, the step of obtaining the second expected block read count comprises: Obtaining a second average block read count according to the second read count and a second physical unit quantity corresponding to the second storage group, wherein the second physical unit quantity is a total quantity of all first physical units belonging to the second storage group; and The second average block read count is used as the second expected block read count.

8. The memory management method according to claim 5, characterized in that: Based on the target first read count and the second read count, the step of obtaining the expected block read count comprises: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group, wherein the number of first physical units is the total number of the plurality of first physical units belonging to the target first storage group; Obtaining a second average block read count according to the second read count and a second physical unit quantity corresponding to the second storage group, wherein the second physical unit quantity is a total quantity of all first physical units belonging to the second storage group; and The expected block read number is obtained according to the first average block read number and the second average block read number.

9. The memory management method according to claim 8, characterized in that: The step of acquiring the expected block read number according to the first average block read number and the second average block read number comprises: Obtaining a larger value of the first average block read count and the second average block read count; obtaining an absolute difference between the first average block read count and the second average block read count; and The sum of the larger value and the absolute difference is taken as the expected block reading number.

10. The memory management method according to claim 5, characterized in that: Based on the target first read count and the second read count, the step of obtaining the expected block read count comprises: Acquire an imbalance coefficient, where the imbalance coefficient reflects the imbalance degree of the number of reads of each first physical unit in the second storage group; The unbalance coefficient is multiplied by an average number of reads of the first physical unit in the second storage group to obtain the expected number of block reads.

11. The memory management method according to claim 10, characterized in that: The step of obtaining the imbalance coefficient comprises: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group; Obtaining a second average block read count according to the second read count and the number of second physical units corresponding to the second storage group; Calculating a maximum expected number of reads, wherein the maximum expected number of reads is the sum of a larger value of the first average block read number and the second average block read number and an absolute value of a difference between the two; Divide the maximum expected number of reads by the second average number of block reads to obtain a current imbalance coefficient; The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

12. A memory controller for controlling a storage device equipped with a rewritable non-volatile memory module, characterized in that: The memory controller comprises: a memory interface control circuit, for electrically connecting to the rewritable non-volatile memory module, wherein the rewritable non-volatile memory module includes a plurality of physical units; and a processor electrically connected to the memory interface control circuit, wherein the processor is configured to: Identifying a plurality of first storage groups of the rewritable non-volatile memory module, wherein each first storage group includes a plurality of first physical units, wherein the plurality of first storage groups belong to a second storage group; Counting the first reading times of each first storage group, wherein the first reading times reflects the sum of the reading times of each first physical unit belonging to the corresponding first storage group; According to a plurality of first read times of the plurality of first storage groups, acquiring a target first storage group among the plurality of first storage groups; After acquiring the target first storage group, counting a target first read count of the target first storage group and a second read count of the second storage group, wherein the second read count reflects the sum of read counts of all first physical units belonging to the second storage group; Based on at least one of the target first read count and the second read count, obtaining an expected block read count; If the expected block read count exceeds a preset read count threshold, a read verification operation is performed on the second storage group.

13. The memory controller according to claim 12, wherein: The processor is also configured to: During counting the first number of reads of each first storage group, dividing a predetermined storage space into a plurality of first counting spaces, wherein a plurality of storage bits of the plurality of first counting spaces are used to respectively record the first number of reads of each first storage group, wherein a first number of the plurality of storage bits of the plurality of first counting spaces reflects a maximum number of reads that can be recorded; When the target first reading number recorded in a target first counting space among the plurality of first counting spaces reaches the maximum reading number, the target first storage group corresponding to the target first counting space is determined.

14. The memory controller according to claim 13, wherein: The step of counting the target first reading number of the target first storage group and the second reading number of the second storage group comprises: After acquiring the target first storage group, re-dividing the predetermined storage space into a second counting space and a third counting space, wherein the second counting space is used to record the second reading number, and the third counting space is used to record the target first reading number, A second number of the plurality of storage bits in the second counting space and a third number of the plurality of storage bits in the third counting space are both greater than the first number, and the second number is greater than the third number.

15. The memory controller according to claim 14, wherein: The processor is also configured to: During counting of the first reading times of each first storage group, whenever a reading operation is performed on any first physical unit belonging to a first storage group, the first reading times recorded in the corresponding first counting space are increased; During counting of the target first reading number of the target first storage group and the second reading number of the second storage group: Whenever a read operation is performed on any first physical unit belonging to the target first storage group, the target first read count recorded in the third counting space is increased; as well as Whenever a read operation is performed on any first physical unit belonging to the second storage group, the second read count recorded in the second counting space is increased.

16. The memory controller according to claim 12, wherein: Based on at least one of the target first read count and the second read count, the step of obtaining the expected block read count comprises: Based on the target first read count, obtaining a first expected block read count; Based on the second read count, obtaining a second expected block read count; According to the first expected block read number and the second expected block read number, the expected block read number is obtained, wherein the expected block read number is the largest one of the first expected block read number and the second expected block read number; or The expected block read number is obtained based on the target first read number and the second read number.

17. The memory controller according to claim 16, wherein: Based on the target first read count, the step of obtaining the first expected block read count includes: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group, wherein the number of first physical units is the total number of the plurality of first physical units belonging to the target first storage group; and The first average block read count is used as the first expected block read count.

18. The memory controller according to claim 16, wherein: Based on the second read count, the step of obtaining the second expected block read count comprises: Obtaining a second average block read count according to the second read count and a second physical unit quantity corresponding to the second storage group, wherein the second physical unit quantity is a total quantity of all first physical units belonging to the second storage group; and The second average block read count is used as the second expected block read count.

19. The memory controller according to claim 16, wherein: Based on the target first read count and the second read count, the step of obtaining the expected block read count comprises: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group, wherein the number of first physical units is the total number of the plurality of first physical units belonging to the target first storage group; Obtaining a second average block read count according to the second read count and a second physical unit quantity corresponding to the second storage group, wherein the second physical unit quantity is a total quantity of all first physical units belonging to the second storage group; and The expected block read number is obtained according to the first average block read number and the second average block read number.

20. The memory controller according to claim 19, wherein: The step of acquiring the expected block read number according to the first average block read number and the second average block read number comprises: Obtaining a larger value of the first average block read count and the second average block read count; obtaining an absolute difference between the first average block read count and the second average block read count; and The sum of the larger value and the absolute difference is taken as the expected block reading number.

21. The memory controller according to claim 16, wherein: Based on the target first read count and the second read count, the step of obtaining the expected block read count comprises: Acquire an imbalance coefficient, where the imbalance coefficient reflects the imbalance degree of the number of reads of each first physical unit in the second storage group; The unbalance coefficient is multiplied by an average number of reads of the first physical unit in the second storage group to obtain the expected number of block reads.

22. The memory controller according to claim 21, wherein: The step of obtaining the imbalance coefficient comprises: Obtaining a first average block read count according to the target first read count and the number of first physical units corresponding to the target first storage group; Obtaining a second average block read count according to the second read count and the number of second physical units corresponding to the second storage group; Calculating a maximum expected number of reads, wherein the maximum expected number of reads is the sum of a larger value of the first average block read number and the second average block read number and an absolute value of a difference between the two; Divide the maximum expected number of reads by the second average number of block reads to obtain a current imbalance coefficient; The current imbalance coefficient is compared with the historical maximum imbalance coefficient, and the larger value is taken as the imbalance coefficient.

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