Direct memory access controller, processing method, computing device and storage medium

Abstract

The embodiment of the invention relates to a direct memory access controller, a direct memory access task processing method, a computing device and a storage medium. The direct memory access controller comprises an execution unit, and the execution unit is configured to read a direct memory access task to be processed from a first storage space, and store the read direct memory access task to be processed in a second storage space as a direct memory access task to be executed, and executing the to-be-executed direct memory access task stored in the second storage space. According to the method, the direct memory access tasks are stored by setting the two-stage storage space, so that the direct memory access controller caches the multiple direct memory access tasks and executes the cached tasks, the direct memory access tasks do not need to be stored in a memory and read-write pointers do not need to be maintained, frequent interaction of the read-write pointers is not needed for starting the tasks, and the task starting efficiency is improved. Task starting is faster, and resource consumption is smaller.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to a direct memory access controller and a method for processing a direct memory access task, a computing device, and a computer-readable storage medium. Background Art

[0002] With the development of computer technology, the performance challenges faced by processors such as central processing units (CPU), graphics processing units (GPU), and artificial intelligence (AI) chips are not mainly in terms of data calculation capabilities, but in terms of data transfer capabilities.

[0003] For example, processes such as AI computing and image processing require the participation of a large amount of data, so the processor needs to interact frequently with the memory (such as double-rate synchronous dynamic random access memory or high-bandwidth memory), resulting in the processor's focus on data movement, which will undoubtedly affect the system's computing or image / video processing efficiency. Summary of the invention

[0004] At least one embodiment of the present disclosure provides a direct memory access controller, including an execution unit, which is configured to: read a pending direct memory access task from a first storage space, store the read pending direct memory access task in a second storage space as a pending direct memory access task, and execute the pending direct memory access task stored in the second storage space.

[0005] At least one embodiment of the present disclosure provides a method for processing a direct memory access task, comprising: reading a pending direct memory access task from a first storage space; receiving and storing the pending direct memory access task in the first storage space; storing the read pending direct memory access task in a second storage space as a pending direct memory access task; and executing the pending direct memory access task stored in the second storage space.

[0006] At least one embodiment of the present disclosure provides a direct memory access controller, including: a processing unit; and a storage medium storing one or more computer program instructions, wherein the one or more computer program instructions, when executed by the processing unit, perform a processing method for a direct memory access task provided by any embodiment of the present disclosure.

[0007] At least one embodiment of the present disclosure provides a computing device, comprising a direct memory access controller provided by any embodiment of the present disclosure; and at least one processor configured to send pending direct memory access tasks and store the pending direct memory access tasks to a first storage space.

[0008] At least one embodiment of the present disclosure provides a computer-readable storage medium that non-temporarily stores computer-readable instructions, wherein when the computer-readable instructions are executed by a processor, the processing method of the direct memory access task provided by any embodiment of the present disclosure is implemented. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings of the embodiments will be briefly introduced below. Obviously, the drawings in the following description only relate to some embodiments of the present disclosure, but are not intended to limit the present disclosure.

[0010] Figure 1 The working principle diagram of the direct memory access controller of the first embodiment of the present disclosure is schematically shown;

[0011] Figure 2 The working principle diagram of the direct memory access controller of the second embodiment of the present disclosure is schematically shown;

[0012] Figure 3 The processing flow chart of the direct memory access task according to the embodiment of the present disclosure is schematically shown;

[0013] Figure 4 The processing flow chart of the direct memory access task according to the embodiment of the present disclosure is schematically shown;

[0014] Figure 5 The working principle diagram of the direct memory access controller of the third embodiment of the present disclosure is schematically shown;

[0015] Figure 6 A schematic diagram of a direct memory access controller according to an embodiment of the present disclosure is shown;

[0016] Figure 7 A schematic diagram of the structure of a computing device according to an embodiment of the present disclosure is shown;

[0017] Figure 8 A schematic diagram schematically shows the structure of a computing device according to another embodiment of the present disclosure; and

[0018] Fig. 9 A schematic diagram schematically illustrates a computer-readable storage medium according to an embodiment of the present disclosure. DETAILED DESCRIPTION

[0019] In order to make the purpose, technical solution and advantages of the embodiments of the present disclosure clearer, the technical solution of the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings of the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, not all of the embodiments. Based on the described embodiments of the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0020] Unless otherwise defined, the technical terms or scientific terms used in the present disclosure should be understood by people with ordinary skills in the field to which the present disclosure belongs. The "first", "second" and similar words used in the present disclosure do not indicate any order, quantity or importance, but are only used to distinguish different components. Similarly, similar words such as "one", "one" or "the" do not indicate quantity restrictions, but indicate that there is at least one. Similar words such as "include" or "comprise" mean that the elements or objects appearing before the word cover the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Similar words such as "connect" or "connected" are not limited to physical or mechanical connections, but can include electrical connections, whether direct or indirect. "Up", "down", "left", "right" and the like are only used to indicate relative positional relationships. When the absolute position of the described object changes, the relative positional relationship may also change accordingly.

[0021] The widespread application of AI computing and image processing has brought revolutionary development to many technologies, but the challenge faced by AI computer systems and image processing units (such as GPUs) in improving performance is not mainly the ability to calculate data, but the ability to move data, which limits the performance of the overall system. In particular, considering that the AI ​​computing and image processing processes require a large amount of data to participate, there is frequent interaction between the AI ​​computing engine and the image processing engine and the memory, the delay of read and write operations is large, and the access rate of a large amount of data is relatively low. If the focus of the processor's work is on data movement, it will affect the efficiency of AI computing and image processing. Therefore, improving the data movement efficiency between the memory units of different processing engines is a problem that needs to be solved.

[0022] In order to allow the processor to focus on other tasks besides data transfer, Direct Memory Access (DMA) technology came into being. The DMA system uses the internal controller to realize data transfer between memory and peripherals. With DMA technology, the data transfer process can be completely completed by the DMA system.

[0023] For example, the DMA system stores the information of DMA tasks by setting up a ring buffer in the memory. The implementation of the ring buffer requires setting up a read pointer and a write pointer. The values ​​of the read pointer and the write pointer are updated interactively, and the execution of the DMA task is started by judging the difference between the read pointer and the write pointer. Specifically, after the DMA task issued by the processor is written to the ring buffer, the value of the write pointer is updated. The DMA system can obtain the value of the write pointer in real time and compare the value of the write pointer with the value of the read pointer. If the two are not equal, it means that a new DMA task has been written, and a new DMA task is read to execute. However, the interaction cycle between the read pointer and the write pointer is relatively long. On the other hand, since the DMA task is stored in the memory, the startup of the DMA task needs to access the memory, and the DMA task resources and computing resources cannot be separated well. The acquisition of DMA task resources and computing resources requires occupying the bus, which will affect the acquisition efficiency of DMA task resources and computing resources to a certain extent.

[0024] At least one embodiment of the present disclosure provides a new DMA controller, so that the execution of DMA tasks can be independent of the ring buffer working mode of the memory, so that the task startup does not need to update and read the values ​​of the read pointer and the write pointer. For example, the startup efficiency of the DMA task and the efficiency of obtaining computing resources can be improved, thereby further improving the work efficiency of the processor.

[0025] In at least one embodiment of the present disclosure, two levels of storage space can be set to store DMA tasks (specifically, DMA tasks issued by the processor are stored in the first level storage space, and DMA tasks to be executed are read from the first level storage space and written into the second level storage space), so that the DMA controller can directly select the DMA tasks in the second level storage space for execution, for example, the startup process of the DMA task does not need to access the memory, and in at least one example, it is also unnecessary to update and read the values ​​of the read pointer and the write pointer. In this way, at least one embodiment of the present disclosure can improve the efficiency of task startup and reduce the impact on computing resources caused by the startup of the DMA task.

[0026] The following will be combined Figure 1 to Figure 5 The new DMA controller provided by the present disclosure and its working principle are described in detail.

[0027] Figure 1 The working principle diagram of the direct memory access controller according to the first embodiment of the present disclosure is schematically shown.

[0028] like Figure 1As shown, in the embodiment 100, the DMA controller 101 may include an execution unit 111. The execution unit 111 may access the first storage space 103 and the second storage space 104. The DMA controller may execute DMA tasks in a computer system including multiple task processing devices (eg, processors). Figure 1 As shown, the computer system includes one or more processors, two processors are taken as an example here, and the embodiments of the present disclosure are not limited to this; the computer system may also include, for example, a memory (not shown), etc. In the computer system, the processor and components such as a DMA controller are communicatively connected through, for example, a bus.

[0029] The first storage space 103 is used to store, for example, a DMA task issued by a processor, so as to treat the DMA task as a pending DMA task. For example, the first storage space can receive and store a DMA task issued by at least one processor. Here, at least one processor includes processor 112 and processor 122 as an example. According to actual needs, at least one processor may also include three or more processors. It is understandable that the processor may be a task processing device with data processing capabilities such as a CPU, GPU or AI chip, and the embodiments of the present disclosure are not limited to this.

[0030] In one embodiment, the first storage space 103 may be independent of the DMA controller, for example, it may be provided by a register, a static random access memory (SRAM), etc. For example, the storage form of the memory providing the first storage space is simpler than the storage form of the memory using a double data rate synchronous dynamic random access memory (DDR) and a high bandwidth memory (HBM). It is understandable that the first storage space is not limited to a static storage space, and the present disclosure does not limit the implementation form of the first storage space, as long as the first storage space can receive and store the task information of the DMA task.

[0031] In one embodiment, the second storage space 104 can be provided by the same memory as the first storage space 103, or can be provided by a different memory. The second storage space 104 can receive DMA tasks from the first storage space and store them as DMA tasks to be executed. Specifically, the execution unit 111 can read the DMA tasks to be processed from the first storage space 103, and store the DMA tasks to be processed in the second storage space 104 as DMA tasks to be executed.

[0032] In one embodiment, the DMA controller may be a hardware device independent of the processor, and the DMA controller includes a storage unit. In this embodiment, the first storage space and the second storage space may be set by multiplexing the storage space of the storage unit included in the DMA controller.

[0033] Figure 2 The working principle diagram of the direct memory access controller according to the second embodiment of the present disclosure is schematically shown.

[0034] like Figure 2 As shown, the DMA controller 201 of the embodiment 200 includes an execution unit 211 and a storage unit 221. The storage unit 221 provides a first storage space 2211 and a second storage space 2221.

[0035] In one embodiment, the first storage space 2211 and the second storage space 2221 may be provided by the same memory. For example, the storage space corresponding to the first address segment in the memory may be used as the first storage space, and the storage space corresponding to the second address segment in the memory may be used as the second storage space. In some scenarios, the second storage space may also be a part of the first storage space.

[0036] In one embodiment, the first storage space 2211 and the second storage space 2221 may be provided by different memories. For example, the storage unit 221 may include a first sub-storage unit and a second sub-storage unit, the first sub-storage unit provides the first storage space 2211, and the second sub-storage unit provides the second storage space 2221.

[0037] In one embodiment, the storage unit 221 included in the DMA controller 201 may include a function register. This embodiment may provide a first storage space by reusing the storage space of the function register used by the DMA controller for other functions. For example, the first sub-storage unit providing the first storage space may include a plurality of function storage spaces, which are configured to be operated through the interface of the DMA controller. In this way, the processor 212 or the processor 222 may write a DMA task into the first storage space through the interface of the DMA controller. In an actual scenario, the function storage space included in the first sub-storage unit may be software configured through the bus, for example, the format of the written DMA task, the information stored in association with the DMA task, etc. may be configured to set the first storage space. In this way, the function of the DMA controller provided in at least one embodiment of the present disclosure may be realized on the basis of minimizing hardware improvements, which is conducive to reducing the cost of the DMA controller.

[0038] In one embodiment, a unique address space may also be allocated to the first sub-storage unit, for example, a memory independent of the second sub-storage unit is provided to provide the first storage space. If the address used by the information sent by the processor (which may be a DMA task) is located in the address space, the sent information is stored in the first storage space provided by the first sub-storage unit.

[0039] In one embodiment, the storage unit 221 may also provide a third storage space for storing configuration information. For example, the configuration information may include strategy information for the execution unit to execute the DMA task to be executed. For example, the third storage space may be accessible to the execution unit 211, and the configuration information stored therein may be read by the execution unit 211. Accordingly, the execution unit 211 may be configured to execute the DMA task to be executed stored in the second storage space based on the read configuration information. For example, a user (such as a software process or thread) may operate the third storage space through an interface provided by the DMA controller to add, delete or modify configuration information.

[0040] It should be noted that the implementation forms of the second storage space and the third storage space can be similar to the implementation form of the first storage space. And the sizes of the three storage spaces can be set according to actual needs. For example, the size of the second storage space can be less than or equal to the size of the first storage space, and the size of the third storage space can be less than or equal to the size of the second storage space. The embodiments of the present disclosure do not limit this.

[0041] For example, the DMA controller may use Figure 3 The DMA task is processed by the process shown in the figure. Figure 3 As shown, the processing flow of the DMA task may include the following operations S301 to S303.

[0042] Operation S301: reading a pending DMA task from a first storage space.

[0043] Operation S302: storing the read DMA task to be processed into the second storage space as a DMA task to be executed.

[0044] Operation S303: executing the to-be-executed DMA task stored in the second storage space.

[0045] It can be understood that the processing flow can be executed by a DMA controller, and specifically can be executed by an execution unit included in the DMA controller.

[0046] Exemplarily, after writing the DMA task into the first storage space, the processor may send an instruction to the DMA controller, and the DMA controller may determine based on the instruction that a new DMA task to be processed is stored in the first storage space, and read the DMA task to be processed from the first storage space. Alternatively, the DMA controller may periodically read the DMA task to be processed from the first storage space. Alternatively, the DMA controller may also read the DMA task to be processed from the first storage space when determining that there is free storage space in the second storage space, so as to make full use of the second storage space and facilitate the DMA controller to efficiently process the DMA task.

[0047] In one embodiment, the DMA controller can write the pending DMA tasks read from the first storage space into the second storage space as pending DMA tasks. The DMA controller can execute the pending DMA tasks stored in the second storage space in parallel, or can execute the DMA tasks in sequence according to the writing order of the pending DMA tasks in the second storage space, or can execute the DMA tasks according to the importance of the pending DMA tasks in the second storage space. It should be noted that the DMA tasks executed in parallel are tasks that do not conflict in execution order, and the strategy of the DMA controller to execute the pending DMA tasks in the second storage space can be determined based on the aforementioned configuration information.

[0048] In one embodiment, after executing a DMA task stored in the second storage space, the DMA controller may delete the completed DMA task to be executed from the second storage space to release the occupation of the second storage space by the completed DMA task, so that the second storage space can store new DMA tasks to be executed.

[0049] In one embodiment, a task status flag indicating whether the DMA task is executed can be set for the DMA task to better maintain the execution of the DMA task and facilitate the out-of-order execution of the DMA task. For example, by setting the task status flag, it is possible to avoid the situation where some DMA tasks are omitted or some DMA tasks are repeatedly executed during the out-of-order execution process. For example, the task status flag can be added when the DMA task is written to the first storage space, or it can be added when the DMA task read from the first storage space is written to the second storage space, and different values ​​can be set according to the execution status of the DMA task to indicate different execution states of the DMA task. For example, different execution states can include at least an executing state and an executed state, or, for another example, according to actual needs, different execution states can also include an unexecuted state, etc., which is not limited in the present disclosure.

[0050] The following will be combined Figure 4The processing flow of a DMA task with a task status identifier according to at least one embodiment of the present disclosure is further described.

[0051] like Figure 4 As shown, the execution unit included in the DMA controller can read the pending DMA task from the first storage space through the aforementioned operation S301, and store the pending DMA task in the second storage space through operation S302 as the pending DMA task, and then perform operation S404 to set the task status identifier of the pending DMA task to a first value. The first value can be a value indicating the execution state. Exemplarily, the first value can be a value set according to actual needs such as 1, and the present disclosure does not limit this.

[0052] After the execution unit included in the DMA controller executes a DMA task to be executed stored in the second storage space, operation S405 can be performed. In response to the DMA task to be executed in the second storage space being completed, the task status identifier of the DMA task to be executed stored in the second storage space is set to a second value. The second value can be a value indicating the execution completion state, which is different from the above-mentioned first value. Exemplarily, the second value can be a value set according to actual needs, such as 2, which is not limited in the present disclosure.

[0053] By setting the task status identifier, the execution unit can only execute DMA tasks whose task status identifier is the first value during out-of-order execution of to-be-executed DMA tasks stored in the second storage space, thereby avoiding the situation where the executed DMA tasks are repeatedly executed.

[0054] It is understandable that the task status flag can be set during the process of out-of-order execution of the to-be-executed DMA tasks stored in the second storage space. In this way, the setting of the task status flag is not perceived by the issuer of the DMA task (eg, the processor).

[0055] In one embodiment, the task status identifier may also be set when the DMA task is stored in the first storage space, and the initial value of the task status identifier may be a third value, and the third value may be a value indicating an unexecuted state. For example, after the first storage space receives and stores the pending DMA task, the task status identifier of the pending DMA task may be set to a third value. Exemplarily, the third value may be a value set according to actual needs, such as 1, and the present disclosure does not limit this. The third value may be set by the execution subject (e.g., a processor) that writes the pending DMA task into the first storage space, or may be set by the execution unit after receiving an instruction sent by the processor.

[0056] Exemplarily, the execution unit may also set the task status identifier of the pending DMA task stored in the first storage space to the first value after storing the pending DMA task read from the first storage space into the second storage space, and after the pending DMA task corresponding to the pending DMA task in the second storage space is completed, set the task status identifier of the pending DMA task stored in the first storage space to the second value. In this way, when reading the pending DMA task from the first storage space, the execution unit may only read the pending DMA task whose task status identifier is the third value, thereby avoiding the situation where the pending DMA task is repeatedly read and repeatedly executed during the out-of-order execution of the DMA task.

[0057] It is understandable that no matter how the setting time of the task status flag is set, the change of the task status flag is not perceived by the issuer of the DMA task (such as a processor). At least one embodiment of the present disclosure can realize the acquisition and execution of DMA tasks through the task status flag, that is, at least a single-bit flag can be used to replace the read pointer and write pointer on which the acquisition and execution of DMA tasks under the ring buffer mechanism depend. Compared with the ring buffer mechanism, it can also support out-of-order execution of DMA tasks.

[0058] According to at least one embodiment of the present disclosure, corresponding indication information can be set for DMA tasks to determine the execution order of DMA tasks based on the indication information. In this way, compared with the ring buffer mechanism, flexible execution of DMA can be achieved, rather than only executing according to the order in which DMA tasks are issued.

[0059] Exemplarily, the indication information may include information indicating the execution priority of the DMA task. The execution priority may be set according to the urgency of the execution of the task, the importance of the task, etc. For example, the execution priority may include three levels of high priority, medium priority, and ordinary, or may include four levels of emergency (highest priority), second highest priority, medium priority, and ordinary. The number of levels of the execution priority may be set according to actual needs, and the present disclosure does not limit this.

[0060] Exemplarily, the indication information may include information indicating the order of issuing the DMA tasks. For example, the issuing time of the DMA tasks may be used to indicate the issuing order, and the earlier the issuing time, the higher the issuing order.

[0061] The execution unit can select a pending DMA task from the first storage space for reading according to the indication information, and write the read DMA task into the second storage space as a pending DMA task. For example, the execution unit can select the DMA task with the highest execution priority indicated by the indication information, or select the DMA task with the highest sending order indicated by the indication information, and read the selected DMA task. In the case where there are at least two DMA tasks with the highest execution priority, the execution unit can also select the DMA task with the highest sending order from the at least two DMA tasks.

[0062] According to an embodiment of the present disclosure, when the execution unit executes the pending DMA tasks stored in the second storage space, the pending DMA tasks can be selected from the second storage space based on the indication information of the pending DMA tasks stored in the second storage space to execute the selected pending DMA tasks. The strategy of the execution unit selecting the pending DMA tasks from the second storage space is similar to the strategy of selecting the pending DMA tasks from the first storage space, for example, it can be selected according to priority or according to the order of issuance, and the present disclosure does not limit this.

[0063] According to at least one embodiment of the present disclosure, in a computer system, when executing a DMA task, the data is transferred via a bus. In this embodiment, the execution unit can split the target DMA task to be executed selected from the second storage space into multiple subtasks when executing the DMA task, and the amount of data transferred by each subtask after the split meets the bus width requirement for the amount of data transferred in a single transmission. The execution unit can then execute the multiple subtasks obtained by the split.

[0064] Exemplarily, the DMA task to be executed selected by the execution unit from the second storage space can be split into multiple subtasks according to the bus width. For example, if the selected DMA task to be executed needs to carry 1K Byte of data, and the bus requires that the maximum amount of data to be transmitted each time is 64 Byte of data, then the task that needs to carry 1K Byte of data can be split into 16 subtasks.

[0065] For example, according to actual needs, when the currently executed DMA task can be split into multiple subtasks, when executing the DMA task stored in the second storage space based on the aforementioned configuration information, some of the multiple subtasks can be executed first. After the execution of the partial subtasks is completed, the remaining subtasks are not executed temporarily, but other DMA tasks to be executed are selected from the second storage space to be executed first, and the remaining subtasks are executed after the selected other DMA tasks to be executed are completed. The specific execution strategy can be determined according to the configuration information, and the task execution strategy and the switching method during the task execution process can be flexibly set according to the software requirements and the actual execution requirements, so that the execution of the DMA task is more flexible and convenient, for example, it can also avoid the situation where other urgent tasks cannot be executed in time because a certain DMA task is too large.

[0066] According to at least one embodiment of the present disclosure, the execution unit of the DMA controller may be implemented, for example, by hardware, software, firmware, or any combination thereof, for example, by an integrated circuit (eg, FPGA), and the present disclosure does not impose any limitation on this.

[0067] The following will be combined Figure 5 The principle of a DMA controller processing DMA tasks provided by at least one embodiment of the present disclosure is further described.

[0068] Figure 5 The working principle diagram of the direct memory access controller according to the third embodiment of the present disclosure is schematically shown.

[0069] like Figure 5 As shown, in embodiment 500, the operation flow may include steps 1 to 4, which are described in detail below. For example, an external processor (e.g., may include processor 512 and processor 522) may operate the first storage space 5211 provided by the storage unit in the DMA controller via the interface of the DMA controller to execute step 1, and write the DMA task to be executed into the first storage space 5211 as a DMA task to be processed.

[0070] The execution unit 511 included in the DMA controller can read the pending DMA tasks from the first storage space 5211. Specifically, based on the indication information of the pending DMA tasks stored in the first storage space 5211, it can select one or at least two pending DMA tasks, read the selected pending DMA tasks, and write the read pending DMA tasks into the second storage space 5221 as the pending DMA tasks (i.e., execute step 2).

[0071] Subsequently, the execution unit 511 may select a to-be-executed DMA task stored in the second storage space 5221 based on the indication information, and execute the selected to-be-executed DMA task (i.e., execute step 3). After executing the selected to-be-executed DMA task, the execution unit 511 may also send feedback information corresponding to the executed to-be-executed DMA task, for example, the feedback information may be sent to the processor 512 that issued the selected to-be-executed DMA task, so as to inform the processor 512 that the DMA task issued by the processor 512 has been executed.

[0072] In one embodiment, each DMA task may have a task identifier that uniquely indicates the task, and the task identifier may, for example, indicate the task issuer and the task number issued by the task issuer. When sending feedback information, the execution unit may determine the sending object of the feedback information according to the task identifier, and use the task number as part of the feedback information, so that the task issuer can distinguish the DMA tasks that have been executed among the multiple DMA tasks issued by it.

[0073] Exemplarily, when the execution unit splits the DMA task to be executed into multiple subtasks, the execution unit may send feedback information corresponding to the DMA task to be executed after all the multiple subtasks are executed.

[0074] It is understandable that the execution order of the above steps 1 to 4 is only for a single DMA task. For multiple DMA tasks, at least some of the steps 1 to 4 can be executed in parallel. For example, at the same time, for the nth DMA task, the current execution step is step 3, and for the n+mth DMA task, the current execution step is step 1. Wherein, n and m are both natural numbers.

[0075] In addition, it should be noted that in the working principle of the DMA controller described in any of the aforementioned embodiments, the execution unit can send feedback information corresponding to the completed DMA task to be executed in response to the completion of the DMA task to be executed stored in the second storage space.

[0076] The DMA controller provided by at least one embodiment of the present disclosure has two storage spaces, and the second storage space stores DMA tasks read from the first storage space. Therefore, one or at least two DMA tasks can be taken out from the second storage space at one time for execution. Therefore, the execution method of DMA tasks has more possible combinations, and the specific execution method can be flexibly set according to the actual needs of software and equipment. Compared with the method of executing DMA tasks according to the first-in-first-out order such as the ring buffer mechanism, it has higher flexibility.

[0077] Based on the DMA controller provided by at least one embodiment of the present disclosure, the data of the DMA task can be transferred to other hardware of the independent memory, for example, the processor performing AI operation or image processing can be freed from the inefficient memory access work. The DMA controller provided by at least one embodiment of the present disclosure can utilize the existing paths and resources, and implement the complex DMA task execution strategy with less resource consumption as the premise, without the need for memory to participate in the startup execution of DMA; because the task startup method does not involve the frequent interaction of the read and write pointers, the task startup is also faster.

[0078] Based on the method for processing DMA tasks implemented by the DMA controller provided in at least one embodiment of the present disclosure, DMA tasks can be executed according to multiple strategies, and the execution dependency between DMA tasks can be reduced. In addition, by setting indication information and configuration information, urgent DMA tasks can be executed quickly, so that the execution between DMA tasks does not block each other, and the execution of DMA tasks is more flexible and efficient.

[0079] It should be noted that the DMA task may include a task of reading data from device A and writing the read data to device B, or may be any other type of data transfer task, which is not limited in the present disclosure. The number of DMA tasks that can be executed in parallel may be less than or equal to the number of DMA tasks to be executed that can be stored in the second storage space, and the number of DMA tasks that can be executed in parallel may be set according to the actual processing performance of the DMA controller, etc., which is not limited in the present disclosure.

[0080] Based on the DMA task processing method provided by at least one embodiment of the present disclosure, the present disclosure also provides a DMA controller for executing the processing method. Figure 6 Describe in detail.

[0081] Figure 6 The structure block diagram of the direct memory access controller according to the embodiment of the present disclosure is schematically shown.

[0082] like Figure 6 As shown, the DMA controller 600 of this embodiment includes a processing unit 610 and a storage medium 620. The storage medium 620 is used to store non-temporary computer-readable instructions (e.g., one or more computer program modules). The processing unit 610 is used to run the computer program instructions, and the computer program instructions are executed by the processing unit 610 to perform the processing method of the DMA task provided by any embodiment of the present disclosure. The processing unit 610 and the storage medium 620 can be interconnected through a bus system and / or other forms of communication mechanisms (not shown).

[0083] The processing unit 610 may be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component, etc. The processing unit 610 may be a general-purpose processor or a dedicated processor, and may control other components in the DMA controller 600 to perform desired functions.

[0084] For example, the storage medium 620 may include any combination of one or more computer program products, and the computer program product may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. Volatile memory may include, for example, random access memory (RAM) and / or cache memory (cache), etc. Non-volatile memory may include, for example, read-only memory (ROM), hard disk, erasable programmable read-only memory (EPROM), portable compact disk read-only memory (CD-ROM), USB memory, flash memory, etc. One or more computer program modules may be stored on the computer-readable storage medium, and the processing unit 610 may run one or more computer program modules to implement various functions of the DMA controller 600. Various applications and various data, as well as various data used and / or generated by the application, etc. may also be stored in the computer-readable storage medium.

[0085] It should be noted that, in the embodiment of the present disclosure, the specific functions and technical effects of the DMA controller 600 can refer to the description of the processing method of the DMA task in the above text, and will not be repeated here.

[0086] Based on the DMA controller provided in the embodiment of the present disclosure, the present disclosure also provides a computing device, which will be combined with Figure 7-Figure 8 The computing device is described in detail.

[0087] Figure 7 The structural diagram of the computing device of the embodiment of the present disclosure is schematically shown.

[0088] like Figure 7 As shown, the computing device 700 of this embodiment includes a DMA controller 701 and at least one processor 702. For example, the processor 702 may be a CPU, a GPU, or an AI chip, etc. The DMA controller 701 may be a DMA controller provided by any of the aforementioned embodiments. For example, the DMA controller 701 may be integrated with at least one processor 702 on the same circuit board.

[0089] In this embodiment, at least one processor may send a pending DMA task and store the pending DMA task in the first storage space described above. The DMA controller 701 may read the pending DMA task from the first storage space and store the read pending DMA task in the second storage space as a pending DMA task. The DMA controller 701 may also execute the pending DMA task stored in the second storage space.

[0090] In one embodiment, the DMA controller 701 may send the above-mentioned feedback information to the processor that sent the DMA task after the to-be-executed DMA task is completed.

[0091] Figure 8 A schematic diagram of the structure of a computing device according to another embodiment of the present disclosure is shown.

[0092] like Figure 8 As shown, in addition to the DMA controller 801 and at least one processor 802, the computing device 800 of this embodiment also includes a memory 803 and a bus 804. The memory 803 is independent of the DMA controller 801, and the memory 803, the DMA controller 801 and the at least one processor 802 communicate through the bus 804. The embodiments of the present disclosure do not limit the implementation of the memory.

[0093] For example, when the DMA task to be executed by the DMA controller 801 is to transfer the data stored in the memory 803 to the external device, the DMA controller 801 can first read the data stored in the memory 803 through the bus during the execution of the DMA task, and then send the read data to the external device connected thereto to write the read data to the external device. This process does not affect the communication between at least one processor 802 through the bus. For example, when the DMA task to be executed by the DMA controller is to transfer the data cached by the first processor in at least one processor 802 to the second processor in at least one processor 802, the DMA controller can first read the data cached in the first processor through the bus during the execution of the DMA task, and then send the read data to the second processor to write the read data into the cache of the second processor. This process does not affect the access of at least one processor to the memory.

[0094] At least some embodiments of the present disclosure also provide a non-transitory storage medium. Fig. 9 A schematic diagram of a computer-readable storage medium provided by an embodiment of the present disclosure is schematically shown. Fig. 9As shown, the storage medium 900 stores non-temporary computer-readable instructions 901. When the non-temporary computer-readable instructions 901 are executed by a computer (including a processor), a method for processing a direct memory access task provided by any embodiment of the present disclosure can be executed. The method enables the execution of a DMA task to be independent of the ring buffer working mode of the memory, so that the task startup does not need to update and read the values ​​of the read pointer and the write pointer. For example, the startup efficiency of the DMA task and the acquisition efficiency of computing resources can be improved, thereby further improving the work efficiency of the processor.

[0095] For example, one or more computer instructions may be stored on the storage medium 900. Some of the computer instructions stored on the storage medium 900 may be, for example, instructions for implementing one or more steps in the processing method for the above-mentioned direct memory access task.

[0096] For example, the storage medium may include a storage component of a tablet computer, a hard disk of a personal computer, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM), a compact disk read-only memory (CD-ROM), a flash memory, or any combination of the above storage media, or other applicable storage media. For example, the storage medium 900 may be the storage medium 620 in the aforementioned DMA controller 600.

[0097] The technical effects of the storage medium provided by the embodiments of the present disclosure can be referred to the corresponding descriptions of the DMA controller and the processing method of the DMA task in the above embodiments, which will not be repeated here.

[0098] There are a few points to note about this disclosure:

[0099] (1) In the drawings of the embodiments of the present disclosure, only the structures related to the embodiments of the present disclosure are involved, and other structures can refer to the general design.

[0100] (2) In the absence of conflict, features in the same embodiment or in different embodiments of the present disclosure may be combined with each other.

[0101] The above are only specific embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any technician familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims

1. A direct memory access controller, comprising: The execution unit is configured to read the pending direct memory access task from the first storage space, store the read pending direct memory access task in the second storage space as the pending direct memory access task, and execute the pending direct memory access task stored in the second storage space.

2. The direct memory access controller according to claim 1, further comprising a storage unit, wherein: The storage unit is configured to provide a first storage space and a second storage space, The first storage space is configured to receive and store the pending direct memory access task, The second storage space is configured to receive and store the to-be-executed direct memory access task from the first storage space.

3. The direct memory access controller according to claim 2, wherein: The storage unit includes a first sub-storage unit and a second sub-storage unit, The first sub-storage unit is configured to provide the first storage space; and the second sub-storage unit is configured to provide the second storage space.

4. The direct memory access controller according to claim 3, wherein: The first sub-storage unit includes a plurality of functional storage spaces, and the functional storage spaces are configured to be operated through an interface of the direct memory access controller; or, The first sub-storage unit is provided independently of the second sub-storage unit and has an independent address space.

5. The direct memory access controller according to claim 2, wherein: The storage unit is further configured to provide a third storage space, wherein the third storage space is configured to store configuration information. The configuration information is used to be read by the execution unit to execute the to-be-executed direct memory access task stored in the second storage space based on the configuration information.

6. The direct memory access controller according to claim 1, wherein: The to-be-executed direct memory access tasks stored in the second storage space each have a task status identifier, and the task status identifier is used to indicate whether the corresponding to-be-executed direct memory access task is executed; The execution unit is further configured to set a task status identifier of the to-be-executed direct memory access task during out-of-order execution of the to-be-executed direct memory access task stored in the second storage space.

7. The direct memory access controller according to claim 6, wherein: The execution unit is further configured to: After reading the to-be-processed direct memory access task from the first storage space into the second storage space as the to-be-executed direct memory access task, setting the task state identifier of the to-be-executed direct memory access task to a first value; In response to the to-be-executed direct memory access task stored in the second storage space being completed, the task state identifier of the to-be-executed direct memory access task stored in the second storage space is set to a second value.

8. The direct memory access controller according to claim 1, wherein: The execution unit includes a subtask execution unit, The execution unit is further configured to split the target to-be-executed direct memory access task stored in the second storage space into a plurality of subtasks. The subtask execution unit is configured to execute the plurality of subtasks.

9. The direct memory access controller according to claim 1, wherein: The to-be-processed direct memory access tasks stored in the first storage space respectively have indication information; The execution unit is further configured to select the to-be-processed direct memory access task from the first storage space according to the indication information, and write the to-be-processed direct memory access task into the second storage space as the to-be-executed direct memory access task.

10. The direct memory access controller according to claim 1 or 9, wherein: The execution unit is further configured to, in response to the second storage space having free storage space, select the to-be-processed direct memory access task from the first storage space, and write the task into the second storage space as the to-be-executed direct memory access task.

11. The direct memory access controller according to claim 9, wherein: The to-be-executed direct memory access task stored in the second storage space also has corresponding indication information already in the first storage space; The execution unit is further configured to select the to-be-executed direct memory access task from the second storage space according to the indication information for execution.

12. The direct memory access controller according to claim 1, wherein: The execution unit is further configured to: In response to the to-be-executed direct memory access tasks stored in the second storage space being completed, the to-be-executed direct memory access tasks that have been completed are deleted from the second storage space.

13. The direct memory access controller according to claim 1, wherein: The execution unit is further configured to: In response to the to-be-executed direct memory access task stored in the second storage space being completed, feedback information corresponding to the to-be-executed direct memory access task that has been completed is sent.

14. A method for processing a direct memory access task, comprising: Reading a pending direct memory access task from the first storage space; The first storage space receives and stores the pending direct memory access task; storing the read direct memory access task to be processed into the second storage space as a direct memory access task to be executed; as well as Execute the to-be-executed direct memory access task stored in the second storage space.

15. The method according to claim 14, wherein: The to-be-executed direct memory access tasks stored in the second storage space each have a task status identifier, and the task status identifier is used to indicate whether the corresponding to-be-executed direct memory access task is executed; the method further includes: In the process of out-of-order execution of the to-be-executed direct memory access task stored in the second storage space, a task state identifier of the to-be-executed direct memory access task is set.

16. The method according to claim 15, further comprising: After storing the read direct memory access task to be processed in the second storage space as a direct memory access task to be executed, setting the task state of the direct memory access task to be executed to a first value; In response to the direct memory access task to be executed stored in the second storage space being completed, the task state identifier of the direct memory access task to be executed stored in the second storage space is set to a second value.

17. A direct memory access controller comprising: Processing unit; as well as A storage medium storing one or more computer program instructions, wherein the one or more computer program instructions, when executed by the processing unit, perform the method according to any one of claims 14 to 16.

18. A computing device comprising: The direct memory access controller according to any one of claims 1 to 13 or 17; as well as At least one processor is configured to send the pending direct memory access task and store the pending direct memory access task in the first storage space.

19. The computing device of claim 18, further comprising a memory and a bus, the memory being independent of the direct memory access controller, and the memory, the direct memory access controller, and the at least one processor communicating via the bus.

20. A computer-readable storage medium that non-transitorily stores computer-readable instructions, wherein: When the computer-readable instructions are executed by a processor, the method according to any one of claims 14 to 16 is implemented.

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