Register-based interface signal control method and system

Abstract

The application relates to the computer technical field and provides a register-based interface signal control method and system. The method comprises the following steps: determining interface signal requirements of at least one module in at least one working mode; generating register codes based on the interface signal requirements; generating interface top-level codes based on the interface signal requirements; and controlling the at least one interface signal according to the interface logic mode by using the at least one register. In this way, the automation efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, in particular to an interface signal control method and system based on register. BACKGROUND

[0002] With the expansion of the scale and the improvement of the complexity of digital integrated circuits, the integrated circuits are generally divided into multiple modules according to functions, each module has input signals and output signals, which are used for information interaction between different modules and interaction between the modules and the top architecture. Among them, the control of the key interface signals needs to meet the specific control logic requirements and meet the specific connection requirements. When a module is integrated, if some signals are connected incorrectly or no effective interface signal control is applied, it may cause functional errors and performance degradation. In the prior art, the chip design code needs to be iterated frequently and the module division and structure inside the integrated circuit may need to be changed during the chip design and development process, which needs to rely on the manual addition of control logic by the R&D personnel and the verification and maintenance by the verification personnel, thereby increasing the development difficulty and cost and prolonging the development cycle.

[0003] Therefore, the present application provides an interface signal control method and system based on register to solve the technical problems in the prior art. SUMMARY

[0004] In a first aspect, the present application provides an interface signal control method based on register. The interface signal control method comprises: determining interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements comprise at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal; generating register code based on the interface signal requirements, wherein the register code comprises control logic, the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then utilizing a control logic template, the control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes; generating interface top-level code based on the interface signal requirements, and generating a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code; and controlling the at least one interface signal according to the interface logic mode by using the at least one register.

[0005] According to the first aspect of the present application, the register code and the interface top-level code are generated based on the interface signal requirements, on the one hand, the control logic is generated by using the control logic template after the at least one logic mode is extracted from the interface signal requirements, which not only can define multiple logic modes and pre-set the control logic template based on the limited change rule of the interface logic mode of the interface signal in advance, thereby improving the automation script processing efficiency, but also can change the first connection relationship, i.e., adjust the connection between the interface signal and the control logic, based on the unchanged control logic in combination with the variable working mode; on the other hand, the related information of the interface signal (for example, by flexibly filling in the interface signal table) can be defined in combination with the project requirements and the customer customization requirements, so that the register related details and the enable signal related details can be flexibly adjusted greatly, for example, different configurations of the interface signal can be realized by changing the register values to be filled in, so that the adjustment of the interface signal connection can be realized by changing the connection between the interface signal and the control logic, i.e., changing the first connection relationship, thereby realizing the flexible adjustment in the aspects of the interface signal connection and the control logic applied to the interface signal, and ensuring that the information interaction between the modules in the integrated circuit and the interaction between the modules and the top-level architecture can run correctly, which is helpful to adapt to the complex and variable application scenarios and the frequent iteration and modification requirements in the chip design and development process.

[0006] In a possible implementation manner of the first aspect of the present application, the at least one working mode is variable, and the at least one logic mode does not change with the change of the at least one working mode.

[0007] In a possible implementation manner of the first aspect of the present application, when the at least one interface signal changes with the change of the at least one working mode, the first connection relationship changes with the change of the at least one working mode.

[0008] In a possible implementation manner of the first aspect of the present application, the control logic does not change with the change of the at least one working mode, and the control logic is register readable and controllable.

[0009] In a possible implementation manner of the first aspect of the present application, the change of the at least one working mode is realized by changing the register value of the at least one register and then changing the configuration of the at least one interface signal.

[0010] In a possible implementation manner of the first aspect of the present application, the interface top-level code includes the register connection attribute, the register type, the register name and the register default value of each of the at least one module.

[0011] In a possible implementation of the first aspect of the application, the interface top-level code is generated based on the interface signal requirements, including: generating register output signals for connecting the at least one module based on respective register connection attributes, register types, register names and register default values of the at least one module.

[0012] In a possible implementation of the first aspect of the application, the plurality of logic modes include: a readable logic mode, a rewrite logic mode, a readable and rewrite combined logic mode, and a no-processing logic mode.

[0013] In a possible implementation of the first aspect of the application, the interface signal table records the interface signal requirements in a preset specification format, and the interface signal requirements are determined by parsing the interface signal table, and the preset specification format includes a table file format and a table entry definition.

[0014] In a possible implementation of the first aspect of the application, the register code is generated by parsing a register table, and the register table is obtained by converting the interface signal table by using an automated script.

[0015] In a possible implementation of the first aspect of the application, the preset specification format can be adjusted by an automated script, and the table entry definition includes a register name entry or a fixed signal prefix and suffix entry.

[0016] In a possible implementation of the first aspect of the application, the interface signal requirements include input signal requirements and output signal requirements.

[0017] In a possible implementation of the first aspect of the application, the interface signal requirements further include signal names, input and output, control modes, control enables, data bit widths, register names, register initial values and register addresses.

[0018] In a possible implementation of the first aspect of the application, the first connection relationship between the at least one interface signal and the control logic is generated by implementing a connection between the at least one interface signal and the control logic by using an assignment statement, and the second connection relationship between the at least one register and the control logic is generated by implementing a connection between the at least one register and the control logic by using an assignment statement.

[0019] In a second aspect, the embodiments of the application further provide a computer device, which includes a memory, a processor, and a computer program stored in the memory and capable of running on the processor, and the processor implements the method according to any of the implementation modes of any of the above aspects when executing the computer program.

[0020] In a third aspect, the embodiments of the present application further provide a computer readable storage medium, which stores computer instructions. When the computer instructions are run on a computer device, the computer device is caused to perform the method according to any implementation manner of any of the above aspects.

[0021] In a fourth aspect, the embodiments of the present application further provide a computer program product, which includes instructions stored on a computer readable storage medium. When the instructions are run on a computer device, the computer device is caused to perform the method according to any implementation manner of any of the above aspects.

[0022] In a fifth aspect, the embodiments of the present application further provide a register-based interface signal control system. The interface signal control system includes: an input module configured to input an interface signal table; an extraction module configured to parse the interface signal table to determine interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements include at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal; a processing module configured to generate register code based on the interface signal requirements, wherein the register code includes control logic, the control logic is generated by using a control logic template after extracting the at least one logic mode from the interface signal requirements, the control logic template is pre-set based on a plurality of logic modes, the at least one logic mode is selected from the plurality of logic modes, and the processing module is further configured to generate interface top-level code based on the interface signal requirements, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code; and an output module configured to output the register code, the interface top-level code, the first connection relationship, and the second connection relationship, wherein the at least one register is configured to control the at least one interface signal according to the interface logic mode.

[0023] Through the fifth aspect of this application, register code and top-level interface code are generated based on the interface signal requirements. On the one hand, after extracting at least one logic mode from the interface signal requirements and then generating the control logic using a control logic template, multiple logic modes can be pre-defined based on the limited variation rules of the interface logic modes of the interface signals, and the control logic template can be pre-set, improving the efficiency of automated script processing. Furthermore, while maintaining an unchanged control logic, the first connection relationship can be changed by combining variable working modes, i.e., adjusting the connections between each interface signal and the control logic. On the other hand, relevant information about the interface signals (e.g., ...) can be defined based on project requirements and customer customization needs. By flexibly filling in the interface signal table, significant adjustments can be made to register-related details and enable signal-related details. For example, different configurations of interface signals can be achieved by changing the register values ​​to be filled in. This can be combined with adjusting the interface signal connection by changing the connection between the interface signal and the control logic, i.e., changing the first connection relationship. This achieves flexible adjustment in both interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between various modules within the integrated circuit and the interaction between the module and the top-level architecture can operate correctly. This helps to adapt to complex and ever-changing application scenarios and the needs of frequent iterative modifications during chip design and development. Attached Figure Description

[0024] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0025] Figure 1 A flowchart illustrating a register-based interface signal control method provided in an embodiment of this application;

[0026] Figure 2 A schematic diagram of a register-based interface signal control system provided in an embodiment of this application;

[0027] Figure 3 This is a schematic diagram of the structure of a computing device provided in an embodiment of this application. Detailed Implementation

[0028] The embodiments of this application will now be described in further detail with reference to the accompanying drawings.

[0029] It should be understood that in the description of the present application, "at least one" means one or more, and "multiple" means two or more. In addition, the words "first", "second", and the like, unless otherwise specified, are only used to distinguish the description purpose, and cannot be understood as indicating or implying relative importance, nor can it be understood as indicating or implying order.

[0030] Figure 1 A flowchart of a register-based interface signal control method provided for an embodiment of the present application is shown. As shown in Figure 1 the interface signal control method includes the following steps.

[0031] Step S110: determining interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal.

[0032] Step S120: generating register code based on the interface signal requirements, wherein the register code includes control logic, the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template, the control logic template is pre-set based on multiple logic modes, and the at least one logic mode is selected from the multiple logic modes.

[0033] Step S130: generating interface top-level code based on the interface signal requirements, and generating a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code.

[0034] Step S140: controlling the at least one interface signal according to the interface logic mode by using the at least one register.

[0035] Figure 1The illustrated register-based interface signal control method aims at the pain points in the chip design development process, that is, the chip design code needs to be frequently iterated and the internal module partitioning and structure of the integrated circuit may need to be changed during the chip design development process. Therefore, it is necessary to ensure that the information interaction between each module in the integrated circuit and the interaction between the module and the top-level architecture can operate correctly, that is, it is necessary to ensure that the specific interface signal connection requirements are met and the correct control logic is applied to the interface signal. In addition, the trend of integrated circuits is to provide higher flexibility, so multiple working modes are often provided, that is, the same module can exhibit different characteristics in multiple working modes, thereby adapting to complex and variable application environments. Therefore, it is required that the interface signal connection and the control logic of the interface signal can adapt to the needs of multiple module chips in multiple working modes. Here, in step S110, the interface signal requirements of at least one module in at least one working mode are determined. The interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal. In this way, the interface signal requirements reflect the needs of the multi-module chip in multiple working modes. The same module can have multiple working modes, and in different working modes, information interaction with firmware and the like can be achieved through interface signals. The interface signal requirements include at least one interface signal, which generally includes at least input signals and output signals. The interface logic mode associated with the at least one interface signal represents how to apply control logic to the interface signal. For example, the interface logic mode can include a rewrite logic mode, that is, reassigning through a register, for another example, the interface logic mode can include a readable logic mode, that is, reading the interface signal through a register. The interface logic mode can include other logic modes and can include various possible combinations of these logic modes. It should be understood that here, the at least one logic mode included in the interface logic mode associated with the at least one interface signal reflects the control logic aspect of the interface signal corresponding to the interface signal requirements.

[0036] With reference to the foregoing Figure 1At step S120, register code is generated based on the interface signal requirement. The register code includes control logic, which is generated by extracting the at least one logic pattern from the interface signal requirement and using a control logic template. The control logic template is pre-set based on a plurality of logic patterns, and the at least one logic pattern is selected from the plurality of logic patterns. Here, the control logic template is a template for generating the code of the part of the register code related to the control logic. In this way, by distinguishing the control logic aspect of the interface signal, the control logic of the interface signal varies in a regularity of limited possibilities, i.e., the possible variation of the control logic of the interface signal can be pre-covered by a limited plurality of logic patterns, and the at least one logic pattern can be selected from the plurality of logic patterns, i.e., the at least one logic pattern currently applicable is selected within the range of the possible variation of the control logic of the interface signal determined in advance, so that the control logic in the register code can be conveniently generated by using the control logic template. For example, the plurality of logic patterns can be readable logic patterns, rewrite logic patterns, and combinations, so that the requirements of the control logic aspect imposed on the interface signal under a specific chip project can be covered. Moreover, any combination of the readable logic patterns and the rewrite logic patterns can be implemented based on the register, including control logic with a certain complexity level, e.g., first reading the interface signal value by the register, then rewriting the interface signal value by the register, then reading the rewritten interface signal value by the register, and then secondly rewriting the rewritten interface signal value by the register.

[0037] With reference to the foregoing Figure 1At step S130, interface top-level code is generated based on the interface signal requirements, and a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic are generated. The at least one register is instantiated based on the register code. The interface top-level code can be in the form of an interface signal top-level file. The interface top-level code corresponds to a top-level architecture, which generally includes a top-level module and sub-level modules included in the top-level module, and module interconnection relationships between the sub-level modules and direct connection relationships between the sub-level modules and the top-level module. As mentioned above, in the chip design development process, the chip design code needs to be frequently iterated and the module partition and structure inside the integrated circuit may need to be changed. Therefore, it is necessary to ensure that the information interaction between the modules inside the integrated circuit and the interaction between the modules and the top-level architecture can operate correctly, and it is also necessary to ensure that the specific interface signal connection requirements are met and the correct control logic is applied to the interface signal. Based on the generation of the register code (including the generation of the control logic in the register code using the control logic template) based on the interface signal requirements at step S120, at step S130, the interface top-level code is generated based on the interface signal requirements, and the first connection relationship and the second connection relationship are generated. In this way, the connection between the interface signals and the control logic is realized, and the connection between the registers and the control logic is also realized. Therefore, the mapping relationship from the registers to the interface signals is established through the control logic as an intermediary, which provides convenience for subsequent use of the registers to realize the readability and controllability of the interface signals. Moreover, the control logic is generated by extracting the at least one logic pattern from the interface signal requirements and then using the control logic template, so that the control logic is isolated from the multiple working modes of the multiple modules. In other words, when the multiple modules are in different working modes, the interface logic pattern may remain unchanged, that is, at least one logic pattern remains unchanged, which means that the control logic also remains unchanged. With the unchanged control logic as an intermediary, different configurations of the interface signals can be realized by changing the register values to be filled, and adjustments in the interface signal connection can be realized by changing the connection between the interface signals and the control logic, that is, changing the first connection relationship, which is conducive to meeting the needs of the multiple-module chip in multiple working modes. In addition, the second connection relationship between the registers and the control logic can be flexibly adapted according to the actually available register resources.For example, the interface signals included in the interface signal requirements, and the interface top-level code generated based on the interface signal requirements, can be obtained based on an interface signal table in which information about a specific interface signal can be defined, such as a signal name, an identifier indicating whether the interface signal is an input signal or an output signal, a signal bit width, a digital identifier used to indicate a logic mode, a reset value of a control register used to correspond to the control logic, a register name used to correspond to the control logic, and the like. Other information about a specific interface signal can also be defined in the interface signal table, such as a register name and a domain segment name corresponding to a rewrite enable signal corresponding to a rewrite logic mode, a reset value of a control register corresponding to the rewrite enable signal, and the like. As can be seen, there is a large degree of flexibility in terms of the information about the register, and the enable signal such as the rewrite enable signal corresponding to the rewrite logic mode, that is, the interface signal table can be filled in according to project needs and customer customization requirements. In this way, when generating the register code and the interface top-level code based on the interface signal requirements, on the one hand, after extracting the at least one logic mode from the interface signal requirements, the control logic is generated using the control logic template, not only can a plurality of logic modes be circumscribed based on the limited change rule of the interface logic mode of the interface signal in advance and the control logic template be preset, improving the automation script processing efficiency, but also the first connection relationship can be changed, that is, the connection between the interface signals and the control logic is adjusted, based on the control logic that remains unchanged and in combination with the variable working mode; on the other hand, the information about the interface signal can be defined in combination with the project needs and the customer customization requirements (for example, by flexibly filling in the interface signal table), so that the register-related details and the enable signal-related details are greatly flexibly adjusted, for example, different configurations of the interface signal can be realized by changing the register values to be filled in, so that the adjustment of the interface signal connection can be realized by changing the connection between the interface signal and the control logic, that is, by changing the first connection relationship, so that flexible adjustment is realized in terms of the interface signal connection and the control logic applied to the interface signal, while ensuring that the information interaction between the modules inside the integrated circuit and the interaction between the modules and the top-level architecture can be correctly run, which is helpful to adapt to complex and variable application scenarios and the frequent iteration and modification needs in the chip design and development process.

[0038] With reference to the foregoing Figure 1At step S140, the at least one interface signal is controlled according to the interface logic mode by using the at least one register. As mentioned above, the plurality of logic modes are defined and the control logic template is preset based on the limited variation rule of the interface logic mode of the interface signal in advance, which improves the efficiency of the automatic script processing, and enables flexible adjustment in the interface signal connection and the control logic applied to the interface signal while ensuring the correct operation of the information interaction between the modules in the integrated circuit and the interaction between the modules and the top architecture, which helps to adapt to the complex and changeable application scenarios and the frequent iterative modification requirements in the chip design and development process. In this way, the development difficulty and cost are reduced, and the development cycle is shortened.

[0039] In summary, Figure 1 The register-based interface signal control method shown can generate register code and interface top-level code based on the interface signal requirements. On the one hand, the control logic is generated by using the control logic template after the at least one logic mode is extracted from the interface signal requirements, which not only enables the plurality of logic modes to be defined and the control logic template to be preset based on the limited variation rule of the interface logic mode of the interface signal in advance, thereby improving the efficiency of the automatic script processing, but also enables the first connection relationship to be changed, i.e., the connection between the interface signal and the control logic to be adjusted, based on the unchanged control logic and the variable working mode. On the other hand, the related information of the interface signal (e.g., by flexibly filling in the interface signal table) can be defined in combination with the project requirements and the customer's customized requirements, so that the register-related details and the enable signal-related details can be flexibly adjusted to a large extent, e.g., different configurations of the interface signal can be realized by changing the register values to be filled in, which enables the adjustment of the interface signal connection by changing the connection between the interface signal and the control logic, i.e., changing the first connection relationship, thereby enabling flexible adjustment in the interface signal connection and the control logic applied to the interface signal while ensuring the correct operation of the information interaction between the modules in the integrated circuit and the interaction between the modules and the top architecture, which helps to adapt to the complex and changeable application scenarios and the frequent iterative modification requirements in the chip design and development process.

[0040] In a possible implementation, the at least one working mode is variable, and the at least one logic mode does not change with the change of the at least one working mode. In some embodiments, the first connection relationship changes with the change of the at least one working mode when the at least one interface signal changes with the change of the at least one working mode. In this way, the interface signal requirement embodies the needs of the multi-module chip in multiple working modes. The same module can have multiple working modes, and information interaction with firmware and the like can be achieved through the interface signal in different working modes. The control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, and therefore, the isolation between the control logic and multiple working modes of the multi-module is achieved. In other words, when the multi-module is in different working modes, it is possible to keep the interface logic mode unchanged, that is, to keep the at least one logic mode unchanged, which means that the control logic is also kept unchanged. With the unchanged control logic as an intermediary, different configurations of the interface signal can be achieved by changing the register values to be filled, and the adjustment of the interface signal connection can be achieved by changing the connection between the interface signal and the control logic, that is, changing the first connection relationship, which is conducive to meeting the needs of the multi-module chip in multiple working modes.

[0041] In a possible implementation, the control logic does not change with the change of the at least one working mode, and the control logic is register readable and controllable. In some embodiments, the change of the at least one working mode is achieved by changing the register values of the at least one register and then changing the configuration of the at least one interface signal. In this way, when the register code and the interface top-level code are generated based on the interface signal requirement, on the one hand, the control logic is generated by extracting the at least one logic mode from the interface signal requirement and then using a control logic template, which not only can circumscribe multiple logic modes based on the limited change law of the interface logic mode of the interface signal in advance and pre-set the control logic template, but also can define the related information of the interface signal (for example, by flexibly filling the interface signal table) based on the unchanged control logic, in combination with the project needs and customer customization needs, so as to make a substantial flexible adjustment to the register related details and the enable signal related details, for example, different configurations of the interface signal can be achieved by changing the register values to be filled, so that flexible adjustment is achieved in the aspects of the interface signal connection and the control logic exerted on the interface signal, while ensuring that the information interaction between the internal modules of the integrated circuit and the interaction between the module and the top-level architecture can run correctly, which is helpful to adapt to complex and changeable application scenarios and the needs of frequent iterative modification in the chip design and development process.

[0042] In a possible implementation, the interface top-level code includes register connection attributes, register types, register names and register default values of the at least one module respectively. In some embodiments, the interface top-level code is generated based on the interface signal requirements, including generating register output signals for connecting the at least one module based on the register connection attributes, the register types, the register names and the register default values of the at least one module respectively. In this way, it is helpful to make a substantial flexibility adjustment to register-related details and enable signal-related details.

[0043] In a possible implementation, the plurality of logic modes include a readable logic mode, a rewrite logic mode, a readable and rewrite combined logic mode, and a no-process logic mode. The readable logic mode is to read an interface signal through a register. The rewrite logic mode is to reassign an interface signal through a register. The no-process logic mode means no reading or reassigning process. The readable and rewrite combined logic mode means a combination between the readable logic mode and the rewrite logic mode. In this way, the control logic for the interface signal is changed in a limited possibility, i.e., the possible change rule of the control logic for the interface signal can be covered in advance by a limited plurality of logic modes, and then the at least one logic mode can be selected from the plurality of logic modes, i.e., the at least one logic mode currently applicable is selected within the range of the possible change rule of the control logic for the interface signal determined in advance, so that the control logic in the register code can be conveniently generated by using the control logic template. The plurality of logic modes can be the readable logic mode, the rewrite logic mode and the combination, so that the demand for the control logic exerted on the interface signal under a specific chip project can be covered. Moreover, any combination of the rewrite logic mode and the readable logic mode can be implemented based on the register, including control logic with a certain complexity level, e.g., first reading an interface signal value through a register, then rewriting the interface signal value through a register, then reading the rewritten interface signal value through a register, and then rewriting the rewritten interface signal value through a register for a second time.

[0044] In one possible implementation, the interface signal table records the interface signal requirements in a preset specification format, and the interface signal requirements are determined by parsing the interface signal table. The preset specification format includes a table file format and a table entry definition. In some embodiments, the register code is generated by parsing a register table, which is converted from the interface signal table by using an automated script. In some embodiments, the preset specification format can be adjusted by the automated script, and the table entry definition includes a register name entry or a fixed signal prefix / suffix entry. The interface signal table can define information about a specific interface signal, such as a signal name, an identifier indicating whether the interface signal is an input signal or an output signal, a signal bit width, a numerical identifier indicating a logic mode, a reset value of a control register corresponding to the interface signal, a register name of a control logic corresponding to the interface signal, and the like. The interface signal table can also define other information about a specific interface signal, such as a register name and a domain segment name of a rewrite enable signal corresponding to a rewrite logic mode, a reset value of a control register corresponding to the rewrite enable signal, and the like. It can be seen that there is a large degree of flexibility in the information about the register and the enable signal, such as the rewrite enable signal corresponding to the rewrite logic mode, that is, the interface signal table can be filled according to the project needs and customer customization requirements.

[0045] Referring to Figure 1 , the interface signal table records the interface signal requirements in a preset specification format, and a code template of the specification can be defined in a hardware language, such as Verilog, for the automated script to compile. In this way, the automated script can rewrite the signals that need to be rewritten in the instantiated module based on the information read from the interface signal table, and directly connect out the signals that can be read and do not need to be processed. In addition, the register table is converted from the interface signal table by using an automated script, so that the table can be filled according to the same specification, and the consistency between the register table and the interface signal table can be ensured. The register table can record register information for generating register code. The interface signal table is used to extract control logic signals and register signals, that is, the interface signal requirements are determined by parsing the interface signal table, and then interface top-level code and register code can be generated, and the connections between the control logic and the interface signals and the connections between the control logic and the registers can be automatically generated. The following takes four interface signals as an example to illustrate how a user fills in the interface signal table based on the automated script usage instructions, according to the project specific conditions and the control mode type.

[0046] The first interface signal is named "test_signal0", is an input signal, has a bit width of 2, and has a control mode of 0, which means that no control is performed. The file name to which the first interface signal belongs is "DEMO_OVRT". The second interface signal is named "test_signal1", is an output signal, has a bit width of 1, and has a control mode of 1, which means that the rewriting control logic is performed, and the default rewriting value is 0x0. The corresponding register is "TEST_REG_1", the corresponding rewriting enable register name is "TEST_REG_1", and the domain segment name is "TEST_SIGNAL1_OVRD_EN". The default rewriting enable is 0x0, that is, the rewriting function is enabled by default. The register description is "for test", the register address is 0x0, and the file name to which the register belongs is "DEMO_OVRT". The third interface signal is named "test_signal2", is an input signal, has a bit width of 1, and has a control mode of 2, which means that the readable control logic is performed, and the default rewriting value is 0x0. The corresponding register is "TEST_REG_2_RO", and there is no corresponding rewriting enable, so there is no default rewriting enable. The register description is "for test", the register address is 0x1, and the file name to which the register belongs is "DEMO_OVRT". The fourth interface signal is named "test_signal3", is an input signal, has a bit width of 1, and has a control mode of "2-1", which means that the readable logic is performed first and then the rewriting control logic is performed. The default rewriting value is 0x0. The corresponding register is "TEST_REG_3_RO and TEST_REG_3". The corresponding rewriting enable register name is "TEST_REG_3", and the domain segment name is "TEST_SIGNAL3_OVRD_EN". The default rewriting enable is 0x0, that is, the rewriting function is not enabled by default. The register description is "for test", the register address is "0x2 and 0x3", and the file name is "DEMO_OVRT". In this way, it can be seen that there is a large degree of flexibility in the related information of the register and the enable signal, such as the rewriting enable signal corresponding to the rewriting logic mode, that is, the interface signal table can be filled according to the project needs and customer customization requirements.Thus, in the process of generating register code and interface top-level code based on the interface signal requirements, on one hand, the control logic is generated after the at least one logic mode is extracted from the interface signal requirements, which not only can define multiple logic modes and set control logic templates in advance based on the limited change rules of the interface logic modes of the interface signals, thereby improving the efficiency of automatic script processing, but also can change the first connection relationship, i.e., adjust the connection between the interface signals and the control logic, based on the unchanged control logic in combination with the variable working mode; on the other hand, the related information of the interface signals can be defined in combination with the project requirements and customer customization requirements (e.g., by flexibly filling in the interface signal table), so that the register-related details and the enable signal-related details can be flexibly adjusted to a large extent, e.g., different configurations of the interface signals can be realized by changing the register values to be filled in, so that the adjustment of the interface signal connection can be realized by changing the connection between the interface signals and the control logic, i.e., changing the first connection relationship, thereby realizing flexible adjustment in the aspects of the interface signal connection and the control logic applied to the interface signals, while ensuring that the information interaction between the modules in the integrated circuit and the interaction between the modules and the top-level architecture can be correctly operated, which is helpful to adapt to complex and variable application scenarios and the frequent iteration and modification requirements in the chip design and development process.

[0047] In a possible implementation, the interface signal requirements include input signal requirements and output signal requirements. Thus, the interface signal table can be filled in according to the project requirements and customer customization requirements, and there is a large degree of flexibility in the related information of the registers and the enable signals, such as the rewrite enable signals corresponding to the rewritten logic modes.

[0048] In a possible implementation, the interface signal requirements further include a signal name, an input / output, a control mode, a control enable, a data bit width, a register name, a register initial value, and a register address. Thus, the interface signal table can be filled in according to the project requirements and customer customization requirements, and there is a large degree of flexibility in the related information of the registers and the enable signals, such as the rewrite enable signals corresponding to the rewritten logic modes.

[0049] In one possible implementation, generating the first connection relationship between the at least one interface signal and the control logic includes: establishing the connection between the at least one interface signal and the control logic through assignment statements. Generating the second connection relationship between the at least one register and the control logic includes: establishing the connection between the at least one register and the control logic through assignment statements. This achieves flexible adjustment in both interface signal connections and the control logic applied to the interface signals, while ensuring correct operation of information interaction between various modules within the integrated circuit and the interaction between modules and the top-level architecture. This helps adapt to complex and ever-changing application scenarios and the frequent iterative modifications required during chip design and development. Thus, it reduces the overhead of R&D personnel manually adding control logic and verification personnel performing verification and maintenance, lowering development difficulty and costs, and shortening the development cycle.

[0050] Figure 2 This is a schematic diagram of a register-based interface signal control system provided in an embodiment of this application. Figure 2 As shown, the interface signal control system includes an input module 210, an extraction module 220, a processing module 230, and an output module 240. The input module 210 is used to input an interface signal table. The extraction module 220 is used to parse the interface signal table to determine the interface signal requirements of at least one module in at least one operating mode. The interface signal requirements include at least one interface signal and at least one logic mode included in the interface logic mode associated with the at least one interface signal. The processing module 230 is used to generate register code based on the interface signal requirements. The register code includes control logic, which is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template. The control logic template is based on a set of multiple logic modes, and the at least one logic mode is selected from these multiple logic modes. The processing module 230 is also used to: generate top-level interface code based on the interface signal requirements, and generate a first connection relationship between the at least one interface signal and the control logic, and a second connection relationship between at least one register and the control logic. The at least one register is instantiated based on the register code. The output module 240 is used to output the register code, the interface top-level code, the first connection relationship, and the second connection relationship. The at least one register is used to control the at least one interface signal according to the interface logic mode.

[0051] Figure 2The register-based interface signal control system shown generates register code and interface top-level code based on the interface signal requirements, on one hand, the control logic is generated after the at least one logic mode is extracted from the interface signal requirements, not only can the multiple logic modes be circled based on the limited change rule of the interface logic mode of the interface signal in advance and the control logic template be preset, the automation script processing efficiency is improved, but also the first connection relationship can be changed, that is, the connection between the interface signal and the control logic is adjusted, on the basis of the unchanged control logic in combination with the variable working mode; on the other hand, the related information of the interface signal (for example, the interface signal table is filled in flexibly) can be defined in combination with the project demand and the customer customization demand, so that the register related details and the enable signal related details are flexibly adjusted greatly, for example, different configurations of the interface signal can be realized by changing the register values to be filled in, so that the adjustment of the interface signal connection can be realized by changing the connection between the interface signal and the control logic, that is, the first connection relationship is changed, so that the flexible adjustment is realized in the interface signal connection and the control logic applied to the interface signal, and meanwhile, the information interaction between the modules in the integrated circuit and the interaction between the modules and the top-level architecture can be correctly run, which helps to adapt to the complex and changeable application scenarios and the frequent iteration and modification demand in the chip design and development process.

[0052] Figure 3 Fig. 1 is a structural schematic diagram of a computing device provided by an embodiment of the present application. The computing device 300 includes one or more processors 310, a communication interface 320, and a memory 330. The processor 310, the communication interface 320, and the memory 330 are connected to each other through a bus 340. Optionally, the computing device 300 can further include an input / output interface 350 connected with an input / output device for receiving parameters set by a user and the like. The computing device 300 can be used to implement part or all of the functions of the device embodiments or system embodiments of the above-described embodiments of the present application; the processor 310 can also be used to implement part or all of the operation steps of the above-described method embodiments of the present application. For example, the specific implementation of the computing device 300 performing various operations can refer to the specific details in the above-described embodiments, for example, the processor 310 is used to perform part or all of the steps in the above-described method embodiments or part or all of the operations in the above-described method embodiments. For another example, in the embodiments of the present application, the computing device 300 can be used to implement part or all of the functions of one or more components in the above-described device embodiments, in addition, the communication interface 320 can be specifically used for the communication functions necessary for implementing the functions of these devices, components, and the like, and the processor 310 can be specifically used for the processing functions necessary for implementing the functions of these devices, components, and the like.

[0053] It should be appreciated that Figure 3 The computing device 300 can include one or more processors 310, and the plurality of processors 310 can cooperatively provide processing capabilities in a parallel connection manner, a serial connection manner, a serial-parallel connection manner, or any connection manner, or the plurality of processors 310 can constitute a processor sequence or a processor array, or the plurality of processors 310 can be divided into a main processor and an auxiliary processor, or the plurality of processors 310 can have different architectures, such as using a heterogeneous computing architecture. In addition, Figure 3 The computing device 300 shown, the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 can include more or fewer components than those shown, or combine certain components, or split certain components, or have a different arrangement of components. Figure 3 The computing device 300 shown, the related structural description and functional description are exemplary and non-limiting. In some exemplary embodiments, the computing device 300 can include more or fewer components than those shown, or combine certain components, or split certain components, or have a different arrangement of components.

[0054] The processor 310 can have various specific implementations. For example, the processor 310 can include one or a combination of central processing units (CPUs), graphic processing units (GPUs), neural-network processing units (NPUs), tensor processing units (TPUs), data processing units (DPUs), and the like. The processor 310 can also be a single-core processor or a multi-core processor. The processor 310 can be a combination of a CPU and a hardware chip. The hardware chip can be an application-specific integrated circuit (ASIC), a programmable logic device (PLD), or a combination thereof. The PLD can be a complex programmable logic device (CPLD), a field-programmable gate array (FPGA), a generic array logic (GAL), or any combination thereof. The processor 310 can also be implemented by a logic device with built-in processing logic, such as an FPGA or a digital signal processor (DSP). The communication interface 320 can be a wired interface or a wireless interface, and is configured to communicate with other modules or devices. The wired interface can be an Ethernet interface, a local interconnect network (LIN), or the like. The wireless interface can be a cellular network interface or a wireless local area network interface, or the like.

[0055] The memory 330 can be a non-volatile memory, for example, a read-only memory (ROM), a programmable ROM (PROM), an erasable PROM (EPROM), an electrically EPROM (EEPROM), or a flash memory. The memory 330 can also be a volatile memory, which can be a random access memory (RAM) used as an external cache. By way of example, and not limitation, many forms of RAM can be used, for example, a static RAM (SRAM), a dynamic RAM (DRAM), a synchronous DRAM (SDRAM), a double data rate SDRAM (DDR SDRAM), an enhanced SDRAM (ESDRAM), a synchlink DRAM (SLDRAM), and a direct rambus RAM (DR RAM). The memory 330 can also be used for storing programs codes and data to facilitate the processor 310 to invoke the program codes stored in the memory 330 to execute a portion or all of the procedures of the above method embodiments, or to execute the related functions of the above device embodiments. Moreover, the computing device 300 can contain more or less components, or have different configurations of components, than those shown in the drawings. Figure 3 More or less components can be used, or different configurations of components can be used.

[0056] The bus 340 can be a peripheral component interconnect express (PCIe) bus, or an extended industry standard architecture (EISA) bus, a unified bus (Ubus or UB), a compute express link (CXL), a cache coherent interconnect for accelerators (CCIX), etc. The bus 340 can be divided into an address bus, a data bus, a control bus, etc. In addition to including a data bus, the bus 340 can also include a power bus, a control bus, a status signal bus, etc. However, for the sake of clarity,Figure 3 Only one bus or bus type is used in the figure, but it is understood that the computer system 100 can use more buses or bus types.

[0057] The method and device provided by the embodiments of the present application are based on the same inventive concept, and the embodiments, implementation manners, examples or implementation modes of the method and device are similar in principle for solving problems, and thus the embodiments, implementation manners, examples or implementation modes of the method and device can be referred to each other, and the repeated parts will not be described herein. The embodiments of the present application further provide a system, which includes a plurality of computing devices, and the structure of each computing device can refer to the structure of the computing device described above. The functions or operations that can be implemented by the system can refer to the specific implementation steps in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0058] The embodiments of the present application further provide a computer readable storage medium, which stores computer instructions, and when the computer instructions run on a computer device (such as one or more processors), the method steps in the above method embodiments can be implemented. The specific implementation of the processor of the computer readable storage medium in executing the above method steps can refer to the specific operations described in the above method embodiments and / or the specific functions described in the above device embodiments, and will not be described herein.

[0059] Those skilled in the art will appreciate that embodiments of the present application can be readily used as a method, apparatus, or computer program product. Embodiments of the present application can be implemented in hardware, software, firmware, or any combination thereof. Embodiments of the present application can be implemented in software and / or firmware to operate on a computer or other programmable processing device, which can be a general purpose computer, a special purpose computer, a computer network, or other programmable processing device to produce a machine, such that the computer program product, when loaded and / or executed on the computer or other programmable processing device, can implement processes or functions described herein. Such computer program product can be a computer- readable storage medium having computer readable program code embodied therein, which causes a computer to function in a particular manner, such that the computer

[0060] The computer program instructions can also be loaded onto a computer, other programmable processing device, or network device to cause a series of operations to be performed on the computer, other programmable processing device, or network device to produce a computer implemented process such that the instructions which execute on the computer or other programmable processing device implement the functions / acts specified in the flowchart and / or block diagram block or blocks. Figure 1 The flowchart and / or block diagram in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each flowchart and / or block diagram can represent a method, module, and / or portion of code which comprises one or more executable instructions implemented in computer readable program code to be executed by a processor system, such as a general purpose computer, special purpose computer, embedded processor, or Figure 1 The flowchart and / or block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of systems, methods and computer program products according to various embodiments of the present application. In this regard, each flowchart and / or block diagram can represent a method, module, and / or portion of code which comprises one or more executable instructions implemented in computer readable program code to be executed by a processor system, such as a general purpose computer, special purpose computer, embedded processor, or Figure 1one or more processes and / or functions specified in the flow block or blocks Figure 1 These computer program instructions can also be loaded into computer or other programmable data processing devices, so that a series of operation steps are performed on the computer or other programmable data processing devices to generate computer-implemented processes, thus the instructions executed on the computer or other programmable data processing devices provide a process for implementing the function specified in the flow block or blocks. Figure 1 one or more processes and / or functions specified in the flow block or blocks Figure 1 one or more processes and / or functions specified in the flow block or blocks

[0061] In the above embodiments, the description of each embodiment has its own focus, and the parts not described in detail in a certain embodiment can be referred to the related description of other embodiments. Obviously, those skilled in the art can make various modifications and variations to the embodiments of the present application without departing from the spirit and scope of the embodiments of the present application. The steps in the method of the embodiments of the present application can be adjusted, combined or deleted according to actual needs; the modules in the system of the embodiments of the present application can be divided, combined or deleted according to actual needs. If these modifications and variations of the embodiments of the present application belong to the scope of the claims of the present application and the equivalent technologies thereof, the present application also intends to include these modifications and variations.

Claims

1. A register-based interface signal control method, characterized by, The interface signal control method comprises: determining interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements comprise at least one interface signal and at least one logic mode included in an interface logic mode associated with the at least one interface signal, the at least one working mode is variable, and the at least one logic mode does not change with the change of the at least one working mode; generating register code based on the interface signal requirements, wherein the register code comprises control logic, the control logic is generated by extracting the at least one logic mode from the interface signal requirements and then using a control logic template, the control logic template is preset based on a plurality of logic modes, the at least one logic mode is selected from the plurality of logic modes, and the control logic does not change with the change of the at least one working mode; generating interface top-level code based on the interface signal requirements, and generating a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code, and when the at least one interface signal changes with the change of the at least one working mode, the first connection relationship changes with the change of the at least one working mode; controlling the at least one interface signal according to the interface logic mode by using the at least one register.

2. The interface signal control method according to claim 1, characterized by, The control logic is register readable and controllable.

3. The interface signal control method according to claim 1, wherein The change of the at least one working mode is achieved by changing the register value of the at least one register to change the configuration of the at least one interface signal.

4. The interface signal control method according to claim 1, characterized by, The interface top-level code comprises register connection attributes, register types, register names and register default values of the at least one module.

5. The interface signal control method according to claim 4, wherein Generating the interface top-level code based on the interface signal requirements comprises generating register output signals for connecting the at least one module based on the register connection attributes, register types, register names and register default values of the at least one module.

6. The interface signal control method according to claim 1, wherein The plurality of logic modes comprise readable logic mode, rewrite logic mode, readable and rewrite combined logic mode, and no processing logic mode.

7. The interface signal control method according to claim 1, wherein An interface signal table records the interface signal requirements in a preset specification format, and the interface signal requirements are determined by parsing the interface signal table, the preset specification format comprises a table file format and a table entry definition.

8. The interface signal control method according to claim 7, wherein The register code is generated by parsing a register table, and the register table is obtained by converting the interface signal table by using an automated script.

9. The interface signal control method according to claim 7, wherein The preset specification format can be adjusted by an automated script, and the table entry definition comprises a register name entry or a fixed signal prefix and suffix entry.

10. The interface signal control method of claim 1, wherein The interface signal requirements comprise input signal requirements and output signal requirements.

11. The interface signal control method according to claim 1, wherein The interface signal requirements further comprise signal names, input and output, control modes, control enables, data bit widths, register names, register initial values and register addresses.

12. The interface signal control method according to claim 1, wherein The first connection relationship between the at least one interface signal and the control logic is generated by a value assignment statement.

13. A computer device, comprising: The computer device comprises a memory, a processor, and a computer program stored in the memory and executable on the processor, and the processor implements the method according to any one of claims 1 to 12 when executing the computer program.

14. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer instructions, which, when executed on a computer device, cause the computer device to execute the method according to any one of claims 1 to 12.

15. A register-based interface signal control system, characterized by, The interface signal control system comprises: An input module configured to input an interface signal table; An extraction module configured to parse the interface signal table to determine interface signal requirements of at least one module in at least one working mode, wherein the interface signal requirements comprise at least one interface signal and at least one logic mode included in interface logic mode associated with the at least one interface signal, the at least one working mode is variable, and the at least one logic mode does not change with the change of the at least one working mode; A processing module configured to generate register code based on the interface signal requirements, wherein the register code comprises control logic, the control logic is generated by using a control logic template after extracting the at least one logic mode from the interface signal requirements, the control logic template is pre-set based on a plurality of logic modes, the at least one logic mode is selected from the plurality of logic modes, and the control logic does not change with the change of the at least one working mode; The processing module is further configured to generate interface top-level code based on the interface signal requirements, and generate a first connection relationship between the at least one interface signal and the control logic and a second connection relationship between at least one register and the control logic, wherein the at least one register is instantiated based on the register code, and the first connection relationship changes with the change of the at least one working mode when the at least one interface signal changes with the change of the at least one working mode; An output module configured to output the register code, the interface top-level code, the first connection relationship, and the second connection relationship, wherein the at least one register is configured to control the at least one interface signal according to the interface logic mode.

Images