Chip layout processing method, device, equipment, computer storage medium and program product

Abstract

The application discloses a chip layout processing method, device, equipment, computer storage medium and program product. The chip layout processing method comprises the following steps: acquiring a chip layout; performing division processing on the chip layout according to a preset division rule to obtain a plurality of division region graphs, wherein the preset division rule is used to make the graph in each division region graph not in conflict with any graph in adjacent division region graphs; coloring each graph in each division region graph according to a graph coloring algorithm to obtain a colored region graph; acquiring a graph feature of each graph, adjusting the coloring of each colored region graph according to the graph feature of each graph to obtain a plurality of target colored region graphs; and performing splitting processing on the graphs with different colors in each target colored region graph to obtain a chip splitting graph. The method can uniformly split the graphs involved in the chip layout.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of chips, and particularly relates to a chip layout processing method and device, equipment, a computer storage medium and a program product. BACKGROUND

[0002] With the development of technology, the complexity of modern semiconductor integrated circuit (IC) design has significantly increased. Integrated circuits need to implement complex functions in a very small area, resulting in more and more parameters and factors to be considered in the design process.

[0003] Traditional photolithography technology relies on a single exposure to form a circuit pattern, but as the size of integrated circuits continues to shrink, the resolution (i.e., the smallest manufacturable feature size) that can be achieved by a single exposure is facing limitations. Double patterning technology (DPT) bypasses the limitation of optical resolution by splitting a complex pattern into multiple sub-patterns, each of which is exposed using an independent mask. As the demand for high-precision manufacturing processes continues to increase, how to effectively split the layout becomes a key to improving overall production efficiency and reducing defect rates. SUMMARY

[0004] Embodiments of the application provide a chip layout processing method, device, equipment, computer storage medium and program product, which can uniformly split the graphics involved in the chip layout.

[0005] In a first aspect, embodiments of the application provide a chip layout processing method, which comprises:

[0006] Obtaining a chip layout, the chip layout comprising a plurality of graphics;

[0007] Performing division processing on the chip layout according to a preset division rule to obtain a plurality of division region graphics, the preset division rule being used to make the graphics in each division region graphic not have a conflict relationship with any graphic in an adjacent division region graphic;

[0008] According to a graphic coloring algorithm, coloring each graphic in each division region graphic to obtain a colored region graphic, the graphic coloring algorithm being used to make the coloring colors of the graphics having a conflict relationship in each division region graphic different;

[0009] Obtaining a graphic feature of each graphic;

[0010] According to the graphic feature of each graphic, adjusting the coloring of each colored region graphic to obtain a plurality of target colored region graphics, so that the ratio of the coloring areas of the graphics having different coloring colors in all target colored region graphics satisfies an area ratio condition;

[0011] The figures with different colors in the target colored region map are respectively split into different chip split maps.

[0012] In a second aspect, an embodiment of the present application provides a chip layout processing device, the device comprising:

[0013] The acquisition module is configured to acquire the chip layout, wherein the chip layout comprises a plurality of figures.

[0014] The division module is configured to perform division processing on the chip layout according to a preset division rule to obtain a plurality of division region maps, wherein the preset division rule is configured to make the figures in each division region map not have a conflict relationship with any figure in an adjacent division region map.

[0015] The coloring module is configured to color each figure in each division region map according to a figure coloring algorithm to obtain a colored region map, wherein the figure coloring algorithm is configured to make the coloring of the figures having a conflict relationship in each division region map different.

[0016] The acquisition module is further configured to acquire the figure features of each figure.

[0017] The adjustment module is configured to adjust the coloring of each colored region map according to the figure features of each figure to obtain a plurality of target colored region maps, so that the area ratio of the figures with different coloring in all target colored region maps satisfies an area ratio condition.

[0018] The split module is configured to respectively split the figures with different colors in the target colored region map into different chip split maps.

[0019] In a third aspect, an embodiment of the present application provides a chip layout processing device, the device comprising a processor and a memory storing computer program instructions; and the processor executes the computer program instructions to implement the chip layout processing method described above.

[0020] In a fourth aspect, an embodiment of the present application provides a computer readable storage medium, the computer readable storage medium storing computer program instructions, and the computer program instructions are executed by a processor to implement the chip layout processing method described above.

[0021] In a fifth aspect, an embodiment of the present application provides a computer program product, and instructions in the computer program product are executed by a processor of an electronic device to make the electronic device execute the chip layout processing method described above.

[0022] In this embodiment, by acquiring the chip layout and dividing it using preset partitioning rules, the graphics in the divided areas are free from conflict, avoiding image overlap or excessively close image distances. A coloring algorithm is used to color the graphics, ensuring that conflicting graphics have different colors, effectively distinguishing different graphics. Graphics of the same color are assigned to the same layer in subsequent operations, facilitating simultaneous splitting of different areas and reducing interference between adjacent areas. Acquiring graphic features helps analyze the distribution of each graphic in the layout. The coloring results are optimized based on these features, enabling more even processing of different areas during splitting and ensuring uniform color distribution of the split graphics. Finally, graphics of different colors are actually split in the colored area map, ensuring a uniform distribution of graphics in the final chip split map. Attached Figure Description

[0023] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0024] Figure 1 This is a schematic flowchart of the chip layout processing method provided in the embodiments of this application;

[0025] Figure 2 This is a dyeing effect diagram corresponding to dyeing based on the initial dyeing priority, provided in the embodiments of this application;

[0026] Figure 3 This is a dyeing effect diagram corresponding to dyeing according to the target dyeing priority provided in the embodiments of this application;

[0027] Figure 4 This is a schematic diagram of layout provided in an embodiment of this application;

[0028] Figure 5 This is a schematic diagram of the chip layout processing apparatus provided in the embodiments of this application;

[0029] Figure 6 This is a schematic diagram of the hardware structure of the chip layout processing device provided in the embodiments of this application. Detailed Implementation

[0030] The features and exemplary embodiments of the various aspects of the present application will be described in detail below with reference to the figures. To make the present application more clear and more comprehensive, the present application will be further described in detail below with reference to the figures and specific embodiments. It should be understood that the specific embodiments described herein are only intended to explain the present application, but not to limit the present application. The present application can be implemented without some of the specific details for those skilled in the art. The following description of the embodiments is only intended to provide a better understanding of the present application by showing examples of the present application.

[0031] It should be noted that, in this paper, the relationship terms such as first and second are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between the entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or equipment including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or equipment. Without more limitations, the elements defined by the statement "include" do not exclude the presence of other identical elements in the process, method, article or equipment including the elements.

[0032] Semiconductor layout design involves arranging circuit elements on a chip. In order to optimize chip performance and manufacturing cost, it is often necessary to split the design into multiple regions for processing. Such splitting must be uniform to balance the wiring needs, logic complexity and manufacturing difficulty of each part.

[0033] The prior art mainly calculates the density of the graph when splitting, and balances the density between different regions by exchanging part of the graph. For example, part of the graph in the dense area of P1 is exchanged to the relatively sparse area of P2.

[0034] Although the application of the prior art in the double graph technique solves the problem of uneven density of the graph to some extent, it is easy to ignore the uneven density of some key areas due to its dependence on the calculation and optimization of local density, thereby affecting the quality of lithography. In addition, this method may fall into a local optimal solution when facing complex graphs, so it cannot achieve global optimization. This local optimization strategy may result in significant density differences in the global range, thereby reducing the accuracy and consistency of the final graph.

[0035] In addition, the existing technology has limited calculation accuracy on the local optimization algorithm, especially when dealing with some extremely dense or sparse areas, which may not effectively capture and correct potential lithography errors. This lack of accuracy will directly affect the yield of the final manufacturing, resulting in a higher defect rate.

[0036] To solve the problems in the prior art, embodiments of the present application provide a chip layout processing method, device, equipment, computer storage medium and computer program product. First, the chip layout processing method provided by the embodiments of the present application is introduced.

[0037] Figure 1 The flowchart of the chip layout processing method provided by an embodiment of the present application is shown. As shown in Figure 1 Figure 1 The following steps S101-S106 are included.

[0038] S101, acquiring a chip layout.

[0039] The chip layout includes a plurality of patterns.

[0040] The chip layout is a representation of circuit design, usually including patterns corresponding to a plurality of circuit elements (such as resistors, capacitors, transistors, etc.), used to show the structure and circuit connection inside the chip.

[0041] As an example but not limited, suppose there are a plurality of rectangular regions (which can also be other arbitrary shapes of patterns that can represent circuit elements) on the chip layout, representing different circuit elements, such as a part representing logic gates and another part representing power lines. It can be understood that the specific patterns corresponding to different types of chip layout are not the same, and the patterns in the specific chip layout can be determined according to the actual situation.

[0042] S102, performing division processing on the chip layout according to a preset division rule to obtain a plurality of division region patterns.

[0043] The preset division rule is used to make the patterns in each division region pattern have no conflict relationship with any pattern in the adjacent division region pattern.

[0044] The conflict relationship can be understood as the distance between the patterns being too close or the patterns overlapping.

[0045] As an example but not limited, suppose the partial regions of two patterns overlap, then it is considered that the two rectangular patterns have a conflict relationship.

[0046] Correspondingly, the preset division rule can be understood as re-planning the layout in the chip according to some set rules, so that the patterns in the chip layout have no phenomenon of too close distance or overlap.​

[0047] As an example but not limitation, the preset division rule can be to traverse the distance between the patterns, and divide the patterns without conflict relationship into adjacent regions. For example, assuming that two patterns A and B do not have conflict relationship, then the A pattern is divided into a first region, and the B pattern is divided into a second region, the first region and the second region are adjacent, thereby obtaining a plurality of division region maps.

[0048] As an example but not limitation, the preset division rule can be to divide the regions by using geometric segmentation (such as grid segmentation), and the regions can be divided by adjusting the size of the grid, so that the patterns in adjacent grids (which can be considered as adjacent regions) do not have conflict relationship.

[0049] As an example but not limitation, the preset division rule can be to divide by using density segmentation, for example, according to the pattern density, and the regions can be divided by adjusting the pattern density in each region, and the patterns in the region with high density are adjusted to other regions with low density, so that the patterns in adjacent regions after division do not have conflict relationship.

[0050] As an example but not limitation, the preset division rule can be to divide by using logical segmentation, for example, according to the circuit function, and the patterns implementing the same circuit function are divided into the same region, while also considering the conflict relationship of the patterns in the region, so that the patterns in adjacent regions after division do not have conflict relationship.

[0051] It can be understood that the preset division rule is used to divide the chip layout, so that the patterns in adjacent regions after division do not have conflict relationship, which can avoid the problems of image overlap or too close distance, and is beneficial to avoid the image connection phenomenon in the subsequent exposure process.

[0052] S103, color each pattern in each division region map according to a graph coloring algorithm, to obtain a colored region map.

[0053] The graph coloring algorithm is used to color two adjacent patterns in each division region map differently.

[0054] The graph coloring algorithm is an algorithm for solving graph theory problems, especially a strategy for coloring the vertices or edges of a graph to meet certain conditions. The goal of the algorithm is to color the vertices of the graph with the least number of colors, so that the vertices with conflict relationship do not use the same color.

[0055] Suppose there is a graph, the vertices of the graph represent objects that need to be colored, and the edges between points represent the conflict or mutual exclusive relationship between these objects (i.e. adjacent objects cannot have the same color). For example, there are vertices A, B, C; edges: A is adjacent to B, B is adjacent to C.

[0056] Starting from the uncolored vertex A, color A with color 1. Next, look at B adjacent to A, since the color of A is 1, B cannot use color 1, so color B with color 2; then look at C, C is adjacent to B, so C cannot use color 2, can be colored with color 1.

[0057] The final coloring result can be: A: color 1. B: color 2. C: color 1.

[0058] In combination with multiple partition region graphs, suppose there are two circuit elements forming an "L" shape, one can be colored red and the other blue, and so on, traverse all partition region graphs to get a coloring region graph, which will ensure that the regions at the edge of the region do not use the same color.

[0059] Color the graph by the graph coloring algorithm, so as to ensure that the graphs with conflict relationship have different colors, which can effectively distinguish different graphs. Graphs of the same color will be allocated to the same layer in subsequent operations, thereby facilitating the simultaneous splitting of different regions, reducing the interference of adjacent regions, and facilitating the implementation of uniform splitting.

[0060] S104, obtain the graph feature of each graph.

[0061] The graph feature can be understood as a parameter that describes the properties of the graph itself (such as shape, area occupied, etc.). By using the graph feature, the graph status on the layer can be understood, so as to determine whether the graphs included in any two layers are uniformly distributed according to the graph status.

[0062] The graph feature includes at least one of the following: graph projection overlap length and graph area.

[0063] The graph area can be calculated according to the shape and size of different graphs, for example, the area of a rectangular graph can be calculated after knowing the side length, and the specific calculation method can refer to the relevant mathematical principles, which will not be repeated here.

[0064] The graph projection overlap length refers to the length of the overlapping part of the projection of two or more graphs in a certain direction (usually the x-axis or y-axis in a two-dimensional space). In other words, when two graphs have overlapping projections in the same direction, the length of the overlapping part is the part that overlaps in this direction.

[0065] The specific area data and the projection overlap length data can be calculated according to actual conditions, which are not listed one by one here.

[0066] In addition, other features of the pattern that can be used to determine whether the patterns included in any two layers are evenly distributed can also be included, which are not listed one by one here.

[0067] It can be understood that the pattern features are beneficial to analyze the relative position and the occupied area of each pattern in the layout, thereby providing a basis for determining how to evenly split.

[0068] S105, adjusting the dyeing of each dyeing area map according to the pattern features of each pattern, to obtain a plurality of target dyeing area maps, so that the ratio of the dyeing areas of the patterns with different dyeing colors in all target dyeing area maps meets the area ratio condition.

[0069] The purpose of this step is to dynamically adjust the dyeing result by analyzing and comparing the pattern features to meet the division area requirement or optimize the overall design.

[0070] The area ratio condition refers to a condition that can reflect whether the size of the dyeing area corresponding to the patterns with different dyeing colors meets the corresponding proportion range.

[0071] As an example but not limitation, the area of the dyed pattern can be directly calculated to determine whether the areas corresponding to the patterns with different colors meet the corresponding proportion range.

[0072] As an example but not limitation, the size of the dyeing area of the pattern can also be indirectly determined by calculating other features of the pattern to determine whether the areas corresponding to the patterns with different colors meet the corresponding proportion range, for example, the proportion range of the area of the pattern can be indirectly reflected by calculating the projection overlap length of the pattern.

[0073] For example, by calculating the areas of the blue region and the red region, the calculation result is that the area of the blue region is too small and the area of the red region is too large, then a part of the color of the red region can be adjusted to blue, so that the areas of the regions corresponding to the two colors are evenly distributed. It can be understood that the even distribution can be 1:1 distribution, or 1.1:1 distribution, etc., and the specific proportion can be adjusted according to different process requirements, which is not limited here.

[0074] For another example, the dyeing result can be adjusted by calculating the pattern projection overlap length of a plurality of patterns. Assuming that the pattern projection overlap length between any two patterns is found to exceed the preset range (which can be customized), it can be considered that the dyeing between the two patterns is in conflict, so that the colors of the two patterns are changed to be different from the previous dyeing.

[0075] By traversing the graphic area and / or the graphic projection overlap length on all the colored region maps, whether there is a region with a too large difference in colored area or a region with a graphic projection overlap length not meeting the preset range is found, so as to further adjust the coloring color of the region, and finally obtain the target colored region map.

[0076] According to the characteristics of the graphics, the colored region map is updated to reflect a more reasonable region allocation. This step can ensure that the coloring result is properly adjusted in consideration of the characteristics of the graphics, so that different regions can be more evenly processed when splitting, and the uniformity of the characteristics after splitting is ensured.

[0077] S106, respectively split the graphics with different colors in the target colored region map to different chip split maps.

[0078] As an example but not limitation, the colored area of the graphics in the chip split map meets the preset area condition.

[0079] The preset area condition can be calculated according to the area of all graphics and the number of chip split maps. For example, the graphic area of all graphics is 4, and two chip split maps are needed, then the preset area condition is 4 divided by 2, that is, 2. The specific data can be set according to the actual situation, which will not be listed one by one here.

[0080] This step means that graphics with different colors are split onto different mask layers, which can also be understood as the colors of the graphics on the same mask layer are consistent, and there is no conflict relationship between the graphics.

[0081] Here, color threshold or color range can be used to identify different color regions. For example, to identify the red region, the RGB range of red can be set. Traverse the image pixels, if the color of the pixel is in the red range, mark it as graphic 1, if it is in the blue range, mark it as graphic 2. Create two new maps, extract all red graphics to a new Figure 1 map, and extract all blue graphics to another new Figure 2 At the same time, the area of the split red graphics and the area of the blue graphics meet the preset area condition.

[0082] Finally, the graphics with different colors in the colored region map are actually split to ensure that the graphic area of the finally formed chip split map meets the preset area condition.

[0083] By acquiring the chip layout, the chip layout is divided by using preset division rules, so that the graphics in the divided area do not have conflict relations, which can avoid the problems of image overlap or too close distance. By coloring the graphics by using the graph coloring algorithm, it is ensured that the graphics with conflict relations have different colors, so that different graphics can be effectively distinguished. Graphics with the same color will be allocated to the same layer in subsequent operations, thereby facilitating the simultaneous splitting of different areas and reducing the interference of adjacent areas. By acquiring the graphic features, it is beneficial to analyze the relative position and occupied area of each graphic in the layout. According to the graphic features, the coloring result is optimized and adjusted, so that different areas can be more evenly processed during splitting, and the uniformity of the graphic color after splitting is ensured. Finally, the graphics with different colors in the colored area graph are actually split to ensure that the graphics of the finally formed chip split graph are uniformly distributed.

[0084] In an implementation manner, the graphic features include at least one of the following: graphic projection overlap length and graphic area; the coloring of the coloring area graphs is adjusted according to the graphic features of each graphic to obtain a plurality of target coloring area graphs, including: obtaining the coloring priority of each graphic in each division area graph to obtain an initial coloring priority, the coloring priority is used to determine the coloring color corresponding to each graphic, wherein the coloring colors corresponding to the graphics with different coloring priorities are different; the initial coloring priority is adjusted according to the graphic area corresponding to each graphic until the ratio of the coloring areas corresponding to the graphics with different coloring colors meets the area ratio condition to obtain a target coloring priority; or, the initial coloring priority is adjusted according to the graphic projection overlap length until the projection overlap length corresponding to the graphics with different coloring colors meets the preset projection overlap length to obtain a target coloring priority; the coloring of the coloring area graphs is adjusted according to the target coloring priority to obtain a plurality of target coloring area graphs.

[0085] It can be understood that an initial coloring priority can be assigned to each graphic according to the user's custom settings.

[0086] This can be evaluated based on the characteristics, size, shape, position, etc. of the graphics, such as area, perimeter, shape complexity, etc. The initial coloring priority is set according to these attributes, for example: the larger the area, the higher the priority.

[0087] As an example but not limitation, assuming there are three graphics A, B and C with areas of 100, 50 and 150 respectively, the initial coloring priority can be A:1, B:2, C:1 (assuming that the smaller the priority, the higher the priority).

[0088] The priority is adjusted in combination with the graphic features (graphic area and / or graphic projection overlapping length) in the foregoing. For example, if the dyeing areas of certain graphics differ too much, causing color conflicts, the dyeing priorities of these graphics are adjusted. The graphics are updated by dyeing according to the adjusted target dyeing priorities, ensuring that the final color distribution is uniform.

[0089] By way of example but not limitation, assume that the initial dyeing priority of graphic A is 1, the corresponding dyeing color is red, the dyeing priority of graphic B is 2, and the corresponding dyeing color is blue, and the initial dyeing priority of graphic C is 1, and the corresponding dyeing color is red. By calculating the areas of the three graphics, it is found that the area of the red region (250) is much larger than the area of the blue region (50). At this time, the dyeing priority of graphic A can be adjusted to 2 (i.e., the target dyeing priority), so that the corresponding dyeing color of graphic A is adjusted to blue. The adjusted area of the red region is 150, and the area of the blue region is also 150, so that the final color distribution is uniform.

[0090] By way of example but not limitation, assume that the initial dyeing priority of graphic A is 1, the corresponding dyeing color is red, the dyeing priority of graphic B is 2, and the corresponding dyeing color is blue, and the initial dyeing priority of graphic C is 1, and the corresponding dyeing color is red. By calculating the areas of the three graphics, it is found that the area of the red region (250) is much larger than the area of the blue region (50). At this time, the dyeing priority of graphic A can be adjusted to 2 (i.e., the target dyeing priority), so that the corresponding dyeing color of graphic A is adjusted to blue. The adjusted area of the red region is 150, and the area of the blue region is also 150, so that the final color distribution is uniform.

[0091] The specific adjustment method can be selected according to actual conditions, which is not limited here.

[0092] The following will be compared Figure 2 and Figure 3 to introduce the dyeing effects of different dyeing priorities.

[0093] Figure 2 is the dyeing effect diagram corresponding to dyeing according to the initial dyeing priority provided by the embodiment of the present application.

[0094] As shown in Figure 2 , there is a problem in the dyeing effect after dyeing according to the initial dyeing priority, that is, the area of the pink region and the area of the purple region differ too much.

[0095] Figure 3 is the dyeing effect diagram corresponding to dyeing according to the target dyeing priority provided by the embodiment of the present application.

[0096] As shown in Figure 3 , the dyeing priority of the pink region in the first row in Figure 2 is adjusted, so that the dyeing color of the region becomes purple.

[0097] is the dyeing effect diagram corresponding to dyeing according to the target dyeing priority provided by the embodiment of the present application. Figure 2The purple area in the first row of the figure is adjusted in color priority, so that the color of the area becomes pink. After the adjustment, the pink area and the purple area correspond to the basic uniform distribution of the coloring area.

[0098] It can be understood that the priority adjustment here is to adjust the color of the coloring area again after coloring according to the initial coloring priority by checking whether the coloring area is uniform and whether the coloring area projection overlap length meets the preset range, so as to avoid color conflict in some areas after coloring, so that the final color distribution is uniform.

[0099] In an implementation, after coloring the plurality of graphs in the plurality of divided region graphs according to the graph coloring algorithm to obtain the coloring region graph, the method further includes: determining the edge weight of each edge corresponding to the plurality of divided region graphs, the edge weight being in a positive correlation with the nearest distance from the edge of a graph in a divided region graph to the edge of a graph in an adjacent divided region graph; and obtaining the edge weight order of each edge corresponding to the plurality of divided region graphs, the edge weight order being used to represent the size order of the edge weight of each edge of each divided region graph.

[0100] The edge weight refers to the value on the edge connecting two nodes (vertices), which is usually used to represent the distance between the two points.

[0101] By way of example and not limitation, the edge weight can be determined based on a plurality of factors, such as the area of the region, the shape complexity, the position, and the adjacent relationship with other regions, etc.

[0102] For example, the edge weight is in a correlation with the distance between each divided region graph and an adjacent divided region graph, the closer the distance between two divided region graphs, the higher (or lower) weight is given to the edge formed by the two divided region graphs.

[0103] By way of example and not limitation, it is assumed that the edge weights of the region graphs A, B, C, and D are respectively:

[0104] A: 3; B: 1; C: 4; D: 2;

[0105] The edge weight order can be B (1) < D (2) < A (3) < C (4).

[0106] It can be understood that the edge weight is used to determine the relative importance of each region map, so that the processing can be performed in a specific order when processing adjacent regions. It is judged whether the ratio between the areas corresponding to the patterns with different coloring colors in the two adjacent divided region maps meets the area ratio condition; when the ratio between the areas corresponding to the patterns with different coloring colors in the two adjacent divided region maps does not meet the area ratio condition, the coloring color corresponding to at least one of the two adjacent divided region maps is flipped to obtain a flipped divided region map; and the adjacent flipped divided region maps are sequentially merged in the order from small to large according to the edge weight order to obtain a merged divided region map.

[0107] The main goal of this step is to avoid color conflicts between adjacent regions (which can also be understood as avoiding uneven coloring areas of adjacent regions) by re-optimizing the coloring result after the coloring region map is completed.

[0108] According to the edge weight order in the region map, adjacent regions are gradually merged from the smallest edge. When merging, the two region maps are flipped as a whole. The purpose of flipping is to make the area proportion of the polygons allocated to the two masks (i.e., the chip splitting map mentioned above) close.

[0109] It can be understood that the main purpose of flipping is to make the area proportions of the patterns with different coloring colors in the two adjacent divided region maps closer. When flipping, one of the two divided region maps can be selected for flipping, or both of the two divided region maps can be selected for flipping. The specific flipping pattern can be determined according to actual conditions, which is not limited here.

[0110] That is, if it is found that the areas of the patterns split into two masks differ too much, the colors of the patterns can be flipped. For example, if the area of a red region is much larger than the area of a blue region, the color of the red region with an appropriate area can be changed to blue, so that the areas corresponding to the two colors are basically equal.

[0111] In one implementation, the above method further includes: performing a global consistency check on the merged divided region map to determine whether there is a pattern conflict region; and in the case where there is a pattern conflict region, processing the pattern conflict region by using a preset global optimization algorithm to correct the color corresponding to the pattern conflict region.

[0112] This step can ensure that the color of the merged divided region map is uniform as a whole and there is no region with coloring conflict. Even after the local optimization or flipping processing, there can still be hidden conflicts (for example, due to complex region shapes). This check can identify and further process the conflicts.

[0113] The preset global optimization algorithm can include an integer linear programming algorithm, a heuristic optimization algorithm, etc. The specific algorithm principle can be referred to related technical principles, which will not be described here.

[0114] Suppose that after the global consistency check of the merged division region map, it is found that there are conflicting regions in the merged map, such as region X (red) and region Y (red) are adjacent, but region Z (blue) is very close. By using the global optimization algorithm, the above regions can be adjusted, for example, the color of region Z is adjusted from blue to red.

[0115] It can be understood that the specific color adjustment can be determined according to the actual situation. The dyeing method in the above can make the dyeing color of the corresponding local region uniformly distributed, but the whole after merging may exist conflict, after using the preset global optimization algorithm for optimization, the existing local conflict can be resolved, and the dyeing result of the whole is more uniform.

[0116] It can also be understood that after all the regions are merged, a global consistency check is performed on the entire layout to ensure that there is no graphic conflict. If there are still a small amount of conflicts or other design rule problems, a global optimization algorithm (such as integer linear programming or heuristic optimization) can be applied to further optimize the color allocation.

[0117] In one implementation, the chip layout is divided according to a preset division rule to obtain a plurality of division region maps, including: obtaining the distance between any two adjacent graphics in the chip layout; comparing the distance between any two adjacent graphics with a preset distance, and in the case that the distance between any two adjacent graphics is less than the preset distance, it is determined that the two graphics have a conflict relationship; the two graphics with a conflict relationship are divided into different regions to obtain a plurality of division region maps.

[0118] It can be understood that in the chip layout, each design element (such as resistance, capacitance, wire, etc.) can be regarded as a graphic. By calculating the distance between these graphics, the spatial relationship between them can be evaluated.

[0119] For example, the shortest distance between each graphic is calculated using a geometric distance formula (such as Euclidean distance).

[0120] It can be understood that the minimum safe distance between graphics is usually specified to ensure reliability and effectiveness in the manufacturing process. For example, a certain safety distance needs to be maintained between circuit elements to prevent short circuits or signal interference. For each pair of graphics A and B, check the actual distance D between them, and if D is less than the preset distance T, it is considered that they have a conflict.

[0121] If the distance between the two is detected to be less than the preset distance, it means that they are designed to be non-compliant and can cause manufacturing or performance problems. In this case, these patterns need to be considered as conflicting patterns.

[0122] By identifying the conflicting relationship between patterns, designers can actively avoid potential problems during the design process, ensuring good circuit performance and higher manufacturing quality. Dividing different conflicting patterns into different regions can help better adjust and optimize in subsequent processing (such as layout optimization) and avoid interference with each other.

[0123] Suppose in a chip design layout, there are several patterns (A, B, C, D) and the distances between them are as follows: the distance between pattern A and pattern B is 3 units; the distance between pattern A and pattern C is 5 units; the distance between pattern B and pattern C is 2 units; the distance between pattern D and other patterns is greater than the preset distance of 5 units; the preset distance T is 4 units.

[0124] It is detected that the distance between A and B (3 units) and the distance between B and C (2 units) are both less than 4 units.

[0125] Conflict relationship identification: A and B conflict; B and C conflict; the distance between A and C (5 units) does not touch the preset, so they do not conflict.

[0126] Divide the conflict region (A, B, C) into different regions. For example, A can be placed in region 1, B in region 2, and C in region 3. D can exist independently in other regions.

[0127] Through these steps, the pattern region with potential problems can be quickly identified to avoid potential problems, that is, to find and eliminate the conflict relationship in the early stage of the design phase, which can save subsequent modification work, reduce cost and risk. Early separation of conflicting patterns makes it easier to avoid problems and ensure logical reasonableness in subsequent layout optimization, color filling or other design adjustments. Ultimately, it improves the reliability of the circuit, reduces the failure rate, and makes it easier to meet the technical specifications in the manufacturing process.

[0128] In one implementation, a plurality of patterns with conflicting relationships are divided into different regions to obtain a plurality of divided region graphs, including: simplifying different regions to nodes to obtain a plurality of nodes; and connecting the plurality of nodes with edges to obtain a plurality of divided region graphs.

[0129] Simplifying different regions into nodes. The purpose of this step is to abstract the complex region representation into a few key nodes to simplify subsequent processing.

[0130] A node represents a set of figures in a region, which can be defined by location and attributes (such as color, type, etc.).

[0131] The following will be specifically explained in combination with Figure 4 .

[0132] Figure 4 is a layout division schematic diagram provided by an embodiment of the present application.

[0133] As Figure 4 shown, assume that there are n regions (region 1, region 2,..., region n), each containing different figures. After simplification, we can simplify these regions into nodes N1, N2,..., Nn respectively, where N1 represents all figure sets of region 1, N2 represents all figure sets of region 2,..., and Nn represents all figure sets of region n.

[0134] Edges are used to connect multiple nodes to represent the relationship between regions. For example, a node can be connected to its adjacent nodes (representing proximity or functional relationship) through an edge.

[0135] As an example but not limitation, assume that N1 and N2 are connected by edge E1.

[0136] The node graph after simplification can be used for fast calculation, optimization, etc. algorithms, saving processing time and improving processing efficiency.

[0137] In summary, before splitting, the layout is first divided into different regions according to the conflict relationship. The polygons between different regions do not have conflict relationship. First, color allocation is performed on each region using an algorithm, and all conflicts are solved. The whole layout is expanded.

[0138] When performing color allocation for each region, in order to achieve uniform area, not only the different priorities set by the user are considered, but also the projection overlap length and area factor between polygons with conflicts are used to correct the priority to obtain a more uniform region result.

[0139] The dyeing results on different regions are flipped according to the principle that the area ratio of the two masks is equal, to further optimize the result.

[0140] By the above method, the pattern conflict between the two mask layers can be effectively reduced. This reduces the short circuit, open circuit or other defects that may occur in the manufacturing process, thereby significantly improving the manufacturing yield. The pattern density on each mask layer is more uniform, which helps to balance the exposure energy distribution in the photolithography process and reduces pattern distortion and errors caused by uneven energy. This enables each mask layer to perform more stably in subsequent processes such as etching and polishing, thereby reducing the impact of process fluctuations and improving production consistency. Moreover, the method can reduce the need for manual correction due to rule conflicts based on better meeting design rules. This can speed up the design verification process and reduce the design cycle.

[0141] Based on the chip layout processing method provided in the above embodiments, the application also provides a specific implementation of a chip layout processing device. Please refer to the following embodiments.

[0142] Figure 5 is a structural schematic diagram of a chip layout processing device provided by an embodiment of the application.

[0143] First, referring to Figure 5 The chip layout processing device provided by the embodiment of the application includes the following modules:

[0144] The acquisition module 1001 is configured to acquire a chip layout, and the chip layout includes a plurality of patterns.

[0145] The division module 1002 is configured to perform division processing on the chip layout according to a preset division rule to obtain a plurality of division region patterns, and the preset division rule is used to make the patterns in each division region pattern not have a conflict relationship with any pattern in an adjacent division region pattern.

[0146] The coloring module 1003 is configured to color each pattern in each division region pattern according to a pattern coloring algorithm to obtain a colored region pattern, and the pattern coloring algorithm is used to make the coloring colors of the patterns having a conflict relationship different.

[0147] The acquisition module 1001 is further configured to acquire the pattern feature of each pattern.

[0148] The adjustment module 1004 is configured to adjust the coloring of each colored region pattern according to the pattern feature of each pattern to obtain a plurality of target colored region patterns, so that the ratio of the coloring areas of the patterns having different coloring colors in all target colored region patterns satisfies an area ratio condition.

[0149] The splitting module 1005 is configured to split the patterns having different coloring colors in each target colored region pattern to different chip split patterns.

[0150] As an implementation form of the present application, the graphic feature comprises at least one of the following: a graphic projection overlap length and a graphic area; the adjusting module 1004 is further configured to update each of the dyeing region graphs according to the graphic feature of each graphic, to obtain a plurality of target dyeing region graphs, comprising: obtaining a dyeing priority corresponding to each graphic in each of the divided region graphs, to obtain an initial dyeing priority, the dyeing priority being used to determine a dyeing color corresponding to each graphic, wherein the dyeing colors corresponding to graphics with different dyeing priorities are different; adjusting the initial dyeing priority according to the graphic area corresponding to each graphic, until the ratio between the dyeing areas corresponding to graphics with different dyeing colors satisfies an area ratio condition, to obtain a target dyeing priority; or, adjusting the initial dyeing priority according to the graphic projection overlap length, until the projection overlap lengths corresponding to graphics with different dyeing colors satisfy a preset projection overlap length, to obtain a target dyeing priority; adjusting each of the dyeing region graphs according to the target dyeing priority, to obtain a plurality of target dyeing region graphs.

[0151] It can be understood that the priority adjustment here is to adjust the color of the dyeing region again after dyeing according to the initial dyeing priority, by checking whether the graphic area after dyeing is uniform and whether the graphic projection overlap length after dyeing meets the preset range, to avoid color conflicts in some regions after dyeing, so that the final color distribution is uniform.

[0152] As an implementation form of the present application, the device can further comprise a flipping module, which is configured to, after dyeing the graphics in the plurality of divided region graphs according to the graph dyeing algorithm to obtain the dyeing region graphs, determine the edge weight of each edge corresponding to the plurality of divided region graphs, the edge weight being in a positive correlation with the nearest distance from the edge of a graphic in a divided region graph to the edge of a graphic in a neighboring divided region graph; obtain the edge weight order of each edge corresponding to the plurality of divided region graphs, the edge weight order being used to represent the size order of the edge weight of each edge of each divided region graph, the edge weight being in a correlation with the distance between each divided region graph and a neighboring divided region graph; determine whether the ratio between the dyeing areas corresponding to graphics with different dyeing colors in two neighboring divided region graphs satisfies an area ratio condition; when the ratio between the dyeing areas corresponding to graphics with different dyeing colors in two neighboring divided region graphs does not satisfy the area ratio condition, flip the dyeing color of at least one of the two neighboring divided region graphs to obtain a flipped divided region graph; and merge the neighboring flipped divided region graphs in the order from small to large according to the edge weight order, to obtain a merged divided region graph.

[0153] The main target of this step is to optimize the dyeing result again after the dyeing region graph is completed, to avoid color conflicts between adjacent regions (which can also be understood as avoiding uneven dyeing areas of the dyeing graphics in adjacent regions).

[0154] As an implementation form of the present application, the apparatus can further include an inspection module configured to perform global consistency inspection processing on the merged partition region map to determine whether there is a graphic conflict region, and perform processing on the graphic conflict region using a preset global optimization algorithm to correct the color corresponding to the graphic conflict region in the case where there is a graphic conflict region.

[0155] This step can ensure that the color of the merged partition region map is overall uniform and there is no region of dyeing conflict. Even after the local optimization or flipping processing, there can still be invisible conflicts (for example, due to complex region shape), and this inspection can identify and further process them.

[0156] As an implementation form of the present application, the partition module 1002 is further configured to perform partition processing on the chip layout according to a preset partition rule to obtain a plurality of partition region maps, including: obtaining the distance between any two adjacent graphics in the chip layout; comparing the distance between any two adjacent graphics with a preset distance, and determining that there is a conflict relationship between the two graphics in the case where the distance between any two adjacent graphics is less than the preset distance; and partitioning the two graphics with the conflict relationship into different regions to obtain a plurality of partition region maps.

[0157] By identifying the conflict relationship between graphics, the designer can actively avoid potential problems in the design process, ensuring good circuit performance and higher manufacturing quality. Partitioning different conflict graphics into different regions can help better adjust and optimize in subsequent processing (such as layout optimization) and avoid interference with each other.

[0158] As an implementation form of the present application, the apparatus can further include a simplification module configured to partition a plurality of graphics with conflict relationships into different regions to obtain a plurality of partition region maps, including: simplifying different regions to nodes to obtain a plurality of nodes; and connecting the plurality of nodes with edges to obtain a plurality of partition region maps.

[0159] Simplifying different regions to nodes. The purpose of this step is to abstract the complex region representation into a few key nodes to simplify subsequent processing.

[0160] Figure 6 FIG. 1 is a schematic diagram of a hardware structure of a chip layout processing device provided by an embodiment of the present application.

[0161] The chip layout processing device can include a processor 2001 and a memory 2002 having stored computer program instructions.

[0162] In particular, the processor 2001 can include a central processing unit (CPU), or an application-specific integrated circuit (ASIC), or can be configured to implement one or more integrated circuits that embody the embodiments of the present application.

[0163] The memory 2002 can include mass storage for data or instructions. As an example and not by way of limitation, the memory 2002 can include a hard disk drive (HDD), a floppy disk drive, flash memory, an optical disc (e.g., a compact disc (CD) or a digital versatile disc (DVD)), a tape drive, a USB drive, or a combination of two or more of these. The memory 2002 can include removable or non-removable (or fixed) media, where appropriate. The memory 2002 can be internal or external to the integrated gateway disaster recovery device, where appropriate. In particular embodiments, the memory 2002 is non-volatile, solid-state memory.

[0164] In particular embodiments, the memory can include read-only memory (ROM), random access memory (RAM), magnetic disk storage mediums, optical storage mediums, flash memory devices, electrical, optical, or other physical / tangible memory storage devices. Thus, in general, the memory includes one or more tangible (non-transitory) computer-readable storage media (e.g., a memory device) encoded with software that, when executed (by one or more processors), is operable to perform operations described with reference to the methods according to the aspects of the present disclosure.

[0165] The processor 2001 implements the chip layout processing method of any one of the above embodiments by reading and executing the computer program instructions stored in the memory 2002.

[0166] In one example, the chip layout processing device can further include a communication interface 2003 and a bus 2000. As shown, the processor 2001, the memory 2002, and the communication interface 2003 are connected by the bus 2000 and complete communication with each other. Figure 6

[0167] The communication interface 2003 is mainly used to realize the communication between the modules, devices, units and / or equipment in the embodiments of the present application.

[0168] ​Bus 2000 includes a hardware, software, or both that couples components of the online data traffic metering device to each other. As an example without limitation, bus can include an Accelerated Graphics Port (AGP) or other graphics bus, an Enhanced Industry Standard Architecture (EISA) bus, a Front Side Bus (FSB), a HyperTransport (HT) interconnect, an Industry Standard Architecture (ISA) bus, an Infmiband interconnect, a Low Pin Count (LPC) bus, a memory bus, a Micro Channel Architecture (MCA) bus, a Peripheral Component Interconnect (PCI) bus, a PCI-Express (PCI-X) bus, a Serial Advanced Technology Attachment (SATA) bus, a Video Electronics Standards Association Local (VLB) bus, or another suitable bus or combination of two or more of these. Where appropriate, bus 2000 can include one or more buses. Although this application describes and illustrates a particular bus, this application contemplates any suitable bus or interconnect.

[0169] In addition, in combination with the method for chip layout processing in the above embodiments, the embodiments of the present application can provide a computer storage medium for implementation. The computer storage medium has computer program instructions stored thereon; the computer program instructions are executed by a processor to implement any of the methods for chip layout processing in the above embodiments.

[0170] The embodiments of the present application also provide a computer program product, comprising a computer program, the computer program being executed by a processor to implement any of the methods for chip layout processing in the above embodiments.

[0171] It needs to be clear that the present application is not limited to the specific configurations and processes described above and shown in the drawings. For the sake of brevity, detailed descriptions of well-known methods are omitted here. In the above embodiments, several specific steps are described and shown as examples. However, the method processes of the present application are not limited to the specific steps described and shown, and those skilled in the art can make various changes, modifications and additions, or change the order between steps, after understanding the spirit of the present application.

[0172] The functions noted in the description of the structural block diagrams above can be implemented as hardware, software, firmware, or a combination thereof. When implemented in hardware, they can be, for example, electronic circuits, application specific integrated circuits (ASICs), appropriate firmware, plug-ins, functional cards, and the like. When implemented in software, the elements of the present application are program or code segments that are used to perform the required tasks. The program or code segments can be stored in a machine-readable medium or transmitted through a data signal carried in a carrier wave over a transmission medium or communication link. A "machine-readable medium" includes any medium that can store or transport information. Examples of machine-readable media include electronic circuits, semiconductor memory devices, ROM, flash memory, erasable ROM (EROM), floppy disks, CD-ROMs, optical disks, hard disks, fiber optic media, radio frequency (RF) links, and the like. The code segments can be downloaded via computer networks such as the Internet, intranets, and the like.

[0173] It is also important to note that the examples described herein can be implemented in a variety of systems, including and not limited to a digital electronic circuit, an analog electronic circuit, a computer hardware, firmware, software, or in combinations of them. The example described herein can be implemented as one or more computer programs running on a computer or other programmable data processing devices, a computer program, a computer program product, a computer, a mobile phone, a portable computer, a portable computer, a server, or other programmable data processing devices. The computer program is a set of instructions that can be used to program a computer or other programmable data processing devices to perform a certain task, or to implement a certain abstract data type. The program can be written in any form of programming language, including compiled or interpreted languages, and can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment.

[0174] The computer program can be deployed in any form, including, but not limited to, a stand-alone program, a subroutine, a software module, a software component, or other units suitable for use in a computing environment. A computer program in the present sense can, but need not, be embodied in the form of a source code, an object code, or an intermediate code between a source code and an object code, such as a compiled object code or an interpreted code. The computer program can be deployed to be executed by a single computer or by a computer network or other programmable data processing devices. When the computer program is implemented in a computer system, it can be stored in a computer usable medium, such as a storage device, a memory, or a computer network, or a data signal carrying a computer program in a carrier wave.

[0175] The above merely describes a specific implementation of the present application. Those skilled in the art can clearly understand the specific working processes of the system, modules and units described above for the convenience and brevity of description, and can refer to the corresponding processes in the foregoing method embodiments, which will not be described herein again. It should be understood that the protection scope of the present application is not limited to this, and any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed by the present application, and these modifications or replacements should be covered within the protection scope of the present application.

Claims

1. A method of chip layout processing, characterized by, The method comprises the following steps: obtaining a chip layout, wherein the chip layout comprises a plurality of patterns; performing division processing on the chip layout according to a preset division rule to obtain a plurality of division region maps, wherein the preset division rule is used to make the patterns in each division region map not in conflict with any pattern in adjacent division region maps; performing coloring on each pattern in each division region map according to a graph coloring algorithm to obtain a colored region map, wherein the graph coloring algorithm is used to make the coloring of the patterns in conflict in each division region map different; obtaining a pattern feature of each pattern; adjusting the coloring of each colored region map according to the pattern feature of each pattern to obtain a plurality of target colored region maps, so that the area ratio of the coloring areas of the patterns with different coloring in all target colored region maps satisfies an area ratio condition; splitting the patterns with different coloring in each target colored region map into different chip split maps, respectively; the pattern feature comprises at least one of the following: pattern projection overlap length and pattern area; the adjusting of each colored region map according to the pattern feature of each pattern to obtain a plurality of target colored region maps comprises the following steps: obtaining a coloring priority corresponding to each pattern in each division region map to obtain an initial coloring priority, wherein the coloring priority is used to determine the coloring of the corresponding pattern, and wherein the coloring of the patterns with different coloring priorities is different; adjusting the initial coloring priority according to the pattern area of each pattern until the ratio of the coloring areas of the patterns with different coloring satisfies an area ratio condition to obtain a target coloring priority; or adjusting the initial coloring priority according to the pattern projection overlap length until the projection overlap length of the patterns with different coloring satisfies a preset projection overlap length to obtain a target coloring priority; adjusting the coloring of each colored region map according to the target coloring priority to obtain a plurality of target colored region maps.

2. The method of claim 1, wherein, After the coloring of the patterns in the plurality of division region maps is performed according to the graph coloring algorithm to obtain a colored region map, the method further comprises the following steps: determining the edge weight of each edge corresponding to the plurality of division region maps, wherein the edge weight is in a positive correlation with the nearest distance from the edge of a pattern in one division region map to the edge of a pattern in an adjacent division region map; obtaining the edge weight order of each edge corresponding to the plurality of division region maps, wherein the edge weight order is used to represent the size order of the edge weight of each edge of each division region map; judging whether the ratio of the coloring areas of the patterns with different coloring in two adjacent division region maps satisfies an area ratio condition; when the ratio of the coloring areas of the patterns with different coloring in the two adjacent division region maps does not satisfy the area ratio condition, performing flip processing on the coloring of at least one division region map corresponding to the two adjacent division region maps to obtain a flipped division region map; merging the adjacent flipped division region maps in the order from small to large according to the edge weight order to obtain a merged division region map.

3. The method of claim 2, wherein, The method further comprises: performing a global consistency check on the merged partition region map to determine whether there is a graphic conflict region; in the case where the graphic conflict region exists, processing the graphic conflict region by using a preset global optimization algorithm, and correcting the color corresponding to the graphic conflict region.

4. The method according to any one of claims 1-3, characterized in that, The method further comprises: obtaining the distance between any two adjacent graphics in the chip layout; comparing the distance between the any two adjacent graphics with a preset distance, and determining that the two graphics have a conflict relationship in the case where the distance between the any two adjacent graphics is less than the preset distance; dividing the two graphics having the conflict relationship into different regions to obtain the plurality of partition region maps.

5. The method of claim 4, wherein, The method further comprises: simplifying the different regions to nodes to obtain a plurality of nodes; connecting the plurality of nodes by edges to obtain the plurality of partition region maps.

6. A chip layout processing apparatus characterized by comprising: The device comprises: an obtaining module configured to obtain a chip layout, the chip layout comprising a plurality of graphics; a dividing module configured to divide the chip layout according to a preset division rule to obtain a plurality of partition region maps, the preset division rule being configured to make the graphics in each partition region map not have a conflict relationship with any graphic in an adjacent partition region map; a coloring module configured to color each graphic in each partition region map according to a graph coloring algorithm to obtain a colored region map, the graph coloring algorithm being configured to make the coloring of the graphics having a conflict relationship in each partition region map different; the obtaining module is further configured to obtain a graphic feature of each graphic; an adjusting module configured to adjust the coloring of each colored region map according to the graphic feature of each graphic to obtain a plurality of target colored region maps, so that the ratio of the coloring area of the graphics having different coloring in all target colored region maps satisfies an area ratio condition; a splitting module configured to split the graphics having different coloring in each target colored region map into different chip split maps; the graphic feature comprises at least one of a graphic projection overlap length and a graphic area. The adjusting module is further configured to obtain a coloring priority corresponding to each of the graphs in each of the divided region graphs, to obtain an initial coloring priority, the coloring priority being used to determine a coloring color corresponding to the each of the graphs, wherein the coloring colors corresponding to the graphs with different coloring priorities are different; adjust the initial coloring priority according to graph areas corresponding to the each of the graphs until a ratio of coloring areas corresponding to the coloring colors of the graphs with different coloring colors satisfies an area ratio condition, to obtain a target coloring priority; or adjust the initial coloring priority according to graph projection overlapping lengths, until the projection overlapping lengths corresponding to the graphs with different coloring colors satisfy a preset projection overlapping length, to obtain the target coloring priority; and adjust coloring of each of the coloring region graphs according to the target coloring priority, to obtain a plurality of target coloring region graphs.

7. A chip floorplanning apparatus, comprising: The device comprises a processor and a memory storing computer program instructions; the processor implements the method of any one of claims 1-5 when executing the computer program instructions.

8. A computer-readable storage medium, characterized in that, The computer readable storage medium stores computer program instructions, and the computer program instructions are executed by a processor to implement the method of any one of claims 1-5.

9. A computer program product, characterised in that, The instructions in the computer program product are executed by a processor of an electronic device, so that the electronic device executes the method of any one of claims 1-5.

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