Topological shader techniques

Abstract

The invention relates to a topology shader technology. Systems, apparatuses, and methods may provide techniques for receiving an object description at a topology shader in a graphics pipeline and generating a set of polygons at the topology shader based on the object description. In addition, the set of polygons is sent to a vertex shader.

Description

Technical Field

[0001] Embodiments of the present application generally relate to graphics processing architectures. More specifically, embodiments relate to topological shader techniques in graphics processing architectures. Background Art

[0002] In a conventional graphics processing architecture, a central processing unit (CPU) may determine the complexity and topology of a scene to be rendered and generate an instruction stream that is further processed by a vertex shader in a graphics pipeline. The instruction stream may include parameters such as vertex data of a high-order surface, primitives, etc., wherein a vertex shader may transform the vertex data from an object-based coordinate representation (object space) to an alternatively based coordinate system such as world space or normalized device coordinate (NDC) space. Such an architecture may be limited to a fixed topology for each video frame depicting a scene, wherein the fixed topology may limit quality and / or performance. Furthermore, conventional approaches may use later tessellation stages in the graphics pipeline to generate vertex attributes and surface representations for each vertex associated with a geometric primitive. Relying solely on later stage tessellation to generate the surface representation may further limit quality and / or performance. BRIEF DESCRIPTION OF THE DRAWINGS

[0003] Various advantages of the embodiments will become apparent to those skilled in the art from a reading of the following description and appended claims, and from a reference to the following drawings, in which: Figure 1 is a block diagram illustrating a computer system configured to implement one or more aspects of the embodiments described herein; Figures 2A-2D shows a parallel processor component according to an embodiment; Figure 3A-3B is a block diagram of a graphics multiprocessor according to an embodiment; Figures 4A-4F An exemplary architecture is shown in which multiple GPUs are communicatively coupled to multiple multi-core processors; Figure 5 shows a graphics processing pipeline according to an embodiment; Figure 6 is a block diagram of an example of a graphics processing pipeline according to another embodiment; Figure 7 is an illustration of an example of a topological representation of a sphere at varying levels of detail according to an embodiment; Figure 8 is an illustration of an example of a lack of visibility condition according to an embodiment; Fig.9A is a flowchart of an example of a method of operating a semiconductor packaging apparatus according to an embodiment; Fig. 9B is a flowchart of an example of a method of generating a set of polygons according to an embodiment; Fig. 10A is a block diagram of an example of a computing system according to an embodiment; Fig. 10B is a diagram of an example of a semiconductor packaging device according to an embodiment; Fig.11 is a diagram of an example of a head mounted display (HMD) system according to an embodiment; Fig.12 According to the embodiment, it includes Fig.11 A block diagram of an example of functional components in an HMD system; Fig.13 is a block diagram of an example of a general processing cluster included in a parallel processing unit according to an embodiment; Fig.14 is a conceptual illustration of an example of a graphics processing pipeline that may be implemented within a parallel processing unit according to an embodiment; Fig.15 is a block diagram of an example of a streaming multiprocessor according to an embodiment; Figure 16-18 is a block diagram of an example of an overview of a data processing system according to an embodiment; Fig.19 is a block diagram of an example of a graphics processing engine according to an embodiment; Figure 20-22 is a block diagram of an example of an execution unit according to an embodiment; Fig.23 is a block diagram of an example of a graphics pipeline according to an embodiment; Figures 24A-24B is a block diagram of an example of graphics pipeline programming according to an embodiment; Fig.25 is a block diagram of an example of a graphics software architecture according to an embodiment; Fig.26 is a block diagram of an example of an intellectual property (IP) core development system according to an embodiment; and Fig. 27 is a block diagram of an example of a system on chip integrated circuit according to an embodiment. DETAILED DESCRIPTION

[0004] In the following description, many specific details are set forth to provide a more comprehensive understanding of the present disclosure. However, it will be apparent to one of ordinary skill in the art that the present invention may be practiced without one or more of these specific details. In other instances, well-known features have not been described in order to avoid obscuring the present invention.

[0005] System Overview Figure 1 1 is a block diagram illustrating a computing system configured to implement one or more aspects of the embodiments described herein. The computing system 100 includes a processing subsystem 101 having one or more processors 102 and a system memory 104, the one or more processors 102 communicating with the system memory 104 via an interconnect path that may include a memory hub 105. The memory hub 105 may be a separate component within a chipset component, or may be integrated within the one or more processors 102. The memory hub 105 is coupled to an I / O subsystem 111 via a communication link 106. The I / O subsystem 111 includes an I / O hub 107 that may enable the computing system 100 to receive input from one or more input devices 108. Additionally, the I / O hub 107 may enable a display controller to provide output to one or more display devices 110A, which may be included in the one or more processors 102. In one embodiment, the one or more display devices 110A coupled to the I / O hub 107 may include local, internal, or embedded display devices.

[0006] In one embodiment, the processing subsystem 101 includes one or more parallel processors 112, which are coupled to the memory hub 105 via a bus or other communication link 113. The communication link 113 can be one of any number of standard-based communication link technologies or protocols (such as, but not limited to, PCI Express), or can be a vendor-specific communication interface or communication structure. In one embodiment, the one or more parallel processors 112 form a computationally focused parallel or vector processing system that includes a large number of processing cores and / or processing clusters (such as, an integrated many-core (MIC) processor). In one embodiment, the one or more parallel processors 112 form a graphics processing subsystem that can output pixels to one of the one or more display devices 110A coupled via the I / O hub 107. The one or more parallel processors 112 may also include a display controller and display interface (not shown) to enable direct connection to one or more display devices 110B.

[0007] Within the I / O subsystem 111, a system storage unit 114 may be connected to the I / O hub 107 to provide a storage mechanism for the computing system 100. An I / O switch 116 may be used to provide an interface mechanism to enable connection between the I / O hub 107 and other components, such as a network adapter 118 and / or a wireless network adapter 119 that may be integrated into the platform, and various other devices that may be added via one or more plug-in devices 120. The network adapter 118 may be an Ethernet adapter or another wired network adapter. The wireless network adapter 119 may include one or more of the following: Wi-Fi, Bluetooth, near field communication (NFC), or another network device including one or more wireless radios.

[0008] The computing system 100 may include other components not explicitly shown, including USB or other port connections, optical storage drives, video capture devices, and the like, which may also be connected to the I / O hub 107. Figure 1 The communication paths interconnecting the various components in the system may be implemented using any suitable protocol, such as a PCI (Peripheral Component Interconnect) based protocol (e.g., PCI Express) or any other bus or point-to-point communication interface and / or protocol (such as, NV-Link high-speed interconnect, or interconnect protocols known in the art).

[0009] In one embodiment, the one or more parallel processors 112 incorporate circuits optimized for graphics and video processing (including, for example, video output circuits) and constitute a graphics processing unit (GPU). In another embodiment, the one or more parallel processors 112 incorporate circuits optimized for general-purpose processing while maintaining the underlying computing architecture described in more detail herein. In yet another embodiment, the components of the computing system 100 may be integrated on a single integrated circuit along with one or more other system elements. For example, the one or more parallel processors 112, the memory hub 105, the processor 102, and the I / O hub 107 may be integrated into a system on a chip (SoC) integrated circuit. Alternatively, the components of the computing system 100 may be integrated into a single package to form a system in package (SIP) configuration. In one embodiment, at least a portion of the components of the computing system 100 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0010] It will be appreciated that the computing system 100 shown herein is illustrative and that variations and modifications are possible. The connection topology, including the number and arrangement of bridges, the number of processor(s) 102, and the number of parallel processor(s) 112, may be modified as desired. For example, in some embodiments, the system memory 104 is connected to the processor(s) 102 directly rather than through a bridge, while other devices communicate with the processor(s) 102 and the system memory 104 via the memory hub 105. In other alternative topologies, the parallel processor(s) 112 are connected to the I / O hub 107 or directly to one of the processor(s) 102, rather than to the memory hub 105. In other embodiments, the I / O hub 107 and the memory hub 105 may be integrated into a single chip. Some embodiments may include two or more groups of processors 102 attached via multiple sockets, which may be coupled to two or more instances of the parallel processor(s) 112.

[0011] Some of the specific components shown herein are optional and may not be included in all implementations of computing system 100. For example, any number of plug-in cards or peripheral devices may be supported, or some components may be eliminated. In addition, some architectures may be different from those described above. Figure 1 Different terminology is used for components that are similar to those shown in FIG. 1. For example, in some architectures, memory hub 105 may be referred to as a north bridge, while I / O hub 107 may be referred to as a south bridge.

[0012] Figure 2A 200 according to an embodiment. The various components of the parallel processor 200 may be implemented using one or more integrated circuit devices, such as a programmable processor, an application specific integrated circuit (ASIC), or a field programmable gate array (FPGA). Figure 1 A variation of one or more parallel processors 112 is shown in .

[0013] In one embodiment, parallel processor 200 includes parallel processing unit 202. The parallel processing unit includes an I / O unit 204, which is capable of communicating with other devices (including other instances of parallel processing unit 202). I / O unit 204 can be directly connected to other devices. In one embodiment, I / O unit 204 is connected to other devices via the use of a hub or switch interface (such as memory hub 105). The connection between memory hub 105 and I / O unit 204 forms a communication link 113. Within parallel processing unit 202, I / O unit 204 is connected to a host interface 206 and a memory crossbar 216, wherein host interface 206 receives commands for performing processing operations and memory crossbar 216 receives commands for performing memory operations.

[0014] When the host interface 206 receives the command buffer via the I / O unit 204, the host interface 206 can direct the work operations for executing those commands to the front end 208. In one embodiment, the front end 208 is coupled with a scheduler 210, which is configured to distribute commands or other work items to the processing cluster array 212. In one embodiment, the scheduler 210 ensures that the processing cluster array 212 is properly configured and in a valid state before tasks are distributed to the processing clusters of the processing cluster array 212. In one embodiment, the scheduler 210 is implemented via firmware logic executed on a microcontroller. The microcontroller-implemented scheduler 210 can be configured to perform complex scheduling and work distribution operations at coarse and fine granularity, thereby enabling context switching and rapid preemption of threads executing on the processing array 212. In one embodiment, the host software can verify that the workload is scheduled on the processing array 212 via one of a plurality of graphics processing doorbells. The workload may then be automatically distributed across the processing array 212 by the scheduler 210 logic within the scheduler microcontroller.

[0015] The processing cluster array 212 may include up to "N" processing clusters (e.g., cluster 214A, cluster 214B, up to cluster 214N). Each cluster 214A-214N of the processing cluster array 212 may execute a large number of concurrent threads. The scheduler 210 may use various scheduling and / or work distribution algorithms to assign work to the clusters 214A-214N of the processing cluster array 212, which may vary depending on the workload generated for each type of program or calculation. Scheduling may be handled dynamically by the scheduler 210, or may be assisted in part by compiler logic during the compilation of program logic configured for execution by the processing cluster array 212. In one embodiment, different clusters 214A-214N of the processing cluster array 212 may be assigned to process different types of programs, or to perform different types of calculations.

[0016] Processing cluster array 212 may be configured to perform various types of parallel processing operations. In one embodiment, processing cluster array 212 is configured to perform general-purpose parallel computing operations. For example, processing cluster array 212 may include logic for performing processing tasks including filtering video and / or audio data, performing modeling operations (including physics operations), and performing data transformations.

[0017] In one embodiment, processing cluster array 212 is configured to perform parallel graphics processing operations. In embodiments where parallel processor 200 is configured to perform graphics processing operations, processing cluster array 212 may include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In addition, processing cluster array 212 may be configured to execute graphics processing related shader programs, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. Parallel processing unit 202 may transfer data from system memory via I / O unit 204 for processing. During processing, the transferred data may be stored to on-chip memory (e.g., parallel processor memory 222) during processing and then written back to system memory.

[0018] In one embodiment, when parallel processing unit 202 is used to perform graphics processing, scheduler 210 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to multiple clusters 214A-214N in processing cluster array 212. In some embodiments, multiple portions of processing cluster array 212 can be configured to perform different types of processing. For example, a first portion can be configured to perform vertex shading and topology generation, a second portion can be configured to perform tessellation and geometry shading, and a third portion can be configured to perform pixel shading or other screen space operations to generate a rendered image for display. Intermediate data generated by one or more of clusters 214A-214N can be stored in a buffer to allow the intermediate data to be transferred between clusters 214A-214N for further processing.

[0019] During operation, the processing cluster array 212 may receive processing tasks to be performed via the scheduler 210, which receives commands defining the processing tasks from the front end 208. For graphics processing operations, the processing tasks may include commands and state parameters defining how data is to be processed (e.g., what program is to be executed) and indices of the data to be processed (e.g., surface (patch) data, primitive data, vertex data, and / or pixel data). The scheduler 210 may be configured to obtain an index corresponding to a task, or may receive an index from the front end 208. The front end 208 may be configured to ensure that the processing cluster array 212 is configured to a valid state before initiating a workload specified by an incoming command buffer (e.g., a batch buffer, a push buffer, etc.).

[0020] Each of the one or more instances of the parallel processing unit 202 can be coupled to a parallel processor memory 222. The parallel processor memory 222 can be accessed via a memory crossbar switch 216, which can receive memory requests from the processing cluster array 212 and the I / O unit 204. The memory crossbar switch 216 can access the parallel processor memory 222 via a memory interface 218. The memory interface 218 can include a plurality of partition units (e.g., partition unit 220A, partition unit 220B, up to partition unit 220N), which can each be coupled to a portion of the parallel processor memory 222 (e.g., memory cells). In one implementation, the number of partition units 220A-220N is configured to be equal to the number of memory cells, such that the first partition unit 220A has a corresponding first memory cell 224A, the second partition unit 220B has a corresponding memory cell 224B, and the Nth partition unit 220N has a corresponding Nth memory cell 224N. In other embodiments, the number of partition units 220A-220N may not be equal to the number of memory devices.

[0021] In various embodiments, the memory units 224A-224N may include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In one embodiment, the memory units 224A-224N may also include 3D stacked memory, including but not limited to high bandwidth memory (HBM). Those skilled in the art will recognize that the specific implementation of the memory units 224A-224N may vary and may be selected from one of various conventional designs. Rendering targets (such as frame buffers or texture maps) may be stored across the memory units 224A-224N, allowing the partition units 220A-220N to write multiple portions of each rendering target in parallel to efficiently use the available bandwidth of the parallel processor memory 222. In some embodiments, local instances of the parallel processor memory 222 may be excluded to facilitate the unified memory design of the system memory to be utilized in conjunction with the local cache memory.

[0022] In one embodiment, any of the clusters 214A-214N of the processing cluster array 212 can process data to be written to any of the memory units 224A-224N within the parallel processor memory 222. The memory crossbar 216 can be configured to transfer the output of each cluster 214A-214N to any partition unit 220A-220N or another cluster 214A-214N, which can perform additional processing operations on the output. Each cluster 214A-214N can communicate with the memory interface 218 through the memory crossbar 216 to read from or write to various external memory devices. In one embodiment, the memory crossbar 216 has a connection to the memory interface 218 to communicate with the I / O unit 204, as well as a connection to a local instance of the parallel processor memory 222, thereby enabling the processing units within different processing clusters 214A-214N to communicate with the system memory or other memory that is not local to the parallel processing unit 202. In one embodiment, the memory crossbar switch 216 may use virtual channels to separate traffic flows between the clusters 214A-214N and the partition units 220A-220N.

[0023] Although a single instance of parallel processing unit 202 is shown in parallel processor 200, any number of instances of parallel processing unit 202 may be included. For example, multiple instances of parallel processing unit 202 may be provided on a single plug-in card, or multiple plug-in cards may be interconnected. Different instances of parallel processing unit 202 may be configured to interoperate even if the different instances have different numbers of processing cores, different amounts of local parallel processor memory, and / or other configuration differences. For example and in one embodiment, some instances of parallel processing unit 202 may include higher precision floating point units relative to other instances. Systems that incorporate one or more instances of parallel processing unit 202 or parallel processor 200 may be implemented in a variety of configurations and form factors, including but not limited to desktop, laptop, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0024] Figure 2B is a block diagram of a partition unit 220 according to an embodiment. In one embodiment, the partition unit 220 is Figure 2AAn example of one of the partition units 220A - 220N. As shown, the partition unit 220 includes an L2 cache 221, a frame buffer interface 225, and a ROP 226 (raster operation unit). The L2 cache 221 is a read / write cache configured to perform load and store operations received from the memory crossbar 216 and the ROP 226. Read misses and urgent writeback requests are output from the L2 cache 221 to the frame buffer interface 225 for processing. Updates can also be sent via the frame buffer interface 225 to the frame buffer for processing. In one embodiment, the frame buffer interface 225 interfaces with one of the memory units in the parallel processor memory (such as the memory units 224A - 224N of FIG. 2 (e.g., within the parallel processor memory 222)).

[0025] In a graphics application, the ROP 226 is a processing unit that performs raster operations such as stencil, z - test, blending, and the like. Subsequently, the ROP 226 outputs the processed graphics data stored in the graphics memory. In some embodiments, the ROP 226 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. The compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. The type of compression performed by the ROP 226 can vary based on the statistical characteristics of the data to be compressed. For example, in one embodiment, delta - color compression is performed on depth and color data on a per - tile basis.

[0026] In some embodiments, the ROP 226 is included within each processing cluster (e.g., clusters 214A - 214N of FIG. 2) rather than within the partition unit 220. In such embodiments, read and write requests for pixel data rather than pixel fragment data are conveyed through the memory crossbar 216. The processed graphics data can be displayed on a display device (such as Figure 1 one of the one or more display devices 110), routed for further processing by the (one or more) processors 102, or routed for further processing by Figure 2A one of the processing entities within the parallel processor 200.

[0027] Figure 2CIt is a block diagram of a processing cluster 214 in a parallel processing unit according to an embodiment. In one embodiment, the processing cluster is an instance of one of the processing clusters 214A-214N of Figure 2. The processing cluster 214 can be configured to execute many threads in parallel, wherein the term "thread" refers to an instance of a specific program executed on a specific set of input data. In some embodiments, when multiple independent instruction units are not provided, a single instruction multiple data (SIMD) instruction issuance technology is used to support the parallel execution of a large number of threads. In other embodiments, a public instruction unit configured to issue instructions to a group of processing engines in each of the processing clusters is used, and a single instruction multiple thread (SIMT) technology is used to support the parallel execution of a large number of generally synchronized threads. Different from the SIMD execution regime (wherein, all processing engines usually execute the same instruction), SIMT execution allows different threads to more easily pass through a given thread program along a divergent execution path. It will be understood by those skilled in the art that the SIMD processing regime represents a functional subset of the SIMT processing regime.

[0028] The operation of the processing cluster 214 can be controlled via a pipeline manager 232, which distributes processing tasks to SIMT parallel processors. The pipeline manager 232 receives instructions from the scheduler 210 of Figure 2, and manages the execution of those instructions via a graphics multiprocessor 234 and / or a texture unit 236. The illustrated graphics multiprocessor 234 is an exemplary instance of a SIMT parallel processor. However, various types of SIMT parallel processors of different architectures may be included in the processing cluster 214. One or more instances of the graphics multiprocessor 234 may be included in the processing cluster 214. The graphics multiprocessor 234 may process data, and a data crossbar 240 may be used to distribute the processed data to one of a plurality of possible destinations (including other shader units). The pipeline manager 232 may facilitate the distribution of processed data by specifying the destination of the processed data to be distributed via the data crossbar 240.

[0029] Each graphics multiprocessor 234 within a processing cluster 214 may include the same set of function execution logic (e.g., arithmetic logic units, load-store units, etc.). The function execution logic may be configured in a pipelined manner, in which a new instruction may be issued before a previous instruction is completed. The function execution logic supports a wide variety of operations, including integer and floating point arithmetic, comparison operations, Boolean operations, bit-shifting, and calculation of various algebraic functions. In one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may be present.

[0030] The instructions transmitted to the processing cluster 214 constitute threads. A group of threads executed across a group of parallel processing engines is a thread group. A thread group executes the same program on different input data. Each thread in a thread group can be assigned to a different processing engine in the graphics multiprocessor 234. A thread group may include fewer threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes fewer threads than the number of processing engines, one or more of the processing engines may be idle during the cycle in which the thread group is being processed. A thread group may also include more threads than the number of processing engines in the graphics multiprocessor 234. When a thread group includes more threads than the number of processing engines in the graphics multiprocessor 234, processing may be performed on consecutive clock cycles. In one embodiment, multiple thread groups may be executed concurrently on the graphics multiprocessor 234.

[0031] In one embodiment, the graphics multiprocessor 234 includes an internal cache memory for performing load and store operations. In one embodiment, the graphics multiprocessor 234 can abandon the internal cache and use the cache memory (e.g., L1 cache 308) within the processing cluster 214. Each graphics multiprocessor 234 also has access to the L2 cache in the partition unit (e.g., partition unit 220A-220N of Figure 2) shared in all processing clusters 214 and can be used to transfer data between threads. The graphics multiprocessor 234 can also access the off-chip global memory, which can include one or more of the local parallel processor memory and / or system memory. Any memory outside the parallel processing unit 202 can be used as a global memory. An embodiment (wherein the processing cluster 214 includes multiple instances of the graphics multiprocessor 234) can share common instructions and data, which can be stored in the L1 cache 308.

[0032] Each processing cluster 214 may include an MMU 245 (memory management unit) configured to map virtual addresses into physical addresses. In other embodiments, one or more instances of the MMU 245 may reside within the memory interface 218 of FIG. 2 . The MMU 245 includes: a set of page table entries (PTEs) for mapping virtual addresses of tiles (more on tiling) to physical addresses; and optionally a cache line index. The MMU 245 may include an address translation lookaside buffer (TLB) or cache that may reside within the graphics multiprocessor 234 or L1 cache or processing cluster 214. Physical addresses are processed to distribute surface data access locality, thereby allowing efficient request interleaving in partition units. The cache line index can be used to determine whether a request for a cache line is a hit or a miss.

[0033] In graphics and computing applications, the processing clusters 214 may be configured such that each graphics multiprocessor 234 is coupled to a texture unit 236 for performing texture mapping operations, such as determining texture sample locations, reading texture data, and filtering texture data. Texture data is read from an internal texture L1 cache (not shown) or in some embodiments from an L1 cache within the graphics multiprocessor 234, and retrieved from an L2 cache, local parallel processor memory, or system memory, as needed. Each graphics multiprocessor 234 outputs a processed task to a data crossbar 240 to provide the processed task to another processing cluster 214 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or system memory via a memory crossbar 216. A preROP 242 (e.g., a pre-raster operation unit) is configured to receive data from the graphics multiprocessor 234, direct the data to a ROP unit, which may be located with a partition unit (e.g., partition units 220A-220N of FIG. 2 ) as described herein. The preROP 242 unit may perform optimizations for color blending, organize pixel color data, and perform address translations.

[0034] It will be appreciated that the core architecture described herein is illustrative, and variations and modifications are possible. Any number of processing units (e.g., graphics multiprocessor 234, texture unit 236, preROP 242, etc.) may be included within a processing cluster 214. Furthermore, while only one processing cluster 214 is shown, a parallel processing unit as described herein may include any number of instances of a processing cluster 214. In one embodiment, each processing cluster 214 may be configured to operate independently of other processing clusters 214 using separate and distinct processing units, L1 caches, etc.

[0035] Figure 2D A graphics multiprocessor 234 is shown according to one embodiment. In such embodiments, the graphics multiprocessor 234 is coupled to a pipeline manager 232 of a processing cluster 214. The graphics multiprocessor 234 has an execution pipeline that includes, but is not limited to, an instruction cache 252, an instruction unit 254, an address mapping unit 256, a register file 258, one or more general purpose graphics processing unit (GPGPU) cores 262, and one or more load / store units 266. The GPGPU cores 262 and the load / store units 266 are coupled to a cache memory 272 and a shared memory 270 via a memory and cache interconnect 268.

[0036] In one embodiment, the instruction cache 252 receives a stream of instructions to be executed from the pipeline manager 232. The instructions are cached in the instruction cache 252 and dispatched by the instruction unit 254 for execution. The instruction unit 254 can dispatch instructions into thread groups (e.g., warps), where each thread of the thread group is assigned to a different execution unit within the GPGPU core 262. Instructions can access any of the local, shared, or global address spaces by specifying an address within the unified address space. The address mapping unit 256 can be used to convert addresses in the unified address space into distinct memory addresses that can be accessed by the load / store unit 266.

[0037] The register file 258 provides a set of registers for the functional units of the graphics multiprocessor 324. The register file 258 provides temporary storage for operands for the data paths of the functional units (e.g., GPGPU core 262, load / store unit 266) connected to the graphics multiprocessor 324. In one embodiment, the register file 258 is divided between each of the functional units so that each functional unit is allocated a dedicated portion of the register file 258. In one embodiment, the register file 258 is divided between different warps executed by the graphics multiprocessor 324.

[0038] The GPGPU cores 262 may each include a floating point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 324. Depending on the embodiment, the GPGPU cores 262 may be similar in architecture, or may be different in architecture. For example and in one embodiment, the first portion of the GPGPU core 262 includes a single-precision FPU and an integer ALU, while the second portion of the GPGPU core includes a double-precision FPU. In one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point arithmetic, or may be capable of variable-precision floating-point arithmetic. The graphics multiprocessor 324 may additionally include one or more fixed-function or special-function units to perform specific functions (such as copying rectangles or pixel blending operations). In one embodiment, one or more of the GPGPU cores may also include fixed or special-function logic.

[0039] In one embodiment, GPGPU core 262 includes SIMD logic capable of executing a single instruction to multiple groups of data. In one embodiment, GPGPU core 262 can physically execute SIMD4, SIMD8 and SIMD16 instructions, and logically execute SIMD1, SIMD2 and SIMD32 instructions. SIMD instructions for GPGPU core can be generated by shader compiler at compile time, or can be automatically generated when executing a program written and compiled for single program multiple data (SPMD) or SIMT architecture. Multiple threads of a program configured for SIMT execution model can be executed via a single SIMD instruction. For example and in one embodiment, eight SIMT threads performing the same or similar operation can be executed in parallel via a single SIMD8 logic unit.

[0040] The memory and cache interconnect 268 is an interconnect network that connects each of the functional units of the graphics multiprocessor 234 to the register file 258 and to the shared memory 270. In one embodiment, the memory and cache interconnect 268 is a crossbar interconnect that allows the load / store unit 266 to implement load and store operations between the shared memory 270 and the register file 258. The register file 258 can operate at the same frequency as the GPGPU core 262, so that data transfer between the GPGPU core 262 and the register file 258 is very low latency. The shared memory 270 can be used to enable communication between threads executed on the functional units within the graphics multiprocessor 234. The cache memory 272 can be used, for example, as a data cache to cache texture data communicated between the functional units and the texture unit 236. The shared memory 270 can also be used as a program-managed cache. Threads executing on the GPGPU core 262 can programmatically store data in the shared memory in addition to the automatically cached data stored in the cache memory 272.

[0041] Figure 3A-3B Additional graphics multiprocessors are shown according to an embodiment. The graphics multiprocessors 325, 350 shown are Figure 2C The illustrated graphics multiprocessors 325, 350 may be configured as streaming multiprocessors (SMs) capable of executing a large number of execution threads simultaneously.

[0042] Figure 3A A graphics multiprocessor 325 is shown according to an additional embodiment. The graphics multiprocessor 325 is Figure 2DThe graphics multiprocessor 234 includes multiple additional instances of execution resource units. For example, the graphics multiprocessor 325 may include multiple instances of instruction units 332A-332B, register files 334A-334B, and texture units 344A-344B. The graphics multiprocessor 325 also includes multiple groups of graphics or computing execution units (e.g., GPGPU cores 336A-336B, GPGPU cores 337A-337B, GPGPU cores 338A-338B) and multiple groups of load / store units 340A-340B. In one embodiment, the execution resource unit has a common instruction cache 330, texture and / or data cache memory 342, and shared memory 346.

[0043] Various components may communicate via interconnect structure 327. In one embodiment, interconnect structure 327 includes one or more crossbar switches to enable communication between various components of graphics multiprocessor 325. In one embodiment, interconnect structure 327 is a separate high-speed network fabric layer on which each component of graphics multiprocessor 325 is stacked. Components of graphics multiprocessor 325 communicate with remote components via interconnect structure 327. For example, GPGPU cores 336A-336B, 337A-337B, and 3378A-338B may each communicate with shared memory 346 via interconnect structure 327. Interconnect structure 327 may arbitrate communications within graphics multiprocessor 325 to ensure fair bandwidth allocation between components.

[0044] Figure 3B A graphics multiprocessor 350 according to an additional embodiment is shown. The graphics processor includes multiple sets of execution resources 356A-356D, wherein each set of execution resources includes multiple instruction units, register files, GPGPU cores, and load storage units, such as Figure 2D and Figure 3A . Execution resources 356A-356D may work in concert with texture units 360A-360D for texture operations while sharing instruction cache 354 and shared memory 362. In one embodiment, execution resources 356A-356D may share multiple instances of instruction cache 354 and shared memory 362 as well as texture and / or data cache memories 358A-358B. The various components may be communicated to one another via a communication protocol similar to Figure 3A The interconnect structure 327 and the interconnect structure 352 communicate with each other.

[0045] Those skilled in the art will understand that Figure 1 , 2AThe architectures described in Figures 2-2D and 3A-3B are illustrative and non-restrictive with respect to the scope of the present embodiments. Thus, without departing from the scope of the embodiments described herein, the techniques described herein may be implemented on any properly configured processing unit, including but not limited to one or more mobile application processors, one or more desktop or server central processing units (CPUs) (including multi-core CPUs), one or more parallel processing units (such as parallel processing unit 202 of Figure 2), and one or more graphics processors or special processing units.

[0046] In some embodiments, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. The GPU may be communicatively coupled to the host processor / core via a bus or another interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In other embodiments, the GPU may be integrated on the same package or chip as the core and communicatively coupled to the core via an internal processor bus / interconnect (i.e., inside the package or chip). Regardless of the manner in which the GPU is connected, the processor core can assign work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. The GPU then uses dedicated circuits / logic to efficiently process these commands / instructions.

[0047] Technologies for GPU to host processor interconnect Figure 4A An exemplary architecture is shown in which multiple GPUs 410-413 are communicatively coupled to multiple multi-core processors 405-406 via high-speed links 440-443 (e.g., buses, point-to-point interconnects, etc.). In one embodiment, the high-speed links 440-443 support 4GB / s, 30GB / s, 80GB / s, or higher communication throughputs, depending on the implementation. Various interconnect protocols may be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. However, the underlying principles of the invention are not limited to any specific communication protocol or throughput.

[0048] Additionally, in one embodiment, two or more of the GPUs 410-413 are interconnected via high-speed links 444-445, which may be implemented using the same or different protocols / links as used for high-speed links 440-443. Similarly, two or more of the multi-core processors 405-406 may be connected via high-speed link 433, which may be a symmetric multiprocessor (SMP) bus operating at 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, Figure 4AAll communications between the various system components shown in can be achieved using the same protocol / links (eg, through a common interconnect structure). However, as mentioned, the underlying principles of the invention are not limited to any particular type of interconnect technology.

[0049] In one embodiment, each multi-core processor 405-406 is communicatively coupled to processor memory 401-402 via memory interconnects 430-431, respectively, and each GPU 410-413 is communicatively coupled to GPU memory 420-423 via GPU memory interconnects 450-453, respectively. Memory interconnects 430-431 and 450-453 may utilize the same or different memory access technologies. By way of example and not limitation, processor memory 401-402 and GPU memory 420-423 may be volatile memory, such as dynamic random access memory (DRAM) (including stacked DRAM), graphics DDR SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram. In one embodiment, a portion of the memory may be volatile memory and another portion may be non-volatile memory (e.g., using two-level memory (2LM) hierarchy).

[0050] As described below, although the various processors 405-406 and GPUs 410-413 may be physically coupled to specific memories 401-402, 420-423, respectively, a unified memory architecture may be implemented in which the same virtual system address space (also referred to as an "effective address" space) is distributed across all of the various physical memories. For example, the processor memories 401-402 may each include 64GB of system memory address space, and the GPU memories 420-423 may each include 32GB of system memory address space (yielding a total of 256GB of addressable memory in this example).

[0051] Figure 4B Additional details are shown for the interconnection between the multi-core processor 407 and the graphics acceleration module 446 according to one embodiment. The graphics acceleration module 446 may include one or more GPU chips integrated on a line card that is coupled to the processor 407 via the high-speed link 440. Alternatively, the graphics acceleration module 446 may be integrated on the same package or chip as the processor 407.

[0052] The processor 407 shown includes multiple cores 460A-460D, each of which has a translation lookaside buffer 461A-461D and one or more caches 462A-462D. The core may include various other components (e.g., instruction acquisition unit, branch prediction unit, decoder, execution unit, reorder buffer, etc.) for executing instructions and processing data, which are not shown to avoid obscuring the underlying principles of the present invention. Caches 462A-462D may include level 1 (L1) and level 2 (L2) caches. In addition, one or more shared caches 426 may be included in the cache hierarchy and shared by multiple groups of cores 460A-460D. For example, one embodiment of the processor 407 includes 24 cores, each of which has its own L1 cache, twelve shared L2 caches, and twelve shared L3 caches. In this embodiment, one of the L2 and L3 caches is shared by two adjacent cores. The processor 407 and the graphics accelerator integrated module 446 are connected to the system memory 441, which may include the processor memories 401-402.

[0053] The coherence of data and instructions stored in the various caches 462A-462D, 456 and the system memory 441 is maintained via inter-core communications over the coherence bus 464. For example, each cache may have cache coherence logic / circuitry associated therewith to communicate over the coherence bus 464 in response to a detected read or write to a particular cache line. In one implementation, a cache snooping protocol is implemented over the coherence bus 464 to snoop cache accesses. Cache snooping / coherence techniques are well understood by those skilled in the art and will not be described in detail herein to avoid obscuring the underlying principles of the present invention.

[0054] In one embodiment, the proxy circuit 425 communicatively couples the graphics acceleration module 446 to the coherence bus 464, thereby allowing the graphics acceleration module 446 to participate in the cache coherence protocol as a peer of the core. Specifically, the interface 435 provides connectivity to the proxy circuit 425 through a high-speed link 440 (e.g., a PCIe bus, NVLink, etc.), and the interface 437 connects the graphics acceleration module 446 to the link 440.

[0055] In one implementation, the accelerator integrated circuit 436 provides cache management, memory access, context management, and interrupt management services on behalf of the multiple graphics processing engines 431, 432, N of the graphics acceleration module 446. The graphics processing engines 431, 432, N may each include a separate graphics processing unit (GPU). Alternatively, the graphics processing engines 431, 432, N may include different types of graphics processing engines within the GPU, such as a graphics execution unit, a media processing engine (e.g., a video encoder / decoder), a sampler, and a blit engine. In other words, the graphics acceleration module may be a GPU with multiple graphics processing engines 431-432, N, or the graphics processing engines 431-432, N may be individual GPUs integrated on a common package, line card, or chip.

[0056] In one embodiment, the accelerator integrated circuit 436 includes a memory management unit (MMU) 439 for performing various memory management functions, such as virtual to physical memory translation (also known as effective to real memory translation) and memory access protocols for accessing the system memory 441. The MMU 439 may also include a translation lookaside buffer (TLB) (not shown) for caching virtual / effective to physical / real address translations. In one implementation, the cache 438 stores commands and data for efficient access by the graphics processing engines 431-432, N. In one embodiment, the data stored in the cache 438 and the graphics memory 433-434, N is kept consistent with the core caches 462A-462D, 456 and the system memory 411. As mentioned, this may be achieved via proxy circuitry 425, which participates in cache coherence mechanisms on behalf of cache 438 and memories 433-434, N (e.g., sending updates relating to modifications / accesses of cache lines on processor caches 462A-462D, 456 to cache 438, and receiving updates from cache 438).

[0057] A set of registers 445 stores context data for threads executed by the graphics processing engines 431-432, N, and context management circuitry 448 manages thread contexts. For example, context management circuitry 448 may perform save and restore operations during context switching to save and restore contexts of various threads (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, upon context switching, context management circuitry 448 may store current register values ​​to a designated area in memory (e.g., identified by a context pointer). It may then restore the register values ​​upon returning to the context. In one embodiment, interrupt management circuitry 447 receives and processes interrupts received from system devices.

[0058] In one implementation, virtual / effective addresses from the graphics processing engine 431 are converted to real / physical addresses in the system memory 411 by the MMU 439. One embodiment of the accelerator integrated circuit 436 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 446 and / or other accelerator devices. The graphics accelerator module 446 may be dedicated to a single application executed on the processor 407, or may be shared between multiple applications. In one embodiment, a virtualized graphics execution environment is presented in which the resources of the graphics processing engines 431-432, N are shared with multiple applications or virtual machines (VMs). The resources may be subdivided into "slices" that are allocated to the VMs and / or applications based on the processing requirements and priorities associated with the different VMs and / or applications.

[0059] Thus, the accelerator integrated circuit acts as a bridge to the system of graphics acceleration module 446 and provides address translation and system memory cache services. In addition, the accelerator integrated circuit 436 can provide virtualization facilities for the host processor to manage virtualization, interrupts, and memory management of the graphics processing engine.

[0060] Since the hardware resources of the graphics processing engines 431-432, N are explicitly mapped to the real address space seen by the host processor 407, any host processor can directly address these resources using effective address values. In one embodiment, one function of the accelerator integrated circuit 436 is the physical separation of the graphics processing engines 431-432, N so that they appear to the system as independent units.

[0061] As mentioned, in the illustrated embodiment, one or more graphics memories 433-434, M are respectively coupled to each of the graphics processing engines 431-432, N. The graphics memories 433-434, M store instructions and data being processed by each of the graphics processing engines 431-432, N. The graphics memories 433-434, M may be volatile memory, such as DRAM (including stacked DRAM), GDDR memory (e.g., GDDR5, GDDR6), or HBM, and / or may be non-volatile memory, such as 3D XPoint or Nano-Ram.

[0062] In one embodiment, to reduce data traffic on link 440, biasing techniques are used to ensure that the data stored in graphics memory 433-434, M is data that will be used most frequently by graphics processing engines 431-432, N and preferably not used (at least not frequently) by cores 460A-460D. Similarly, the biasing mechanism attempts to keep data needed by a core (and preferably not graphics processing engines 431-432, N) within system memory 411 and the core's cache 462A-462D, 456.

[0063] Figure 4C Another embodiment is shown in which an accelerator integrated circuit 436 is integrated within the processor 407. In this embodiment, the graphics processing engines 431-432, N communicate directly to the accelerator integrated circuit 436 via the interface 437 and the interface 435 (again, which may utilize any form of bus or interface protocol) through the high-speed link 440. The accelerator integrated circuit 436 may perform operations related to Figure 4B The same operations as those described, but at potentially higher throughput given their close proximity to the coherency bus 462 and caches 462A-462D, 426.

[0064] One embodiment supports different programming models, including a dedicated process programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization). The latter may include a programming model controlled by accelerator integrated circuit 436 and a programming model controlled by graphics acceleration module 446.

[0065] In one embodiment of a dedicated process model, the graphics processing engines 431-432, N are dedicated to a single application or process under a single operating system. A single application can funnel another application's request to the graphics engine 431-432, N, thereby providing virtualization within a VM / partition.

[0066] In a dedicated process programming model, graphics processing engines 431-432, N can be shared by multiple VM / application partitions. The shared model requires a hypervisor to virtualize graphics processing engines 431-432, N to allow access by each operating system. For a single partition system without a hypervisor, graphics processing engines 431-432, N are owned by the operating system. In both cases, the operating system can virtualize graphics processing engines 431-432, N to provide access to each process or application.

[0067] For the shared programming model, the graphics acceleration module 446 or each graphics processing engine 431-432, N uses a process handle to select a process element. In one embodiment, the process element is stored in the system memory 411 and is addressable using the effective address to real address conversion technology described herein. The process handle can be an implementation-specific value provided to the host process when registering its context with the graphics processing engine 431-432, N (i.e., calling the system software to add the process element to the process element linked list). The lower 16 bits of the process handle can be the offset of the process element within the process element linked list.

[0068] Figure 4D An exemplary accelerator integrated slice 490 is shown. As used herein, a "slice" includes a specified portion of the processing resources of an accelerator integrated circuit 436. The application effective address space 482 within the system memory 411 stores process elements 483. In one embodiment, the process element 483 is stored in response to a GPU call 481 from an application 480 executed on the processor 407. The process element 483 contains the process state of the corresponding application 480. The work descriptor (WD) 484 contained in the process element 483 can be a single job requested by the application, or can contain a pointer to a job queue. In the latter case, WD 484 is a pointer to a job request queue in the address space 482 of the application.

[0069] Graphics acceleration module 446 and / or individual graphics processing engines 431-432, N may be shared by all processes or a subset of processes in the system. Embodiments of the present invention include infrastructure for setting process state and sending WD 484 to graphics acceleration module 446 to start a job in a virtualized environment.

[0070] In one implementation, the dedicated process programming model is implementation specific. In this model, a single process owns the graphics acceleration module 446 or individual graphics processing engine 431. Since the graphics acceleration module 446 is owned by a single process, when the graphics acceleration module 446 is assigned, the hypervisor initializes the accelerator integrated circuit 436 for the owning partition and the operating system initializes the accelerator integrated circuit 436 for the owning process.

[0071] In operation, the WD acquisition unit 491 in the accelerator integrated slice 490 acquires the next WD 484, which includes an indication of work to be completed by one of the graphics processing engines of the graphics acceleration module 446. Data from the WD 484 may be stored in registers 445 and used by the MMU 439, interrupt management circuitry 447, and / or context management circuitry 446 as shown. For example, one embodiment of the MMU 439 includes a segment / page walk circuitry for accessing a segment / page table 486 within the OS virtual address space 485. The interrupt management circuitry 447 may process an interrupt event 492 received from the graphics acceleration module 446. When performing graphics operations, the effective address 493 generated by the graphics processing engines 431-432, N is converted to a real address by the MMU 439.

[0072] In one embodiment, the same set of registers 445 is replicated for each graphics processing engine 431-432, N, and / or graphics acceleration module 446, and can be initialized by a hypervisor or operating system. Each of these replicated registers can be included in an accelerator integrated slice 490. Exemplary registers that can be initialized by a hypervisor are shown in Table 1.

[0073] Table 1 - Registers initialized by the hypervisor 1 Slice Control Register 2 Real address (RA) dispatched process area pointer 3 Permission Mask Override Register 4 Interrupt vector table entry offset 5 Interrupt Vector Table Entry Limits 6 Status Register 7 Logical Partition ID 8 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 9 Storage Description Register Example registers that may be initialized by the operating system are shown in Table 2.

[0074] Table 2 - Registers initialized by the operating system 1 Process and thread identities 2 Effective Address (EA) context save / restore pointer 3 Virtual Address (VA) Accelerator Utilizes Record Pointers 4 Virtual Address (VA) Segment Table Pointer 5 Permission masking 6 Job Descriptor In one embodiment, each WD 484 is specific to a particular graphics acceleration module 446 and / or graphics processing engine 431-432, N. It contains all the information needed for the graphics processing engine 431-432, N to complete its work, or it may be a pointer to a memory location of a command queue where the application has set up work to be done.

[0075] Figure 4E Additional details of one embodiment of a sharing model are shown. This embodiment includes a hypervisor real address space 498 in which a process element list 499 is stored. The hypervisor real address space 498 is accessible via a hypervisor 496 that virtualizes a graphics acceleration module engine for an operating system 495.

[0076] The shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 446. There are two programming models where the graphics acceleration module 446 is shared by multiple processes and partitions: time-slice shared and graphics directed shared.

[0077] In this model, the hypervisor 496 owns the graphics acceleration module 446 and makes its functionality available to all operating systems 495. In order for the graphics acceleration module 446 to support virtualization by the hypervisor 496, the graphics acceleration module 446 may comply with the following requirements: 1) The application's job requests must be autonomous (i.e., no state needs to be maintained between jobs), or the graphics acceleration module 446 must provide a context save and restore mechanism. 2) The application's job requests are guaranteed to be completed within a specified amount of time by the graphics acceleration module 446 (including any transition failures), or the graphics acceleration module 446 provides the ability to preempt the processing of a job. 3) When operating in a directed sharing programming model, the graphics acceleration module 446 must be guaranteed fairness between processes.

[0078] In one embodiment, for the shared model, the application 480 is required to use the graphics acceleration module 446 type, work descriptor (WD), permission mask register (AMR) value and context save / restore region pointer (CSRP) to make an operating system 495 system call. The graphics acceleration module 446 type describes the acceleration function targeted for the system call. The graphics acceleration module 446 type can be a system-specific value. The WD is formatted specifically for the graphics acceleration module 446 and can be in the form of a graphics acceleration module 446 command, an effective address pointer to a user-defined structure, an effective address pointer to a command queue, or any other data structure for describing the work to be completed by the graphics acceleration module 446. In one embodiment, the AMR value is the AMR state to be used for the current process. The value passed to the operating system is similar to the application of setting the AMR. If the accelerator integrated circuit 436 and the graphics acceleration module 446 implementation do not support the user permission mask override register (UAMOR), the operating system can apply the current UAMOR value to the AMR value and then pass the AMR in the hypervisor call. Optionally, the hypervisor 496 may apply the current privilege mask overwrite register (AMOR) value before placing the AMR into the process element 483. In one embodiment, the CSRP is one of the registers 445 that contains the effective address of an area in the application's address space 482 for the graphics acceleration module 446 to save and restore context state. This pointer is optional if state does not need to be saved between jobs or when a job is preempted. The context save / restore area may be pinned system memory.

[0079] Upon receiving the system call, the operating system 495 may verify that the application 480 has been registered and has been given permission to use the graphics acceleration module 446. The operating system 495 then calls the hypervisor 496 with the information shown in Table 3.

[0080] Table 3 – OS to Hypervisor call parameters 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) Upon receiving the hypervisor call, the hypervisor 496 verifies that the operating system 495 has registered and has been given permission to use the graphics acceleration module 446. The hypervisor 496 then places the process element 483 into a linked list of process elements of the corresponding graphics acceleration module 446 type. The process element may include the information shown in Table 4.

[0081] Table 4 - Process element information 1 Work Descriptor (WD) 2 Authority Mask Register (AMR) value (potentially masked) 3 Effective Address (EA) Context Save / Restore Region Pointer (CSRP) 4 Process ID (PID) and optional thread ID (TID) 5 Virtual Address (VA) Accelerator Utilization Record Pointer (AURP) 6 Virtual address of the storage segment table pointer (SSTP) 7 Logical Interrupt Service Number (LISN) 8 Interrupt vector table derived from hypervisor call parameters 9 Status Register (SR) Value 10 Logical Partition ID (LPID) 11 Real Address (RA) Hypervisor Accelerator Utilizing Record Pointers 12 Storage Descriptor Register (SDR) In one embodiment, the hypervisor initializes the plurality of accelerator integrated slice 490 registers 445 .

[0082] like Figure 4F As shown in, one embodiment of the present invention employs a unified memory addressable via a common virtual memory address space, which is used to access physical processor memory 401-402 and GPU memory 420-423. In this implementation, operations executed on GPU 410-413 utilize the same virtual / effective memory address space to access processor memory 401-402 and vice versa, thereby simplifying programmability. In one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 401, a second portion is allocated to second processor memory 402, a third portion is allocated to GPU memory 420, and so on. The entire virtual / effective memory space (sometimes referred to as the effective address space) is thereby distributed across each of processor memory 401-402 and GPU memory 420-423, thereby allowing any processor or GPU to access any physical memory (with a virtual address mapped to that memory).

[0083] In one embodiment, bias / coherency management circuits 494A-494E within one or more of MMUs 439A-439E ensure cache coherency between caches of a host processor (e.g., 405) and GPUs 410-413 and implement biasing techniques that indicate physical memory where certain types of data should be stored. Figure 4FMultiple instances of bias / consistency management circuits 494A- 494E are shown in , but bias / consistency circuits may be implemented within an MMU of one or more host processors 405 and / or within an accelerator integrated circuit 436 .

[0084] One embodiment allows the use of shared virtual memory (SVM) technology to access GPU-attached memory 420-423 and map it as part of system memory without suffering the typical performance drawbacks associated with full system cache coherence. The ability to access GPU-attached memory 420-423 as system memory without heavy cache coherence overhead provides a beneficial operating environment for GPU offloading. This arrangement allows host processor 405 software to set operands and access calculation results without the overhead of traditional I / O DMA data copying. Such traditional copies involve driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all inefficient relative to simple memory accesses. At the same time, the ability to access GPU-attached memory 420-423 without cache coherence overhead can be critical to the runtime of offloaded calculations. In the case of having substantial streaming write memory traffic, for example, cache coherence overhead can significantly reduce the effective write bandwidth seen by GPU 410-413. The efficiency of operand setup, the efficiency of result access, and the efficiency of GPU computation all play a role in determining the effectiveness of GPU offloading.

[0085] In one implementation, the selection between GPU bias and host processor bias is driven by a bias tracker data structure. A bias table may be used, for example, which may be a page granularity structure comprising 1 or 2 bits per GPU attached memory page (i.e., controlled at the granularity of a memory page). The bias table may be implemented in a stolen memory range of one or more GPU attached memories 420-423, with or without a bias cache in the GPUs 410-413 (e.g., to cache frequently / recently used entries of the bias table). Alternatively, the entire bias table may be maintained within the GPU.

[0086] In one implementation, the bias table entry associated with each access to GPU-attached memory 420-423 is accessed before actually accessing the GPU memory, resulting in the following operations. First, local requests from GPUs 410-413 that find their pages in the host bias are forwarded directly to the corresponding GPU memory 420-423. Local requests from the GPUs are forwarded to processor 405 (e.g., via a high-speed link as discussed above). In one embodiment, requests from processor 405 that find the requested page in the host processor bias complete requests similar to normal memory reads. Alternatively, requests for pages of the GPU bias can be forwarded to GPUs 410-413. Then, if the GPU is not currently using the page, the GPU can transfer the page to the host processor bias.

[0087] The bias state of a page may be changed by a software-based mechanism, a hardware-assisted software-based mechanism, or, for a limited set of situations, a purely hardware-based mechanism.

[0088] One mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the GPU's device driver, which in turn sends a message (or enqueues a command descriptor) to the GPU, instructing it to change the bias state and perform a cache flush operation in the host for some transitions. The cache flush operation is required for transitions from host processor 405 bias to GPU bias, but not for the reverse transition.

[0089] In one embodiment, cache coherency is maintained by temporarily rendering GPU bias pages that are not cacheable by host processor 405. To access these pages, processor 405 may request access from GPU 410, which may or may not be immediately granted, depending on the implementation. Therefore, to reduce communication between processor 405 and GPU 410, it is ensured that GPU bias pages are those pages that are needed by the GPU but not by host processor 405 and vice versa.

[0090] Graphics processing pipeline Figure 5 2. A graphics processing pipeline 500 is shown according to an embodiment. In one embodiment, a graphics processor may implement the illustrated graphics processing pipeline 500. The graphics processor may be included in a parallel processing subsystem as described herein (such as parallel processor 200 of FIG. 2), which in one embodiment is Figure 12 . Various parallel processing systems may implement the graphics processing pipeline 500 via one or more instances of a parallel processing unit (e.g., parallel processing unit 202 of FIG. 2 ) as described herein. For example, a shader unit (e.g., graphics multiprocessor 234 of FIG. 3 ) may be configured to perform the functions of one or more of a vertex processing unit 504, a tessellation control processing unit 508, a tessellation evaluation processing unit 512, a geometry processing unit 516, and a fragment / pixel processing unit 524. The functions of the data assembler 502, primitive assemblers 506, 514, 518, tessellation unit 510, rasterizer 522, and raster operation unit 526 may also be performed by other processing engines within a processing cluster (e.g., processing cluster 214 of FIG. 3 ) and corresponding partition units (e.g., partition units 220A-220N of FIG. 2 ). The graphics processing pipeline 500 may also be implemented using dedicated processing units for one or more functions. In one embodiment, one or more portions of the graphics processing pipeline 500 may be executed by parallel processing logic within a general purpose processor (e.g., a CPU). In one embodiment, one or more portions of the graphics processing pipeline 500 may access on-chip memory (e.g., such as parallel processor memory 222 in FIG. 2 ) via a memory interface 528, which may be an example of the memory interface 218 of FIG. 2 .

[0091] In one embodiment, data assembler 502 is a processing unit that collects vertex data for surfaces and primitives. Data assembler 502 then outputs vertex data including vertex attributes to vertex processing unit 504. Vertex processing unit 504 is a programmable execution unit that executes vertex shader programs to lighten and transform vertex data as specified by the vertex shader programs. Vertex processing unit 504 reads data stored in cache, local or system memory for use in processing vertex data, and vertex processing unit 504 can be programmed to transform vertex data from an object-based coordinate representation to a world space coordinate space or a normalized device coordinate space.

[0092] A first instance of primitive assembler 506 receives vertex attributes from vertex processing unit 504. Primitive assembler 506 reads the stored vertex attributes as needed and builds graphics primitives for processing by tessellation control processing unit 508. Graphics primitives include triangles, line segments, points, patches, etc. as supported by various graphics processing application programming interfaces (APIs).

[0093] The tessellation control processing unit 508 treats the input vertices as control points for the geometric patch. The control points are transformed from an input representation from a patch (e.g., a basis of the patch) to a representation suitable for use in surface evaluation by the tessellation evaluation processing unit 512. The tessellation control processing unit 508 may also calculate tessellation factors for the edges of the geometric patch. The tessellation factors are applied to a single edge and quantize the view-dependent level of detail associated with the edge. The tessellation unit 510 is configured to receive the tessellation factors for the edges of the patch and tessellate the patch into a plurality of geometric primitives such as lines, triangles, or quadrilateral primitives, which are transmitted to the tessellation evaluation processing unit 512. The tessellation evaluation processing unit 512 operates on the parameterized coordinates of the subdivided patch to generate a surface representation and vertex attributes for each vertex associated with the geometric primitive.

[0094] A second instance of primitive assembler 514 receives vertex attributes from tessellation evaluation processing unit 512, reads stored vertex attributes as needed, and builds graphics primitives for processing by geometry processing unit 516. Geometry processing unit 516 is a programmable execution unit that executes geometry shader programs to transform graphics primitives received from primitive assembler 514 as specified by the geometry shader programs. In one embodiment, geometry processing unit 516 is programmed to subdivide a graphics primitive into one or more new graphics primitives and to compute parameters for rasterizing the new graphics primitives.

[0095] In some embodiments, the geometry processing unit 516 may add or delete elements in the geometry stream. The geometry processing unit 516 outputs parameters and vertices specifying new graphics primitives to the primitive assembler 518. The primitive assembler 518 receives the parameters and vertices from the geometry processing unit 516 and constructs the graphics primitives for processing by the viewport scaling, picking, and clipping unit 520. The geometry processing unit 516 reads data stored in the parallel processor memory or the system memory for use in processing the geometry data. The viewport scaling, picking, and clipping unit 520 performs clipping, picking, and viewport scaling, and outputs the processed graphics primitives to the rasterizer 522.

[0096] The rasterizer 522 may perform depth sorting and other depth-based optimizations. The rasterizer 522 also performs scan conversion on new graphics primitives to generate fragments, and outputs those fragments and associated coverage data to the fragment / pixel processing unit 524. The fragment / pixel processing unit 524 is a programmable execution unit configured to execute a fragment shader program or a pixel shader program. The fragment / pixel processing unit 524 transforms the fragments or pixels received from the rasterizer 522 as specified by the fragment or pixel shader program. For example, the fragment / pixel processing unit 524 may be programmed to perform the following operations to generate shaded fragments or pixels output to the raster operation unit 526, including but not limited to texture mapping, shading, blending, texture correction, and perspective correction. The fragment / pixel processing unit 524 may read data stored in a parallel processor memory or system memory for use in processing fragment data. The fragment or pixel shader program may be configured to shade at a sample, pixel, tile, or other granularity (depending on the sampling rate configured for the processing unit).

[0097] Raster operations unit 526 is a processing unit that performs raster operations including, but not limited to, stenciling, z-testing, blending, and the like, and outputs pixel data as processed graphics data for storage in graphics memory (e.g., parallel processor memory 222 in FIG. 2 and / or as Figure 1 The raster operations unit 526 may be configured to compress the z or color data written to the memory and to decompress the z or color data read from the memory.

[0098] Topological Shader Technology Now go to Figure 6, a graphics pipeline 600 is shown in which a topology shader 602 receives an object description 604, for example, from a host processor (e.g., a central processing unit / CPU), an application programming interface (API), a driver, etc. The object description 604 may contain general information about the type of object to be rendered (e.g., a sphere with a determined center and radius, a person with a determined skeletal shape, etc.) without specifying the topology of the object to be displayed. The topology shader 602 may receive the object description 604, generate a set of polygons 606 (e.g., triangles, primitives) based on the object description, and send the set of polygons 606 to a vertex shader 608 ("VS"). Thus, the topology shader 602 may determine the proper topology of the outer surface of a sphere given only the center coordinates and radius of the sphere. Similarly, the topology shader 602 may determine the proper topology of the skin of a person / character in the scene given only the skeletal shape and depth of the person / character.

[0099] As will be discussed in greater detail, generation of the set of polygons 606 may involve detecting a lack of visibility conditions relative to one or more polygons, and excluding polygons from the set of polygons 606 that are sent to the VS 608. Lack of visibility conditions may include, for example, an occluded state (e.g., a polygon is behind another polygon in a three-dimensional / 3D scene), an off-screen state (e.g., a polygon is outside the field of view), etc. Generating the set of polygons 606 may further include determining a level of detail (LOD) associated with an object description based on depth information (e.g., a sphere center z coordinate). The depth information may be obtained from one or more visibility samples and / or the object description associated with the polygon.

[0100] With respect to LODs, the topological data of the scene may be subdivided into an octree data structure, where each internal node has eight child nodes (e.g., partitioning the 3D space / model by recursively subdividing the 3D space / model into eight octants). In such cases, topological shader 602 may be invoked for the identified child octree (e.g., LOD). Enabling graphics pipeline 600 to determine the topology of an object being rendered may increase flexibility (e.g., through variable topology), improve efficiency, increase performance, and reduce power consumption by reducing the number of memory transactions associated with transferring topological data from a host processor to graphics pipeline 600.

[0101] The vertex shader 608 can process the vertices of the set of polygons 606 by performing operations such as transformation, skinning, and lightening. The vertex shader 608 can produce the same number of vertices that it takes as input. In addition, the hull shader 610 ("HS") can process control points that define low-order surfaces such as lines, triangles, or quadrilaterals. As output, the HS 610 can produce high-order geometry "patches" and patch constants, which are passed to the fixed-function tessellator 612. The tessellator 612 can pre-process the domain represented by the output of the HS 610. As output, the tessellator 612 can create a sampling pattern for the domain and a set of small primitives (e.g., points, lines, triangles) that connect the samples. The illustrated pipeline 600 also includes a domain shader 614 ("DS"), which processes the high-order geometry patches from the HS 610 together with the tessellation factors from the tessellator 612. The tessellation factors may include tessellator input factors and output factors. As output, DS 614 may calculate the vertex positions of points on the output patch that combines the tessellation factors.

[0102] Additionally, a geometry shader 616 ("GS") may process an entire primitive (e.g., a point, line, or triangle) along with optional vertex data for edge-adjacent primitives. Unlike VS 608, GS 616 may generate more or fewer primitives than it takes as input. Pipeline 600 may also include a pixel shader 618 ("PS") that processes rasterized primitives along with interpolated vertex data to generate per-pixel values ​​(such as color and depth). The illustrated pipeline 600 therefore does not rely solely on tessellator 612 to generate a surface representation of the scene to be rendered.

[0103] Figure 7 The diagram illustrates a topology shader 602 ( Figure 6) is used to process the LOD analysis by a topology shader of the octree. In the illustrated example, a sphere is represented at a relatively high LOD (e.g., a high-fidelity topology including a relatively large number of polygons) at a first level 700 ("level_0") of the octree. If the sphere has, for example, a short distance to the camera and / or the user (e.g., a foreground object), the first level 700 may be selected. In contrast, a second level 702 ("level_1") of the octree may represent the sphere at an intermediate LOD (e.g., including an intermediate number of polygons). Thus, if the sphere has, for example, an intermediate distance to the camera and / or the user, the second level 702 may be selected. Additionally, the sphere may be represented at a relatively low LOD (e.g., a low-fidelity topology including a relatively small number of polygons) at a third level 704 ("level_2") . If the sphere has, for example, a long distance to the camera and / or the user (e.g., a background object), the third level 704 may be selected. The topology shader may therefore be called at the selected sub-octree primarily based on the depth information. As already noted, the topology shader can determine the appropriate LOD based on limited / based information in the object description.

[0104] Determining the LOD may also involve interpolation between two LODs. For example, an object description may indicate support for three graphical levels 700, 702, 704, where the topology shader selects a level between the first level 700 and the second level 702 based on the distance of the sphere from the camera / user. In such a case, the selected LOD may include more polygons than the second level 702 and fewer polygons than the first level 700 in proportion to the actual distance.

[0105] Figure 8 A field of view 800 is shown relative to a scene to be rendered. In the illustrated example, an object 802 (e.g., a sphere) in the scene is only partially within the field of view. In such a case, one or more polygons 804 of the object 802 may be considered to lack a visibility condition because the one or more polygons 804 of the object 802 are outside the field of view 800 (e.g., in an "off-screen state"). Similarly, even though one or more other polygons 806 are within the field of view 800, they are obscured by polygons located closer to the camera / user, so one or more other polygons 806 may be considered to lack a visibility condition. Again, the topology shader may detect the lack of a visibility condition based on, for example, restricted / based information in the object description obtained from the host processor.

[0106] Fig.9AA method 900 of operating a semiconductor packaging device is shown. The method 900 may be implemented as one or more modules in a set of logic instructions stored in a non-transitory machine or computer readable storage medium, such as a random access memory (RAM), a read-only memory (ROM), a programmable ROM (PROM), firmware, flash memory, etc.; stored in a configurable logic, such as, for example, a programmable logic array (PLA), a field programmable gate array (FPGA), a complex programmable logic device (CPLD); stored in a fixed-functional hardware logic using circuit technology, such as, for example, an application specific integrated circuit (ASIC), a complementary metal oxide semiconductor (CMOS), or a transistor-transistor logic (TTL) technology, or any combination thereof.

[0107] For example, computer program code to perform the operations shown in method 900 may be written in any combination of one or more programming languages, including object-oriented programming languages ​​such as JAVA, SMALLTALK, C++, or the like, and conventional procedural programming languages ​​such as the "C" programming language or similar programming languages. In addition, the logic instructions may include assembler instructions, instruction set architecture (ISA) instructions, machine instructions, machine-dependent instructions, microcode, state setting data, configuration data for integrated circuits, state information of personalized electronic circuits and / or other structural components native to hardware (e.g., host processors, central processing units / CPUs, microcontrollers, etc.).

[0108] The illustrated processing block 902 receives an object description at a topology shader. The object description may provide a general description of an object without describing or specifying the topology of the object. Block 904 may generate a set of polygons based on the object description at the topology shader, wherein the set of polygons may be sent to a vertex shader at block 906.

[0109] Fig. 9B A method 910 for generating a set of polygons is shown. The method 910 may thus generally be incorporated into the already discussed block 904 ( Fig.9A More specifically, method 910 may be implemented as one or more modules in a set of logic instructions stored in a non-transitory machine or computer readable storage medium, such as RAM, ROM, PROM, firmware, flash memory, etc.; stored in configurable logic, such as, for example, PLA, FPGA, CPLD; stored in fixed functionality hardware logic using circuit technology, such as, for example, ASIC, CMOS or TTL technology, or any combination thereof.

[0110] The illustrated processing block 912 determines a level of detail associated with the object description based on the depth information. Block 912 may, for example, include identifying a sub-octree corresponding to the object description, wherein a topology shader is invoked for the identified sub-octree. As already discussed, determining the level of detail may also involve interpolating between two levels of detail. A lack of a visibility condition may be detected relative to one or more polygons at block 914, wherein (one or more) polygons may be excluded from the set of polygons in response to the lack of a visibility condition at block 916. The lack of a visibility condition may include, for example, an occluded state, an off-screen state, etc., or any combination thereof.

[0111] Fig. 10A A computing system 100 with increased performance is shown. In the example shown, a host processor 1002 includes an integrated memory controller (IMC) 1004 that communicates with a system memory 1006 (e.g., DRAM). The host processor 1002 may be coupled to a graphics processor 1008, which may include a graphics pipeline 1016, and an input / output (IO) module 1010. The illustrated graphics processor 1008 is also coupled to a dedicated graphics memory 1022. The IO module 1010 may be coupled to a network controller 1012 (e.g., wireless and / or wired), a display 1014 (e.g., a fixed or head-mounted liquid crystal display / LCD, a light emitting diode / LED display, etc., for visually presenting video of a 3D scene), and a mass storage device 1018 (e.g., flash memory, an optical disk, a solid state drive / SSD).

[0112] System memory 1006 and / or mass storage device 1018 may include instructions 1020 that, when executed by host processor 1002, cause host processor 1002 to generate object descriptions associated with visual content to be presented by display 1014. Additionally, graphics pipeline 1016 of graphics processor 1008 may include a topological shader that performs method 900 ( Fig.9A ) and / or method 910( Fig. 9B ). Thus, the graphics pipeline 1016 may be configured to receive an object description at a topology shader, generate a set of polygons at the topology shader based on the object description, and send the set of polygons to the vertex shader. The illustrated solution thus reduces the number of memory transfers between the system memory 1006 / mass storage 1018 and the graphics memory 1022. Thus, higher efficiency and performance may be achieved while improving quality in the system 1000.

[0113] Fig. 10BA semiconductor package device 1030 (e.g., a chip) is shown including a substrate 1032 (e.g., silicon, sapphire, gallium arsenide) and logic 1034 (1034a-1034c, such as transistor arrays and other integrated circuit / IC components) coupled to the substrate 1032. The logic 1034, which may be implemented in configurable logic and / or fixed functionality logic hardware, includes a graphics processor 1034a, a host processor 1034b, and an IO module 1034c. The logic 1034 may generally implement the method 900 ( Fig.9A ) and / or method 910( Fig. 9B Thus, the logic 1034 may receive an object description at a topology shader (e.g., of a graphics pipeline), generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader.

[0114] In one example, the logic 1034 detects a lack of visibility conditions (e.g., blocked state, off-screen state) with respect to one or more polygons and excludes the one or more polygons from the set of polygons in response to the lack of visibility conditions. Additionally, the logic 1034 may be configured to determine a level of detail associated with the object description, for example, by identifying a child octree corresponding to the object description. The logic 1034 may also interpolate between two levels of detail.

[0115] Head-Mounted Display System Overview Fig.11 A head mounted display (HMD) system 1100 is shown being worn by a user while experiencing an immersive environment, such as, for example, a virtual reality (VR) environment, an augmented reality (AR) environment, a multiplayer three-dimensional (3D) game, etc. In the example shown, one or more straps 1120 hold a frame 1102 of the HMD system 1100 in front of the user's eyes. Accordingly, a left eye display 1104 is positioned to be viewed by the user's left eye and a right eye display 1106 is positioned to be viewed by the user's right eye. In certain examples, such as, for example, a smartphone worn by a user, the left eye display 1104 and the right eye display 1106 may be optionally integrated into a single display. In the case of AR, the displays 1104, 1106 may be see-through displays that allow the user to view the physical environment while other rendered content (e.g., virtual characters, informational annotations, heads-up display / HUD) is presented above a live feed of the physical environment.

[0116] In one example, the frame 1102 includes a left bottom looking camera 1108 to capture images from an area generally in front of the user and below the left eye (e.g., a left hand gesture). Additionally, a right bottom looking camera 1110 can capture images from an area generally in front of the user and below the right eye (e.g., a right hand gesture). The illustrated frame 1102 also includes a left front looking camera 1112 and a right front looking camera 1114 to capture images in front of the user's left and right eyes, respectively. The frame 1102 may also include a left side looking camera 1116 to capture images from an area to the left of the user, and a right side looking camera 1118 to capture images from an area to the right of the user.

[0117] Images captured by cameras 1108, 1110, 1112, 1114, 1116, 1118, which may have overlapping fields of view, may be used to detect gestures made by the user and to analyze and / or reproduce the external environment on displays 1104, 1106. In one example, the detected gestures are used by a graphics processing architecture (e.g., internal and / or external) to render and / or control a virtual representation of the user in a 3D game. In fact, overlapping fields of view may enable the capture of gestures made by other individuals (e.g., in a multiplayer game), where the gestures of other individuals may also be used to render / control an immersive experience. Overlapping fields of view may also enable the HMD system 1100 to automatically detect obstructions or other hazards near the user. Such an approach is particularly advantageous in advanced driver assistance system (ADAS) applications.

[0118] In one example, a left bottom looking camera 1108 and a right bottom looking camera 1110 provided with overlapping fields of view provide a stereoscopic view with increased resolution. The increased resolution can in turn enable very similar user movements to be distinguished from each other (e.g., with sub-millimeter accuracy). The result can be an improved performance of the HMD system 1100 with respect to reliability. In fact, the solution shown is useful in a variety of applications, such as, for example, coloring information in an AR setting, exchanging virtual tools / devices between users in a multi-user environment, rendering virtual items (e.g., weapons, swords, personnel), etc. The postures of other objects, limbs, and / or body parts can also be detected and used to render / control the virtual environment. For example, myelogram signals, electroencephalogram signals, eye tracking, breathing or panting, hand movements, etc. can be tracked in real time, whether from the wearer or from another individual in a shared environment. Images captured by cameras 1108, 1110, 1112, 1114, 1116, 1118 can also be used as contextual input. For example, it may be determined that the user is indicating a specific word to be edited or a specific key to be pressed in a word processing application, a specific weapon to be deployed or a direction of travel in a game, and so on.

[0119] In addition, the images captured by the cameras 1108, 1110, 1112, 1114, 1116, 1118 can be used to implement shared communication or networked interaction in equipment operation, medical training and / or remote / teleoperation guidance applications. Task-specific gesture libraries or neural network machine learning can enable tool identification and feedback on tasks. For example, virtual tools converted into remote, real actions can be enabled. In another example, the HMD system 1100 converts the manipulation of a virtual drill within a virtual scene into remote operation of a drill on a robotic device deployed to search for collapsed buildings. Moreover, the HMD system 1100 can be programmable to the extent that it includes, for example, a protocol that enables a user to add a new gesture to a list of identifiable gestures associated with a user's action.

[0120] In addition, the various cameras in the HMD 1100 can be configurable to detect spectral frequencies outside the visible wavelengths of the spectrum. The multispectral imaging capabilities in the input cameras allow positional tracking of users and / or objects by eliminating non-essential image features (e.g., background noise). For example, in augmented reality (AR) applications such as surgery, instruments and equipment can be tracked by their infrared reflectivity without the need for additional tracking aids. Moreover, the HMD 1100 can be employed in low-visibility situations, where the "live feeds" from the various cameras can be improved or enhanced by computer analysis and displayed to the user as visual or audio cues.

[0121] The HMD system 1100 may also forgo performing any type of data communication with a remote computing system or requiring a power line (e.g., standalone operation mode). In this regard, the HMD system 1100 may be a "cordless" device having a power unit that enables the HMD system 1100 to operate independently of an external power system. Accordingly, a user can play full-featured games without being tethered to another device (e.g., a game console) or a power supply. In a word processing example, the HMD system 1100 presents a virtual keyboard and / or a virtual mouse on displays 1104 and 1106 to provide a virtual desktop or word processing scene. Thus, gesture recognition data captured by one or more of the cameras may represent user typing activity on a virtual keyboard or movement of a virtual mouse. Advantages include, but are not limited to, portability and the freedom of privacy of a virtual desktop to isolate nearby individuals. The underlying graphics processing architecture may support compression and / or decompression of video and audio signals. Moreover, providing separate images to the user's left and right eyes may facilitate rendering, generation, and / or perception of 3D scenes. The relative positions of the left eye display 1104 and the right eye display 1106 may also be adjustable to match variations in interocular spacing between different users.

[0122] Fig.11The number of cameras shown in is only to facilitate discussion. In fact, depending on the environment, the HMD system 1100 may include less than six or more than six cameras.

[0123] Functional components of an HMD system Fig.12 The HMD system is shown in more detail. In the example shown, the framework 1102 includes a power unit 1200 (e.g., battery power, adapter) that applies power to the HMD system. The illustrated framework 1102 also includes a motion tracking module 1220 (e.g., accelerometer, gyroscope), wherein the motion tracking module 1220 provides motion tracking data, orientation data, and / or position data to the processor system 1204. The processor system 1204 may include a network adapter 1224 coupled to the I / O bridge 1206. The I / O bridge 1206 can enable communication between the network adapter 1224 and various components such as, for example, the audio input module 1210, the audio output module 1208, the display device 1207, the input camera 1202, and the like.

[0124] In the example shown, the audio input module 1210 includes a right audio input 1218 and a left audio input 1216 that detect sounds that can be processed for the purpose of recognizing voice commands of the user and nearby individuals. Voice commands recognized in the captured audio signals can enhance gesture recognition during modal switching and other applications. Moreover, the captured audio signals can provide 3D information for enhancing the immersive experience.

[0125] The audio output module 1208 may include a right audio output 1214 and a left audio output 1212. The audio output module 1208 may deliver sound to the ears of the user and / or other nearby individuals. The audio output module 1208 may be in the form of earplugs, on-ear speakers, cover-ear speakers, loudspeakers, etc. or any combination thereof, and the audio output module 1208 may deliver stereo and / or 3D audio content to the user (e.g., spatial positioning). The illustrated framework 1102 also includes a wireless module 1222, which may facilitate communication between the HMD system and various other systems (e.g., computers, wearable devices, game consoles). In one example, the wireless module 1222 communicates with the processor system 1204 via a network adapter 1224.

[0126] The display device 1207 shown includes a left eye display 1104 and a right eye display 1106, wherein the visual content presented on the displays 1104, 1106 may be obtained from the processor system 1204 via the I / O bridge 1206. The input cameras 1202 may include the left looking camera 1116, the right looking camera 1118, the lower left looking camera 1108, the left front looking camera 1112, the right front looking camera 1114, and the lower right looking camera 1110 already discussed.

[0127] Now turn to Fig.13 , a general processing cluster (GPC) 1300 is shown. The GPC 1300 shown may be incorporated into a processor system such as, for example, the processor system 1204 ( Fig.12 ) in a processing system of a GPC 1300. GPC 1300 may include a pipeline manager 1302 that communicates with a scheduler. In one example, the pipeline manager 1302 receives tasks from the scheduler and distributes the tasks to one or more streaming multiprocessors (SMs) 1304. Each SM 1304 may be configured to process thread groups, where a thread group may be viewed as a plurality of related threads that perform the same or similar operations on different input data. Thus, each thread in a thread group may be assigned to a specific SM 1304. In another example, the number of threads may be greater than the number of execution units in SM 1304. In this regard, the threads in a thread group may operate in parallel. The pipeline manager 1302 may also specify the destination of the processed data to a work distribution crossbar 1308 that communicates with a memory crossbar.

[0128] Thus, as each SM 1304 passes processed tasks to the work distribution crossbar 1308, the processed tasks may be provided to another GPC 1300 for further processing. The output of the SM 1304 may also be sent to a pre-raster operation (preROP) unit 1314, which in turn directs the data to one or more raster operation units, or performs other operations (e.g., performing address translation, organizing picture color data, blending colors, etc.). The SM 1304 may include an internal level 1 (L1) cache (not shown) in which the SM 1304 may store data. The SM 1304 may also have access to a level 1.5 (L1.5) cache 1306 and a level 2 (L2) cache (not shown) via a memory management unit (MMU) 1310. The MMU 1310 may map virtual addresses to physical addresses. In this regard, the MMU 1310 may include page table entries (PTEs) used to map virtual addresses to physical addresses of tiles, memory pages, and / or cache line indexes. The illustrated GPU 1300 also includes a texture unit 1312 .

[0129] Graphics pipeline architecture Now turn to Fig.14 , a graphics pipeline 1400 is shown. In the example shown, the world space pipeline 1420 includes a primitive distributor (PD) 1402. The PD 1402 may collect vertex data associated with high-order services, graphics primitives, triangles, etc., and transmit the vertex data to a vertex attribute fetch unit (VAF) 1404. The VAF 1404 may retrieve vertex attributes associated with each incoming vertex from a shared memory and store the vertex data and the associated vertex attributes in the shared memory.

[0130] The illustrated world space pipeline 1420 also includes a vertex, tessellation, geometry processing unit (VTG) 1406. The VTG 1406 may include, for example, a vertex processing unit, a tessellation initialization processing unit, a task distributor, a task generation unit, a topology generation unit, a geometry processing unit, a tessellation processing unit, the like, or any combination thereof. In one example, the VTG 1406 is a programmable execution unit configured to execute geometry programs, tessellation programs, and vertex shader programs. The program executed by the VTG 1406 may process vertex data and vertex attributes received from the VAF 1404. Moreover, the program executed by the VTG 1406 may generate graphics primitives, color values, surface normalization factors, and transparency values ​​at each vertex of the graphics primitives for further processing within the graphics processing pipeline 1400.

[0131] The vertex processing unit of VTG 1406 may be a programmable execution unit that executes a vertex shader program, lighting and transforming vertex data as specified by the vertex shader program. For example, the vertex processing unit may be programmed to transform vertex data from an object-based coordinate representation (e.g., object space) to an alternative coordinate system such as world space or normalized device coordinate (NDC) space. In addition, the vertex processing unit may read vertex data and vertex attributes stored in a shared memory by VAF 1404, and process the vertex data and vertex attributes. In one example, the vertex processing unit stores the processed vertices in a shared memory.

[0132] The tessellation initialization processing unit (e.g., hull shader, tessellation control shader) may execute a tessellation initialization shader program. In one example, the tessellation initialization processing unit processes the vertices generated by the vertex processing unit and generates graphics primitives sometimes referred to as "patches". The tessellation initialization processing unit may also generate various patch attributes, wherein the patch data and patch attributes are stored in a shared memory. The task generation unit of the VTG 1406 may retrieve data and attributes of vertices and patches from the shared memory. In one example, the task generation unit generates tasks for processing vertices and patches for processing by a later stage in the graphics processing pipeline 1400.

[0133] The tasks generated by the task generation unit may be redistributed by the task distributor of VTG 1406. For example, the tasks generated by various instances of vertex shader programs and tessellation initialization programs may vary significantly between one graphics processing pipeline 1400 and another. Accordingly, the task distributor may redistribute these tasks so that each graphics processing pipeline 1400 has approximately the same workload during later pipeline stages.

[0134] As already noted, VTG 1406 may also include a topology generation unit. In one example, the topology generation unit retrieves tasks distributed by the task distributor, indexes vertices including vertices associated with patches, and calculates tessellation vertices and coordinates (UVs) of indices that connect tessellation vertices to form graphics primitives. The indexed vertices may be stored in a shared memory by the topology generation unit. The tessellation processing unit of VTG 1406 may be configured to execute a tessellation shader program (e.g., a domain shader, a tessellation evaluation shader). The tessellation processing unit may read input data from the shared memory and write output data to the shared memory. The output data may be passed from the shared memory to a geometry processing unit (e.g., a next shader level) as input data.

[0135] The geometry processing unit of VTG 1406 may execute geometry shader programs to transform graphics primitives (e.g., triangles, line segments, points, etc.). In one example, vertices are grouped to construct graphics primitives, where the geometry processing unit subdivides the graphics primitives into one or more new graphics primitives. The geometry processing unit may also compute parameters that may be used to rasterize the new graphics primitives, such as, for example, plain equation coefficients.

[0136] The illustrated world space pipeline 1420 also includes a viewport scaling, picking, and clipping unit (VPC) 1408 that receives parameters and vertices that specify new graphics primitives from the VTG 1406. In one example, the VPC 1408 performs clipping, flanging, perspective correction, and viewport transformation to identify graphics primitives that are potentially viewable in the final rendered image. The VPC 1408 may also identify graphics primitives that may not be viewable.

[0137] The graphics processing pipeline 1400 may also include a tile unit 1410 coupled to the world space pipeline 1420. The tile unit 1410 may be a graphics primitive classification engine, wherein the graphics primitives are processed in the world space pipeline 1420 and then transmitted to the tile unit 1410. In this regard, the graphics processing pipeline 1400 may also include a screen space pipeline 1422, wherein the screen space may be divided into cache tiles. Each cache tile may therefore be associated with a portion of the screen space. For each graphics primitive, the tile unit 1410 may identify a set of cache tiles that intersect the graphics primitive (e.g., "tiles"). After tiling a plurality of graphics primitives, the tile unit 1410 may process the graphics primitives cache tile by cache tile. In one example, the graphics primitives associated with a particular cache tile are transmitted to the setup unit 1412 in the screen space pipeline 1422 one tile at a time. Graphics primitives that intersect multiple cache tiles may be processed once in the world-space pipeline 1420 and transferred to the screen-space pipeline 1422 multiple times.

[0138] In one example, the setup unit 1412 receives vertex data from the VPC 1408 via the tiling unit 1410 and computes parameters associated with the graphics primitives. The parameters may include, for example, edge equations, partial plane equations, and depth plane equations. The screen space pipeline 1422 may also include a rasterizer 1414 coupled to the setup unit 1412. The rasterizer may scan convert new graphics primitives and transmit fragments and coverage data to a pixel shading unit (PS) 1416. The rasterizer 1414 may also perform Z-picking and other Z-based optimizations.

[0139] The PS 1416, which can access the shared memory, can execute a fragment shader program that transforms the fragments received from the rasterizer 1414. More specifically, the fragment shader program can shade the fragments at a pixel level granularity (e.g., working as a pixel shader program). In another example, the fragment shader program shades the fragments at a sample level granularity, where each pixel includes multiple samples and each sample represents a portion of a pixel. Moreover, depending on the environment (e.g., sampling rate), the fragment shader program can shade the fragments at any other granularity. The PS 1416 can perform blending, shading, perspective correction, texture mapping, etc. to generate shaded fragments.

[0140] The illustrated screen space pipeline 1422 also includes a raster operations unit (ROP) 1418, which may perform operations such as, for example, stencil printing, Z testing, blending, etc. The ROP 1418 may then transmit the pixel data as processed graphics data to one or more rendered targets (e.g., graphics memory). The ROP 1418 may be configured to compress Z or color data written to memory and decompress Z or color data read from memory. The location of the ROP 1418 may vary depending on the environment.

[0141] Graphics processing pipeline 1400 may be implemented by one or more processing elements. For example, VTG 1406 and / or PS 1416 may be implemented in one or more SMs, PD 1402, VAF 1404, VPC 1408, tile unit 1410, setup unit 1412, rasterizer 1414, and / or ROP 1418 may be implemented in a processing element of a specific GPC along with a corresponding partition unit. Graphics processing pipeline 1400 may also be implemented in fixed functionality hardware logic. In fact, graphics processing pipeline 1400 may be implemented in a PPU.

[0142] Thus, the illustrated world space pipeline 1420 processes graphics objects in 3D space, where the position of each graphics object relative to other graphics objects and relative to a 3D coordinate system is known. In contrast, the screen space pipeline 1422 may process graphics objects that have been projected from a 3D coordinate system onto a 2D planar surface representing the surface of a display device. In addition, the world space pipeline 1420 may be divided into an alpha stage pipeline and a beta stage pipeline, wherein the alpha stage pipeline includes pipeline stages from the PD 1402 to the task generation unit. The beta stage pipeline may include pipeline stages from the topology generation unit to the VPC 1408. In such a case, the graphics processing pipeline 1400 may perform a first set of operations (e.g., a single thread, a thread group, a plurality of thread groups acting in concert) in the alpha stage pipeline and a second set of operations (e.g., a single thread, a thread group, a plurality of thread groups acting in concert) in the beta stage pipeline.

[0143] If multiple graphics processing pipelines 1400 are in use, the vertex data and vertex attributes associated with a set of graphics objects may be partitioned so that each graphics processing pipeline 1400 has a similar workload throughout the alpha stage. Accordingly, the alpha stage processing may substantially expand the amount of vertex data and vertex attributes, so that the amount of vertex data and vertex attributes generated by the task generation units is significantly greater than the amount of vertex data and vertex attributes processed by the PD 1402 and the VAF 1404. Moreover, even when the alpha stage is started with the same number of attributes, the task generation units associated with different graphics processing pipelines 1400 may generate vertex data and vertex attributes with different quality levels. In such cases, the task distributor may redistribute the attributes generated by the alpha stage pipelines so that each graphics processing pipeline 1400 has approximately the same workload at the beginning of the beta stage pipeline.

[0144] Now turn to Fig.15 , a stream delivery multiprocessor (SM) 1500 is shown. The illustrated SM 1500 includes K scheduler units 1504 coupled to an instruction cache 1502, wherein each scheduler unit 1504 receives a thread block array from a pipeline manager (not shown) and manages instruction scheduling of one or more thread blocks in each active thread block array. The scheduler unit 1504 can schedule threads for execution in parallel thread groups, wherein each group can be referred to as a "thread warp". Thus, each thread warp may include, for example, sixty-four threads. In addition, the scheduler unit 1504 can manage a plurality of different thread blocks, assigning thread blocks to thread warps for execution. The scheduler unit may then schedule instructions from a plurality of different thread warps on various functional units during each clock cycle. Each scheduler unit 1504 may include one or more instruction dispatch units 1522, wherein each dispatch unit 1522 transmits instructions to one or more of the functional units. The number of dispatch units 1522 may vary depending on the environment. In the example shown, the scheduler unit 1504 includes two dispatch units 1522 that enable two different instructions from the same warp to be dispatched during each clock cycle.

[0145] SM 1500 may also include a register file 1506. Register file 1506 may include a set of registers that are divided between functional units so that each functional unit is assigned a dedicated portion of register file 1506. Register file 1506 may also be divided between different thread warps being executed by SM 1500. In one example, register file 1506 provides temporary storage for operands of data paths connected to functional units. The illustrated SM 1500 also includes L processing cores 1508, where L may be a relatively large number (e.g., 192). Each core 1508 may be a pipelined single-precision processing unit that includes a floating-point arithmetic logic unit (e.g., IEEE 754-2008) and an integer arithmetic logic unit.

[0146] The illustrated SM 1500 also includes M double precision units (DPUs) 1510, N special function units (SFUs) 1512, and P load / store units (LSUs) 1514. Each DPU 1510 can implement double precision floating point arithmetic and each SFU 1512 can perform special functions such as, for example, rectangular copy pixel blending. In addition, each LSU 1514 can implement load and store operations between shared memory 1518 and register file 1506. In one example, the load and store operations are implemented through J texture units / L1 caches 1520 and interconnect network 1516. In one example, the J texture units / L1 caches 1520 are also coupled to a crossbar switch (not shown). Therefore, the interconnection network 1516 can connect each of the functional units to the register file 1506 and the shared memory 1518. In one example, the interconnection network 1516 acts as a crossbar switch that connects any of the functional units to any register in the register file 1506.

[0147] SM 1500 may be implemented within a graphics processor (e.g., a graphics processing unit / GPU), where a texture unit / L1 cache 1520 may access a texture map from memory and sample the texture map to produce sampled texture values ​​for use in a shader program. Texture operations performed by texture unit / L1 cache 1520 include, but are not limited to, mipmap-based anti-aliasing.

[0148] Additional System Overview Examples Fig.1616 is a block diagram of a processing system 1600 according to an embodiment. In various embodiments, the system 1600 includes one or more processors 1602 and one or more graphics processors 1608, and may be a server system, a single processor desktop system, or a multi-processor workstation system having a large number of processors 1602 or processor cores 1607. In one embodiment, the system 1600 is a processing platform incorporated into a system on a chip (SoC) integrated circuit for use in a mobile, handheld, or embedded device.

[0149] Embodiments of system 1600 may include or be incorporated into the following: a server-based gaming platform, a gaming console (including gaming and media consoles, mobile gaming consoles, handheld gaming consoles, or online gaming consoles). In some embodiments, system 1600 is a mobile phone, a smart phone, a tablet computing device, or a mobile Internet device. Data processing system 1600 may also include, be coupled to, or be integrated into the following: a wearable device, such as a smart watch wearable device, a smart eye wearable device, an augmented reality device, or a virtual reality device. In some embodiments, data processing system 1600 is a television or set-top box device having one or more processors 1602 and a graphical interface generated by one or more graphics processors 1608.

[0150] In some embodiments, the one or more processors 1602 each include one or more processor cores 1607 for processing instructions, which perform the operation of the system and user software when executed. In some embodiments, each of the one or more processor cores 1607 is configured to process a specific instruction set 1609. In some embodiments, the instruction set 1609 can facilitate complex instruction set computing (CISC), reduced instruction set computing (RISC), or computing via very long instruction words (VLIW). Multiple processor cores 1607 can each process different instruction sets 1609, and the instruction set may include instructions for facilitating emulation of other instruction sets. The processor core 1607 may also include other processing devices, such as a digital signal processor (DSP).

[0151] In some embodiments, the processor 1602 includes a cache memory 1604. Depending on the architecture, the processor 1602 may have a single internal cache or multiple levels of internal cache. In some embodiments, the cache memory is shared among various components of the processor 1602. In some embodiments, the processor 1602 also uses an external cache (e.g., a level 3 (L3) cache or a last level cache (LLC)) (not shown), which may be shared among the processor core 1607 using known cache coherence techniques. A register file 1606 is additionally included in the processor 1602, and the register file may include different types of registers (e.g., integer registers, floating point registers, status registers, and instruction pointer registers) for storing different types of data. Some registers may be general purpose registers, while other registers may be specific to the design of the processor 1602.

[0152] In some embodiments, the processor 1602 is coupled to a processor bus 1610 component for transmitting communication signals (such as address, data or control signals) between the processor 1602 and other components in the system 1600. In one embodiment, the system 1600 uses an exemplary 'hub' system architecture, including a memory controller hub 1616 and an input output (I / O) controller hub 1630. The memory controller hub 1616 facilitates communication between memory devices and other components of the system 1600, while the I / O controller hub (ICH) 1630 provides connections to I / O devices via a local I / O bus. In one embodiment, the logic of the memory controller hub 1616 is integrated within the processor.

[0153] The memory device 1620 may be a dynamic random access memory (DRAM) device, a static random access memory (SRAM) device, a flash memory device, a phase change memory device, or some other memory device having suitable properties to act as a process memory. In one embodiment, the memory device 1620 may operate as a system memory of the system 1600 to store data 1622 and instructions 1621 for use when the one or more processors 1602 execute applications or processes. The memory controller hub 1616 is also coupled to an optional external graphics processor 1612, which may communicate with one or more graphics processors 1608 in the processor 1602 to perform graphics and media operations.

[0154] In some embodiments, the ICH 1630 enables peripheral devices to connect to the memory device 1620 and the processor 1602 via a high-speed I / O bus. The I / O peripheral devices include, but are not limited to, an audio controller 1646, a firmware interface 1628, a wireless transceiver 1626 (e.g., Wi-Fi, Bluetooth), a data storage device 1624 (e.g., a hard drive, flash memory, etc.), and a traditional I / O controller 1640 for coupling traditional (e.g., Personal System 2 (PS / 2)) devices to the system. One or more Universal Serial Bus (USB) controllers 1642 connect input devices (such as a keyboard and mouse 1644 combination). A network controller 1634 may also be coupled to the ICH 1630. In some embodiments, a high-performance network controller (not shown) is coupled to the processor bus 1610. It will be appreciated that the system 1600 shown is exemplary and not limiting, as other types of data processing systems configured in different ways may also be used. For example, the I / O controller hub 1630 may be integrated within the one or more processors 1602 , or the memory controller hub 1616 and the I / O controller hub 1630 may be integrated into a discreet external graphics processor (such as the external graphics processor 1612 ).

[0155] Fig.17 is a block diagram of an embodiment of a processor 1700 having one or more processor cores 1702A- 1702N, an integrated memory controller 1714 , and an integrated graphics processor 1708 . Fig.17 Those elements in the figure having the same reference numbers (or names) as those of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto. Processor 1700 may include additional cores up to and including additional core 1702N represented by a dashed box. Each of processor cores 1702A-1702N includes one or more internal cache units 1704A-1704N. In some embodiments, each processor core is also able to access one or more shared cache units 1706.

[0156] Internal cache units 1704A-1704N and shared cache unit 1706 represent a cache memory hierarchy within processor 1700. The cache memory hierarchy may include at least one level of instruction and data cache within each processor core and one or more levels of shared intermediate level caches (such as level 2 (L2), level 3 (L3), level 4 (L4), or other levels of cache), where the highest level cache in front of external memory is classified as LLC. In some embodiments, cache coherence logic maintains coherence between the various cache units 1706 and 1704A-1704N.

[0157] In some embodiments, the processor 1700 may also include a set of one or more bus controller units 1716 and a system agent core 1710. The one or more bus controller units 1716 manage a set of peripheral buses, such as one or more peripheral component interconnect buses (e.g., PCI, PCI Express). The system agent core 1710 provides management functionality for various processor components. In some embodiments, the system agent core 1710 includes one or more integrated memory controllers 1714 to manage access to various external memory devices (not shown).

[0158] In some embodiments, one or more of the processor cores 1702A-1702N include support for simultaneous multithreading. In such embodiments, the system agent core 1710 includes components for coordinating and operating the cores 1702A-1702N during multithreaded processing. The system agent core 1710 may additionally include a power control unit (PCU) that includes logic and components for regulating the power state of the processor cores 1702A-1702N and the graphics processor 1708.

[0159] In some embodiments, the processor 1700 further includes a graphics processor 1708 for performing graphics processing operations. In some embodiments, the graphics processor 1708 is coupled to a set of shared cache units 1706 and a system agent core 1710 (including the one or more integrated memory controllers 1714). In some embodiments, a display controller 1711 is coupled to the graphics processor 1708 to drive the graphics processor output to one or more coupled displays. In some embodiments, the display controller 1711 can be a separate module coupled to the graphics processor via at least one interconnect, or can be integrated within the graphics processor 1708 or the system agent core 1710.

[0160] In some embodiments, a ring-based interconnect unit 1712 is used to couple the internal components of the processor 1700. However, alternative interconnect units may be used, such as point-to-point interconnects, switched interconnects, or other technologies, including those well known in the art. In some embodiments, the graphics processor 1708 is coupled to the ring interconnect 1712 via an I / O link 1713.

[0161] Exemplary I / O links 1713 represent at least one of a variety of I / O interconnects, including an on-package I / O interconnect that facilitates communication between various processor components and high-performance embedded memory modules 1718 (such as eDRAM modules). In some embodiments, each of processor cores 1702-1702N and graphics processor 1708 use embedded memory modules 1718 as a shared last-level cache.

[0162] In some embodiments, processor cores 1702A-1702N are homogeneous cores that execute the same instruction set architecture. In another embodiment, processor cores 1702A-1702N are heterogeneous in terms of instruction set architecture (ISA), wherein one or more of processor cores 1702A-N execute a first instruction set, while at least one of the other cores executes a subset of the first instruction set or a different instruction set. In one embodiment, processor cores 1702A-1702N are heterogeneous in terms of microarchitecture, wherein one or more cores with relatively higher power consumption are coupled with one or more power cores with lower power consumption. In addition, processor 1700 may be implemented on one or more chips or as a SoC integrated circuit having the components shown in addition to other components.

[0163] Fig.18 1 is a block diagram of a graphics processor 1800, which may be a discrete graphics processing unit, or may be a graphics processor integrated with multiple processing cores. In some embodiments, the graphics processor communicates via a memory-mapped I / O interface to registers on the graphics processor and with commands placed into processor memory. In some embodiments, the graphics processor 1800 includes a memory interface 1814 for accessing memory. The memory interface 1814 may be an interface to local memory, one or more internal caches, one or more shared external caches, and / or to system memory.

[0164] In some embodiments, the graphics processor 1800 also includes a display controller 1802 for driving display output data to a display device 1820. The display controller 1802 includes hardware for one or more overlapping planes of the display and a composition of multiple layers of video or user interface elements. In some embodiments, the graphics processor 1800 includes a video codec engine 1806 for encoding, decoding, or transcoding media to, from, or between one or more media encoding formats, including but not limited to: Moving Picture Experts Group (MPEG) formats (such as MPEG-2), Advanced Video Coding (AVC) formats (such as H.264 / MPEG-4 AVC), and Society of Motion Picture & Television Engineers (SMPTE) 421M / VC-1, and Joint Photographic Experts Group (JPEG) formats (such as JPEG, and Motion JPEG (MJPEG) formats).

[0165] In some embodiments, graphics processor 1800 includes a block map transfer (BLIT) engine 1804 for performing two-dimensional (2D) rasterizer operations, including, for example, bit boundary block transfers. However, in one embodiment, 2D graphics operations are performed using one or more components of a graphics processing engine (GPE) 1810. In some embodiments, graphics processing engine 1810 is a compute engine for performing graphics operations, including three-dimensional (3D) graphics operations and media operations.

[0166] In some embodiments, GPE 1810 includes a 3D pipeline 1812 for performing 3D operations, such as rendering three-dimensional images and scenes using processing functions that act on 3D primitive shapes (e.g., rectangles, triangles, etc.). 3D pipeline 1812 includes programmable and fixed function elements that perform various tasks within the element and / or spawn execution threads to 3D / media subsystem 1815. While 3D pipeline 1812 can be used to perform media operations, embodiments of GPE 1810 also include a media pipeline 1816 that is specifically used to perform media operations, such as video post-processing and image enhancement.

[0167] In some embodiments, the media pipeline 1816 includes fixed function or programmable logic units for performing one or more specialized media operations (such as video decoding acceleration, video deinterlacing, and video encoding acceleration) instead of or on behalf of the video codec engine 1806. In some embodiments, the media pipeline 1816 additionally includes a thread generation unit to generate threads for execution on the 3D / media subsystem 1815. The generated threads perform calculations for the media operations on one or more graphics execution units included in the 3D / media subsystem 1815.

[0168] In some embodiments, the 3D / media subsystem 1815 includes logic for executing threads generated by the 3D pipeline 1812 and the media pipeline 1816. In one embodiment, the pipeline sends thread execution requests to the 3D / media subsystem 1815, which includes thread dispatch logic for arbitrating and dispatching various requests for available thread execution resources. The execution resources include an array of graphics execution units for processing 3D and media threads. In some embodiments, the 3D / media subsystem 1815 includes one or more internal caches for thread instructions and data. In some embodiments, the subsystem also includes shared memory (including registers and addressable memory) to share data between threads and store output data.

[0169] 3D / Media Processing Fig.19 is a block diagram of a graphics processing engine 1910 of a graphics processor in accordance with some embodiments. In one embodiment, GPE 1910 is Fig.18 A version of the GPE 1810 shown in . Fig.19 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0170] In some embodiments, the GPE 1910 is coupled to a command streamer 1903 that provides a command stream to the GPE 3D and media pipelines 1912, 1916. In some embodiments, the command streamer 1903 is coupled to a memory, which may be a system memory, or one or more of an internal cache memory and a shared cache memory. In some embodiments, the command streamer 1903 receives commands from the memory and sends the commands to the 3D pipeline 1912 and / or the media pipeline 1916. The commands are instructions obtained from a circular buffer storing commands for the 3D and media pipelines 1912, 1916. In one embodiment, the circular buffer may further include a batch command buffer storing multiple batches of multiple commands. The 3D and media pipelines 1912, 1916 process the commands by performing operations via logic within the corresponding pipeline or by dispatching one or more execution threads to the execution unit array 1914. In some embodiments, execution unit array 1914 is scalable such that the array includes a variable number of execution units based on the target power and performance level of GPE 1910 .

[0171] In some embodiments, sampling engine 1930 is coupled to a memory (e.g., cache memory or system memory) and execution unit array 1914. In some embodiments, sampling engine 1930 provides a memory access mechanism for execution unit array 1914 that allows execution array 1914 to read graphics and media data from memory. In some embodiments, sampling engine 1930 includes logic for performing specialized image sampling operations for media.

[0172] In some embodiments, the specialized media sampling logic in the sampling engine 1930 includes a denoising / de-interlacing module 1932, a motion estimation module 1934, and an image scaling and filtering module 1936. In some embodiments, the denoising / de-interlacing module 1932 includes logic for performing one or more of a denoising or de-interlacing algorithm on the decoded video data. The de-interlacing logic combines alternating fields of interlaced video content into a single frame of video. The denoising logic reduces or removes data noise from the video and image data. In some embodiments, the denoising logic and de-interlacing logic are motion adaptive and use spatial or temporal filtering based on the amount of motion detected in the video data. In some embodiments, the denoising / de-interlacing module 1932 includes dedicated motion detection logic (e.g., within the motion estimation engine 1934).

[0173] In some embodiments, the motion estimation engine 1934 provides hardware acceleration of video operations by performing video acceleration functions (such as motion vector estimation and prediction) on the video data. The motion estimation engine determines motion vectors that describe the transformation of image data between consecutive video frames. In some embodiments, the graphics processor media codec uses the video motion estimation engine 1934 to perform operations on the video at the macroblock level that would otherwise be too computationally intensive to perform with a general purpose processor. In some embodiments, the motion estimation engine 1934 may be generally used for graphics processor components to assist in video decoding and processing functions that are sensitive or adaptive to the direction or magnitude of motion within the video data.

[0174] In some embodiments, the image scaling and filtering module 1936 performs image processing operations to improve the visual quality of the generated images and videos. In some embodiments, the scaling and filtering module 1936 processes the image and video data during a sampling operation before providing the data to the execution unit array 1914.

[0175] In some embodiments, GPE 1910 includes a data port 1944 that provides an additional mechanism for the graphics subsystem to access memory. In some embodiments, data port 1944 facilitates memory access for operations including render target writes, constant buffer reads, scratch memory space reads / writes, and media surface accesses. In some embodiments, data port 1944 includes a cache memory space for caching accesses to memory. The cache memory can be a single data cache, or multiple caches (e.g., render buffer cache, constant buffer cache, etc.) separated into multiple subsystems that access memory via a data port. In some embodiments, threads executing on execution units in execution unit array 1914 communicate with the data port by exchanging messages via a data distribution interconnect that couples each subsystem of GPE 1910.

[0176] Execution Unit Fig. 20 is a block diagram of another embodiment of a graphics processor 2000 . Fig. 20 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0177] In some embodiments, graphics processor 2000 includes ring interconnect 2002, pipeline front end 2004, media engine 2037, and graphics cores 2080A-2080N. In some embodiments, ring interconnect 2002 couples the graphics processor to other processing units, including other graphics processors or one or more general-purpose processor cores. In some embodiments, the graphics processor is one of many processors integrated into a multi-core processing system.

[0178] In some embodiments, the graphics processor 2000 receives batches of commands via the ring interconnect 2002. The incoming commands are interpreted by a command streamer 2003 in the pipeline front end 2004. In some embodiments, the graphics processor 2000 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2080A-2080N. For 3D geometry processing commands, the command streamer 2003 supplies the commands to the geometry pipeline 2036. For at least some media processing commands, the command streamer 2003 supplies the commands to the video front end 2034, which is coupled to the media engine 2037. In some embodiments, the media engine 2037 includes a video quality engine (VQE) 2030 for video and image post-processing and a multi-format encoding / decoding (MFX) 2033 engine for providing hardware accelerated media data encoding and decoding. In some embodiments, the geometry pipeline 2036 and the media engine 2037 each generate execution threads for thread execution resources provided by at least one graphics core 2080A.

[0179] In some embodiments, the graphics processor 2000 includes scalable thread execution resources featuring modular cores 2080A-2080N (sometimes referred to as core slices), each modular core having multiple sub-cores 2050A-2050N, 2060A-2060N (sometimes referred to as core sub-slices). In some embodiments, the graphics processor 2000 can have any number of graphics cores 2080A to 2080N. In some embodiments, the graphics processor 2000 includes a graphics core 2080A, and the graphics core 2080A has at least a first sub-core 2050A and a second sub-core 2060A. In other embodiments, the graphics processor is a low-power processor with a single sub-core (e.g., 2050A). In some embodiments, the graphics processor 2000 includes multiple graphics cores 2080A-2080N, each graphics core including a group of first sub-cores 2050A-2050N and a group of second sub-cores 2060A-2060N. Each sub-core in the group of first sub-cores 2050A-2050N includes at least a first group of execution units 2052A-2052N and a media / texture sampler 2054A-2054N. Each sub-core in the group of second sub-cores 2060A-2060N includes at least a second group of execution units 2062A-2062N and a sampler 2064A-2064N. In some embodiments, each sub-core 2050A-2050N, 2060A-2060N shares a group of shared resources 2070A-2070N. In some embodiments, the shared resources include a shared cache memory and a pixel operation logic. Other shared resources may also be included in various embodiments of the graphics processor.

[0180] Fig.21Thread execution logic 2100 is shown, including an array of processing elements employed in some embodiments of a GPE. Fig.21 Those elements in the EMBODIMENTS 100 having the same reference numbers (or names) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0181] In some embodiments, the thread execution logic 2100 includes a pixel shader 2102, a thread dispatcher 2104, an instruction cache 2106, a scalable execution unit array (including multiple execution units 2108A-2108N), a sampler 2110, a data cache 2112, and a data port 2114. In one embodiment, the included components are interconnected via an interconnect structure that links to each of the components. In some embodiments, the thread execution logic 2100 includes one or more connections to a memory (such as a system memory or a cache memory) through one or more of the instruction cache 2106, the data port 2114, the sampler 2110, and the execution unit array 2108A-2108N. In some embodiments, each execution unit (e.g., 2108A) is a separate vector processor that is capable of executing multiple simultaneous threads and processing multiple data elements in parallel for each thread. In some embodiments, the execution unit array 2108A-2108N includes any number of separate execution units.

[0182] In some embodiments, execution unit arrays 2108A-2108N are primarily used to execute "shader" programs. In some embodiments, the execution units in arrays 2108A-2108N execute an instruction set that includes native support for many standard 3D graphics shader instructions, so that shader programs from graphics libraries (e.g., Direct 3D and OpenGL) are executed with minimal conversion. The execution units support vertex and geometry processing (e.g., vertex programs, geometry programs, vertex shaders), pixel processing (e.g., pixel shaders, fragment shaders), and general processing (e.g., compute and media shaders).

[0183] Each execution unit in the execution unit array 2108A-2108N operates on an array of data elements. The number of data elements is the "execution size" or number of lanes for an instruction. An execution lane is a logical unit used for flow control, data element access, and masked execution within an instruction. The number of lanes may be independent of the number of physical arithmetic logic units (ALUs) or floating point units (FPUs) of a particular graphics processor. In some embodiments, the execution units 2108A-2108N support integer and floating point data types.

[0184] The execution unit instruction set includes single instruction multiple data (SIMD) instructions. Various data elements can be stored in registers as compact data types, and the execution unit will process various elements based on the data size of the element. For example, when operating on a 256-bit wide vector, the 256-bit vector is stored in a register, and the execution unit operates on the vector as four independent 64-bit compact data elements (data elements of quadruple word length (QW) size), eight independent 32-bit compact data elements (data elements of double word length (DW) size), sixteen independent 16-bit compact data elements (data elements of word length (W) size), or thirty-two independent 8-bit data elements (data elements of byte (B) size). However, different vector widths and register sizes are possible.

[0185] One or more internal instruction caches (e.g., 2106) are included in the thread execution logic 2100 to cache thread instructions for the execution unit. In some embodiments, one or more data caches (e.g., 2112) are included to cache thread data during thread execution. In some embodiments, a sampler 2110 is included to provide texture sampling for 3D operations and media sampling for media operations. In some embodiments, the sampler 2110 includes specialized texture or media sampling functionality to process texture or media data during the sampling process before providing the sampled data to the execution unit.

[0186] During execution, the graphics and media pipelines send thread initiation requests to the thread execution logic 2100 via thread generation and dispatch logic. In some embodiments, the thread execution logic 2100 includes a local thread dispatcher 2104 that arbitrates thread initiation requests from the graphics and media pipelines and instantiates the requested threads on one or more execution units 2108A-2108N. For example, the geometry pipeline (e.g., Fig. 20 2036) dispatches vertex processing, tessellation or geometry processing threads to thread execution logic 2100 ( Fig.21 ). In some embodiments, thread dispatcher 2104 may also process execution time thread generation requests from executing shader programs.

[0187] Once the group of geometric objects has been processed and rasterized into pixel data, the pixel shader 2102 is called to further calculate output information and cause the results to be written to the output surface (e.g., color buffer, depth buffer, stencil buffer, etc.). In some embodiments, the pixel shader 2102 calculates the values ​​of various vertex attributes to be interpolated across the rasterized objects. In some embodiments, the pixel shader 2102 then executes a pixel shader program supplied by an application programming interface (API). To execute the pixel shader program, the pixel shader 2102 dispatches threads to execution units (e.g., 2108A) via a thread dispatcher 2104. In some embodiments, the pixel shader 2102 uses texture sampling logic in a sampler 2110 to access texture data in a texture map stored in memory. Arithmetic operations performed on the texture data and the input geometric data operate on the pixel color data for each geometric fragment, or discard one or more pixels from further processing.

[0188] In some embodiments, data port 2114 provides a memory access mechanism for thread execution logic 2100 to output processed data to memory for processing on the graphics processor output pipeline. In some embodiments, data port 2114 includes or is coupled to one or more cache memories (e.g., data cache 2112) to cache data for memory access via the data port.

[0189] Fig. 22 is a block diagram illustrating a graphics processor instruction format 2200 according to some embodiments. In one or more embodiments, a graphics processor execution unit supports an instruction set having instructions in multiple formats. Solid line boxes show components that are typically included in an execution unit instruction, while dashed lines include components that are optional or included only in a subset of instructions. In some embodiments, the instruction format 2200 described and illustrated are macroinstructions because they are instructions supplied to the execution unit, as opposed to micro-operations derived from instruction decoding (once the instruction is processed).

[0190] In some embodiments, the graphics processor execution unit natively supports instructions in 128-bit format 2210. A 64-bit compact instruction format 2230 is available for some instructions based on the selected instruction, instruction options, and the number of operands. The native 128-bit format 2210 provides access to all instruction options, while some options and operations are limited to the 64-bit format 2230. The native instructions available in the 64-bit format 2230 vary with the embodiment. In some embodiments, instructions are partially compacted using a set of index values ​​in the index field 2213. The execution unit hardware references a set of compact tables based on the index values, and uses the compact table output to reconstruct the native instructions in 128-bit format 2210.

[0191] For each format, the instruction opcode 2212 defines the operation to be performed by the execution unit. The execution unit executes each instruction in parallel across multiple data elements of each operand. For example, in response to an addition instruction, the execution unit performs a simultaneous addition operation across each color channel representing a texture element or a picture element. By default, the execution unit executes each instruction across all data channels of the operand. In some embodiments, the instruction control field 2214 enables control of certain execution options (such as channel selection (e.g., prediction) and data channel ordering (e.g., swizzling). For 128-bit instructions 2210, the execution size field 2216 limits the number of data channels that will be executed in parallel. In some embodiments, the execution size field 2216 is not available for use in a 64-bit compact instruction format 2230.

[0192] Some execution unit instructions have up to three operands, including two source operands src0 2220, src1 2222 and one destination 2218. In some embodiments, the execution unit supports dual destination instructions, where one of the destinations is implicit. Data manipulation instructions may have a third source operand (e.g., SRC2 2224), where the instruction opcode 2212 determines the number of source operands. The last source operand of an instruction may be an immediate (e.g., hard-coded) value passed by the instruction.

[0193] In some embodiments, the 128-bit instruction format 2210 includes access / address mode information 2226, which specifies (for example) whether direct register addressing mode or indirect register addressing mode is used. When direct register addressing mode is used, the register address of one or more operands is provided directly through bits in the instruction 2210.

[0194] In some embodiments, the 128-bit instruction format 2210 includes an access / address mode field 2226, which specifies an address mode and / or access mode for the instruction. In one embodiment, the access mode is used to define the data access alignment for the instruction. Some embodiments support access modes including 16-byte aligned access modes and 1-byte aligned access modes, wherein the byte alignment of the access mode determines the access alignment of the instruction operand. For example, when in the first mode, the instruction 2210 may use byte-aligned addressing for source and destination operands, and when in the second mode, the instruction 2210 may use 16-byte aligned addressing for all source and destination operands.

[0195] In one embodiment, the address mode portion of the access / address mode field 2226 determines whether the instruction will use direct or indirect addressing. When direct register addressing mode is used, the bits in the instruction 2210 directly provide the register address of one or more operands. When indirect register addressing mode is used, the register address of one or more operands can be calculated based on the address immediate field and the address register value in the instruction.

[0196] In some embodiments, instructions are grouped based on the opcode 2212 bit field to simplify opcode decoding 2240. For 8-bit opcodes, positions 4, 5 and 6 allow execution units to determine the type of opcode. The precise opcode grouping shown is only an example. In some embodiments, move and logic opcode groups 2242 include data movement and logic instructions (e.g., move (mov), compare (cmp)). In some embodiments, move and logic groups 2242 share five most significant bits (MSB), wherein the move (mov) instruction adopts the form of 0000xxxxb, and the logic instruction adopts the form of 0001xxxxb. Flow control instruction groups 2244 (e.g., call, jump (jmp)) include instructions using 0010xxxxb form (e.g., 0x20). Miscellaneous instruction groups 2246 include a mixture of instructions, which include synchronization instructions (e.g., wait, send) using 0011xxxxb form (e.g., 0x30). The parallel math instruction group 2248 includes component-wise arithmetic instructions (e.g., add, multiply (mul)) in the form of 0100xxxxb (e.g., 0x40). The parallel math group 2248 performs arithmetic operations in parallel across data lanes. The vector math group 2250 includes arithmetic instructions (e.g., dp4) in the form of 0101xxxxb (e.g., 0x50). The vector math group performs arithmetic such as dot product operations on vector operands.

[0197] Graphics Pipeline Fig.23 is a block diagram of another embodiment of a graphics processor 2300 . Fig.23 Elements in FIG. 1 having the same reference number (or name) as elements of any other figure herein may operate or function in any manner similar to that described elsewhere herein, but are not limited thereto.

[0198] In some embodiments, the graphics processor 2300 includes a graphics pipeline 2320, a media pipeline 2330, a display engine 2340, a thread execution logic 2350, and a rendering output pipeline 2370. In some embodiments, the graphics processor 2300 is a graphics processor within a multi-core processing system that includes one or more general-purpose processing cores. The graphics processor is controlled by register writes to one or more control registers (not shown) or via commands issued to the graphics processor 2300 via a ring interconnect 2302. In some embodiments, the ring interconnect 2302 couples the graphics processor 2300 to other processing components, such as other graphics processors or general-purpose processors. Commands from the ring interconnect 2302 are interpreted by a command stream transmitter 2303, which supplies instructions to individual components of the graphics pipeline 2320 or the media pipeline 2330.

[0199] In some embodiments, the command streamer 2303 directs the operation of the vertex fetcher 2305, which reads vertex data from memory and executes vertex processing commands provided by the command streamer 2303. In some embodiments, the vertex fetcher 2305 provides the vertex data to the vertex shader 2307, which performs coordinate space transformation and lighting operations on each vertex. In some embodiments, the vertex fetcher 2305 and the vertex shader 2307 execute the vertex processing instructions by dispatching execution threads to the execution units 2352A, 2352B via the thread dispatcher 2331.

[0200] In some embodiments, execution units 2352A, 2352B are arrays of vector processors with instruction sets for performing graphics and media operations. In some embodiments, execution units 2352A, 2352B have an attached L1 cache 2351 specific for each array or shared between arrays. The cache can be configured as a data cache, an instruction cache, or a single cache that is partitioned to contain data and instructions in different partitions.

[0201] In some embodiments, the graphics pipeline 2320 includes a tessellation component for performing hardware accelerated tessellation of 3D objects. In some embodiments, a programmable hull shader 2311 configures the tessellation operation. A programmable domain shader 2317 provides back-end evaluation of the tessellation output. The tessellation unit 2313 operates at the direction of the hull shader 2311 and contains dedicated logic for generating a set of detailed geometric objects based on a coarse geometric model that is provided as input to the graphics pipeline 2320. In some embodiments, the tessellation components 2311, 2313, 2317 can be bypassed if tessellation is not used.

[0202] In some embodiments, the complete geometric object may be processed by the geometry shader 2319 via one or more threads dispatched to the execution units 2352A, 2352B, or may proceed directly to the clipper 2329. In some embodiments, the geometry shader operates on entire geometric objects (rather than patches or vertices of vertices as in previous stages of the graphics pipeline). If tessellation is disabled, the geometry shader 2319 receives input from the vertex shader 2307. In some embodiments, if the tessellation unit is disabled, the geometry shader 2319 may be programmed by a geometry shader program to perform geometry tessellation.

[0203] Before rasterization, the clipper 2329 processes the vertex data. The clipper 2329 can be a programmable clipper or a fixed function clipper with clipping and geometry shader functions. In some embodiments, a rasterizer 2373 (e.g., a depth test component) in the render output pipeline 2370 dispatches a pixel shader to convert geometric objects into their pixel-by-pixel representations. In some embodiments, the pixel shader logic is included in the thread execution logic 2350. In some embodiments, the application can bypass the rasterizer 2373 and access the unrasterized vertex data via the stream out unit 2323.

[0204] The graphics processor 2300 has an interconnect bus, interconnect structure, or some other interconnect mechanism that allows data and messages to be passed among the main components of the processor. In some embodiments, the execution units 2352A, 2352B and associated cache(s) 2351, texture and media samplers 2354, and texture / sampler cache 2358 are interconnected via data ports 2356 to perform memory accesses and communicate with the rendering output pipeline components of the processor. In some embodiments, the samplers 2354, caches 2351, 2358, and execution units 2352A, 2352B each have separate memory access paths.

[0205] In some embodiments, the rendering output pipeline 2370 includes a rasterizer 2373, which converts vertex-based objects into associated pixel-based representations. In some embodiments, the rasterizer logic includes a windower / masker unit for performing fixed-function triangle and line rasterization. An associated rendering cache 2378 and a depth cache 2379 are also available in some embodiments. The pixel operation component 2377 performs pixel-based operations on data, although in some examples, pixel operations associated with 2D operations (e.g., bit block maps are transferred using blending) are performed by the 2D engine 2341, or replaced by overlapping display planes by the display controller 2343 at display time. In some embodiments, a shared L3 cache 2375 can be used for all graphics components, allowing data to be shared without using main system memory.

[0206] In some embodiments, the graphics processor media pipeline 2330 includes a media engine 2337 and a video front end 2334. In some embodiments, the video front end 2334 receives pipeline commands from the command streamer 2303. In some embodiments, the media pipeline 2330 includes a separate command streamer. In some embodiments, the video front end 2334 processes the media commands before sending them to the media engine 2337. In some embodiments, the media engine 2337 includes thread generation functionality for generating threads for dispatching to the thread execution logic 2350 via the thread dispatcher 2331.

[0207] In some embodiments, the graphics processor 2300 includes a display engine 2340. In some embodiments, the display engine 2340 is external to the processor 2300 and is coupled to the graphics processor via the ring interconnect 2302, or some other interconnect bus or structure. In some embodiments, the display engine 2340 includes a 2D engine 2341 and a display controller 2343. In some embodiments, the display engine 2340 includes dedicated logic that can operate independently of the 3D pipeline. In some embodiments, the display controller 2343 is coupled to a display device (not shown), which can be a system integrated display device (such as in a laptop computer), or can be an external display device attached via a display device connector.

[0208] In some embodiments, graphics pipeline 2320 and media pipeline 2330 can be configured to perform operations based on multiple graphics and media programming interfaces, and are not specific to any one application programming interface (API). In some embodiments, driver software for graphics processor converts API calls specific to specific graphics or media libraries into commands that can be processed by graphics processor. In some embodiments, support is provided for Open Graphics Library (OpenGL) and Open Computing Language (OpenCL) from Khronos Group, Direct3D library from Microsoft Corporation, or support can be provided for both OpenGL and D3D. Support can also be provided for open source computer vision library (OpenCV). If mapping from the pipeline of future API to the pipeline of graphics processor can be performed, future API with compatible 3D pipeline will also be supported.

[0209] Graphics Pipeline Programming Fig.24A is a block diagram of a graphics processor command format 2400 according to some embodiments. Fig. 24B is a block diagram of a graphics processor command sequence 2410 according to an embodiment. Fig.24A The solid-line boxes in show components that are generally included in the graphics command, while the dashed lines include components that are optional or included only in a subset of the graphics commands. Fig.24A The exemplary graphics processor command format 2400 includes a data field for identifying the target client 2402 of the command, a command operation code (opcode) 2404, and associated data 2406 for the command. In some commands, a sub-opcode 2405 and a command size 2408 are also included.

[0210] In some embodiments, client 2402 specifies the client unit of the graphics device that processes the command data. In some embodiments, the graphics processor command parser checks the client field of each command to adjust the further processing of the command and routes the command data to the appropriate client unit. In some embodiments, the graphics processor client unit includes a memory interface unit, a rendering unit, a 2D unit, a 3D unit, and a media unit. Each client unit has a corresponding processing pipeline for processing commands. Once the command is received by the client unit, the client unit reads the opcode 2404 and (if present) the sub-opcode 2405 to determine the operation to be performed. The client unit uses the information in the data field 2406 to execute the command. For some commands, an explicit command size 2408 is expected to specify the size of the command. In some embodiments, the command parser automatically determines the size of at least some of the commands in the command based on the command opcode. In some embodiments, the commands are aligned via multiples of the double word length.

[0211] Fig. 24B An exemplary graphics processor command sequence 2410 is shown in the flowchart in FIG. 2410. In some embodiments, software or firmware of a data processing system featuring an embodiment of a graphics processor uses a version of the command sequence shown to set up, execute, and terminate a set of graphics operations. The sample command sequence is shown and described for exemplary purposes only, as embodiments are not limited to these particular commands or this command sequence. In addition, the commands may be issued as a batch of commands in a command sequence so that the graphics processor will process the sequence of commands at least partially simultaneously.

[0212] In some embodiments, the graphics processor command sequence 2410 may begin with a pipeline dump clear command 2412 to cause any active graphics pipeline to complete the current pending commands of the pipeline. In some embodiments, the 3D pipeline 2422 and the media pipeline 2424 do not operate simultaneously. The pipeline dump clear is performed to cause the active graphics pipeline to complete any pending commands. In response to the pipeline dump clear, the command parser for the graphics processor will suspend command processing until the active drawing engine completes the pending operation and the related read cache is invalid. Optionally, any data marked as 'dirty' in the rendering cache can be dumped and cleared to memory. In some embodiments, the pipeline dump clear command 2412 can be used for pipeline synchronization or before the graphics processor is placed in a low power state.

[0213] In some embodiments, when a command sequence requires the graphics processor to explicitly switch between pipelines, pipeline select command 2413 is used. In some embodiments, pipeline select command 2413 is required only once within an execution context before issuing pipeline commands unless the context is to issue commands for both pipelines. In some embodiments, pipeline flush command 2412 is required immediately prior to a pipeline switch via pipeline select command 2413.

[0214] In some embodiments, pipeline control commands 2414 configure the graphics pipeline for operation and are used to program 3D pipeline 2422 and media pipeline 2424. In some embodiments, pipeline control commands 2414 configure the pipeline state for the active pipeline. In one embodiment, pipeline control commands 2414 are used for pipeline synchronization and for clearing data from one or more cache memories within the active pipeline before processing a batch of commands.

[0215] In some embodiments, a set of return buffers for the corresponding pipeline to write data is configured using return buffer state commands 2416. Some pipeline operations require the allocation, selection, or configuration of one or more return buffers into which the operation writes intermediate data during processing. In some embodiments, the graphics processor also uses one or more return buffers to store output data and perform cross-thread communication. In some embodiments, return buffer state 2416 includes selecting the size and number of return buffers to use for a set of pipeline operations.

[0216] The remaining commands in the command sequence differ based on the active pipeline for operation. Based on pipeline determination 2420 , the command sequence is tailored for either 3D pipeline 2422 , which starts with 3D pipeline state 2430 , or media pipeline 2424 , which starts with media pipeline state 2440 .

[0217] The commands for 3D pipeline state 2430 include 3D state setting commands for the following: vertex buffer state, vertex element state, constant color state, depth buffer state, and other state variables that will be configured before processing 3D primitive commands. The values ​​of these commands are determined at least in part based on the specific 3D API in use. In some embodiments, the 3D pipeline state 2430 commands can also selectively disable or bypass certain pipeline elements (if those elements will not be used).

[0218] In some embodiments, 3D primitives 2432 commands are used to submit 3D primitives to be processed by the 3D pipeline. The commands and associated parameters passed to the graphics processor via the 3D primitives 2432 are forwarded to the vertex acquisition function in the graphics pipeline. The vertex acquisition function uses the 3D primitives 2432 command data to generate a vertex data structure. The vertex data structure is stored in one or more return buffers. In some embodiments, 3D primitives 2432 commands are used to perform vertex operations on the 3D primitives via vertex shaders. In order to process vertex shaders, the 3D pipeline 2422 dispatches the shader execution thread to the graphics processor execution unit.

[0219] In some embodiments, the 3D pipeline 2422 is triggered via an execution 2434 command or event. In some embodiments, a register write triggers the command execution. In some embodiments, the execution is triggered via a 'go' or 'kick' command in a command sequence. In one embodiment, the command execution is triggered using a pipeline synchronization command to dump and clear the command sequence through the graphics pipeline. The 3D pipeline will perform geometry processing for 3D primitives. Once the operation is completed, the resulting geometric object is rasterized, and the pixel engine colors the resulting pixels. Additional commands for controlling pixel shading and pixel backend operations may also be included for those operations.

[0220] In some embodiments, when performing media operations, the graphics processor command sequence 2410 follows the media pipeline 2424 path. Generally, the specific use and manner of programming for the media pipeline 2424 depends on the media or computing operation to be performed. During media decoding, specific media decoding operations can be offloaded to the media pipeline. In some embodiments, the media pipeline can also be bypassed and media decoding can be performed in whole or in part (using resources provided by one or more general processing cores). In one embodiment, the media pipeline also includes elements for general purpose graphics processor unit (GPGPU) operations, wherein the graphics processor is used to perform SIMD vector operations using compute shader programs that do not explicitly involve rendering of graphics primitives.

[0221] In some embodiments, the media pipeline 2424 is configured in a similar manner to the 3D pipeline 2422. A set of media pipeline state commands 2440 are dispatched or placed into the command queue before the media object commands 2442. In some embodiments, the media pipeline state commands 2440 include data for configuring the media pipeline elements that will be used to process the media objects. This includes data (such as encoding or decoding formats) for configuring the video decoding and video encoding logic within the media pipeline. In some embodiments, the media pipeline state commands 2440 also support the use of one or more pointers to "indirect" state elements that contain a batch of state settings.

[0222] In some embodiments, media object commands 2442 supply pointers to media objects for processing by the media pipeline. The media object includes a memory buffer containing video data to be processed. In some embodiments, all media pipeline states must be valid before issuing media object commands 2442. Once the pipeline state is configured and media object commands 2442 are queued, media pipeline 2424 is triggered via an execution command 2444 or an equivalent execution event (e.g., a register write). The output from media pipeline 2424 can then be post-processed by operations provided by 3D pipeline 2422 or media pipeline 2424. In some embodiments, GPGPU operations are configured and executed in a manner similar to media operations.

[0223] Graphics software architecture Fig.25 An exemplary graphics software architecture for data processing system 2500 is shown in accordance with some embodiments. In some embodiments, the software architecture includes 3D graphics application 2510, operating system 2520, and at least one processor 2530. In some embodiments, processor 2530 includes graphics processor 2532 and one or more general purpose processor cores 2534. Graphics application 2510 and operating system 2520 are each executed in system memory 2550 of the data processing system.

[0224] In some embodiments, the 3D graphics application 2510 includes one or more shader programs that include shader instructions 2512. The shader language instructions may be in a high-level shader language, such as High Level Shader Language (HLSL) or OpenGL Shader Language (GLSL). The application also includes executable instructions 2514 in a machine language suitable for execution by the general purpose processor core 2534. The application also includes graphics objects 2516 defined by vertex data.

[0225] In some embodiments, operating system 2520 is from Microsoft Corporation. Operating system, proprietary UNIX-like operating system, or open source UNIX-like operating system (using a variation of the Linux kernel). When the Direct3D API is in use, the operating system 2520 uses a front-end shader compiler 2524 to compile any shader instructions 2512 in HLSL into a lower-level shader language. The compilation can be a just-in-time (JIT) compilation, or the application can execute shader pre-compilation. In some embodiments, during the compilation of the 3D graphics application 2510, high-level shaders are compiled into low-level shaders.

[0226] In some embodiments, the user mode graphics driver 2526 includes a backend shader compiler 2527 for converting shader instructions 2512 into hardware specific representations. When the OpenGL API is in use, the shader instructions 2512 in the GLSL high level language are passed to the user mode graphics driver 2526 for compilation. In some embodiments, the user mode graphics driver 2526 uses the operating system kernel mode function 2528 to communicate with the kernel mode graphics driver 2529. In some embodiments, the kernel mode graphics driver 2529 communicates with the graphics processor 2532 to dispatch commands and instructions.

[0227] IP Core Implementation One or more aspects of at least one embodiment may be implemented by a representative code stored on a machine-readable medium, which represents and / or defines logic within an integrated circuit such as a processor. For example, a machine-readable medium may include instructions representing various logics within a processor. When read by a machine, the instructions may cause the machine to make logic for performing the technology described herein. Such representations (referred to as "IP cores") are reusable units of logic for an integrated circuit, which may be stored on a tangible machine-readable medium as a hardware model describing the structure of the integrated circuit. The hardware model may be supplied to various consumers or manufacturing facilities, which load the hardware model on a manufacturing machine for manufacturing the integrated circuit. The integrated circuit may be manufactured so that the circuit performs the operations described in association with any embodiment described herein.

[0228] Fig.26 2600 is a block diagram showing an IP core development system 2600 according to an embodiment, and the IP core development system 2600 can be used to manufacture integrated circuits to perform operations. The IP core development system 2600 can be used to generate modular, reusable designs that can be incorporated into a larger design or used to build an entire integrated circuit (e.g., a SOC integrated circuit). The design facility 2630 can use a high-level programming language (e.g., C / C++) to generate a software simulation 2610 of the IP core design. The software simulation 2610 can be used to design, test and verify the behavior of the IP core. Then a register transfer level (RTL) design can be created or synthesized from the simulation model 2600. The RTL design 2615 is an abstraction of the behavior of an integrated circuit (including associated logic executed using the modeled digital signals) that models the flow of digital signals between hardware registers. In addition to the RTL design 2615, a lower-level design at the logic level or transistor level can also be created, designed or synthesized. Therefore, the specific details of the initial design and simulation can vary.

[0229] The RTL design 2615 or equivalent may be further synthesized by the design facility into a hardware model 2620, which may be in a hardware description language (HDL) or some other representation of physical design data. The HDL may be further simulated or tested to verify the IP core design. The IP core design may be stored using a non-volatile memory 2640 (e.g., a hard disk, a flash memory, or any non-volatile storage medium) for delivery to a third-party fabrication facility 2665. Alternatively, the IP core design may be transmitted (e.g., via the Internet) via a wired connection 2650 or a wireless connection 2660. The fabrication facility 2665 may then fabricate an integrated circuit based at least in part on the IP core design. The fabricated integrated circuit may be configured to perform operations in accordance with at least one embodiment described herein.

[0230] Fig. 27 2700, which can be fabricated using one or more IP cores. The exemplary integrated circuit includes one or more application processors 2705 (e.g., CPUs), at least one graphics processor 2710, and may additionally include an image processor 2715 and / or a video processor 2720, any of which may be modular IP cores from the same or multiple different design facilities. The integrated circuit includes peripheral or bus logic, which includes a USB controller 2725, a UART controller 2730, an SPI / SDIO controller 2735, an I 2 S / I 2 The integrated circuit may include a display device 2745 coupled to one or more of a high-definition multimedia interface (HDMI) controller 2750 and a mobile industry processor interface (MIPI) display interface 2755. Storage may be provided by a flash memory subsystem 2760 (including flash memory and a flash memory controller). A memory interface may be provided via a memory controller 2765 for accessing SDRAM or SRAM memory devices. Some integrated circuits additionally include an embedded security engine 2770.

[0231] Additionally, other logic and circuitry may be included in the processor of integrated circuit 2700, including additional graphics processors / cores, peripheral interface controllers, or general purpose processor cores.

[0232] In one example, as relative to Figure 6-10B As described in the following example, the graphics processing pipeline 1400 ( Fig.14 ) contains the topology shader.

[0233] This disclosure / application provides the following technical solutions: 1. A system comprising: a display for presenting visual content; a memory for storing a set of instructions; and A semiconductor packaging device coupled to the display and the memory, the semiconductor packaging device comprising: substrate; a host processor coupled to the substrate, wherein the set of instructions, when executed by the host processor, causes the host processor to generate an object description associated with the visual content, and A graphics processor coupled to the substrate, wherein the graphics processor includes logic to: The topology shader receives the object description, generating a set of polygons in the topology shader based on the object description, and Send this group of polygons to the vertex shader.

[0234] 2. A system as described in technical solution 1, wherein the logic will: detecting a lack of a visibility condition with respect to one or more polygons, and The one or more polygons are excluded from the set of polygons in response to the lack of visibility condition.

[0235] 3. A system as described in technical solution 2, wherein the lack of visibility conditions will include one or more of an obscured state or an off-screen state.

[0236] 4. A system as described in technical solution 1, wherein the logic determines the level of detail associated with the object description based on depth information.

[0237] 5. A system as described in technical solution 4, wherein the logic will identify the sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0238] 6. A system as described in technical solution 4, wherein the logic will interpolate between two levels of detail.

[0239] 7. A device comprising: substrate; and Logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed functionality hardware logic, the logic to: The topology shader receives the object description, generating a set of polygons in the topology shader based on the object description, and Send this group of polygons to the vertex shader.

[0240] 8. The device of claim 7, wherein the logic: detecting a lack of a visibility condition with respect to one or more polygons, and The one or more polygons are excluded from the set of polygons in response to the lack of visibility condition.

[0241] 9. An apparatus as described in technical solution 8, wherein the lack of visibility conditions will include one or more of an obscured state or an off-screen state.

[0242] 10. A device as described in technical solution 7, wherein the logic determines the level of detail associated with the object description based on depth information.

[0243] 11. A device as described in technical solution 10, wherein the logic will identify the sub-octree corresponding to the object description, and wherein the topology shader will be called for the identified sub-octree.

[0244] 12. An apparatus as described in technical solution 10, wherein the logic will interpolate between two levels of detail.

[0245] 13. A method comprising: Receive object description in topology shader; generating a set of polygons in the topology shader based on the object description; and Send this group of polygons to the vertex shader.

[0246] 14. The method of claim 13, wherein generating the set of polygons comprises: detecting a lack of a visibility condition relative to one or more polygons; and The one or more polygons are excluded from the set of polygons in response to the lack of visibility condition.

[0247] 15. A method as described in technical solution 14, wherein the lack of visibility conditions will include one or more of an obscured state or an off-screen state.

[0248] 16. A method as described in technical solution 13, wherein generating the set of polygons includes determining a level of detail associated with the object description based on depth information.

[0249] 17. A method as described in technical solution 16, wherein determining the level of detail includes identifying a sub-octree corresponding to the object description, and wherein the topology shader is to be called for the identified sub-octree.

[0250] 18. A method as described in technical solution 16, wherein determining the detail level includes interpolating between two detail levels.

[0251] 19. At least one computer-readable storage medium comprising a set of instructions that, when executed by a computing system, cause the computing system to: Receive object description in topology shader; generating a set of polygons in the topology shader based on the object description; and Send this group of polygons to the vertex shader.

[0252] 20. At least one computer-readable storage medium as described in technical solution 19, wherein the instructions, when executed, cause the computing system to: detecting a lack of a visibility condition relative to one or more polygons; and The one or more polygons are excluded from the set of polygons in response to the lack of visibility condition.

[0253] 21. At least one computer-readable storage medium as described in technical solution 20, wherein the lack of visibility conditions will include one or more of an obscured state or an off-screen state.

[0254] 22. At least one computer-readable storage medium as described in technical solution 19, wherein the instructions, when executed, cause the computing system to determine a level of detail associated with the object description based on depth information.

[0255] 23. At least one computer-readable storage medium as described in technical solution 22, wherein the instruction, when executed, causes the computing system to identify a sub-octree corresponding to the object description, and wherein the topological shader will be called for the identified sub-octree.

[0256] 24. At least one computer-readable storage medium as described in technical solution 22, wherein the instructions, when executed, cause the computing system to interpolate between two levels of detail.

[0257] Additional Notes and Examples Example 1 may include a computing system with improved performance, comprising: a display for presenting visual content; a memory for storing a set of instructions; and a semiconductor package device coupled to the display and the memory, the semiconductor package device comprising: a substrate; a host processor coupled to the substrate, wherein the set of instructions, when executed by the host processor, causes the host processor to generate an object description associated with the visual content; and a graphics processor coupled to the substrate, wherein the graphics processor includes logic for performing the following operations: receiving the object description at a topology shader, generating a set of polygons at the topology shader based on the object description, and sending the set of polygons to a vertex shader.

[0258] Example 2 may include the system of Example 1, wherein the logic is to detect a lack of a visibility condition with respect to one or more polygons and exclude the one or more polygons from the set of polygons in response to the lack of a visibility condition.

[0259] Example 3 may include the system of Example 2, wherein the lack of visibility condition includes one or more of an obscured state or an off-screen state.

[0260] Example 4 may include the system of any of Examples 1-3, wherein the logic is to determine a level of detail associated with the object description based on depth information.

[0261] Example 5 may include the system of Example 4, wherein the logic is to identify a sub-octree corresponding to the object description, and wherein the topology shader is to be invoked for the identified sub-octree.

[0262] Example 6 may include the system of Example 4, wherein the logic is to interpolate between two levels of detail.

[0263] Example 7 may include a semiconductor package device comprising: a substrate; and logic coupled to the substrate, wherein the logic is implemented in one or more of configurable logic or fixed-functional hardware logic, the logic being used to: receive an object description at a topology shader, generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader.

[0264] Example 8 may include the apparatus of Example 7, wherein the logic is to detect a lack of a visibility condition with respect to one or more polygons and exclude the one or more polygons from the set of polygons in response to the lack of a visibility condition.

[0265] Example 9 may include the apparatus of Example 8, wherein the lack of visibility condition includes one or more of an occluded state or an off-screen state.

[0266] Example 10 may include the apparatus of any of Examples 7 to 9, wherein the logic is to determine a level of detail associated with the object description based on depth information.

[0267] Example 11 may include the apparatus of Example 10, wherein the logic is to identify a sub-octree corresponding to the object description, and wherein the topology shader is to be invoked for the identified sub-octree.

[0268] Example 12 may include the apparatus of Example 10, wherein the logic is to interpolate between two levels of detail.

[0269] Example 13 may include a method of operating a semiconductor packaging device, comprising: receiving an object description at a topology shader, generating a set of polygons at the topology shader based on the object description, and sending the set of polygons to a vertex shader.

[0270] Example 14 may include the method of Example 13, wherein generating the set of polygons includes detecting a lack of a visibility condition with respect to one or more polygons, and excluding the one or more polygons from the set of polygons in response to the lack of a visibility condition.

[0271] Example 15 may include the method of Example 14, wherein the lack of visibility condition will include one or more of an occluded state or an off-screen state.

[0272] Example 16 may include the method of any of Examples 13 to 15, wherein generating the set of polygons includes determining a level of detail associated with the object description based on depth information.

[0273] Example 17 may include the method of Example 16, wherein determining the level of detail comprises identifying a sub-octree corresponding to the object description, and wherein the topology shader is to be invoked for the identified sub-octree.

[0274] Example 18 may include the method of Example 16, wherein determining the level of detail includes interpolating between two levels of detail.

[0275] Example 19 may include at least one computer-readable storage medium, comprising a set of instructions that, when executed by a computing system, cause the computing system to: receive an object description at a topology shader, generate a set of polygons at the topology shader based on the object description, and send the set of polygons to a vertex shader.

[0276] Example 20 may include at least one computer-readable storage medium as described in Example 19, wherein the instructions, when executed, cause the computing system to detect a lack of a visibility condition relative to one or more polygons and exclude the one or more polygons from the group of polygons in response to the lack of visibility condition.

[0277] Example 21 may include the at least one computer-readable storage medium of Example 20, wherein the lack of visibility condition comprises one or more of an obscured state or an off-screen state.

[0278] Example 22 may include the at least one computer-readable storage medium of any of Examples 19 to 21, wherein the instructions, when executed, cause the computing system to determine a level of detail associated with the object description based on depth information.

[0279] Example 23 may include at least one computer-readable storage medium as described in Example 22, wherein the instructions, when executed, cause the computing system to identify a sub-octree corresponding to the object description, and wherein the topology shader is to be invoked for the identified sub-octree.

[0280] Example 24 may include the at least one computer-readable storage medium of Example 22, wherein the instructions, when executed, cause the computing system to interpolate between two levels of detail.

[0281] Example 25 may include a semiconductor package device comprising: a component for receiving an object description in a topology shader; a component for generating a set of polygons in the topology shader based on the object description; and a component for sending the set of polygons to a vertex shader.

[0282] Example 26 may include the apparatus described in Example 25, wherein the component for generating the set of polygons includes a component for detecting a lack of a visibility condition relative to one or more polygons, and a component for excluding the one or more polygons from the set of polygons in response to the lack of visibility conditions.

[0283] Example 27 may include the apparatus of Example 26, wherein the lack of visibility condition includes one or more of an occluded state or an off-screen state.

[0284] Example 28 may include an apparatus as described in any of Examples 25 to 27, wherein the component for generating the set of polygons includes a component for determining a level of detail associated with the object description based on depth information.

[0285] Example 29 may include the apparatus of Example 28, wherein the component for determining the level of detail includes a component for identifying a sub-octree corresponding to the object description, and wherein the topology shader is to be invoked for the identified sub-octree.

[0286] Example 30 may include the apparatus of Example 28, wherein the component for determining the level of detail comprises interpolating between two levels of detail.

[0287] The techniques described herein can thus use a new stage in the graphics pipeline between calls to the vertex shader to determine the complexity / quality of the topology to be rendered when running on a graphics processor. As a result, the graphics processor can generate topology without transferring non-essential data from the host processor memory to the dedicated graphics memory. Geometry can be generated procedurally while minimizing the amount of data called when generating polygons.

[0288] The term "coupled" may be used herein to refer to any type of direct or indirect relationship between the components in question, and may apply to electrical, mechanical, fluid, optical, electromagnetic, electromechanical or other connections. In addition, the terms "first", "second", etc. may be used herein merely to facilitate discussion, and do not carry any particular temporal or temporal order significance unless otherwise indicated. Moreover, the indefinite article "a" or "an" should be understood to carry the meaning of "one or more" or "at least one".

[0289] As used in this application and in the claims, a list of items linked by the term "one or more" may mean any combination of the listed items. For example, the phrase "one or more of A, B, or C" may mean A, B, C; A and B; A and C; B and C; or A, B, and C.

[0290] Embodiments have been described above with reference to specific embodiments. However, it will be appreciated by those skilled in the art that various modifications and changes may be made thereto without departing from the broader spirit and scope of the embodiments as set forth in the appended claims. The foregoing description and drawings are therefore considered to be illustrative rather than restrictive.

Claims

1. A method comprising: At the graphics processor, a set of polygons is generated to create the topology of the scene, instead of generating topology metadata at the host processor, wherein the generating of the set of polygons comprises the following operations: Checks conditions on one or more polygons. excluding the one or more polygons from the set of polygons in response to the condition, and determining a level of detail associated with one or more objects in the scene, wherein the set of polygons includes a first number of polygons at a first level of detail and a second, different number of polygons at a second level of detail; and The scene is provided for display based on the set of polygons generated at the graphics processor.

2. The method according to claim 1, wherein: The conditions may include one or more of an obscured state or an off-screen state.

3. The method according to claim 1, wherein: The generation of the set of polygons comprises the following operations: receiving, at the graphics processor, an object description from the host processor, wherein the object description identifies a type of object to be rendered without specifying topological metadata of the object, and At the graphics processor, the set of polygons is generated based on the object description.

4. The method according to claim 3, wherein: The generating of the set of polygons includes the operation of determining a level of detail associated with the object description based on depth information.

5. The method according to claim 4, wherein: The generating of the set of polygons comprises the following operations: interpolating between two levels of detail.

6. The method according to claim 4, wherein: The generating of the set of polygons includes an operation of identifying a sub-octree corresponding to the object description, and wherein a topology shader is to be invoked for the identified sub-octree.

7. A device comprising: Means for generating a set of polygons to create a topology of a scene instead of generating topology metadata on a host processor, wherein said generating of said set of polygons comprises the following operations: Checks conditions on one or more polygons. excluding the one or more polygons from the set of polygons in response to the condition, and determining a level of detail associated with one or more objects in the scene, wherein the set of polygons includes a first number of polygons at a first level of detail and a second, different number of polygons at a second level of detail; and Means for providing the scene for display based on the generated set of polygons.

8. The device according to claim 7, wherein: The conditions may include one or more of an obscured state or an off-screen state.

9. The device according to claim 7, wherein: The generation of the set of polygons comprises the following operations: receiving an object description from the host processor, wherein the object description identifies a type of object to be rendered without specifying topological metadata of the object, and The set of polygons is generated based on the object description.

10. The device according to claim 9, wherein: The generating of the set of polygons includes the operation of determining a level of detail associated with the object description based on depth information.

11. The device according to claim 10, wherein: The generating of the set of polygons comprises the following operations: interpolating between two levels of detail.

12. The device according to claim 10, wherein: The generating of the set of polygons includes an operation of identifying a sub-octree corresponding to the object description, and wherein a topology shader is to be invoked for the identified sub-octree.

13. A method comprising: At the graphics processor, a set of polygons is generated to create the topology of the scene, instead of generating topology metadata at the host processor, wherein the generating of the set of polygons comprises the following operations: determining a level of detail associated with one or more objects in the scene, wherein the set of polygons includes a first number of polygons at a first level of detail and a second, different number of polygons at a second level of detail; and The scene is provided for display based on the set of polygons generated at the graphics processor.

14. The method according to claim 13, further comprising: A condition of one or more polygons is detected, wherein the condition may include one or more of an occluded state or an off-screen state.

15. The method according to claim 13, wherein: The generation of the set of polygons comprises the following operations: receiving, at the graphics processor, an object description from the host processor, wherein the object description identifies a type of object to be rendered without specifying topological metadata of the object, and At the graphics processor, the set of polygons is generated based on the object description.

16. The method according to claim 15, wherein: The generating of the set of polygons includes the operation of determining a level of detail associated with the object description based on depth information.

17. The method according to claim 16, wherein: The generating of the set of polygons comprises the following operations: interpolating between two levels of detail.

18. The method according to claim 16, wherein: The generating of the set of polygons includes an operation of identifying a sub-octree corresponding to the object description, and wherein a topology shader is to be invoked for the identified sub-octree.

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