Display panel and display device

Abstract

The invention provides a display panel and a display device. The display panel comprises a shift register unit, a scanning line and a plurality of pixel circuits, the pixel circuits are arranged in a pixel circuit row in a first direction, the scanning line extends in the first direction and is connected with the pixel circuits in the pixel circuit row, and the length of the pixel circuit row in the first direction is L; the display panel comprises at least two first areas, and the width of each first area in the first direction is L / 10; each pixel circuit row comprises a first edge and a second edge which are opposite in the first direction, the minimum distance between one first area and the first edge is L / 5, and the minimum distance between the other first area and the second edge is L / 5; the scanning line comprises two sites, one first area comprises one site, and one site is correspondingly connected with the output end of one shift register unit. According to the invention, the delay difference of scanning signals at different positions on the scanning lines can be balanced, and the display uniformity is improved.

Description

Technical Field

[0001] The present invention relates to the field of display technology, and in particular to a display panel and a display device. Background Art

[0002] The display panel is provided with a plurality of scan lines and cascaded shift register units, the output end of the shift register unit is connected to the scan line, and the scan line is connected to a plurality of pixels in a pixel row. The cascaded shift register units sequentially output scan signals to achieve drive display of a plurality of pixel rows row by row. However, currently, the shift register units are arranged on both sides of the display panel, and the scan signal is transmitted from both ends of the scan line to the middle. There is a problem of inconsistent scan signal delay on both sides and the middle of the display area, resulting in poor display uniformity. Summary of the invention

[0003] In order to solve the problems existing in the prior art, the present invention provides a display panel and a display device to solve the technical problem of improving display uniformity.

[0004] In a first aspect, an embodiment of the present invention provides a display panel, the display panel comprising a shift register unit, a scan line, and a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in a pixel circuit row in a first direction, the scan line extends along the first direction and connects the pixel circuits in the pixel circuit row, and the length of the pixel circuit row in the first direction is L;

[0005] The display area of ​​the display panel includes at least two first areas, and the width of the first area in the first direction is L / 10; the pixel circuit row includes a first edge and a second edge opposite to each other in the first direction, and the minimum distance between one first area and the first edge is L / 5, and the minimum distance between another first area and the second edge is L / 5;

[0006] The scan line includes two sites, a first area includes one site, and one site is correspondingly connected to an output end of a shift register unit.

[0007] In a second aspect, based on the same inventive concept, an embodiment of the present invention provides a display device, including the display panel provided by any embodiment of the present invention.

[0008] The display panel and the display device provided by the embodiments of the present invention have the following beneficial effects: the display panel includes two first areas, and the two first areas are respectively located in the middle area of ​​the left and right parts divided by the display panel in the first direction. The site of the scan line is connected to the output end of the shift register unit, and the two sites serve as two signal input sites on the scan line, and the two sites are set in a one-to-one correspondence with the two first areas. The scan signal provided to the scan line by the shift register unit is transmitted to the left and right sides respectively from the positions of the two sites. The setting of the two sites and the areas where they are located makes the delay difference of the scan signal on both sides of the site small, which can balance the delay difference of the scan signal at different positions of the display panel in the first direction x, and improve the display uniformity. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without paying any creative labor.

[0010] Figure 1 A simplified schematic diagram of a display panel provided by an embodiment of the present invention;

[0011] Figure 2 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0012] Figure 3 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0013] Figure 4 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0014] Figure 5 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0015] Figure 6 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0016] Figure 7 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0017] Figure 8 A schematic diagram of a pixel circuit provided by an embodiment of the present invention;

[0018] Fig. 9 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0019] Fig.10A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0020] Fig.11 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0021] Fig.12 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0022] Fig.13 A schematic diagram of a shift register unit provided by an embodiment of the present invention;

[0023] Fig.14 A partial schematic diagram of another display panel provided by an embodiment of the present invention;

[0024] Fig.15 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0025] Fig.16 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0026] Fig.17 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0027] Fig.18 for Fig.17 A schematic diagram of a cross section at the midline AA′;

[0028] Fig.19 for Fig.17 A magnified schematic diagram of the Q2 position in the middle area;

[0029] Fig. 20 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0030] Fig.21 A driving schematic diagram of a display panel provided by an embodiment of the present invention;

[0031] Fig. 22 A schematic diagram of another display panel provided by an embodiment of the present invention;

[0032] Fig.23 A driving schematic diagram of another display panel provided by an embodiment of the present invention;

[0033] Fig.24 A schematic diagram of another pixel circuit provided by an embodiment of the present invention;

[0034] Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0035] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0036] The terms used in the embodiments of the present invention are only for the purpose of describing specific embodiments, and are not intended to limit the present invention. The singular forms "a", "said" and "the" used in the embodiments of the present invention and the appended claims are also intended to include plural forms, unless the context clearly indicates other meanings.

[0037] An embodiment of the present invention provides a display panel, in which signal input sites of scan lines are respectively set in two first areas of the display panel, and the one-quarter and three-quarter dividing lines of the display area are respectively located in one first area. In the application, the signal on the scan line is transmitted from the signal input site position to the left and right sides, which can balance the delay difference of the scan signal at the two sides and the middle position of the display area, and improve the display uniformity. In some embodiments, the shift register unit connected to the upper site on the scan line is also set in the first area, thereby reducing the distance between the output end of the shift register unit and the upper site on the scan line. In some embodiments, the positional relationship and the film layer relationship of the drive signal line and the data line connected to the shift register unit are also set. Further, in some embodiments, in order to cooperate with the design of the film layer where the drive signal line, the data line, and the scan line are located, the structure of other routings in the panel, such as the reset signal line, is designed. The above is a main technical overview of the present invention, and the technical solution of the present invention is described below with specific embodiments.

[0038] Figure 1 A simplified schematic diagram of a display panel provided by an embodiment of the present invention. Figure 1 As shown, the display panel includes a shift register unit 10, a scan line 20 and a plurality of pixel circuits 30, wherein the plurality of pixel circuits 30 are arranged into a pixel circuit row 30H in a first direction x, and the scan line 20 extends along the first direction x and connects the pixel circuits 30 in the pixel circuit row 30H. Figure 1 The pixel circuit 30 is only simplified and schematically illustrated. The pixel circuit 30 can be any one of the prior art, and the pixel circuit 30 includes multiple transistors. For example, the pixel circuit 30 includes a data writing transistor, and the scan line 20 includes a first type of scan line, and the first type of scan line is connected to the gates of multiple data writing transistors in the pixel circuit row 30H. For example, the pixel circuit 30 includes a light emission control transistor, and the scan line 20 includes a second type of scan line, and the second type of scan line is connected to the gates of multiple light emission control transistors in the pixel circuit row 30H.

[0039] like Figure 1 As shown, the length of the pixel circuit row 30H in the first direction x is L. When measuring the length of the pixel circuit row 30H, the edges of the pixel circuit 30 structure at the two end positions are used as boundaries. The pixel circuit row 30H includes a first edge Y1 and a second edge Y2 that are opposite in the first direction x, and the first edge Y1 and the second edge Y2 are the edges on the left and right sides of the pixel circuit row 30H. The display panel includes a plurality of pixel circuit rows 30H, and the first edges Y1 and the second edges Y2 of the plurality of pixel circuit rows 30H arranged in the second direction y are located in the same straight line, and the second direction y intersects the first direction x.

[0040] The display area AA of the display panel includes at least two first areas Q1, and the display area AA includes a plurality of light emitting devices ( Figure 1 (not shown in the figure), the light emitting device is connected to the pixel circuit 30. Among them, the width of the first area Q1 in the first direction x is L / 10; the minimum distance between one first area Q1 and the first edge Y1 is L / 5, and the minimum distance between another first area Q1 and the second edge Y2 is L / 5; the scan line 20 includes two sites W, one first area Q1 includes one site W, and one site W is correspondingly connected to the output end of one shift register unit 10. It can be understood that for one scan line 20, the two shift register units 10 correspondingly connected to the two sites W provide scan signals to the scan line 20 at the same time.

[0041] Figure 1 The center line of the display panel is shown in FIG. 1 , and the second virtual line X2 extending along the second direction y is the center line of the display panel. The first edge Y1 and the second edge Y2 of the pixel circuit row 30H are equidistant from the second virtual line X2. Since the width of the first region Q1 in the first direction x is L / 10, and the minimum distance between the first region Q1 and the edge of the pixel circuit row 30H is L / 5, it can be known that the minimum distance between the first region Q1 and the second virtual line X2 is also L / 5, and the two first regions Q1 are respectively located in the middle areas of the left and right sides of the display panel.

[0042] The display panel provided by the embodiment of the present invention includes two first areas Q1, and the two first areas Q1 are respectively located in the middle area of ​​the left and right parts of the display panel divided in the first direction x. Two sites W on the scan line 20 are set in a one-to-one correspondence with the two first areas Q1, and the site W of the scan line 20 is connected to the output end of the shift register unit 10. The two sites W serve as two signal input sites on the scan line 20, and the scan signal provided to the scan line 20 by the shift register unit 10 is transmitted to the left and right sides respectively from the positions of the two sites W. The setting of the two sites W and the areas where they are located makes the delay difference of the scan signal on both sides of the site W small, which can balance the delay difference of the scan signal at different positions of the display panel in the first direction x, and improve the display uniformity.

[0043] In some embodiments, Figure 1 As shown, the shift register unit 10 connected to the site W is located in the corresponding first area Q1. That is, for a scan line 20, a site W1 is respectively set in the two first areas Q1, and the shift register unit 10 connected to the site W1 is located in the first area Q1 where the site W is located. Such a setting can reduce the winding in the display panel, save wiring space, and shorten the distance between the output end of the shift register unit 10 and the site W connected thereto, thereby reducing the voltage drop of the scan signal transmission. Moreover, setting the shift register unit 10 in the first area Q1 of the display area AA can help narrow the left and right borders of the display panel.

[0044] In some embodiments, Figure 2 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 3 A schematic diagram of another display panel provided by an embodiment of the present invention. Figure 2 and Figure 3 The display panel is only simplified, and only the first edge Y1 and the second edge Y2 of the pixel circuit row 30H are marked, and the pixel circuit 30 in the pixel circuit row 30H is not illustrated. The distance between the first edge Y1 and the second edge Y2 is L. The display panel includes a first virtual line X1 extending along the second direction y, and the second direction y intersects the first direction x. In the first direction x, the distance between the first virtual line X1 and the edge of the pixel circuit row 30H is L / 4; the two first areas Q1 respectively include a first virtual line X1. The two first virtual lines X1 are equivalent to the 1 / 4 dividing line and the 3 / 4 dividing line of the display panel in the first direction x. Figure 2 As shown in FIG. 1 , two shift register units 10 correspondingly connected to two points W on a scan line 20 are located between two first virtual lines X1 . Figure 3 As shown in FIG. 1 , two shift register units 10 corresponding to two points W on a scan line 20 are located between the first virtual line X1 and the first edge Y1, and the other is located between the first virtual line X1 and the second edge Y2. In the embodiment of the present invention, the relative positions of the two shift register units 10 connected to the same scan line 20 in the two first regions Q1 and the first virtual line X1 are designed so that the two shift register units 10 in the two first regions Q1 are approximately symmetrically designed with respect to the second virtual line X2 (the center line of the display panel), so that the delay difference of the scan signal at different positions of the display panel in the first direction x can be further balanced, thereby improving the display uniformity.

[0045] In some embodiments, Figure 2As shown, the display panel includes a second virtual line X2 extending along the second direction y, and the first edge Y1 and the second edge Y2 are at the same distance from the second virtual line X2; the second virtual line X2 is the center line of the display panel. Two points W on a scan line 20 are at the same distance from the second virtual line X2, and the two shift register units 10 corresponding to the two points W are at the same distance from the second virtual line X2. In this embodiment, two points W on a scan line 20 are set symmetrically relative to the second virtual line X2, and the two shift register units 20 corresponding to the two points W are also symmetrical relative to the second virtual line X2. In this way, the scan signals input to the two points W on the scan line 20 can be basically the same, and the voltage drop of the scan signals on the left and right sides of the display panel in the first direction x is basically the same, which can improve the display uniformity.

[0046] In some embodiments, Figure 4 A schematic diagram of another display panel provided by an embodiment of the present invention, Figure 4 The local position of the display area of ​​the display panel is shown. In the embodiment of the present invention, the display area of ​​the display panel includes a transmission area TG and a non-transmission area NT; wherein the transmittance of the transmission area TG is greater than the transmittance of the non-transmission area NT. Figure 4 As shown, n pixel circuits 30 arranged in a first direction x form a circuit group 30Z, where n is an integer, n≥2; Figure 4 As shown in FIG. 3, n=3 is used for illustration. The display panel includes a first wiring area Z1 extending along a first direction x and a second wiring area Z2 extending along a second direction y, and signal lines are arranged in the first wiring area Z1 and the second wiring area Z2, respectively. The first wiring area Z1 overlaps at least partially with the circuit group 30Z. The first wiring area Z1, the second wiring area Z2, and the area where the pixel circuit 30 and the shift register unit 10 are arranged in the display panel form a non-transmitting area NT, and the non-transmitting area NT that crosses horizontally and vertically defines a plurality of transmissive areas TG. In the first area Q1, the shift register unit 10 and the circuit group 30Z adjacent to it in the second direction y form a continuous non-transmitting area NT. In the embodiment of the present invention, the shift register unit 10 and the circuit group 30Z are adjacent in the second direction y, and the distance between the two is relatively close and the arrangement is close. Such an arrangement can reduce the influence of the arrangement of the shift register unit 10 on the area of ​​the transmissive area TG in the display panel, ensure the transmittance of the area where the shift register unit 10 is arranged, and ensure the display effect of transparent display in the application.

[0047] It can be understood that the display panel includes multiple metal layers and multiple insulating layers located on the substrate. When the display panel is manufactured, an etching process is used to etch at least part of the insulating layer to form a hollow. The hollow area on the insulating layer is the transmission zone TG, and the light transmittance in the transmission zone TG is relatively high.

[0048] Figure 4The shift register unit 10 is shown as being located below the circuit group 30Z closest thereto. In other embodiments, the shift register unit 10 is adjacent to the circuit group 30Z in the second direction y, and at least part of the shift register unit 10 is located above the circuit group 30Z closest thereto.

[0049] In some embodiments, Figure 4 As shown, the transmission area TG includes a first transmission area TG1 and a second transmission area TG2, and the length d1 of the first transmission area TG1 in the first direction x is less than the length d2 of the second transmission area TG2 in the first direction x; the display panel includes a driving signal line 40 extending along the second direction y, and the shift register unit 10 is connected to the driving signal line 40; the driving signal line 40 in the first area Q1 is adjacent to the first transmission area TG1. The driving signal line 40 is adjacent to a second routing area Z2. The driving signal line 40 includes a starting signal line, a clock signal line and a power line required to drive the shift register unit 10. In the embodiment of the present invention, the driving signal line 40 needs to occupy a certain space, and the length d1 of the first transmission area TG1 in the first direction x is set to be less than the length d2 of the second transmission area TG2 in the first direction x. When designing, multiple circuit groups 30Z in the entire display area are arranged in a regular array. When making, the metal layers in the circuit group 30Z have strong regularity and good overall etching uniformity, which can ensure that the performance difference of transistors in the circuit is small.

[0050] In some embodiments, Figure 5 A partial schematic diagram of another display panel provided by an embodiment of the present invention. Figure 5 As shown, the shift register unit 10 includes a driving module 11 and an output module 12 arranged in a first direction x, wherein the output end of the output module 12 is connected to a point W on the scan line 20. The arrangement order of the driving module 11 and the output module 12 in the shift register unit 10 is the same in the two first regions Q1. Figure 5 In the figure, the driving module 11 is on the left and the output module 12 is on the right in the two shift register units 10 in the first area Q1. In other embodiments, the driving module 11 is on the right and the output module 12 is on the left in the two shift register units 10 in the first area Q1, which is not illustrated here.

[0051] Combination Figure 4From the embodiment, the display panel provided by the embodiment of the present invention can be a transparent display panel. The shift register unit 10 is set in the first zone Q1, which affects the shape and area of ​​the transmission zone TG where the shift register unit 10 is located. Setting the arrangement order of the driving module 11 and the output module 12 in the shift register unit 10 in the two first zones Q1 to be the same is conducive to making the shape and area of ​​the transmission zone TG where the shift register unit 10 is set in the two first zones Q1 to be roughly the same, thereby ensuring that the transmittance in the two first zones Q1 is the same, so that the display effect of the transparent display is better. In this embodiment, the position design of the two sites W is combined, such as setting the two sites W to be 1 / 4 of the distance from the second virtual line X2 (participate in Figure 2 The distances between the two sides (shown in the figure) are equal or the distance difference is small, which can balance the delay difference of the scanning signal on the left and right sides of the display panel in the first direction x, thereby improving the display uniformity.

[0052] In other embodiments, Figure 6 A partial schematic diagram of another display panel provided by an embodiment of the present invention. Figure 6 As shown, the shift register unit 10 includes a driving module 11 and an output module 12 arranged in a first direction x; the output end of the output module 12 is connected to the site W on the scan line 20. The arrangement order of the driving module 11 and the output module 12 in the two first regions Q1 is a mirror image relationship. In one first region Q1, the driving module 11 is on the left and the output module 12 is on the right, and in the other first region Q1, the driving module 11 is on the right and the output module 12 is on the left. Figure 4 From the embodiment, in the transparent display, the shift register unit 10 is set in the first area Q1, which will affect the shape and area of ​​the transmission area TG where the shift register unit 10 is located. The arrangement order of the driving modules 11 and the output modules 12 in the two first areas Q1 is a mirror image relationship. Although the shapes of the transmission areas TG where the shift register units 10 are located in the two first areas Q1 are slightly different, the relative positions of the driving signal lines and the shift register units 10 in the first area Q1 can be the same (for example, the driving signal lines are all located on the side of the shift register unit 10 away from the center line of the display panel). In combination with the position design of the two sites W, for example, the two sites W are set to be 1 / 4 of the distance from the second virtual line X2 (reference Figure 2 The distance between the two first areas Q1 and the two signal sites W is equal, and the circuit structure and signal sites in the two first areas Q1 are symmetrically designed. The scanning signal is transmitted from the two sites W to the left and right sides respectively. The scanning signal delay difference on both sides of the site W is small, which can improve the display uniformity.

[0053] Figure 7 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Figure 8 A schematic diagram of a pixel circuit provided by an embodiment of the present invention. Figure 7Schematic diagram of three pixel circuits at a circuit group 30Z position, combined with Figure 7 and Figure 8 From the perspective of the display panel, the pixel circuit includes a driving transistor Tm, a gate reset transistor T1, an electrode reset transistor T2, a data writing transistor T3, a threshold compensation transistor T4, a first light-emitting control transistor T5, a second light-emitting control transistor T6, and a storage capacitor Cst. The driving of the pixel circuit requires a selection signal S1, a selection signal S2, a light-emitting control signal Emit, a reset signal Vref, a first power signal Pvdd, and a data signal Data. One electrode of the light-emitting device LED is connected to the pixel circuit, and the other electrode is connected to the second power signal Pvee. The light-emitting device LED is a light-emitting diode (LED), such as a mini-LED or micro-LED. The display panel is arranged with a scan line S1, a scan line S2, a light-emitting control line Emit, and a reset signal line Vref, and each signal line uses the same mark as the signal it provides. Figure 7 The Data shown in FIG. 1 is a data transmission line for transmitting a data signal Data.

[0054] Among them, the selection signal S1 and the selection signal S2 need to be provided by the shift driving circuit, and the light-emitting control signal Emit also needs to be provided by the shift driving circuit. In some embodiments, the selection signal S1 and the selection signal S2 required for a pixel circuit are provided by a two-stage shift register unit cascaded in a driving circuit, and the light-emitting control signal Emit is provided by a shift register unit in another driving circuit. In other embodiments, the selection signal S1 and the selection signal S2 required for a pixel circuit are provided by the shift register units in two driving circuits respectively, and the light-emitting control signal Emit is provided by the shift register unit in another driving circuit.

[0055] In some embodiments, Fig. 9 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig. 9 As shown, n pixel circuits 30 arranged in a first direction x form a circuit group 30Z, where n is an integer, n≥2. Fig. 9As shown in n=3, the second wiring area Z2 extending in the second direction y separates adjacent circuit groups 30Z. The display panel is provided with a driving signal line 40 extending in the second direction y, the second direction y intersects with the first direction x, and the shift register unit 10 is connected to the driving signal line 40. In the first area Q1: the shift register unit 10 is adjacent to the circuit group 30Z in the second direction y, the driving signal line 40 is located on one side of the circuit group 30Z in the first direction x, and the shift register unit 10 includes a driving module 11 and an output module 12, and the driving module 11 is located on the side of the output module 12 close to the driving signal line 40. Such a setting can facilitate the connection between the driving module 11 and the driving signal line 40, reduce winding, save wiring space, and minimize the impact of the shift register unit 10 on the transmission area TG after being arranged in the display area.

[0056] Fig. 9 In the embodiment, the shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b, and the scan line 20 includes a first scan line 21 and a second scan line 22. The point W of the first scan line 21 is connected to the output end of the first shift register unit 10a, and the point W of the second scan line 22 is connected to the output end of the second shift register unit 10b. The pixel circuit in the circuit group 30Z is connected to the first scan line 21 and the second scan line 22. Figure 4 In the description, the first scan line 21 and the second scan line 22 are arranged in the first wiring area Z1. In the embodiment of the present invention, a plurality of first shift register units 10a arranged in the second direction y are cascaded, and a plurality of second shift register units 10b arranged in the second direction y are cascaded, and the first shift register unit 10a and the second shift register unit 10b provide different scan signals.

[0057] In one embodiment, the first shift register unit 10a provides a light emitting control signal Emit required by the pixel circuit, and the second shift register unit 10b provides a strobe signal S1 and / or a strobe signal S2 required by the pixel circuit.

[0058] Fig. 9 The driving signal line 40 is shown in the figure as being located on the right side of the shift register unit 10 connected thereto. In another embodiment, by adjusting the relative positions of the driving module 11 and the output module 12 in the shift register unit 10, the driving signal line 40 can also be set on the left side of the shift register unit 10 connected thereto, which is not shown in the figure here.

[0059] Fig.10 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Fig.10 The partial position of the first shift register unit 10a is shown. Fig.11 A schematic diagram of a shift register unit provided by an embodiment of the present invention. Fig.10The structure of the pixel circuit 30 at the location of the circuit group 30Z is only simplified. The pixel circuit 30 can refer to the above Figure 7 In the instructions, in addition Fig.10 The gate line S1 , the gate line S2 , the light emitting control line Emit, the reset signal line Vref, and the data transmission line Data extending along the first direction x are illustrated.

[0060] Combination Fig.10 and Fig.11 From the perspective of FIG. 1 , the first shift register unit 10a includes sixteen transistors and three capacitors, the sixteen transistors are the first transistor M1 to the sixteenth transistor M16, and the three capacitors are the first capacitor C1, the second capacitor C2 and the third capacitor C3. Among them, the ninth transistor M9 and the tenth transistor M10 constitute the output module 12, and the other transistors constitute the driving module 11. Fig.11 Nodes N1 to N7, input terminal IN and output terminal OUT in the shift register unit are also indicated. The driving signal line 40 in the display panel includes a first driving signal line 41, and the first driving signal line 41 includes a first voltage signal line VGL, a second voltage signal line VGH, a first clock signal line CKE, a second clock signal line CK2, a reset signal line RST, and a first start signal line STVE. Among them, the input terminal IN of the first shift register unit 10a of the first stage is connected to the start signal line STVE, and the input terminal IN of the first shift register unit 10a of the i-th stage is connected to the output terminal OUT of the first shift register unit 10a of the i-1th stage, where i is an integer, i≥2.

[0061] Depend on Fig.10 It can be seen that the first shift register unit 10a includes a driving module 11 and an output module 12, and the driving module 11 is located on a side of the output module 12 close to the first driving signal line 41. A connecting line 60 is arranged in the display panel, and the connecting line 60 includes a first connecting line 61. The output end of the first shift register unit 10a is connected to a site W on the light emitting control line Emit through the first connecting line 61. The light emitting control line Emit is the first scanning line 21 connected to the first shift register unit 10a.

[0062] In some embodiments of the present invention, the output end of the shift register unit 10 is connected to the site W on the scan line 20 via a connecting line 60, and the connecting line 60 and the driving signal line 40 connected to the shift register unit 10 are located in the same layer. Fig.10As shown, the output end of the first shift register unit 10a is connected to the site W on the light emitting control line Emit through the first connecting line 61, the first connecting line 61 and the first driving signal line 41 are located on the same side of the circuit group 30Z in the first direction x, and the first connecting line 61 and the first driving signal line 41 are located in the same layer. The position setting of the connecting line 60 and the driving signal line 41 in the embodiment of the present invention can make the wiring in the panel more compact, and the arrangement of the connecting line 60 will not affect the wiring of the circuit group 30Z in the area where the shift register unit 10 is located, so that the wiring method of the circuit group 30Z at each position in the entire display area is the same, which can ensure the etching uniformity in the manufacturing process.

[0063] In some embodiments, Fig.12 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Fig.13 A schematic diagram of a shift register unit provided by an embodiment of the present invention. Fig.12 The location of the second shift register unit 10b is shown. Fig.14 A partial schematic diagram of another display panel provided by an embodiment of the present invention, Fig.14 The locations of the circuit group 30Z and the second shift register unit 10b are simplified as shown in FIG. Figure 7 and Fig.12 Please understand the instructions in the figure.

[0064] Combination Fig.12 and Fig.13 From the perspective of FIG. 1 , the second shift register unit 10b includes eight transistors and two capacitors, the eight transistors are the first transistor M1 to the eighth transistor M8, and the two capacitors are the first capacitor C1 and the second capacitor C2. The driving module 11 includes the first transistor M1 to the sixth transistor M6, and the output module 12 includes the seventh transistor M7 and the eighth transistor M8. Fig.12 Nodes N1 to N3, input terminal IN and output terminal OUT in the shift register unit are also indicated. The driving signal line 40 in the display panel includes a second driving signal line 42, and the second driving signal line 42 includes a first voltage signal line VGL, a second voltage signal line VGH, a third clock signal line CKS, a fourth clock signal line XCKS, and a second start signal line STVS. Among them, the input terminal IN of the first-stage second shift register unit 10b is connected to the start signal line STVS, and the input terminal IN of the i-th stage second shift register unit 10b is connected to the output terminal OUT of the i-1-th stage second shift register unit 10b, where i is an integer, i≥2.

[0065] Depend on Fig.14It can be seen that the second shift register unit 10b includes a driving module 11 and an output module 12, and the driving module 11 is located on the side of the output module 12 close to the second driving signal line 42. A connecting line 60 is arranged in the display panel, and the connecting line 60 includes a second connecting line 62. The output end of the second shift register unit 10b is connected to the site W on the gate line S1 through the second connecting line 62, and the gate line S1 is the second scanning line 22 connected to the second shift register unit 10b. The second connecting line 62 and the second driving signal line 42 are located on the same side of the circuit group 30Z, and the second connecting line 62 and the second driving signal line 42 are located in the same layer. In the embodiment of the present invention, the position setting of the second connecting line 62 and the second driving signal line 42 can make the wiring in the panel more compact, and the arrangement of the connecting line 60 will not affect the wiring of the circuit group 30Z in the area where the shift register unit 10 is located, so that the wiring mode of the circuit group 30Z at each position in the entire display area is the same, which can ensure the etching uniformity in the manufacturing process.

[0066] When the strobe signal S1 and the strobe signal S2 of the pixel circuit are respectively provided by the two-stage second shift register unit 10b in a set of driving circuits, Fig.12 and Fig.14 From the above, the display panel is also provided with a third connection line 63, which is led out from the output end of the second shift register unit 10b and connected to the gate line S2 corresponding to the pixel circuit in the previous pixel circuit row. In other words, a second shift register unit 10b provides a gate signal S1 to the gate line S1 corresponding to the pixel circuit row where it is located, and provides a gate signal S2 to the gate line S2 corresponding to the previous pixel circuit row.

[0067] In some embodiments, Fig.10 and Fig.14 As shown, the display panel includes a plurality of data lines 50 extending along the second direction y, and one pixel circuit 30 in the circuit group 30Z is connected to one data line 50. Specifically, the pixel circuit 30 is connected to the corresponding data line 50 via the data transmission line Data. The n data lines 50 connected to the circuit group 30Z are located on the same side of the circuit group 30Z in the first direction x. At the position where the shift register unit 10 is provided, the n data lines 50 are located on the side of the driving signal line 40 away from the circuit group 30Z connected thereto. Fig. 9From the perspective of FIG. 3 , the circuit group 30Z is provided with a second wiring area Z2 on both sides of the first direction x, and the second wiring area Z2 is provided with not only data lines 50 but also other signal lines such as power lines. In the embodiment of the present invention, the n data lines 50 connected to the circuit group 30Z are located on the same side of the circuit group 30Z in the first direction x. When some power supply structures are made in the same layer as the data lines 50, it is convenient to arrange an appropriate power supply structure on the other side opposite to the data lines 50 to meet the driving of the pixel circuit 30. In addition, at the position where the shift register unit 10 is arranged, the n data lines 50 are arranged farther away from the circuit group 30Z connected to the data lines 50 than the drive signal lines 40. When the drive signal lines 40 are connected to the shift register unit 10, there is no need to cross the data lines 50, which can prevent the coupling effect between the data lines 50 and the clock signal lines in the drive signal lines 40, and avoid adverse effects on the circuit performance.

[0068] exist Fig.14 The same fill pattern represents the same film layer. Fig.14 It can be seen that the driving signal line 40 and the data line 50 are located in the same layer. In the embodiment of the present invention, the driving signal line 40 and the data line 50 are arranged in the same layer, so that the film layer where the data line 50 is located can be reasonably and fully utilized. In addition, the driving signal line 40 and the data line 50 are located on the same side of the circuit group 30Z. When some power supply structures are made in the same layer as the data line 50, it is convenient to arrange the data line 50 and the power supply structure on the left and right sides of the circuit group 30Z to meet the driving of the pixel circuit 30.

[0069] In some embodiments, Fig.15 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.15 The diagram shows a partial film structure in the display panel, and shows the area where the 2*2 circuit groups 30Z are located. Fig.15 As shown, the display panel includes a first power line 71 extending along the second direction y and a first power electrode 72 extending along the first direction x. The first power line 71, the first power electrode 72, and the data line 50 are located in the same layer. The first power line 71 and the n data lines 50 are located on both sides of the circuit group 30Z, respectively. The first power electrode 72 is connected to the first power line 71 at one end away from the n data lines 50. Fig.15 Where n=3. Fig.15 is a top view of the display panel, and it can be understood that the top view direction is the same as the direction perpendicular to the display panel substrate. Fig.15 It can be seen that, along the direction perpendicular to the plane of the substrate, the first power electrode 72 overlaps and is electrically connected to the circuit group 30Z. Figure 7 From the perspective of FIG. 5 , the first power electrode 72 is connected to the node q1 in the pixel circuit 30 through a via hole penetrating the insulating layer, so as to provide the first power signal Pvdd to the pixel circuit 30 .

[0070] In the embodiment of the present invention, the first power line 71, the first power electrode 72, and the data line 50 are arranged in the same layer, and the first power line 71 and the n data lines 50 connected to the circuit group 30Z are arranged on both sides of the circuit group 30Z. In this way, the film layer where the data line 50 is located can be fully and reasonably utilized, and it is ensured that each pixel circuit 30 in the circuit group 30Z can receive the first power signal Pvdd provided by the first power line 71 through the first power electrode 72.

[0071] In addition, combined Figure 7 From the perspective of FIG. 1 , the first plate B1 of the storage capacitor Cst in the pixel circuit 30 is connected to the node q1, that is, the first plate B1 receives the first power signal Pvdd, and the three first plates B1 in the circuit group 30Z are connected to each other to form an auxiliary power line 71F extending along the first direction x. The extending direction of the auxiliary power line 71F is the same as that of the first plate B1. Fig.15 The extension directions of the first power lines 71 intersect each other, and the two transmit the same signal, thereby forming a grid-like power routing, reducing the voltage drop of the transmitted first power signal Pvdd.

[0072] In other embodiments, Fig.16 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.16 exist Fig.15 Based on the embodiment, a second power line in the display panel is also illustrated. Fig.16 As shown, the display panel also includes a second power line 73 extending along the second direction y and a second auxiliary power line 73F extending along the first direction x. The second power line 73 and the second auxiliary power line 73F cross and are electrically connected to transmit a second power signal Pvee. The second power line 73 and the second auxiliary power line 73F are located in the same layer, and the film layer where the second power line 73 is located is located on the side of the film layer where the first power line 71 is located away from the substrate. A connecting electrode 74 is also provided in the film layer where the second power line 73 is located. The connecting electrode 74 serves as an anode, and a part of the second auxiliary power line 73F serves as a cathode. The light-emitting device is connected to the anode and the cathode correspondingly. Figure 7 Come and see, Figure 7 The node q2 is also illustrated in the figure. In the pixel circuit, the node q2 is connected to the connection electrode 74 through a via hole penetrating the insulating layer, so that power is supplied to the connection electrode 74.

[0073] Combination Fig. 9 and Fig.17 According to the embodiment, at least the data line 50 , the second power line 73 and the first power line 71 are arranged in the second wiring area Q2 extending along the second direction y.

[0074] In other embodiments, Fig.17A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.18 for Fig.17 A schematic cross-sectional view at the midline AA′. Fig.17 Shows the area where a circuit group is located. Fig.17 In the figure, only the signal lines extending along the first direction x across the pixel circuit 30 region are shown, and the pixel circuit 30 is not shown. Fig.17 As shown, the display panel includes a reset signal line 75 extending along the second direction y and an auxiliary reset line 75F extending along the first direction x, the auxiliary reset line 75F and the reset signal line 75 cross and are electrically connected to provide a reset signal Vref; the pixel circuit 30 is electrically connected to the auxiliary reset line 75F, and the auxiliary reset line 75F and the reset signal line 75 are located in the same layer. The signal lines extending along the first direction x include a gate line S1, a gate line S2, a light emitting control line Emit, a reset signal line Vref (that is, an auxiliary reset line 75F), and an auxiliary power line 71F.

[0075] Combination Fig.17 and Fig.18 From the perspective of FIG. 1 , along a direction e perpendicular to the plane of the substrate 00, the reset signal line 75 and the first power line 71 at least partially overlap. Fig.18 As shown, the display panel includes a first metal layer 01 and a second metal layer 02 located on one side of a substrate 00, and the first metal layer 01 is located on a side of the second metal layer 02 away from the substrate 00. The first power line 71 is located in the first metal layer 01, and at least part of the reset signal line 75 is located in the second metal layer 02.

[0076] In the embodiment of the present invention, the auxiliary reset line 75F and the reset signal line 75 are arranged, and the two are crossed and electrically connected to form a grid-like routing, which can reduce the voltage drop of the reset signal transmission and improve the display uniformity. The reset signal line 75 and the first power line 71 with the same extension direction are arranged in different layers and the two are at least partially overlapped, which can save the space occupied by the wiring in the first direction x and improve the resolution.

[0077] Combination Fig. 9 and Fig.17 According to the embodiment, at least a data line 50 , a reset signal line 75 and a first power line 71 are arranged in the second wiring area Q2 extending along the second direction y.

[0078] In some embodiments, Fig.17 and Fig.18As shown, the display panel also includes a third metal layer 03, and the third metal layer 03 is located between the second metal layer 02 and the first metal layer 01; the reset signal line 75 includes a first line segment 751 and a second line segment 752, the first line segment 751 is located in the second metal layer 02, the second line segment 752 is located in the third metal layer 03, and the two ends of the second line segment 752 are respectively connected to a first line segment 751. Specifically, the second line segment 752 and the first line segment 751 are connected through a via V that penetrates the insulating layer. The second line segment 752 is a bridge connection line between the two first line segments 751.

[0079] like Figure 7 As shown, the pixel circuit 30 includes a storage capacitor Cst, and the storage capacitor Cst includes a first plate, Fig.17 The mark in the middle shows the position of the first electrode plate B1. A plurality of first electrode plates B1 in a pixel circuit row are connected to form an auxiliary power line 71F. The auxiliary power line 71F is located in the second metal layer 02. Fig.18 It can be seen that along the direction e perpendicular to the plane where the substrate 00 is located, the auxiliary power line 71F and the second line segment 752 are insulated and crossed. In the embodiment of the present invention, the auxiliary power line 71F and the first power line 71 are crossed and electrically connected to form a grid-like routing, which can reduce the voltage drop of the first power signal during transmission and improve display uniformity. Under the condition that the wiring requirements of the auxiliary power line 71F are met, the structure of the reset signal line 75 is further designed. At the intersection of the reset signal line 75 and the auxiliary power line 71F, the reset signal line 75 adopts a cross-bridge line design to avoid short circuit between the reset signal line 75 and the auxiliary power line 71F.

[0080] In some embodiments, Fig.17 and Fig.18 As shown, the display panel includes a fourth metal layer 04, the fourth metal layer 04 is located on a side of the second metal layer 02 close to the substrate 00, the scan line 20 includes at least one first sub-scan line 211, the first sub-scan line 211 is located in the fourth metal layer 04, and the first sub-scan line 211 includes a light-emitting control line Emit. In a direction perpendicular to the plane where the substrate is located, the first sub-scan line 211 is insulated and crossed with the second line segment 752. Such a setting can increase the distance between the first sub-scan line 211 and the reset signal line 75, thereby reducing the parasitic capacitance between the two, which is conducive to improving the stability of the transmission scan signal.

[0081] In some embodiments, the second metal layer 02 and the fourth metal layer 04 are made of the same material, and the material includes metal molybdenum.

[0082] In some embodiments, the first metal layer 01 and the third metal layer 03 are made of the same material, and the material includes metal titanium and / or aluminum. Optionally, the first metal layer 01 and the third metal layer 03 are both titanium / aluminum / titanium structures.

[0083] In some embodiments, the display panel further includes a semiconductor layer and a light shielding layer, wherein the semiconductor layer is located on a side of the fourth metal layer 04 close to the substrate 00, and the channels of each transistor and some connecting wires are located on the semiconductor layer. The light shielding layer is located on a side of the semiconductor layer close to the substrate 00, and the light shielding layer is used to shield the channels of each transistor from light to prevent light from irradiating the channels and affecting the performance of the transistors.

[0084] Fig.17 In the embodiment, the reset signal line 75 is designed to be replaced by a bridge at the intersection of the reset signal line 75 and the auxiliary power line 71F. In other embodiments, the auxiliary power line 71F is designed to be replaced by a bridge at the intersection of the reset signal line 75 and the auxiliary power line 71F. In other embodiments, the reset signal line 75 and the auxiliary power line 71F are located in different metal layers, which is not illustrated in the figure.

[0085] like Fig.17 As shown, the display panel includes a scan line 20 extending along a first direction x, and the gate line S1, the gate line S2, and the light emitting control line Emit all belong to the scan line 20. Fig.17 It can be seen from the top view that, along the direction perpendicular to the plane of the substrate, the scan line 20 and the reset signal line 75 are insulated and cross each other.

[0086] Combination Fig.18 From the perspective of the display panel, the display panel further includes a third metal layer 03 and a fourth metal layer 04. The third metal layer 03 is located between the second metal layer 02 and the first metal layer 01, and the fourth metal layer 04 is located on the side of the second metal layer 02 close to the substrate 00. The scan line 20 includes at least one second sub-scan line 212, and the second sub-scan line 212 is located in the third metal layer 03. Fig.18 Schematically, the second sub-scan line 212 includes a gate line S1 and a gate line S2.

[0087] Fig.19 for Fig.17 Enlarged schematic diagram of the Q2 position in the middle area, Fig.19 The local position of the gate line S1 is shown in FIG. Fig.19As shown, the pixel circuit 30 includes a first transistor T′, a gate g of the first transistor T′ is located in the fourth metal layer 04, and the gate g of the first transistor T′ is connected to the second sub-scanning line 212 through a via V1. The channel of the first transistor T′ is located in the semiconductor layer 05, and the semiconductor layer 05 is located on the side of the fourth metal layer 04 close to the substrate. In this embodiment, the second sub-scanning line 212 is arranged in the third metal layer 03, and the manufacturing material of the third metal layer 03 includes metal aluminum and / or metal titanium, which can reduce the resistance of the second sub-scanning line 212, thereby reducing the voltage drop of the transmission scanning signal, reducing the delay difference of receiving the scanning signal at each position of the pixel circuit row, and improving the display uniformity.

[0088] In some embodiments, Fig. 9 As shown, the shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b, and the scan line 20 includes a first scan line 21 and a second scan line 22. The two points W of the first scan line 21 are connected to the two first shift register units 10a, and the two points W of the second scan line 22 are connected to the two second shift register units 10b. Fig. 9 The layout of a first region Q1 is shown. The driving signal line 40 includes a first driving signal line 41 and a second driving signal line 42. The first shift register unit 10a is connected to the first driving signal line 41, and the second shift register unit 10b is connected to the second driving signal line 42. In the first region Q1, the arrangement of the first shift register unit 10a and the first driving signal line 41 is the same as the arrangement of the second shift register unit 10b and the second driving signal line 42. Fig. 9 In the figure, the driving signal line 40 is shown to be located on the right side of the shift register unit 10 to which it is connected. In other embodiments, the driving signal line 40 may also be located on the left side of the shift register unit 10 to which it is connected. When applied to transparent display, the design of the embodiment of the present invention can make the width of the non-transmitting area in the first area Q1 relatively regular in the first direction x, avoiding the formation of a non-transmitting area with a larger width between the circuit column where the first shift register unit 10a is located and the circuit column where the second shift register unit 10b is located, which affects the transparent display effect.

[0089] like Fig. 9 As shown, the plurality of circuit groups 30Z are arranged in a second direction y to form a circuit column 30L. In the first region Q1, the circuit column 30L where the first shift register unit 10a is located is adjacent to the circuit column 30L where the second shift register unit 10b is located. Figure 2 The relevant description of the embodiment is understood. Fig. 9In the embodiment, the setting of the circuit column 30L where the first shift register unit 10a and the second shift register unit 10b are located can facilitate setting both the first shift register unit 10a and the second shift register unit 10b near the first virtual line X1, which can balance the delay difference of the scanning signal at different positions of the first scanning line 21 and the delay difference of the scanning signal at different positions of the second scanning line 22 in the first direction x, thereby improving display uniformity.

[0090] In some embodiments, Fig. 9 As shown, the shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b, the scan line 20 includes a first scan line 21 and a second scan line 22, two sites W of the first scan line 21 are connected to the two first shift register units 10a, and two sites W of the second scan line 22 are connected to the two second shift register units 10b. Fig. 9 Only the layout in the first area Q1 is illustrated. In the first area Q1, at the location of the same pixel circuit row 30H, the first shift register unit 10a and the second shift register unit 10b are located on the same side of the circuit group 30Z in the second direction y. This arrangement makes the shape of the transmission area TG in the circuit column 30L where the first shift register unit 10a is located and the circuit column 30L where the second shift register unit 10b is located substantially the same, and the shape of the transmission area TG is more regular, which can ensure the display effect of transparent display.

[0091] In some embodiments, Fig. 20 A schematic diagram of another display panel provided by an embodiment of the present invention, such as Fig. 20 As shown, the shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b, the scan line 20 includes a first scan line 21 and a second scan line 22, two sites W of the first scan line 21 are connected to the two first shift register units 10a, and two sites W of the second scan line 22 are connected to the two second shift register units 10b. The display panel includes a first virtual line X1 and a second virtual line X2 extending along a second direction y, and the second direction y intersects the first direction x; the pixel circuit row ( Fig. 20The first virtual line X1 is a first virtual line X1 having a first edge Y1 and a second edge Y2 opposite to each other in the first direction x. In the first direction x, the first virtual line X1 is at a distance of L / 4 from the edge of the pixel circuit row, and the second virtual line X2 is at an equal distance from the edges on both sides of the pixel circuit row. The two first regions Q1 each include a first virtual line X1. In the two first regions Q1, the first shift register unit 10a and the second shift register unit 10b are respectively located on both sides of the first virtual line X1. In this embodiment, the second virtual line X2 is equivalent to the center line of the display panel, and the two first virtual lines X1 are equivalent to the 1 / 4 dividing line and the 3 / 4 dividing line of the display panel in the first direction x. The first shift register unit 10a and the second shift register unit 10b are both arranged near the first virtual line X1, which can balance the delay difference of the scanning signal at different positions of the first scanning line 21 and the delay difference of the scanning signal at different positions of the second scanning line 22 in the first direction x, thereby improving the display uniformity.

[0092] Further, such as Fig. 20 As shown, two groups of second shift register units 10b located in two first regions Q1 are arranged between two first virtual lines X1, the first shift register unit 10a in one first region Q1 is located between the first virtual line X1 and the first edge Y1, and the first shift register unit 10a in another first region Q1 is located between the first virtual line X1 and the second edge Y2. Such arrangement enables the first shift register units 10a in the two first regions Q1 to be symmetrical with respect to the second virtual line X2, and the second shift register units 10b in the two first regions Q1 to be symmetrical with respect to the second virtual line X2, which is conducive to making the two points W1 on the first scan line 21 symmetrical with respect to the second virtual line X2, and the two points W1 on the second scan line 22 symmetrical with respect to the second virtual line X2, which can further improve the delay difference of the scan signal at different positions on the first scan line 21 and the delay difference of the scan signal at different positions on the second scan line 22, and improve the display uniformity.

[0093] Fig.21 A driving schematic diagram of a display panel provided by an embodiment of the present invention, such as Fig.21 As shown, the driving of the pixel circuit row 30H requires the use of a strobe signal S1, a strobe signal S2 and a light-emitting control signal Emit. A plurality of first shift register units 10a form a first driving circuit 81, and a plurality of cascaded second shift register units 10b form a second driving circuit 82. The first driving circuit 81 is used to provide the light-emitting control signal Emit required by the pixel circuit, and the second driving circuit 82 is used to provide the strobe signal S1 and the strobe signal S2 required by the pixel circuit. Figure 8According to the illustrated pixel circuit, the first light-emitting control transistor T5 and the second light-emitting control transistor T6 in the pixel circuit are connected to the first shift register unit 10a in the first driving circuit 81, and the data writing transistor T3 and the gate reset transistor T1 are correspondingly connected to the second shift register unit 10b in the second driving circuit 82. Fig.21 The driving conditions of the n-th pixel circuit row 30H(n) and the n-1-th pixel circuit row 30H(n-1) are illustrated in FIG. n is an integer, and n≥2. The output end of the n-th first shift register unit 10a(n) is connected to the scan line to provide the n-th pixel circuit row 30H(n) with a light emitting control signal Emit, and the output end of the n-th second shift register unit 10b(n) is connected to a scan line to provide the n-th pixel circuit row 30H(n) with a selection signal S1, and is connected to another scan line to provide the n-1-th pixel circuit row 30H(n-1) with a selection signal S2. In the two first regions Q1 of the display panel, a first driving circuit 81 and a second driving circuit 82 are provided.

[0094] In some embodiments, Fig. 22 A schematic diagram of another display panel provided by an embodiment of the present invention, Fig.23 FIG. 1 is a driving schematic diagram of another display panel provided by an embodiment of the present invention. Fig. 22 As shown, the shift register unit 10 includes a first shift register unit 10a and a second shift register unit 10b, the scan line 20 includes a first scan line 21 and a second scan line 22, a site W1 on the scan line 20 is located in a first region Q1, two sites W of the first scan line 21 are connected to the two first shift register units 10, and two sites W of the second scan line 22 are connected to the two second shift register units 10. Fig. 22 The diagram shows a partial position of a first area Q1 in the display panel, wherein the second shift register unit 10b includes a first gate shift register unit 10b1 and a second gate shift register unit 10b2. The first gate shift register unit 10b1 and the second gate shift register unit 10b2 are connected to the corresponding second scan lines 22, respectively.

[0095] Combination Figure 8From the perspective of FIG. 3 , the pixel circuit 30 includes a data writing module 31, a gate reset module 32 and a light emitting control module 33; the data writing module 31 includes a data writing transistor T3, the gate reset module 32 includes a gate reset transistor T1, and the light emitting control module 33 includes a first light emitting control transistor T5 and a second light emitting control transistor T6. Among them, the second scanning line 22 connected to the first gate shift register unit 10b1 is connected to the gate reset module 32, and the second scanning line 22 connected to the second gate shift register unit 10b1 is connected to the data writing module 31; the first scanning line 21 connected to the first shift register unit 10a is connected to the light emitting control module 33. That is, the second scanning line 22 connected to the first gate shift register unit 10b1 provides the strobe signal S1 required by the pixel circuit 30, and the second scanning line 22 connected to the second gate shift register unit 10b1 provides the strobe signal S2 required by the pixel circuit 30; the first scanning line 21 connected to the first shift register unit 10a provides the light emitting control signal Emit required by the pixel circuit 30.

[0096] like Fig.23 As shown, a plurality of first shift register units 10a form a first driving circuit 91, a plurality of cascaded first gate shift register units 10b1 form a second driving circuit 92, and a plurality of cascaded second gate shift register units 10b2 form a third driving circuit 93. The first driving circuit 91 is used to provide the light emission control signal Emit required by the pixel circuit, the second driving circuit 92 is used to provide the selection signal S1 required by the pixel circuit, and the third driving circuit 93 is used to provide the selection signal S2 required by the pixel circuit. Figure 8 From the illustrated pixel circuit, the light emitting control module 33 in the pixel circuit is connected to the first shift register unit 10a in the first driving circuit 91, the gate reset module 32 is connected to the first gate shift register unit 10b1 in the second driving circuit 92, and the data writing module 31 is connected to the second gate shift register unit 10b2 in the third driving circuit 93. Fig.23 The driving conditions of the n-th pixel circuit row 30H(n) and the n-1-th pixel circuit row 30H(n-1) are illustrated in FIG. n is an integer, and n≥2. The output end of the n-th first shift register unit 10a(n) is connected to the first scan line to provide the n-th pixel circuit row 30H(n) with a light emitting control signal Emit, the output end of the n-th first gate shift register unit 10b1 is connected to a second scan line to provide the n-th pixel circuit row 30H(n) with a selection signal S1, and the n-th second gate shift register unit 10b2 is connected to another second scan line to provide the n-th pixel circuit row 30H(n) with a selection signal S2. The first driving circuit 91, the second driving circuit 92, and the third driving circuit 93 are arranged in the two first regions Q1 of the display panel.

[0097] In the embodiment of the present invention, the data writing module 31 and the gate resetting module 32 in the pixel circuit are provided with selection signals by their corresponding shift register units, which can increase the driving capability and meet the driving requirements of large-size display screens.

[0098] Fig. 22 In the embodiment, for the first gate shift register unit 10b1 and the second gate shift register unit 10b2, one shift register unit drives one pixel circuit row 30H. The layout of the first gate shift register unit 10b1 and the second gate shift register unit 10b2 can be referred to. Fig.12 The design in Fig. 22 In the embodiment, the first gate shift register unit 10b1 and the second gate shift register unit 10b2 do not need to be provided with the third connection line 63 .

[0099] The above-mentioned related embodiments illustrate a pixel circuit 30, which includes 7 transistors and 1 capacitor. When the pixel circuit 30 is driven, the following can be set in the first area Q1: Fig. 20 In the embodiment, the first shift register unit 10a and the second shift register unit 10b are provided, or the first region Q1 is provided with the following Fig. 22 The first shift register unit 10a, the first gate shift register unit 10b1 and the second gate shift register unit 10b2 in the embodiment.

[0100] The pixel circuit in the embodiment of the present invention may also have other structures. Fig.24 Another pixel circuit schematic diagram provided by an embodiment of the present invention. Fig.24 As shown, the pixel circuit includes a first circuit PAM and a second circuit PWM, the first circuit PAM is configured to control the amplitude of the driving current provided to the sub-pixel based on the first data voltage PAM-Data, and the second circuit PWM is configured to control the duration of the driving current provided to the sub-pixel based on the second data voltage PWM-Data, and the sub-pixel includes a light-emitting device LED.

[0101] The first circuit PAM includes a first driving transistor T7, a first gate reset transistor T8, a first data writing transistor T9, a first compensation transistor T10, a first control transistor T11, a second control transistor T12, an electrode reset transistor T13 and a first storage capacitor C20. The first storage capacitor C20 is a storage capacitor in the first circuit PAM. The first driving transistor T7 is connected in series between the first control transistor T11 and the second control transistor T12, the first control transistor T11 is connected between the first power supply voltage PAM-vdd and the first pole of the second driving transistor T7, and the second control transistor T12 is connected between the second pole of the first driving transistor T7 and the light emitting device LED. The first driving transistor T7 is configured to generate a driving current under the control of its gate voltage. The first data writing transistor T9 is connected to the first pole of the first driving transistor T7, the first compensation transistor T10 is connected to the second pole and the control end of the first driving transistor T7, and the first gate reset transistor T8 is connected to the control end (i.e., the gate) of the first driving transistor T7. The first plate of the first storage capacitor C20 is connected to the gate of the first driving transistor T7, and the second plate of the first storage capacitor C20 is connected to the first power supply voltage PAM-vdd. The electrode reset transistor T13 is connected to the first electrode of the light emitting device LED, the second control transistor T12 is also connected to the first electrode of the light emitting device LED, and the second electrode of the light emitting device LED is connected to the third power supply voltage VEE. The gate of the first gate reset transistor T8 is connected to the first scan signal PAM-S1; the gates of the first data writing transistor T9, the first compensation transistor T10, and the electrode reset transistor T13 are connected to the second scan signal PAM-S2. The control end of the first control transistor T11 and / or the control end of the second control transistor T12 receive the first control signal PAM-EM. In addition, Figure 5 The first end of the electrode reset transistor T13 receives the third power supply voltage VEE, and the second end is connected to the first electrode plate of the light emitting device LED. In other embodiments, the first end of the electrode reset transistor T13 may receive the reset signal PAM-REF or the constant voltage signal PAM-INIT.

[0102] The second circuit PWM includes a second driving transistor T1, a second gate reset transistor T2, a second data writing transistor T3, a second compensation transistor T4, a third control transistor T5, a fourth control transistor T6, and a second storage capacitor C10. The third control transistor T5 is connected between the second power supply voltage PWM-vdd and the first electrode of the second driving transistor T1, and the fourth control transistor T6 is connected between the second electrode of the second driving transistor T1 and the gate of the first driving transistor T7. The second data writing transistor T3 is connected to the first electrode of the second driving transistor T1, the second compensation transistor T4 is connected to the second electrode and the gate of the second driving transistor T1, the second gate reset transistor T2 is connected to the gate of the second driving transistor T1, and one plate of the second storage capacitor C10 is connected to the second driving transistor T1, and the other plate receives the sweep signal SWEEP. Among them, the gate of the second gate reset transistor T2 is connected to the third scanning signal PWM-S1; the gates of the second data writing transistor T3 and the second compensation transistor T4 are connected to the fourth scanning signal PWM-S2. The gates of the third control transistor T5 and the fourth control transistor T6 are connected to the second control signal PWM-EM.

[0103] Fig.24 The output end of the second circuit PWM (i.e., the output end of the fourth control transistor T6) is connected to the gate of the first driving transistor T7. In another embodiment, the output end of the second circuit PWM is connected to the gate of the second control transistor T12, which is not shown in the figure. In another embodiment, an additional light-emitting duration control transistor is provided in the light-emitting series circuit of the first circuit PAM, such as Fig.24 A light-emission duration control transistor is connected in series between the second control transistor T12 and the light-emitting device LED, and the output end of the second circuit PWM is connected to the gate of the light-emission duration control transistor.

[0104] Included in the display panel Fig.24 In the pixel circuit of the embodiment, a plurality of shift drive circuits are arranged in the display panel, including at least a first shift drive circuit providing a first scan signal PAM-S1, a second shift drive circuit providing a second scan signal PAM-S2, a third shift drive circuit providing a first control signal PAM-EM, a fourth shift drive circuit providing a third scan signal PWM-S1, a fifth shift drive circuit providing a fourth scan signal PWM-S2, and a sixth shift drive circuit providing a second control signal PWM-EM. In some embodiments, a seventh shift drive circuit providing a sweep signal SWEEP is also included. Each shift drive circuit includes a plurality of cascaded shift register units. The shift register unit in at least one of the above-mentioned shift drive circuits can adopt the design of the above-mentioned related embodiments.

[0105] drive Fig.24At least one of the shift drive circuits of the pixel circuit in the embodiment adopts Figure 1 In the embodiment, the shift register units 10 connected to the same type of scan lines are set in the display areas on the left and right sides of the display panel, and two shift register units 10 are set to be connected to two sites W on a scan line 20, and one site W is located in a first area Q1. The two sites W serve as two signal input sites on the scan line 20, and the scan signal provided by the shift register unit 10 to the scan line 20 is transmitted to the left and right sides respectively from the positions of the two sites W. The setting of the two sites W and the areas where they are located makes the delay difference of the scan signal on both sides of the site W small, which can balance the delay difference of the scan signal at different positions of the display panel in the first direction x, and improve the display uniformity.

[0106] Furthermore, the shift register unit 10 connected to the site W is arranged in the corresponding first area Q1, which reduces the distance between the output end of the shift register unit 10 and the site W connected thereto, reduces the voltage drop of the scanning signal transmission, and is also conducive to narrowing the left and right borders of the display panel.

[0107] Further, if Figure 2 As shown, two shift register units 10 correspondingly connected to two points W on the scan line 10 are located between the two first virtual lines X1. Figure 3 As shown, two shift register units 10 corresponding to two points W on the scan line 10 are arranged, one is located between the first virtual line X1 and the first edge Y1, and the other is located between the first virtual line X2 and the second edge Y2. The relative positions of the two shift register units 10 connected to the same scan line 20 in the two first regions Q1 and the first virtual line X1 are designed so that the two shift register units 10 in the two first regions Q1 are approximately symmetrically designed relative to the second virtual line X2 (the center line of the display panel), so that the delay difference of the scan signal at different positions of the display panel in the first direction x can be further balanced, thereby improving the display uniformity.

[0108] In some embodiments, the distances from two points W on the scan line 10 to the second virtual line X2 may be equal, and the distances from the two shift register units 10 corresponding to the two points W to the second virtual line X2 may be equal. The two points W on a scan line 20 are set symmetrically with respect to the second virtual line X2, and the two shift register units 20 corresponding to the two points W are also symmetrical with respect to the second virtual line X2, so that the scan signals input to the two points W on the scan line 20 are substantially the same, and the voltage drops of the scan signals on the left and right sides of the display panel in the first direction x are substantially the same, which can improve display uniformity.

[0109] In some embodiments, the Figure 5In the design, the shift register unit 10 is configured to include a driving module 11 and an output module 12 arranged in a first direction x, and the arrangement order of the driving modules 11 and the output modules 12 in the two first regions Q1 is the same. Figure 6 In the design, the shift register unit 10 includes a driving module 11 and an output module 12 arranged in a first direction x, and the arrangement order of the driving module 11 and the output module 12 in the two first areas Q1 is a mirror image relationship.

[0110] In addition, when two or more shift register units are provided in a first region Q1, for example, a shift register unit providing a first scan signal PAM-S1 and a shift register unit providing a second scan signal PAM-S2 are two types of shift register units. Fig. 9 In the design of the embodiment, various shift register units and corresponding drive signal lines are arranged in the same arrangement rule.

[0111] When two or more shift register units are provided in a first region Q1, it can be seen that Fig. 9 The shift register units 10 are designed to be disposed at the same pixel circuit row 30H in the first area Q1, and various shift register units 10 are located at the same side of the circuit group 30Z in the second direction y.

[0112] It should be noted that the above Figures 1 to 23 In case of conflict, the technical solutions involved in the embodiments can be applied to Fig.24 In the display panel of the pixel circuit in the embodiment.

[0113] Based on the same inventive concept, an embodiment of the present invention further provides a display device, Fig.25 A schematic diagram of a display device provided by an embodiment of the present invention is shown in FIG. Fig.25 As shown, the display device includes a display panel 100 provided by any embodiment of the present invention. The structure of the display panel has been described in the above embodiment and will not be repeated here. The display device provided by the embodiment of the present invention can be, for example, a mobile phone, a tablet, a computer, a television, a smart wearable product, and other electronic devices with display functions. The display device provided by the embodiment of the present invention can also be a transparent display device, such as a transparent display window; it can also be a spliced ​​display device, such as a large screen in a conference room, a large screen in an exhibition hall, etc.

Claims

1. A display panel, characterized in that: The device comprises a shift register unit, a scan line and a plurality of pixel circuits, wherein the plurality of pixel circuits are arranged in a pixel circuit row in a first direction, the scan line extends along the first direction and connects the pixel circuits in the pixel circuit row, and the length of the pixel circuit row in the first direction is L; The display area of ​​the display panel includes at least two first areas, and the width of the first area in the first direction is L / 10; the pixel circuit row includes a first edge and a second edge opposite to each other in the first direction, and the minimum distance between one of the first areas and the first edge is L / 5, and the minimum distance between another of the first areas and the second edge is L / 5; The scan line includes two sites, one of the first regions includes one of the sites, and one of the sites is connected to an output end of a corresponding shift register unit.

2. The display panel according to claim 1, characterized in that: The shift register unit connected to the site is located in the corresponding first area.

3. The display panel according to claim 2, characterized in that: The display panel includes a first virtual line extending along a second direction, the second direction intersecting the first direction; in the first direction, the first virtual line is at a distance of L / 4 from the edge of the pixel circuit row; the two first regions each include one first virtual line; The two shift register units correspondingly connected to the two sites are located between the two first virtual lines, or one of the two shift register units is located between the first virtual line and the first edge, and the other is located between the first virtual line and the second edge.

4. The display panel according to claim 2, characterized in that: The display panel comprises a second virtual line extending along a second direction, the second direction intersects the first direction, and the first edge and the second edge are equidistant from the second virtual line; The two sites are at an equal distance from the second virtual line, and the two shift register units correspondingly connected to the two sites are at an equal distance from the second virtual line.

5. The display panel according to claim 2, characterized in that: The shift register unit includes a driving module and an output module arranged in the first direction; The arrangement order of the driving modules and the output modules in the two first areas is the same.

6. The display panel according to claim 2, characterized in that: The shift register unit includes a driving module and an output module arranged in the first direction; The arrangement order of the driving modules and the output modules in the two first zones is in a mirror image relationship.

7. The display panel according to claim 2, characterized in that: The display area includes a transmission area and a non-transmission area; n pixel circuits arranged in the first direction form a circuit group, where n is an integer and n≥2; In the first region, the shift register unit and the circuit group adjacent thereto in a second direction form a continuous non-transmitting region, and the second direction intersects the first direction.

8. The display panel according to claim 7, characterized in that: The transmission area includes a first transmission area and a second transmission area, and the length of the first transmission area in the first direction is smaller than the length of the second transmission area in the first direction; The display panel includes a driving signal line extending along the second direction, and the shift register unit is connected to the driving signal line; the driving signal line in the first area is adjacent to the first transmission area.

9. The display panel according to claim 2, characterized in that: The n pixel circuits arranged in the first direction form a circuit group, n is an integer, n≥2, The display panel includes a driving signal line extending in a second direction, the second direction intersects the first direction, and the shift register unit is connected to the driving signal line; In the first area: the shift register unit is adjacent to the circuit group in the second direction, the drive signal line is located on one side of the circuit group in the first direction, the shift register unit includes a drive module and an output module, and the drive module is located on one side of the output module close to the drive signal line.

10. The display panel according to claim 9, characterized in that: The output end of the shift register unit is connected to the site via a connecting line; The connection line and the drive signal line are located at the same side of the circuit group in the first direction, and the connection line and the drive signal line are located at the same layer.

11. The display panel according to claim 9, characterized in that: The display panel comprises a plurality of data lines extending along the second direction, one pixel circuit in the circuit group is connected to one data line, and the n data lines connected to the circuit group are located on the same side of the circuit group in the first direction; At the position where the shift register unit is arranged, the n data lines are located on a side of the driving signal line away from the circuit group connected thereto.

12. The display panel according to claim 11, characterized in that: The driving signal line and the data line are located in the same layer.

13. The display panel according to claim 11, characterized in that: The display panel further includes a first power line extending along the second direction and a first power electrode extending along the first direction, wherein the first power line, the first power electrode and the data line are located in the same layer; The display panel comprises a substrate, and along a direction perpendicular to a plane where the substrate is located, the first power electrode overlaps and is electrically connected to the circuit group; The first power line and the n data lines are respectively located at two sides of the circuit group, and the first power electrode is connected to the first power line at one end away from the n data lines.

14. The display panel according to claim 13, characterized in that: The display panel further includes a reset signal line extending along the second direction and an auxiliary reset line extending along the first direction, wherein the auxiliary reset line crosses and is electrically connected to the reset signal line; the pixel circuit is electrically connected to the auxiliary reset line; Along a direction perpendicular to the plane where the substrate is located, the reset signal line and the first power line at least partially overlap; The display panel comprises a first metal layer and a second metal layer located on one side of the substrate, wherein the first metal layer is located on a side of the second metal layer away from the substrate; The first power line is located in the first metal layer, and at least a portion of the reset signal line and the auxiliary reset line are located in the second metal layer.

15. The display panel according to claim 14, characterized in that: The display panel also includes a third metal layer, the third metal layer is located between the second metal layer and the first metal layer; the reset signal line includes a first line segment and a second line segment, the first line segment is located in the second metal layer, the second line segment is located in the third metal layer, and two ends of the second line segment are respectively connected to one of the first line segments; wherein, The pixel circuit includes a storage capacitor, the storage capacitor includes a first electrode plate, a plurality of the first electrodes in the pixel circuit row are connected to each other to form an auxiliary power line, the auxiliary power line is located in the second metal layer; along a direction perpendicular to the plane where the substrate is located, the auxiliary power line is insulated and crossed with the second line segment; And / or, the display panel includes a fourth metal layer, the fourth metal layer is located on the side of the second metal layer close to the substrate, the scan line includes at least one first sub-scan line, the first sub-scan line is located in the fourth metal layer, and the first sub-scan line is insulated and crossed with the second line segment along a direction perpendicular to the plane of the substrate.

16. The display panel according to claim 14, characterized in that: Along a direction perpendicular to the plane where the substrate is located, the scanning line and the reset signal line are insulated and crossed; The display panel further comprises a third metal layer and a fourth metal layer, wherein the third metal layer is located between the second metal layer and the first metal layer, and the fourth metal layer is located on a side of the second metal layer close to the substrate; The scan line includes at least one second sub-scan line, and the second sub-scan line is located in the third metal layer; the pixel circuit includes a first transistor, the gate of the first transistor is located in the fourth metal layer, and the gate of the first transistor is connected to the second sub-scan line through a via.

17. The display panel according to claim 9, characterized in that: The shift register unit includes a first shift register unit and a second shift register unit, the scan line includes a first scan line and a second scan line, the two points of the first scan line are connected to the two first shift register units, and the two points of the second scan line are connected to the two second shift register units; The driving signal line includes a first driving signal line and a second driving signal line, the first shift register unit is connected to the first driving signal line, and the second shift register unit is connected to the second driving signal line; In the first region, an arrangement mode of the first shift register unit and the first driving signal line is the same as an arrangement mode of the second shift register unit and the second driving signal line.

18. The display panel according to claim 17, characterized in that: A plurality of the circuit groups are arranged in a circuit row in the second direction; In the first region, the circuit column where the first shift register unit is located is adjacent to the circuit column where the second shift register unit is located.

19. The display panel according to claim 9, characterized in that: The shift register unit includes a first shift register unit and a second shift register unit, the scan line includes a first scan line and a second scan line, the two points of the first scan line are connected to the two first shift register units, and the two points of the second scan line are connected to the two second shift register units; At the location of the same pixel circuit row in the first area, the first shift register unit and the second shift register unit are located at the same side of the circuit group in the second direction.

20. The display panel according to claim 2, characterized in that: The shift register unit includes a first shift register unit and a second shift register unit, the scan line includes a first scan line and a second scan line, the two points of the first scan line are connected to the two first shift register units, and the two points of the second scan line are connected to the two second shift register units; The display panel includes a first virtual line extending along a second direction, the second direction intersecting the first direction; in the first direction, the first virtual line is at a distance of L / 4 from the edge of the pixel circuit row; the two first regions each include one first virtual line; In the first region, the first shift register unit and the second shift register unit are respectively located at two sides of the first virtual line.

21. The display panel according to claim 2, characterized in that: The pixel circuit includes a data writing module, a gate resetting module and a light emitting control module; The shift register unit includes a first shift register unit and a second shift register unit, the scan line includes a first scan line and a second scan line, the two points of the first scan line are connected to the two first shift register units, and the two points of the second scan line are connected to the two second shift register units; The second shift register unit includes a first gate shift register unit and a second gate shift register unit, the second scan line connected to the first gate shift register unit is connected to the gate reset module, and the second scan line connected to the second gate shift register unit is connected to the data writing module; The first scanning line is connected to the light emitting control module.

22. A display device, characterized in that: A display panel comprising any one of claims 1 to 21.

Images