Memory device and manufacturing method thereof

Abstract

A memory device includes a substrate, a capacitor, a transistor, a word line, a bit line contact, and a body contact. The capacitor is over the substrate. The transistor is over the capacitor, and the transistor includes a channel region, a gate over the channel region, and a source and a drain on opposite sides of the channel region, with the drain over the capacitor. The word line is over and electrically connected to the gate of the transistor. The bit line contact is over and electrically connected to the source of the transistor. The body contact is underlying the source of the transistor. The present disclosure can be used to reduce off-state leakage current of the transistor.

Description

Technical Field

[0001] The present disclosure relates to a memory device and a method for manufacturing the same. Background Art

[0002] During operation of the transistor, carriers stored in the floating body cell (FBC) are mainly generated by impact ionization similar to hot electron injection operation of the channel near the drain side. Impact ionization generates electron and hole pairs, where the electrons are attracted by the drain and the holes are swept to the floating body and serve as transient storage for n-channel devices. Since the parasitic bipolar junction transistor (BJT) operates in the holes accumulated in the body, the off-state leakage current is quite high. Summary of the invention

[0003] Some embodiments of the present disclosure provide a memory device, including a substrate, a capacitor, a transistor, a word line, a bit line contact, and a body contact. The capacitor is located above the substrate. The transistor is located above the capacitor, and the transistor includes a channel region, a gate located above the channel region, and a source and a drain located on opposite sides of the channel region, wherein the drain is located above the capacitor. The word line is located above the gate of the transistor and is electrically connected to the gate of the transistor. The bit line contact is located above the source of the transistor and is electrically connected to the source of the transistor. The body contact is located below the source of the transistor.

[0004] In some embodiments, a bottom of the drain is lower than a bottom of the source.

[0005] In some embodiments, a bottom portion of the source is vertically spaced apart from the body contact.

[0006] In some embodiments, the bit line contact vertically overlaps the body contact.

[0007] In some embodiments, the drain is in contact with the capacitor.

[0008] In some embodiments, the memory device further includes a bit line over and in contact with the bit line contact.

[0009] Some embodiments of the present disclosure provide a memory device including a plurality of memory cells, a bit line, a plurality of bit line contacts, and a body contact. Each of the memory cells includes a transistor and a capacitor electrically connected to the transistor. The word line is electrically connected to the transistor of each of the memory cells. Each of the bit line contacts is electrically connected to the transistor of a corresponding one of the memory cells. The body contact is located vertically below the bit line contact.

[0010] In some embodiments, the capacitor is in contact with the bottom of the drain of the transistor.

[0011] In some embodiments, the transistor is at a higher level than the capacitor.

[0012] In some embodiments, the bit line contact and the body contact are located on opposite sides of the source of the transistor.

[0013] In some embodiments, the body contact and capacitor are at a lower level than the transistor.

[0014] Some embodiments of the present disclosure provide a method for manufacturing a memory device, comprising: forming a capacitor in a first dielectric layer; forming a body contact in the first dielectric layer, wherein the body contact is separated from the capacitor; forming a semiconductor layer above the first dielectric layer and covering the capacitor and the body contact; forming a transistor above the semiconductor layer; and forming a bit line contact in contact with a source of the transistor.

[0015] In some embodiments, forming a body contact includes: forming a second dielectric layer above a first dielectric layer and a capacitor; forming a hard mask layer having an opening above the second dielectric layer; etching the first dielectric layer and the second dielectric layer through the opening of the hard mask layer to form grooves in the first dielectric layer and the second dielectric layer; removing the hard mask layer; forming a body contact material layer that overfills the grooves; and performing a planarization process on the body contact material layer until the first dielectric layer is exposed.

[0016] In some embodiments, forming a transistor includes: forming a hard mask layer above a semiconductor layer, wherein the hard mask layer has an opening overlapping a capacitor; performing a first implantation process through the opening of the hard mask layer as a mask to form a drain of the transistor in the semiconductor layer; and removing the hard mask layer.

[0017] In some embodiments, forming the transistor further includes performing a second implantation process to form a source of the transistor in the semiconductor layer and overlapping the body contact.

[0018] In some embodiments, the doping intensity of the first implantation process is stronger than the doping intensity of the second implantation process.

[0019] In some embodiments, the source of the transistor vertically overlaps the body contact, while the source of the transistor is vertically spaced apart from the body contact.

[0020] In some embodiments, the drain of the transistor is in contact with the capacitor.

[0021] In some embodiments, a bottom of the drain of the transistor is lower than a bottom of the source of the transistor.

[0022] In some embodiments, the manufacturing method further includes forming a bit line in contact with the bit line contact.

[0023] It should be understood that both the foregoing summary and the following detailed description are exemplary and are intended to provide further explanation of the disclosure as claimed. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] The present disclosure may be more fully understood by reading the detailed description of the embodiments with reference to the following accompanying drawings:

[0025] Figure 1 A top view of a memory array according to some embodiments of the present disclosure is illustrated.

[0026] Figure 2 The diagram shows the Figure 1 Cross-sectional view taken along line AA in FIG.

[0027] Figures 3 to 13 FIG. 1 is a cross-sectional view illustrating a method for manufacturing a memory device in some embodiments of the present disclosure. DETAILED DESCRIPTION

[0028] The memory device in some embodiments of the present disclosure includes a body contact for reducing the off-state leakage current of the transistor. Specifically, the body contact contacts the body of the transistor to lead the accumulated holes out of the body of the transistor. Therefore, the off-state leakage current of the transistor is reduced.

[0029] Figure 1 A top view of a memory array in some embodiments of the present disclosure is shown. Figure 2 The diagram shows the Figure 1 The cross-section taken along the AA line in Figure 2. Figure 1 , shows a memory array including a plurality of memory cells. In some embodiments, Figure 1 The memory array is a dynamic random-access memory (DRAM) array and includes a plurality of DRAM cells. A typical DRAM cell includes a capacitor 110 and a transistor (such as Figure 2), wherein the capacitor 110 temporarily stores data based on the charge state of the capacitor 110. The bit line 170 is electrically connected to the source / drain region of the transistor, and the word line 154 is electrically connected to the gate region of the transistor. The bit line 170 has a length direction along a first direction X, and the word line 154 has a length direction along a second direction Y perpendicular to the first direction X. Assuming that the pitch of each of the word line 154 and the bit line 170 is 2F, the horizontal size of the DRAM cell may be 4F. 2 , which means that a DRAM cell can have approximately 4F 2 or smaller area, where F is the half pitch determined by the design rules.

[0030] Figure 2 Shown along Figure 1 A cross-sectional view of the memory device at line AA. Note that for simplicity, Figure 2 Some components are not in Figure 1 As shown in the figure. Figure 2 , a semiconductor substrate 100 is shown. A conductive layer 102 is disposed on the semiconductor substrate 100. As mentioned above, each memory cell of the memory device (such as a DRAM cell) includes a capacitor 110 and a transistor 140. The capacitor 110 is located in a first dielectric layer 104 above the conductive layer 102. The transistor 140 in each memory cell may include a semiconductor layer 142, a drain 144, a source 146, and a gate dielectric layer 152. The word line 154 can also be used as the gate of the transistor 140, and therefore the word line 154 can be interchangeably referred to as the gate 154 of each transistor 140. From another perspective, the word line 154 is electrically connected to the gate of the transistor 140. It is worth noting that although Figure 1 to Figure 2 The word line 154 is shown as a single gate structure, which means that the word line 154 is located on one side of the channel (ie, the semiconductor layer 142 ), but the word line 154 in the memory device may also be a double gate structure, a triple gate structure, or a surrounding gate structure.

[0031] Specifically, capacitor 110 is located above semiconductor substrate 100. Transistor 140 is located above capacitor 110. The portion of semiconductor layer 142 between drain 144 and source 146 is referred to as a channel region of transistor 140. A gate (i.e., word line 154 in the present disclosure) is located above the channel region. Source 146 and drain 144 are located on opposite sides of the channel region, wherein drain 144 is located above capacitor 110. Gate dielectric layer 152 is located above transistor 140, and word line 154 is located above gate dielectric layer 152. The memory device further includes bit line contact 160 and body contact 130. Bit line contact 160 is located above source 146 of transistor 140 and electrically connected to source 146 of transistor 140, and body contact 130 is located below source 146 of transistor 140. That is, the bit line contact 160 and the body contact 130 are located on opposite sides of the transistor 140, and the body contact 130 and the capacitor 110 are located on the same side of the transistor 140. For example, the body contact 130 and the capacitor 110 are located lower than the transistor 140, and the transistor 140 is located higher than the capacitor 110. The bottom of the source 146 is vertically spaced apart from the body contact 130, and the semiconductor layer 142 extends between the source 146 and the body contact 130. The memory device further includes a dielectric layer 162 and a bit line 170. The bit line 170 is located above the bit line contact 160 and contacts the bit line contact 160. The dielectric layer 162 covers the transistor 140 and laterally surrounds the bit line contact 160.

[0032] Return to reference Figure 1 , Figure 1 The memory array may include a plurality of memory cells MC arranged in a matrix. For example, the memory cells MC are arranged as follows: Figure 12×3 matrix as shown, but the present disclosure is not limited thereto. Each of the memory cells MC includes a transistor 140 and a capacitor 110 electrically connected to the transistor 140. The memory array further includes a plurality of word lines 154 and a plurality of bit lines 170. Each of the word lines 154 is electrically connected to the transistors 140 arranged along the Y direction. Each of the bit lines 170 is electrically connected to the transistors 140 arranged along the X direction via a corresponding bit line contact 160, wherein each of the bit line contacts 160 is electrically connected to the transistor 140 of a corresponding one of the memory cells MC. The memory array further includes a plurality of body contacts 130. Each of the body contacts 130 is located directly below the bit line contact 160. That is, one body contact 130 corresponds to more than one bit line contact 160, and thus corresponds to more than one transistor 140. The capacitor 110 is adjacent to a first side of the word line 154 , and the bit line contact 160 is adjacent to a second side of the word line 154 , wherein the second side is opposite to the first side. That is, the capacitor 110 and the body contact 130 are located on opposite sides of the word line 154 .

[0033] During the operation of the transistor 140, electrons and holes are generated. The electrons are attracted by the drain 144. However, the holes can be swept to the first dielectric layer 104 and stored as transient states. When the transistor 140 is turned off, the transient storage caused by the accumulated holes may cause an off-state leakage current, thereby causing the device performance to deteriorate. In this way, in order to reduce the accumulated holes in the semiconductor layer 142, the body contact 130 is disposed under the semiconductor layer 142 and contacts the semiconductor layer 142 to lead the accumulated holes out of the semiconductor layer 142. Therefore, the off-state leakage current can be reduced.

[0034] Figures 3 to 13 FIG. 2 is a cross-sectional view illustrating a method for manufacturing a memory device in some embodiments of the present disclosure. Figure 3 , a conductive layer 102 and a first dielectric layer 104 are sequentially formed on a semiconductor substrate 100. In some embodiments, the semiconductor substrate 100 may be made of a semiconductor material, such as polysilicon, but the present disclosure is not limited thereto, the conductive layer 102 may be made of tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), but the present disclosure is not limited thereto, and the first dielectric layer 104 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto. Subsequently, a capacitor 110 is formed in the first dielectric layer 104. It should be noted that for simplicity, Figure 3 Capacitor 110 is illustrated as a pillar. In some embodiments, capacitor 110 includes an insulating layer surrounded by two electrodes.

[0035] Reference Figure 4, a second dielectric layer 120 is formed on the first dielectric layer 104 and the capacitor 110. The second dielectric layer 120 may be made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto. Figure 5 , a first hard mask layer HM1 is formed over the second dielectric layer 120 . The first hard mask layer HM1 includes an opening O1 that is over the second dielectric layer 120 and exposes a portion of the second dielectric layer 120 that is not over the capacitor 110 .

[0036] Reference Figure 6 , the first dielectric layer 104 and the second dielectric layer 120 are etched through the opening O1 of the first hard mask layer HM1 to form a groove R in the first dielectric layer 104 and the second dielectric layer 120. The groove R is spaced apart from the capacitor 110, so the groove R does not expose the capacitor 110. In some embodiments, different etchants may be used to etch the second dielectric layer 120 and the first dielectric layer 104. Figure 7 , remove the first hard mask layer HM1. Then, form a body contact material layer 130', which overflows the groove R (see Figure 6 ) and extends to the top surface of the second dielectric layer 120. In some embodiments, the body contact material layer 130' can be a semiconductor material or a conductive material. The semiconductor material can be p-type heavily doped polysilicon. The conductive material can be a metal.

[0037] Reference Figure 8 , a planarization process is performed to remove excess material of the body contact material layer 130' until the first dielectric layer 104 is exposed. In some embodiments, during the planarization process, the second dielectric layer 120 is removed. On the other hand, the remaining portion of the body contact material layer 130' is referred to as the body contact 130. In this way, the body contact 130 is formed in the first dielectric layer 104, and the body contact 130 is spaced apart from the capacitor 110. After the planarization process, the first dielectric layer 104 and the capacitor 110 are exposed.

[0038] Reference Fig. 9 , a semiconductor layer 142 is formed over the first dielectric layer 104 and covers the capacitor 110 and the body contact 130. In some embodiments, the semiconductor layer 142 may be p-type moderately doped silicon. In embodiments where the body contact 130 is made of a semiconductor material such as p-type heavily doped polysilicon, the doping concentration of the semiconductor layer 142 is lower than the doping concentration of the body contact 130.

[0039] Reference Fig.10, a gate dielectric layer 152 and a word line 154 are formed over the semiconductor layer 142. Specifically, a dielectric material layer and a conductive material layer are sequentially formed on the semiconductor layer 142. Subsequently, the conductive material layer is patterned to form the word line 154, and then the dielectric material layer is etched using the word line 154 as an etching mask to form the gate dielectric layer 152. In some embodiments, the gate dielectric layer 152 is made of silicon oxide or silicon nitride, but the present disclosure is not limited thereto, and the word line 154 is made of metal, such as tungsten (W), copper (Cu), or molybdenum (Mo), but the present disclosure is not limited thereto.

[0040] Reference Fig.11 , a drain 144 is formed in the semiconductor layer 142 above the capacitor 110. Specifically, a second hard mask layer HM2 is formed above the word line 154 and above the semiconductor layer 142 above the body contact 130. The second hard mask layer HM2 has an opening O2 overlapping the capacitor 110. Subsequently, a first implantation process IMP1 is performed to form the drain 144 through the opening O2 of the second hard mask layer. During the first implantation process IMP1, an n-type dopant is implanted into the semiconductor layer 142 above the capacitor 110. The drain 144 may be made of n-type heavily doped silicon. The doping intensity of the first implantation process is controlled so that the drain 144 contacts the capacitor 110.

[0041] Reference Fig.12 , remove the second hard mask layer HM2. Then, a source 146 is formed in the semiconductor layer 142 above the body contact 130. The source 146 vertically overlaps the body contact 130, while the source 146 is vertically spaced apart from the body contact 130. In this way, a transistor 140 is formed above the semiconductor layer 142. Specifically, a second implantation process IMP2 is performed to form a source 146 in the semiconductor layer 142 and overlap the body contact 130. During the second implantation process IMP2, an n-type dopant is implanted into the semiconductor layer 142 above the capacitor 110 and the body contact 130. The source 146 may be made of n-type heavily doped silicon. The doping intensity of the second implantation process is controlled so that the bottom of the source 146 is spaced apart from the body contact 130. That is, the doping intensity of the first implantation process IMP1 is stronger than the doping intensity of the second implantation process IMP2, so that the bottom of the drain 144 is lower than the bottom of the source 146. Since the bottom of the drain 144 is lower than the bottom of the source 146 , the n-type dopant implanted into the drain 144 during the second implantation process IMP2 does not affect the range of the drain 144 .

[0042] In some embodiments, the capacitor 110 is formed before the source 146 is formed. Therefore, the thermal process of the capacitor 110 will not affect the scope of the source 146. For example, the dopant of the source 146 will not diffuse during the thermal process of forming the capacitor 110, and thus the source 146 will not contact the body contact 130. In embodiments where the body contact 130 is made of a semiconductor material such as p-type heavily doped polysilicon, the semiconductor layer 142 extending between the body contact 130 and the source 146 can avoid a junction between the p-type heavily doped region (i.e., the body contact 130) and the n-type heavily doped region (i.e., the source 146). Therefore, the off-state leakage current caused by the junction between the p-type heavily doped region (i.e., the body contact 130) and the n-type heavily doped region (i.e., the source 146) can also be reduced.

[0043] Reference Fig.13 , a bit line contact 160 is formed to contact the source 146. Specifically, a dielectric layer 162 is first formed over the semiconductor layer 142 and covers the word line 154. Subsequently, a bit line contact 160 is formed in the dielectric layer 162 and on the source 146. After the bit line contact 160 is formed, the bit line contact 160 vertically overlaps the body contact 130. Subsequently, a bit line 170 is formed on the bit line contact 160 and the dielectric layer 162. In some embodiments, the bit line contact 160 is made of a conductive material, such as tungsten (W), titanium nitride (TiN), tantalum nitride (TaN), a doped semiconductor material (e.g., p-type doped or n-type doped silicon), and / or other CMOS contact metals. The dielectric layer 162 can be made of silicon oxide, silicon nitride, but the present disclosure is not limited thereto. The bit line 170 is made of metal such as tungsten (W), copper (Cu), or molybdenum (Mo), but the present disclosure is not limited thereto.

[0044] As mentioned above, the body contact of the memory device can be used to lead the accumulated holes out of the body of the transistor to reduce the off-state leakage current. The body contact contacts the body of the transistor and is spaced apart from the source of the transistor. Therefore, in some embodiments where the body contact is formed by a p-type heavily doped region and the source is formed by an n-type heavily doped region, a junction between the p-type heavily doped region and the n-type heavily doped region is avoided. Therefore, the off-state leakage current caused by the junction between the p-type heavily doped region and the n-type heavily doped region can also be reduced.

[0045] Although the present disclosure has been described in considerable detail with reference to certain embodiments thereof, other embodiments are possible. Therefore, the spirit and scope of the appended claims should not be limited to the description of the embodiments contained herein.

[0046] It will be apparent to those skilled in the art that various modifications and variations can be made in the present disclosure without departing from the scope or spirit of the present disclosure. In view of the foregoing, the present disclosure is intended to cover modifications and variations of the present disclosure that fall within the scope of the appended claims.

[0047]

Explanation of symbols

[0048] 100:Semiconductor substrate

[0049] 102: Conductive layer

[0050] 104: first dielectric layer

[0051] 110: Capacitor

[0052] 120: second dielectric layer

[0053] 130: Main body contact

[0054] 130': Main contact material layer

[0055] 140: Transistor

[0056] 142: Semiconductor layer

[0057] 144: Drain

[0058] 146: Source

[0059] 152: Gate dielectric layer

[0060] 154: Character Line

[0061] 160: Bit line contact

[0062] 162: Dielectric layer

[0063] 170: Bit line

[0064] HM1: First hard mask layer

[0065] HM2: Second hard mask layer

[0066] O1: Opening

[0067] O2: Opening

[0068] R: Groove

[0069] IMP1: First Implantation Process

[0070] IMP2: Second implantation process.

Claims

1. A memory device, characterized in that: Include: substrate; a capacitor located above the substrate; a transistor located above the capacitor, wherein the transistor comprises: Channel area; A gate, located above the channel region; and a source and a drain located on opposite sides of the channel region, wherein the drain is located above the capacitor; a word line located above the gate of the transistor and electrically connected to the gate of the transistor; a bit line contact located above the source of the transistor and electrically connected to the source of the transistor; and A body contact is located below the source of the transistor.

2. The memory device according to claim 1, wherein: The bottom of the drain is lower than the bottom of the source.

3. The memory device according to claim 1, wherein: Wherein a bottom of the source is vertically spaced apart from the body contact.

4. The memory device according to claim 1, wherein: wherein the bit line contact vertically overlaps the body contact.

5. The memory device according to claim 1, wherein: The drain electrode is in contact with the capacitor.

6. The memory device according to claim 1, wherein: Further including: A bit line is located above the bit line contact and contacts the bit line contact.

7. A memory device, characterized in that: Include: A plurality of memory cells, wherein each of the plurality of memory cells comprises: transistors; and a capacitor electrically connected to the transistor; a word line electrically connected to the transistor of each of the plurality of memory cells; a plurality of bit line contacts, wherein each of the plurality of bit line contacts is electrically connected to the transistor of a respective one of the plurality of memory cells; and The main body contact is located directly below the plurality of bit line contacts.

8. The memory device according to claim 7, wherein: The capacitor is in contact with the bottom of the drain of the transistor.

9. The memory device according to claim 7, wherein: The transistor is located higher than the capacitor.

10. The memory device according to claim 7, wherein: The plurality of bit line contacts and the body contact are located on opposite sides of a source of the transistor.

11. The memory device according to claim 7, wherein: The positions of the body contact and the capacitor are lower than the position of the transistor.

12. A method for manufacturing a memory device, characterized in that: Include: forming a capacitor in the first dielectric layer; forming a body contact in the first dielectric layer, wherein the body contact is spaced apart from the capacitor; forming a semiconductor layer over the first dielectric layer and covering the capacitor and the body contact; forming a transistor above the semiconductor layer; and A bit line contact is formed in contact with the source of the transistor.

13. The manufacturing method according to claim 12, characterized in that: The forming of the main contact comprises: forming a second dielectric layer over the first dielectric layer and the capacitor; forming a hard mask layer having an opening over the second dielectric layer; etching the first dielectric layer and the second dielectric layer through the opening of the hard mask layer to form recesses in the first dielectric layer and the second dielectric layer; removing the hard mask layer; forming a body contact material layer overfilling the groove; and A planarization process is performed on the body contact material layer until the first dielectric layer is exposed.

14. The manufacturing method according to claim 12, characterized in that: Wherein forming the transistor comprises: forming a hard mask layer over the semiconductor layer, wherein the hard mask layer has an opening overlapping the capacitor; performing a first implantation process to form a drain of the transistor in the semiconductor layer through the opening of the hard mask layer as a mask; and The hard mask layer is removed.

15. The manufacturing method according to claim 14, characterized in that: Wherein forming the transistor further comprises: A second implantation process is performed to form the source of the transistor in the semiconductor layer and overlap the body contact.

16. The manufacturing method according to claim 15, characterized in that: The doping intensity of the first implantation process is stronger than the doping intensity of the second implantation process.

17. The manufacturing method according to claim 12, characterized in that: wherein a source of the transistor vertically overlaps the body contact, while the source of the transistor is vertically spaced apart from the body contact.

18. The manufacturing method according to claim 12, characterized in that: The drain of the transistor is in contact with the capacitor.

19. The manufacturing method according to claim 12, characterized in that: The bottom of the drain of the transistor is lower than the bottom of the source of the transistor.

20. The manufacturing method according to claim 12, characterized in that: Further including: A bit line is formed in contact with the bit line contact.

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