Semiconductor devices and methods for manufacturing finished mill time organic insertors using a

Abstract

A semiconductor device has a carrier. A first redistribution layer is formed over the carrier. A capping layer is formed on the first redistribution layer. The cover layer includes an anti-reflective coating. An insulating layer is formed on the capping layer. An opening is formed through the insulating layer using lithography. A conductive layer is formed in the opening.

Description

Technical Field

[0001] The present invention relates generally to semiconductor devices, and more particularly, to semiconductor devices and methods for fabricating fine pitch organic interposers using dual functional capping layers. Background Art

[0002] Semiconductor devices are commonly found in modern electronic products. Semiconductor devices perform a wide range of functions such as signal processing, high-speed computing, sending and receiving electromagnetic signals, controlling electronic devices, power conversion, optoelectronics, and creating visual images for television displays. Semiconductor devices appear in the fields of communications, networking, computers, entertainment, and consumer products. Semiconductor devices can also be found in military applications, aviation, automobiles, industrial controllers, and office equipment.

[0003] Semiconductor device manufacturers are continually striving to manufacture smaller semiconductor devices to meet the needs of electronic device manufacturers and consumers alike. As the density of components within semiconductor packages increases, the redistribution layers (RDLs) used in semiconductor packages must have conductors with smaller cross-sectional dimensions (e.g., width and height). Smaller RDL cross-sectional areas increase current density and lead to electromigration issues, where molecules of the conductor migrate away from the desired locations of the RDL. Therefore, there is a need for semiconductor manufacturing methods and semiconductor devices that are not susceptible to electromigration. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1a-1c shows a semiconductor wafer having a plurality of semiconductor dies separated by saw streets; Figure 2a-2r A process for forming a semiconductor package with a fine pitch organic interposer using a dual functional capping layer is shown; and Figure 3a and 3b Integration of a semiconductor package into an electronic device is shown. DETAILED DESCRIPTION

[0005] In the following description with reference to the accompanying drawings, the present invention is described in one or more embodiments, wherein the same numerals represent the same or similar elements. Although the present invention is described according to the best mode for achieving the purpose of the present invention, it will be understood by those skilled in the art that the present invention is intended to cover substitutions, modifications and equivalents that may be included in the spirit and scope of the present invention as defined by the appended claims and their equivalents, which are supported by the following disclosure and the accompanying drawings. The features shown in the figures are not necessarily drawn to scale. Elements assigned the same figure numbers in the figures have functions similar to each other. The term "semiconductor die" used herein refers to both the singular and plural forms of the word, and therefore can refer to both a single semiconductor device and multiple semiconductor devices.

[0006] Semiconductor devices are typically manufactured using two complex manufacturing processes: front-end manufacturing and back-end manufacturing. Front-end manufacturing involves forming multiple die on the surface of a semiconductor wafer. Each die on the wafer contains active and passive electrical components that are electrically connected to form a functional circuit. Active electrical components such as transistors and diodes have the ability to control the flow of electrical current. Passive electrical components such as capacitors, inductors, and resistors create the relationship between voltage and current necessary to perform the circuit's function.

[0007] Back-end manufacturing refers to cutting or singulating the completed wafer into individual semiconductor dies and packaging the semiconductor dies for structural support, electrical interconnection, and environmental isolation. In order to singulate the semiconductor dies, the wafer is scribed and broken along the non-functional area of ​​the wafer (called a scribe street or scribe). The wafer is singulated using a laser cutting tool or a saw blade. After singulation, each semiconductor die is arranged on a package substrate, which includes pins or contact pads for interconnection with other system components. Then, the contact pads formed above the semiconductor die are connected to the contact pads in the semiconductor package. The electrical connection can be made with a conductive layer, a bump, a columnar bump, a conductive glue, or a wire bond. A sealant or other molding material is deposited above the semiconductor package to provide physical support and electrical insulation. The completed semiconductor package is then inserted into the electrical system, and the functions of the semiconductor device are made available to other system components.

[0008] Figure 1a A semiconductor wafer 100 is shown having a base substrate material 102 such as silicon, germanium, aluminum phosphide, aluminum arsenide, gallium arsenide, gallium nitride, indium phosphide, silicon carbide, or other bulk material for structural support. A plurality of semiconductor dies or electrical components 104 are formed on the wafer 100, separated by passive inter-die wafer regions or scribe streets 106. The scribe streets 106 provide cutting areas to singulate the semiconductor wafer 100 into individual semiconductor dies 104. In one embodiment, the semiconductor wafer 100 has a width or diameter of 100-450 millimeters (mm).

[0009] Figure 1bA cross-sectional view of a portion of a semiconductor wafer 100 is shown. Each semiconductor die 104 has a back or inactive surface 108 and an active surface 110, which contains analog or digital circuits implemented as active devices, passive devices, conductive layers, and dielectric layers formed on or within the die and electrically interconnected according to the electrical design and function of the die. For example, the circuit may include one or more transistors, diodes, and other circuit elements formed within the active surface 110 to implement analog or digital circuits, such as digital signal processors (DSPs), application specific integrated circuits (ASICs), memories, power devices, or other signal processing circuits. Semiconductor die 104 may also include IPDs for RF signal processing, such as inductors, capacitors, and resistors.

[0010] Conductive layer 112 is formed over active surface 110 using physical vapor deposition (PVD), chemical vapor deposition (CVD), electrolytic plating, electroless plating process, or other suitable metal deposition process. Conductive layer 112 can be one or more layers of aluminum (Al), copper (Cu), tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other suitable conductive materials. Conductive layer 112 operates as a contact pad electrically connected to the circuit on active surface 110.

[0011] Conductive bump material is deposited over conductive layer 112 using evaporation, electrolytic plating, electroless plating, ball drop or screen printing processes. The bump material can be Al, Sn, Ni, Au, Ag, lead (Pb), bismuth (Bi), copper, solder and combinations thereof, with an optional flux solution. For example, the bump material can be eutectic Sn / Pb, high lead solder or lead-free solder. The bump material is bonded to conductive layer 112 using a suitable attachment or bonding process. In one embodiment, the bump material is reflowed by heating the material above its melting point to form a ball or bump 114. In one embodiment, bump 114 is formed over an under-bump metallization layer (UBM) having a wetting layer, a barrier layer and an adhesive layer. Bump 114 can also be compression bonded or thermocompression bonded to conductive layer 112. Bump 114 represents a type of interconnect structure that can be formed over conductive layer 112. The interconnect structure can also use bonding wires, conductive glue, columnar bumps, micro bumps or other electrical interconnects.

[0012] exist Figure 1c , semiconductor wafer 100 is singulated into individual semiconductor die 104 through scribe streets 106 using a saw blade or laser cutting tool 118. Individual semiconductor die 104 may be inspected and electrically tested to identify known good dies (KGD) or known good units (KGU) after singulation.

[0013] Figure 2a-2rA process for forming a semiconductor package with a fine pitch organic interposer using a dual functional capping layer is shown. Figure 2a A carrier 120 is shown that includes a sacrificial substrate material such as silicon, polymer, beryllium oxide, glass, or other suitable low-cost rigid material for structural support. Although the carrier 120 is shown as being sized for fabricating a single unit, larger carriers suitable for forming hundreds or thousands of units at a time are typically used. Towards the end of the fabrication process, the units are singulated from one another.

[0014] A temporary bonding (TB) material 122, such as a thermal or ultraviolet (UV) release layer, is disposed on the carrier 120. The TB material 122 may be a liquid adhesive dispensed over the carrier 120, or a tape cut to the carrier size and disposed onto the carrier.

[0015] A metal bonding layer 124 is formed over the TB material 122. The bonding layer 124 may be one or more layers of Al, Sn, Ni, Au, Ag, titanium (Ti), tantalum (Ta), chromium (Cr), or other suitable conductive materials. In some embodiments, the material for the bonding layer 124 is selected from a group consisting of Al, Ti / Cu, Ta / Cu, Cr, and Ni. The bonding layer 124 may be formed using PVD, CVD, electrolytic plating, electroless plating, or another suitable metal deposition process. A second metal layer 126 is formed over the bonding layer 124. The metal layer 126 is formed of a similar material and a similar process as the bonding layer 124. In combination, the bonding layer 124 and the metal layer 126 serve as a laser blocking layer during stripping from the carrier 120.

[0016] exist Figure 2b In the embodiment, the insulating layer 130 is formed over the carrier 120, the TB material 122, the adhesion layer 124 and the metal layer 126. The insulating layer 130 includes one or more layers of silicon dioxide (SiO2), silicon nitride (Si3N4), silicon oxynitride (SiON), tantalum pentoxide (Ta2O5), aluminum oxide (Al2O3), solder resist, polyimide (PI), benzocyclobutene (BCB), polybenzoxazole (PBO), FR-4 and other materials with similar insulating and structural properties. The insulating layer 130 can be formed using PVD, CVD, printing, lamination, spin coating, spray coating, sintering or thermal oxidation.

[0017] exist Figure 2cIn the embodiment of the present invention, openings 132 and 134 are formed in and through insulating layer 130 using photolithography. In some embodiments, insulating layer 130 is a photosensitive polyimide (PSPI) photoresist layer and is etched by exposing the insulating layer to UV light through a mask, developing, and washing away undesired portions. Opening 132 forms a redistribution layer (RDL) pattern including contact pads 132a and conductive traces 132b. Contact pads 132a are areas that are wide enough to ensure that the conductive layer below or above can physically and electrically contact the conductive layer being formed. Conductive traces 132b form RDL patterns to fan-in or fan-out electrical interconnections between layers.

[0018] Opening 132 is formed only partially through insulating layer 130 to form a horizontally oriented conductive layer. Opening 134 is formed completely through photoresist layer 130 within opening 132 to provide vertical interconnection for the conductive layer being formed. After adhesive layer 124 and metal layer 126 are removed, opening 134 provides a location for external interconnection for the conductive layer to be exposed. In some embodiments, opening 132 is formed in a first etching step and opening 134 is formed in a second etching step. Etching can be performed by laser ablation, chemical etching, photolithography, or other suitable means.

[0019] exist Figure 2d , a seed layer 136 for a conductive layer is formed over the insulating layer 130. The seed layer 136 is conformally formed to include a uniform thickness on all top and side surfaces of the insulating layer 130, including within the openings 132 and 134. The seed layer 136 includes an adhesion layer 136a and a seed layer 136b formed over the adhesion layer. The adhesion layer 136a is typically formed of Ti, and the seed layer 136b is typically formed of Cu, but any other suitable material is used in other embodiments. In other embodiments, the seed layer 136 may include more or less than two layers. The seed layer 136 is formed using PVD, CVD, electrolytic plating, electroless plating, or another suitable metal deposition process.

[0020] exist Figure 2e , a photoresist layer 138 is formed over the seed layer 136. The photoresist layer 138 is patterned by exposure, development, and washing to include openings aligned with the openings 132 and 134 of the insulating layer 130. A conductive material is plated over the seed layer 136 and the photoresist layer 138 to form a conductive layer 140. The conductive material is deposited over the photoresist layer 138, but is not shown because the conductive material is removed together with the photoresist layer, as shown in FIG. Figure 2f As shown, the conductive layer 140 is left just formed within the opening of the insulating layer 130 .

[0021] Conductive layer 140 includes contact pads 140a formed within openings 132a, conductive traces 140b formed within openings 132b, and conductive vias 140c formed within openings 134. Conductive layer 140 is shown in simplified form for ease of illustration, and may be formed with any number of contact pads and any suitable conductive trace pattern as desired to achieve the desired electrical function of the package being formed.

[0022] exist Figure 2g In the embodiment of the present invention, the top surface is planarized to remove the seed layer 136 from the topmost surface of the insulating layer 130, thereby electrically isolating the discrete portions of the conductive layer 140 from each other. The planarization may be performed by a mechanical grinder, laser ablation, chemical mechanical planarization (CMP), or another suitable means.

[0023] exist Figure 2h In the embodiment of the present invention, a capping layer 144 is formed over the insulating layer 130 and the conductive layer 140. The capping layer 144 is formed of an insulating material having good adhesion to the conductive layer 140 (typically Cu) and the insulating layer 130 (typically PI). Some potential materials for the capping layer 144 include Al 2 O 3 、TiO 2 ), chromium(IV) oxide (CrO 2 ) and zinc oxide (ZnO). The capping layer 144 can be formed by PVD, CVD or other suitable methods. Silane coupling agents, spin-on glass or spin-on carbon can also be used and deposited as a spin-on liquid, which may be preferred if PVD or CVD processes are not available, for example due to high degassing.

[0024] exist Figure 2i In the embodiment, insulating layer 150 is formed over capping layer 144. Insulating layer 150 may be formed of any of the materials and using any of the methods described above for insulating layer 130. In one embodiment, insulating layer 150 is a PSPI layer.

[0025] exist Figure 2j 1, openings 152 and 154 are formed through insulating layer 150. Openings 152 and 154 are formed as described above for openings 132 and 134. Opening 152 is formed to only partially pass through insulating layer 150 and is shaped as contact pads 152a and conductive traces 152b. Opening 152 is patterned as needed to redistribute electrical signals across the device footprint. Opening 154 is a through hole that passes completely through insulating layer 150 for ultimate electrical connection to the underlying contact pads of conductive layer 140. In one embodiment, opening 152 is formed in a first etching step and then opening 154 is formed in a second etching step.

[0026] FIG. 2 k shows an embodiment in which the insulating layer 150 is a PSPI layer, and the openings 152 and 154 are formed by a photolithography process. Figure 2k-1 The photolithography in this embodiment is shown, and Figure 2k-2 Photolithography in a hypothetical embodiment is shown without cover layer 144 for comparison purposes. Mask 153 is disposed over insulating layer 150, having the desired pattern for openings 154. Ultraviolet light (typically 365 nanometers) is shone onto mask 153 and insulating layer 150, as shown by light 155. Mask 153 blocks light 155 from hitting insulating layer 150 where openings 154 are desired.

[0027] Light 155 striking insulating layer 150 changes the molecular structure of the insulating layer to form hardened region 150a, while the insulating layer in region 150b remains softer. After exposure to UV light and development, portion 150b is relatively easy to remove while leaving portion 150a in place, thereby creating through hole 154.

[0028] The cover layer 144 is a material that absorbs ultraviolet light at the wavelength being used (eg, 365 nm). Other types of anti-reflective coatings are used in other embodiments, such as index matching, single-layer interference, or multi-layer interference. Figure 2k-2 Light rays 155 are shown reflected by conductive layer 140, as shown by light rays 155a, without cover layer 144. Some of reflected light rays 155a travel into the area below mask 153 and cure some of the insulating layer 150 that is desired to be removed for opening 154. Reflected light rays 155a cause cured area 150a to extend further inward, so the resulting opening 154 is smaller. In the absence of cover layer 144, it is more difficult to control the critical dimension or diameter of opening 154 because reflected light rays 155a are not as easily controlled. Figure 2k-1 In the embodiment of the present invention, the capping layer 144 , which absorbs rather than reflects at least a portion of the light 155 , creates a more vertically oriented boundary between regions 150 a and 150 b so that the diameter of the opening 154 is closer to the size of the mask 153 .

[0029] The capping layer 144 makes it easier to control the critical dimension size of the opening 154. In addition, the capping layer 144 improves the adhesion between the insulating layers 130 and 150. Therefore, the capping layer 144 is said to be dual-functional. In addition to helping reduce delamination between the insulating layers 130 and 150, the adhesion aspect also helps reduce electromigration of the conductive material of the conductive trace 140b. The opening 154 is just one example of the benefit provided by the anti-reflective aspect of the capping layer 144. Essentially all lithography is affected.

[0030] exist Figure 2lIn the embodiment of the present invention, the portion of the capping layer 144 exposed in the opening 154 is removed to expose the underlying portion of the conductive layer 140. Depending on the specific material used, the capping layer 144 can be wet or dry etched. Dry etching can be performed using Ar, O 2 、N 2 CF 4 The capping layer 144 remains as an adhesion layer between the insulating layers 130 and 150, but is removed where needed to provide electrical connection to the conductive layer 140.

[0031] In a similar manner as the conductive layer 140 described above, Figure 2m 154. A conductive layer is formed over insulating layer 150 in the embodiment of the present invention. Seed layer 156 has a similar structure to seed layer 136, such as a Ti adhesion layer and a Cu seed layer. Seed layer 156 is formed to completely cover insulating layer 150 and then removed except within openings 152 and 154. Seed layer 156 physically and electrically contacts conductive layer 140 at the bottom of opening 154. Openings 152 and 154 are filled with a conductive material to form conductive layer 160.

[0032] A capping layer 164 is formed over the insulating layer 150 and the conductive layer 160. The capping layer 164 has similar materials and properties as the capping layer 144 described above. The capping layer 164 also has a dual purpose as both an adhesion layer and an anti-reflective coating. The insulating layer 150 and the conductive layer 160 combine to form an RDL layer 166. Any number of RDL layers 166 may be formed in succession to meet the wiring requirements of the particular device being manufactured, including not forming an RDL layer 166 and leaving the conductive layer 140 as the only RDL layer.

[0033] Figure 2n Three RDL layers 166a-166c are shown formed above the conductive layer 140, which is part of the first RDL layer. Each RDL layer 166a-166c includes a capping layer 164 formed on the layer to provide dual functions for the RDL layer. To simplify the description, the RDL layers 166a-166c are shown as being the same. However, in most embodiments, there will be different wiring layouts between different RDL layers. In some embodiments, the RDL pitch, spacing, or material composition is different between the RDL layers 166a-166c.

[0034] exist Figure 2oIn the embodiment of the present invention, contact pads are formed over RDL layer 166 for mounting components. As described above for insulating layer 150, insulating layer 180 is first formed over cover layer 164c. Openings are formed through insulating layer 180 and cover layer 164c for connecting contact pads to conductive layer 160 below RDL layer 166c. Seed layer 186 is formed as described above for seed layers 136 and 156. As described for conductive layers 140 and 160, contact pad 190 is formed on seed layer 186. Contact pad 192 is formed on contact pad 190. Contact pad 192 is formed by any material and any method described above for conductive layers. Solder wetting layer 194 is formed on contact pad 192. Solder wetting layer 194 is formed by any material and any method described above for conductive layers.

[0035] exist Figure 2p , semiconductor die 200 is mounted on contact pads 190-194. Semiconductor die 200a and 200b may be identical, or used for different complementary functions. In one embodiment, semiconductor die 200a is an application specific integrated circuit (ASIC), and semiconductor die 200b is a high bandwidth memory (HBM) chip used by the ASIC. Semiconductor die 200 is formed similarly to semiconductor die 104 above. Conductive pillars 202 are formed on contact pads of semiconductor die 200. Solder caps 204 are formed on conductive pillars 202. With semiconductor die 200 set on contact pads 190-194, solder caps 204 reflow to mechanically couple the semiconductor die to the contact pads below. In addition to semiconductor die 200, or in place of semiconductor die 200, any other desired electrical components may be mounted on contact pads 190-194, such as discrete active or passive components.

[0036] exist Figure 2q , an underfill 210 is dispensed under the semiconductor die 200. Alternatively, the underfill 210 can be applied on top of the insulating layer 180 and the contact pads 190-194, or on the semiconductor die 200, before the semiconductor die is positioned over the contact pads. An encapsulant or mold compound 212 is deposited over and around the semiconductor die 200 using slurry printing, compression molding, transfer molding, liquid encapsulant molding, vacuum lamination, spin coating, or another suitable applicator. The encapsulant 212 can be a liquid or particulate polymer composite material, such as an epoxy resin, epoxy acrylate, or another suitable polymer, with or without a suitable filler. The encapsulant 212 is non-conductive, provides structural support, and environmentally protects the semiconductor device from external factors and contaminants.

[0037] exist Figure 2rIn the embodiment of the present invention, the panel is flipped over and the carrier 120, TB material 122, adhesive layer 124 and metal layer 126 are removed. A laser is used on the carrier 120 to reduce the adhesion of the TB material 122, thereby allowing the carrier to be removed. The adhesive layer 124 and metal layer 126 block the laser from impacting the layers and devices above. Once the carrier 120 is removed, the adhesive layer 124 and metal layer 126 are removed by chemical etching, laser ablation, CMP or other suitable process.

[0038] A solder bump 220 is formed on the now exposed portion of the conductive layer 140 or the seed layer 136. The solder bump 220 is formed as described above with respect to the bump 114. The second bump 220 is formed on the conductive layer 140 or the seed layer 136. Figure 2r 1 is shown on an exposed portion of the seed layer 136 which is only visible in another cross section. Figure 2r A completed semiconductor package 230 is shown. When a panel of multiple devices is formed at one time, the devices are singulated from one another using a saw blade, laser cutting tool, or other suitable means.

[0039] Figure 3a and 3b Integration of the above-described semiconductor packages and devices (eg, semiconductor package 230 ) into a larger electronic device 300 is shown. Figure 3a A partial cross-sectional view of semiconductor package 230 mounted on a printed circuit board (PCB) or other substrate 302 as part of an electronic device 300 is shown. Bumps 220 are reflowed onto conductive layer 304 of PCB 302 to physically attach and electrically connect semiconductor package 230 to the PCB. In other embodiments, heat pressing or other suitable attachment and connection methods are used. In some embodiments, an adhesive or underfill layer is used between semiconductor package 230 and PCB 302. Semiconductor die 200 is electrically coupled to conductive layer 304 through conductive layers 140 and 160.

[0040] Figure 3b An electronic device 300 is shown having a chip carrier substrate or PCB 302 with a plurality of semiconductor packages disposed on a surface of PCB 302, including semiconductor package 230. Electronic device 300 may have one type of semiconductor package or multiple types of semiconductor packages, depending on the application.

[0041] The electronic device 300 may be a stand-alone system that uses a semiconductor package to perform one or more electrical functions. Alternatively, the electronic device 300 may be a subcomponent of a larger system. For example, the electronic device 300 may be part of a tablet computer, a cellular phone, a digital camera, a communication system, or other electronic device. Alternatively, the electronic device 300 may be a graphics card, a network interface card, or other signal processing card that may be inserted into a computer. The semiconductor package may include a microprocessor, a memory, an ASIC, a logic circuit, an analog circuit, an RF circuit, a discrete device, or other semiconductor die or electrical components. Miniaturization and weight reduction are essential for the product to be accepted by the market. The distance between semiconductor devices may be reduced to achieve higher density. The PCB 302 may have a more irregular shape to conveniently fit into a more ergonomic and smaller device housing.

[0042] exist Figure 3b In the embodiment of the present invention, PCB 302 provides a general substrate for structural support and electrical interconnection of semiconductor packages disposed on the PCB. Conductive signal traces 304 are formed over the surface or within the layers of PCB 302 using evaporation, electrolytic plating, electroless plating, screen printing or other suitable metal deposition processes. Signal traces 304 provide electrical communication between each semiconductor package, mounted components and other external system components. Traces 304 also provide power and ground connections for each semiconductor package.

[0043] In some embodiments, the semiconductor device has two levels of packaging. The first level of packaging is a technique for mechanically and electrically attaching the semiconductor die to an intermediate substrate. The second level of packaging includes mechanically and electrically attaching the intermediate substrate to a PCB. In other embodiments, the semiconductor device may have only a first level of packaging, where the die is mechanically and electrically disposed directly on the PCB.

[0044] For illustrative purposes, several types of first level packages are shown on PCB 302, including bond wire packages 346 and flip chips 348. In addition, several types of second level packages, including ball grid arrays (BGA) 350, bump chip carriers (BCC) 352, land grid arrays (LGA) 356, multi-chip modules (MCM) or SIP modules 358, quad flat no-lead packages (QFN) 360, quad flat packages 362, and embedded wafer level ball grid arrays (eWLB) 364, are shown disposed on PCB 302. In one embodiment, eWLB 364 is a fan-out wafer level package (Fo-WLP) or a fan-in wafer level package (Fi-WLP).

[0045] Depending on the system requirements, any combination of semiconductor packages configured with any combination of first and second level packaging types, as well as other electrical components, can be connected to PCB 302. In some embodiments, electronic device 300 includes a single attached semiconductor package, while other embodiments require multiple interconnected packages. By combining one or more semiconductor packages on a single substrate, manufacturers can incorporate prefabricated components into electronic devices and systems. Because semiconductor packages include complex functions, electronic devices can be manufactured using less expensive components and streamlined manufacturing processes. The resulting device is less likely to fail and is less expensive to manufacture, resulting in a lower cost to the consumer.

[0046] While one or more embodiments of the present invention have been described in detail, those skilled in the art will appreciate that modifications and adaptations may be made to the embodiments without departing from the scope of the invention as set forth in the appended claims.

Claims

1. A method for manufacturing a semiconductor device, comprising: Provide a carrier; forming a first redistribution layer over the carrier; forming a capping layer on the first redistribution layer; forming an insulating layer on the cover layer; forming an opening through the insulating layer using photolithography; as well as A conductive layer is formed in the opening. The method of claim 1 , wherein the cover layer comprises an anti-reflective coating.

3. The method of claim 1, wherein the capping layer comprises Al2O3, TiO2, CrO2, or ZnO and is deposited by physical vapor deposition (PVD) or chemical vapor deposition (CVD). 4 . The method of claim 1 , wherein the capping layer comprises a silane coupling agent, spin-on carbon, or spin-on glass, and is deposited by spin coating. 5 . The method of claim 1 , further comprising forming an opening through the cover layer after forming the opening through the insulating layer. The method according to claim 1 , further comprising forming a second capping layer on the insulating layer and the conductive layer.

7. A method for manufacturing a semiconductor device, comprising: forming a first redistribution layer; forming a capping layer on the first redistribution layer; as well as A second redistribution layer is formed on the capping layer. The method of claim 7 , wherein the cover layer comprises an anti-reflective coating. 9 . The method of claim 7 , wherein after forming the second redistribution layer, the cover layer remains formed directly on the conductive traces of the first redistribution layer.

10. A semiconductor device comprising: a first redistribution layer; a capping layer formed over the first redistribution layer; as well as A second redistribution layer is formed over the capping layer. The semiconductor device according to claim 10 , wherein the capping layer comprises an anti-reflective coating. 12 . The semiconductor device according to claim 10 , wherein the capping layer comprises Al 2 O 3 , TiO 2 , CrO 2 or ZnO. 13 . The semiconductor device according to claim 10 , wherein the capping layer comprises a silane coupling agent, spin-on carbon, or spin-on glass. 14 . The semiconductor device according to claim 10 , further comprising a second capping layer formed over the second redistribution layer.

15. The semiconductor device according to claim 10, wherein The second redistribution layer is coupled to the first redistribution layer through the opening of the cover layer.

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