Chip packaging structure, storage system and electronic equipment
By using optical waveguides to connect the first chip and the second chip in the chip package structure, the signal transmission power loss and signal crosstalk problems caused by the reduction of metal wire width and spacing are solved, and more efficient signal transmission and lower wire density are achieved.
Patent Information
- Application Number
- CN202311154706.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2023-09-07
- Publication Date
- 2025-03-11
AI Technical Summary
With the development of electronic integrated circuits, the width and spacing of metal conductors used for signal transmission between different chips have been continuously reduced, resulting in the intensification of transmission power loss during signal transmission and the crosstalk between metal conductors.
By introducing a first optoelectronic component, a second optoelectronic component and an optical waveguide into the chip package structure, signal transmission between the first chip and the second chip is realized. Optical waveguides have characteristics such as bandwidth, small attenuation, and anti-electromagnetic interference. They can effectively reduce power loss during signal transmission, reduce wire density, simplify wiring, and reduce crosstalk between signals.
It effectively reduces power loss during signal transmission between the first chip and the second chip, reduces wire density, simplifies wiring, and reduces crosstalk between signals.
Smart Images
Figure CN119601569A_ABST
Abstract
Description
Technical Field
[0001] The present disclosure relates to the field of semiconductor chip technology, and in particular to a chip packaging structure, a storage system and an electronic device. Background Art
[0002] This section merely provides background information related to the present disclosure and is not necessarily prior art.
[0003] With the development of electronic integrated circuits, the integration level continues to increase, and the width and spacing of metal wires used for signal transmission between different chips continue to shrink, exacerbating the problem of signal crosstalk between metal wires. Summary of the invention
[0004] Embodiments of the present disclosure provide a chip packaging structure, a storage system, and an electronic device, which are intended to solve the problem of aggravated transmission power loss and signal crosstalk between metal wires during signal transmission when the width and spacing of metal wires used for signal transmission between different chips continue to decrease.
[0005] To achieve the above objectives, the embodiments of the present disclosure adopt the following technical solutions:
[0006] In one aspect, a chip packaging structure is provided. The chip packaging structure includes a substrate, a first chip, a second chip, a first optoelectronic component, a second optoelectronic component, and an optical waveguide. The first chip and the second chip are arranged on the substrate at intervals; the first optoelectronic component and the second optoelectronic component both include a photonic circuit and an electronic circuit, the electronic circuit of the first optoelectronic component is connected to the first chip, and the electronic circuit of the second optoelectronic component is connected to the second chip; the optical waveguide is used to connect the photonic circuit of the first optoelectronic component and the photonic circuit of the second optoelectronic component.
[0007] The chip packaging structure provided by the above-mentioned embodiments of the present disclosure realizes signal transmission between the first chip and the second chip through the first optoelectronic component, the second optoelectronic component and the optical waveguide. The optical waveguide has the characteristics of wide bandwidth, low attenuation, and anti-electromagnetic interference, which can effectively reduce the power loss in the signal transmission process between the first chip and the second chip. The optical waveguide can realize multi-bit transmission, which can effectively reduce the number of wires required for signal transmission, reduce wire density, simplify wiring, and reduce crosstalk between signals.
[0008] In some embodiments, the optical waveguide is disposed on a surface of the substrate.
[0009] In some embodiments, the substrate includes a packaging substrate and a transfer layer stacked on the packaging substrate, the first chip and the second chip are arranged on a side surface of the transfer layer away from the packaging substrate; the optical waveguide is arranged on a side surface of the transfer layer away from the packaging substrate.
[0010] In some embodiments, the optical waveguide is disposed inside the substrate.
[0011] In some embodiments, the substrate includes a packaging substrate, and a transfer layer stacked on the packaging substrate, and the first chip and the second chip are arranged on a side surface of the transfer layer away from the packaging substrate; the substrate also includes a bridge substrate embedded in the transfer layer, and the optical waveguide is arranged in the bridge substrate.
[0012] In some embodiments, the optical waveguide is disposed on a side of the substrate where the first chip and the second chip are disposed, and is disposed independently of the substrate.
[0013] In some embodiments, the substrate includes a packaging substrate, and a transfer layer stacked on the packaging substrate, the first chip and the second chip are arranged on a surface of the transfer layer away from the packaging substrate; the optical waveguide is arranged on a side of the transfer layer away from the packaging substrate, and is independently arranged from the transfer layer.
[0014] In some embodiments, the substrate includes a packaging substrate, the first chip and the second chip are arranged on the surface of the packaging substrate; the optical waveguide is arranged on one side of the packaging substrate and is arranged independently of the packaging substrate.
[0015] In some embodiments, the photonic circuit and electronic circuit of the first optoelectronic component are integrated into a first optoelectronic chip, and the photonic circuit and electronic circuit of the second optoelectronic component are integrated into a second optoelectronic chip; the first optoelectronic chip is integrated with the first chip, and the second optoelectronic chip is integrated with the second chip.
[0016] In some embodiments, the photonic circuit and the electronic circuit of the first optoelectronic component are integrated into a first optoelectronic chip, and the photonic circuit and the electronic circuit of the second optoelectronic component are integrated into a second optoelectronic chip; the first optoelectronic chip and the first chip are independently arranged, and the second optoelectronic chip and the second chip are independently arranged, and the first optoelectronic chip and the second optoelectronic chip are both arranged on a substrate.
[0017] In some embodiments, the photonic circuit of the first optoelectronic component is configured as a first optical chip, and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip; the first electrical chip is integrated with the first chip, and the first optical chip is arranged on a substrate; the second electrical chip is integrated with the second chip, and the second optical chip is arranged on a substrate.
[0018] In some embodiments, the substrate includes a first wire and a second wire, the first wire is used to connect the first chip and the first optical chip, and the second wire is used to connect the second chip and the second optical chip.
[0019] In some embodiments, the photonic circuit of the first optoelectronic component is configured as a first optical chip, and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip; the first electrical chip is integrated with the first chip, and the first optical chip is stacked on the first chip; the second electrical chip is integrated with the second chip, and the second optical chip is stacked on the second chip.
[0020] In some embodiments, the first chip is a controller chip, and the second chip is a memory chip; wherein the memory chip includes a plurality of memory array bare chips and peripheral circuit bare chips that are stacked.
[0021] On the other hand, a storage system is provided, comprising the chip packaging structure and a packaging layer as described above; the packaging layer is disposed to cover the outside of the first chip and the second chip.
[0022] On the other hand, an electronic device is provided, comprising: a processor and the storage system as described above, the processor being coupled to the storage system; or comprising: a printed circuit board and the chip packaging structure as described above, the chip packaging structure being arranged on the printed circuit board and electrically connected to the printed circuit board.
[0023] It can be understood that the beneficial effects that can be achieved by the storage system and electronic device provided by the above embodiments of the present disclosure can refer to the beneficial effects of the chip packaging structure described above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS
[0024] In order to more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings described below are only drawings of some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, and are not limitations on the actual size of the product involved in the embodiments of the present disclosure, the actual process of the method, the actual timing of the signal, etc.
[0025] Figure 1 A structural diagram of a chip packaging structure provided according to the relevant technology;
[0026] Figure 2 A structural diagram of an electronic device provided according to some embodiments;
[0027] Figure 3 is another structural diagram of an electronic device provided according to some embodiments;
[0028] Figure 4 A structural diagram of a storage system provided according to some embodiments;
[0029] Figure 5 A structural diagram of a chip packaging structure provided according to some embodiments;
[0030] Figure 6 Another structural diagram of a chip packaging structure provided according to some embodiments;
[0031] Figure 7 is another structural diagram of a chip packaging structure provided according to some embodiments;
[0032] Figure 8 is another structural diagram of a chip packaging structure provided according to some embodiments;
[0033] Fig. 9 is another structural diagram of a chip packaging structure provided according to some embodiments;
[0034] Fig.10 is another structural diagram of a chip packaging structure provided according to some embodiments;
[0035] Fig.11 is another structural diagram of a chip packaging structure provided according to some embodiments;
[0036] Fig.12 A diagram showing another structure of a chip packaging structure provided according to some embodiments;
[0037] Fig.13 A structural diagram of a transfer layer provided according to some embodiments;
[0038] Fig.14 Another structural diagram of a transfer layer provided according to some embodiments. DETAILED DESCRIPTION
[0039] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present disclosure. Obviously, the described embodiments are only part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present disclosure.
[0040] In the description of the present disclosure, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating orientations or positional relationships, are based on the orientations or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present disclosure and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present disclosure.
[0041] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as an open, inclusive meaning, that is, "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples" and the like are intended to indicate that specific features, structures, materials or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representation of the above terms does not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.
[0042] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present disclosure, unless otherwise specified, "plurality" means two or more.
[0043] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. For another example, when describing some embodiments, the term "coupled" may be used to indicate that two or more components are in direct physical or electrical contact. However, the term "coupled" may also refer to two or more components that are not in direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the contents of this document.
[0044] In the context of this disclosure, the meanings of “on,” “above,” and “over” should be interpreted in the broadest manner, so that “on” means not only “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween, and “above” or “over” means not only “above” or “over” something, but also includes the meaning of “above” or “over” something without intervening features or layers therebetween (i.e., directly on something).
[0045] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of the layers and the area of the regions are exaggerated for clarity. Therefore, variations in the shapes relative to the drawings due to, for example, manufacturing techniques and / or tolerances are conceivable. Therefore, the exemplary embodiments should not be interpreted as being limited to the shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shapes of the regions of the device, and are not intended to limit the scope of the exemplary embodiments.
[0046] It should be noted that, for example, 51 / 5 appearing in the drawings of the present disclosure indicates that component 51 belongs to component 5, and other similar numbers appearing in the drawings also follow the above description.
[0047] like Figure 2 and Figure 3 As shown, an embodiment of the present application provides an electronic device 1000. The electronic device 1000 may include a mobile phone, a tablet computer (pad), a smart wearable product (e.g., a smart watch, a smart bracelet), a virtual reality (VR) device, an augmented reality (AR) device, etc. The embodiment of the present application does not impose any special restrictions on the specific form of the above-mentioned electronic device 1000.
[0048] In some embodiments, Figure 2 As shown, the electronic device 1000 may include a chip packaging structure 10 and a printed circuit board (PCB) 11. The chip packaging structure 10 is electrically connected to the printed circuit board 11 through an electrical connection structure 12, so that the chip packaging structure 10 can realize signal transmission with other chips on the printed circuit board 11.
[0049] Exemplarily, one or more chip packaging structures 10 may be disposed on the printed circuit board 11. In the case where multiple chip packaging structures 10 are disposed on the printed circuit board 11, these chip packaging structures 10 may implement the same or different functions, for example, these chip packaging structures 10 may include a chip packaging structure 10 for logic operation, a chip packaging structure 10 with a storage function, and a chip packaging structure 10 with both a logic operation function and a storage function or other functions.
[0050] Exemplarily, the electrical connection structure 12 may be a ball grid array (BGA). In an optional embodiment, if the chip package structure 10 is relatively large in size. In order to ensure the reliability of the electrical connection between the chip package structure 10 and the printed circuit board 11, the electrical connection structure 12 may also use a connection terminal (socket) with a slot-type fixing structure, which may also be called a connector, a plug-in connector, etc.
[0051] By way of example, components such as capacitors, resistors, and inductors may also be disposed on the printed circuit board 11. Among them, resistors can control the magnitude of the current through the resistance value, so that the current is properly adjusted in the circuit; capacitors can store charges and release them when needed, and have the functions of smoothing the power supply voltage, stabilizing the current, and in some cases can complete the filtering function of the electrical signal; inductors have the characteristics of storing and releasing energy, and can complete the energy conversion and distribution of the circuit.
[0052] In other embodiments, Figure 3 As shown, the electronic device 1000 may further include a storage system 100 and a processor 200. The processor 200 is coupled to the storage system 100 to interact with the storage system 100.
[0053] Exemplarily, the processor 200 may be a central processing unit (CPU), or other general-purpose processors, digital signal processors (DSP), application-specific integrated circuits (ASIC), field programmable gate arrays (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, etc. A general-purpose processor may be a microprocessor or the processor may be any conventional processor, etc.
[0054] like Figure 4 As shown, the storage system 100 may include a chip packaging structure 10 and a packaging layer 13. The packaging layer 13 covers the outside of the chip disposed in the chip packaging structure 10. On the one hand, the packaging layer 13 may increase the strength of the chip packaging structure 10, and on the other hand, the packaging layer 13 may also protect the chip in the chip packaging structure 10. Exemplarily, the packaging layer 13 may include epoxy resin, expansion monomer, and curing agent.
[0055] The storage system 100 may be integrated into a memory card. The memory card may include, for example, a PC card (Personal Computer Memory Card International Association, PCMCIA), a Compact Flash (CF) card, a Smart Media (SM) card, a memory stick, a Multimedia Card (MMC), a Secure Digital Memory Card (SD), or any one of UFS.
[0056] The storage system 100 described above can also be integrated into various types of storage devices, for example, included in the same package (e.g., Universal Flash Storage (UFS) package or Embedded Multi Media Card (eMMC) package). That is, the storage system 100 can be applied to and packaged into different types of electronic products, such as mobile phones (e.g., mobile phones), desktop computers, tablet computers, laptop computers, servers, vehicle-mounted devices, game consoles, printers, positioning devices, wearable devices, smart sensors, mobile power supplies, virtual reality (VR) devices, augmented reality (AR) devices, or any other suitable electronic devices having storage therein.
[0057] The storage system 100 may also be integrated into a solid state drive (SSD).
[0058] The structure of the chip packaging structure 10 is described in detail below.
[0059] like Figure 1 As shown, Figure 1 1 is a schematic diagram of a chip packaging structure 10 ′ in the related art, wherein a first chip 21 and a second chip 22 are both fixed on a substrate 5 , and the first chip 21 and the second chip 22 are connected via a metal wire 6 in the substrate 5 .
[0060] With the development of electronic integrated circuits, the integration level continues to increase, and the width and spacing of metal wires used for signal transmission between different chips continue to shrink. This leads to an increase in the resistance of metal wires and the capacitance between metal wires, exacerbating the transmission power loss during signal transmission and the signal crosstalk between metal wires.
[0061] Based on this, Figure 5 to Figure 12 As shown, Figure 5 to Figure 12 The structure diagram of the chip packaging structure 10 provided according to some embodiments. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32 and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first optoelectronic component 31 is electrically connected to the first chip 21, the second optoelectronic component 32 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optoelectronic component 31 and the second optoelectronic component 32.
[0062] The first optoelectronic component 31 and the second optoelectronic component 32 can receive and transmit optical signals through the optical waveguide 4, so that the optical signal can be transmitted to the first optoelectronic component 31 or the second optoelectronic component 32 through the optical waveguide 4. The first chip 21 can transmit an electrical signal to the first optoelectronic component 31, and the first optoelectronic component 31 converts the input electrical signal into an optical signal, and transmits the optical signal to the second optoelectronic component 32 through the optical waveguide 4, and the second optoelectronic component 32 converts the input optical signal into an electrical signal, and the electrical signal is then transmitted to the second chip 22, and the second chip 22 performs arithmetic or logical operations on the electrical signal. Conversely, the second chip 22 can also transmit an electrical signal to the second optoelectronic component 32, and the second optoelectronic component 32 converts the input electrical signal into an optical signal, and transmits the optical signal to the first optoelectronic component 31 through the optical waveguide 4, and the first optoelectronic component 31 converts the input optical signal into an electrical signal, and the electrical signal is then transmitted to the first chip 21, and the first chip 21 performs arithmetic or logical operations on the electrical signal.
[0063] The first optoelectronic component 31 and the second optoelectronic component 32 may both include a photonic circuit (Photonic IC, PIC), and the optical waveguide 4 connects the photonic circuit in the first optoelectronic component 31 and the photonic circuit in the second optoelectronic component 32. In an optional embodiment, it may be necessary to further process the electrical signal converted by the photonic circuit, for example, transform, amplify, etc. In this way, the first optoelectronic component 31 and the second optoelectronic component 32 may both include an electronic circuit (Electrical IC, EIC), the electronic circuit in the first optoelectronic component 31 is electrically connected to the first chip 21, and the electronic circuit in the second optoelectronic component 32 is electrically connected to the second chip 22.
[0064] The photonic circuit of the first optoelectronic component 31 can be configured as a first optical chip 312, and the electronic circuit of the first optoelectronic component 31 can be configured as a first electrical chip 311; the photonic circuit of the second optoelectronic component 32 can be configured as a second optical chip 322, and the electronic circuit of the second optoelectronic component 32 can be configured as a second electrical chip 321.
[0065] The first chip 21 is used to process the electrical signal after the photoelectric conversion of the first optoelectronic component 31, or transmit the processed electrical signal to the first optoelectronic component 31; the second chip 22 is used to process the electrical signal after the photoelectric conversion of the second optoelectronic component 32, or transmit the processed electrical signal to the second optoelectronic component 32. For example, the first chip 21 can be a memory chip, or a controller chip, etc.; the second chip 22 can be a memory chip, or a controller chip, etc. Exemplarily, the memory chip can include a plurality of memory array bare chips 221 and peripheral circuit bare chips 222 stacked.
[0066] Signal transmission between the first chip 21 and the second chip 22 is achieved through the first optoelectronic component 31, the second optoelectronic component 32 and the optical waveguide 4. Compared with the connection between the first chip 21 and the second chip 22 through metal wires in the related art, the optical waveguide 4 has the characteristics of wide bandwidth, low attenuation, and anti-electromagnetic interference, which can effectively reduce the power loss in the signal transmission process between the first chip 21 and the second chip 22, and the optical waveguide 4 can realize multi-bit transmission, which can effectively reduce the number of wires required for signal transmission, reduce wire density, simplify wiring, and reduce crosstalk between signals.
[0067] Exemplarily, the optical waveguide 4 may be made of silicon dioxide, SOI (Silicon-on-Insulator) or polymer material, which has a lower manufacturing cost than metal wires.
[0068] It should be noted that SOI refers to a thin layer of silicon single crystal covered on an insulator made of silicon dioxide or glass. The SOI substrate can be composed of the following three layers: a thin single crystal silicon top layer, a relatively thin insulating silicon dioxide middle layer, and a very thick silicon substrate layer. Among them, the main function of the silicon substrate layer is to provide mechanical support for the single crystal silicon top layer and the insulating silicon dioxide middle layer.
[0069] Please continue to refer to the following Figure 5 to Figure 12 , each embodiment of the present application is described respectively.
[0070] It should be noted that in the specification and drawings of the present application, with respect to the drawings that have already been given, the same symbols are used for the same elements as those described above, and the detailed description is appropriately omitted.
[0071] In some embodiments, Figure 5 As shown, Figure 5The present invention is a structural diagram of a chip packaging structure 10 provided according to some embodiments. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321 and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first electrical chip 311 is electrically connected to the first chip 21, the second electrical chip 321 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optical chip 312 and the second optical chip 322.
[0072] In this embodiment, the substrate 5 may include a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on a surface of the transfer layer 52 away from the packaging substrate 51 .
[0073] Exemplarily, the package substrate 51 may be connected to the transfer layer 52 via bumps.
[0074] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the transfer layer 52 in the substrate 5 via bumps or wire bonding ( Figure 5 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 by wire bonding as an example.
[0075] For example, Figure 5 As shown, in order to improve the reliability of the connection between the packaging substrate 51 and the transfer layer 52 , a dispensing process may be used to fill an underfill in the area AA between the packaging substrate 51 and the transfer layer 52 .
[0076] For example, Fig.13 Schematic diagram of the structure of the redistribution layer 521. The transfer layer 52 may be a redistribution layer (RDL) 521 made by a redistribution process. The redistribution layer 521 includes multiple layers of metal traces 5211 and multiple layers of dielectric layers 5212. Each two adjacent layers of metal traces 5211 are separated by a dielectric layer 5212. The dielectric layer 5212 may be made of an insulating material such as a resin material. In order to electrically connect the metal traces 5211 on different layers, a first conductive channel 5213 may be made in the dielectric layer 5212 so that the metal traces 5211 on different layers are electrically connected through the first conductive channel 5213.
[0077] When the rewiring layer 521 is used as the transfer layer 52, the rewiring layer 521 can be electrically connected to the first chip 21 and the second chip 22 through bumps or wire bonding, and can be electrically connected to the metal wires 6 in the packaging substrate 51 through the first conductive channels 5213 and bumps.
[0078] Fig.14 is a structural diagram of the intermediate layer 522, such as Fig.14 As shown, the transfer layer 52 may also be an interposer 522, including a first substrate 5221, a redistribution layer 5222 integrated on the first substrate 5221, and a second conductive channel 5223 penetrating the first substrate 5221, wherein the second conductive channel 5223 is electrically connected to a metal trace in the redistribution layer 5222. For example, when the first substrate 5221 is a silicon substrate made of a semiconductor material having silicon, the interposer is a silicon interposer (SiInterposer).
[0079] When the intermediate layer 522 is used as the transfer layer 52, the redistribution layer 5222 is close to the first chip 21 and the second chip 22, and can be electrically connected to the first chip 21 and the second chip 22 through bumps or wire bonding. The first base 5221 is close to the packaging substrate 51 and can be electrically connected to the metal wire 6 in the packaging substrate 51 through the second conductive channel 5223 and the bump.
[0080] In this embodiment, the optical waveguide 4 can be implemented in the form of a second optical waveguide 42. The second optical waveguide 42 is arranged on a surface of the transfer layer 52 away from the packaging substrate 51, and the arrangement method can be planar integration.
[0081] For example, the second optical waveguide 42 may be integrated on a surface of the transfer layer 52 that is away from the packaging substrate 51 by using a semiconductor thin film process.
[0082] For example, the second optical waveguide 42 may include a substrate with a refractive index of n2, and a dielectric film with a refractive index of n1 is plated on the substrate by a microelectronic process, and then a cover layer with a refractive index of n3 is added. Usually n1>n2>n3 is taken to confine the light wave to propagate in the dielectric film. For example, the material of the substrate may be one of silicon, gallium arsenide or glass.
[0083] In this embodiment, the first electrical chip 311 is integrated with the first chip 21, and the first optical chip 312 is disposed on the substrate 5; the second electrical chip 321 is integrated with the second chip 22, and the second optical chip 322 can be disposed on the substrate 5. The substrate 5 includes a first wire 71 and a second wire 72, the first wire 71 is used to connect the first chip 21 and the first optical chip 312, and the second wire 72 is used to connect the second chip 22 and the second optical chip 322. Specifically, the first wire 71 is used to connect the electronic circuit in the first chip 21 and the first optical chip 312, and the second wire 72 is used to connect the electronic circuit in the second chip 22 and the second optical chip 322.
[0084] It should be noted that the first conductive line 71 and the second conductive line 72 may be metal traces 5211 in the transfer layer 52 .
[0085] In some embodiments, Figure 6 As shown, Figure 6 1 is another structural diagram of a chip packaging structure 10 provided according to some embodiments. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first optoelectronic component 31 is electrically connected to the first chip 21, the second optoelectronic component 32 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optoelectronic component 31 and the second optoelectronic component 32.
[0086] In this embodiment, the substrate 5 may include a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on a surface of the transfer layer 52 away from the packaging substrate 51 .
[0087] Exemplarily, the package substrate 51 may be connected to the transfer layer 52 via bumps.
[0088] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the transfer layer 52 in the substrate 5 via bumps or wire bonding ( Figure 6 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 by wire bonding as an example.
[0089] For example, the transfer layer 52 may be a redistribution layer (RDL) 521 made by a redistribution process, or an interposer 522. The specific structures of the redistribution layer 521 and the interposer 522 in this embodiment are similar to those in the embodiment of the present invention. Figure 5The embodiments shown are basically the same and will not be described again in detail.
[0090] In this embodiment, the optical waveguide 4 can be implemented in the form of a second optical waveguide 42. The second optical waveguide 42 is arranged on a surface of the transfer layer 52 away from the packaging substrate 51, and the arrangement method can be planar integration.
[0091] It should be noted that the preparation process and specific structure of the second optical waveguide 42 are similar to those of Figure 5 The embodiments shown are basically the same and will not be described in detail here.
[0092] In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 can be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31' can be integrated with the first chip 21, and the second optoelectronic chip 32' can be integrated with the second chip 22. The optical waveguide 4 connects the first chip 21 and the second chip 22. Specifically, the optical waveguide 4 connects the photonic circuit in the first chip 21 and the photonic circuit in the second chip 22.
[0093] Figure 6 The embodiments shown and Figure 5 The differences between the illustrated embodiments are: Figure 6 In the embodiment shown, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', which is integrated with the first chip 21; the electronic circuit and the photonic circuit in the second optoelectronic component 32 are monolithically integrated into a second optoelectronic chip 32', which is integrated with the second chip 22. The optical waveguide 4 connects the first chip 21 and the second chip 22.
[0094] In some embodiments, Figure 7 and Figure 8 As shown, Figure 7 and Figure 8 All of them are another structural diagram of the chip packaging structure 10 provided in some embodiments of the present application. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32 and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first optoelectronic component 31 is electrically connected to the first chip 21, the second optoelectronic component 32 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optoelectronic component 31 and the second optoelectronic component 32.
[0095] In this embodiment, the substrate 5 may include a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on a surface of the transfer layer 52 away from the packaging substrate 51 .
[0096] Exemplarily, the package substrate 51 may be connected to the transfer layer 52 via bumps.
[0097] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the transfer layer 52 in the substrate 5 via bumps or wire bonding ( Figure 7 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 through the bumps as an example. Figure 8 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 by wire bonding as an example.
[0098] For example, the transfer layer 52 may be a redistribution layer (RDL) 521 made by a redistribution process, or an interposer 522. The specific structures of the redistribution layer 521 and the interposer 522 in this embodiment are similar to those in the embodiment of the present invention. Figure 5 The embodiments shown are basically the same and will not be described in detail here.
[0099] In this embodiment, the optical waveguide 4 can be implemented in the form of a third optical waveguide 43. In addition to the packaging substrate 51 and the transfer layer 52 stacked on the packaging substrate 51, the substrate 5 also includes a bridge substrate 53 embedded in the transfer layer 52, and the third optical waveguide 43 is arranged in the bridge substrate 53.
[0100] In this embodiment, the electronic circuit and the photon circuit in the first optoelectronic component 31 can be monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photon circuit in the second optoelectronic component 32 can be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31' can be integrated with the first chip 21, and the second optoelectronic chip 32' can be integrated with the second chip 22. The third optical waveguide 43 connects the first chip 21 and the second chip 22. Specifically, the third optical waveguide 43 connects the photon circuit in the first chip 21 and the photon circuit in the second chip 22.
[0101] Figure 7 and Figure 8 Shown are embodiments and Figure 5 The differences between the embodiments shown are:
[0102] The substrate 5 includes not only a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 , but also a bridge substrate 53 embedded in the transfer layer 52 .
[0103] The optical waveguide 4 is implemented in the form of a third optical waveguide 43 , and the third optical waveguide 43 is disposed in the bridge substrate 53 .
[0104] The electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', which can be integrated with the first chip 21; the electronic circuit and the photonic circuit in the second optoelectronic component 32 can be monolithically integrated into a second optoelectronic chip 32', which can be integrated with the second chip 22. The third optical waveguide 43 connects the first chip 21 and the second chip 22.
[0105] In some embodiments, Fig. 9 As shown, Fig. 9 Another structural diagram of a chip packaging structure 10 provided in some embodiments of the present application. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first optoelectronic component 31 is electrically connected to the first chip 21, the second optoelectronic component 32 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optoelectronic component 31 and the second optoelectronic component 32.
[0106] In this embodiment, the substrate 5 includes a packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on one side surface of the packaging substrate 51 .
[0107] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the package substrate 51 in the substrate 5 via bumps or wire bonding ( Fig. 9 In the figure, the first chip 21 and the second chip 22 are electrically connected to the packaging substrate 51 in the substrate 5 through bumps as an example for illustration).
[0108] In this embodiment, the optical waveguide 4 can be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 can be provided on one side of the package substrate 51 where the first chip 21 and the second chip 22 are provided, and can be provided independently of the package substrate 51. For example, the first optical waveguide 41 can be provided in the air on one side of the package substrate 51, and has no contact with the package substrate 51.
[0109] In this embodiment, the electronic circuit and the photon circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photon circuit in the second optoelectronic component 32 can be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31' can be integrated with the first chip 21, and the second optoelectronic chip 32' can be integrated with the second chip 22. The first optical waveguide 41 connects the first chip 21 and the second chip 22. Specifically, the first optical waveguide 41 connects the photon circuit in the first chip 21 and the photon circuit in the second chip 22. .
[0110] Fig. 9 The embodiment shown is Figure 5 The differences between the illustrated embodiments are:
[0111] The substrate 5 may not include the transfer layer 52 . The first chip 21 and the second chip 22 are disposed on one side surface of the package substrate 51 .
[0112] The optical waveguide 4 is implemented in the form of a first optical waveguide 41. The first optical waveguide 41 is disposed on one side of the package substrate 51 where the first chip 21 and the second chip 22 are disposed, and is independently disposed from the package substrate 51.
[0113] The electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31', which is integrated with the first chip 21; the electronic circuit and the photonic circuit in the second optoelectronic component 32 are monolithically integrated into a second optoelectronic chip 32', which is integrated with the second chip 22. The first optical waveguide 41 connects the first chip 21 and the second chip 22.
[0114] In some embodiments, Fig.10 As shown, Fig.10 Another structural diagram of the chip packaging structure 10 provided in some embodiments of the present application. The chip packaging structure 10 includes a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321 and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first electrical chip 311 is electrically connected to the first chip 21, the second electrical chip 321 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optical chip 312 and the second optical chip 322.
[0115] In this embodiment, the substrate 5 may include a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on a surface of the transfer layer 52 away from the packaging substrate 51 .
[0116] Exemplarily, the package substrate 51 may be connected to the transfer layer 52 via bumps.
[0117] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the transfer layer 52 in the substrate 5 via bumps or wire bonding ( Fig.10 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 through the bumps as an example for illustration).
[0118] For example, the transfer layer 52 may be a redistribution layer (RDL) 521 made by a redistribution process, or an interposer 522. The specific structures of the redistribution layer 521 and the interposer 522 in this embodiment are similar to those in the embodiment of the present invention. Figure 5 The embodiments shown are basically the same and will not be described in detail here.
[0119] In this embodiment, the optical waveguide 4 can be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 can be arranged on one side of the transfer layer 52 where the first chip 21 and the second chip 22 are arranged, and can be arranged independently of the transfer layer 52. For example, the first optical waveguide 41 can be suspended on one side of the transfer layer 52, and has no contact with the transfer layer 52.
[0120] In this embodiment, the first electrical chip 311 is integrated with the first chip 21, and the first optical chip 312 is disposed on the substrate 5; the second electrical chip 321 is integrated with the second chip 22, and the second optical chip 322 can be disposed on the substrate 5. The substrate 5 includes a first wire 71 and a second wire 72, the first wire 71 is used to connect the first chip 21 and the first optical chip 312, and the second wire 72 is used to connect the second chip 22 and the second optical chip 322. Specifically, the first wire 71 is used to connect the electronic circuit in the first chip 21 and the first optical chip 312, and the second wire 72 is used to connect the electronic circuit in the second chip 22 and the second optical chip 322.
[0121] It should be noted that the first conductive line 71 and the second conductive line 72 may be metal traces 5211 in the transfer layer 52 .
[0122] Fig.10 The embodiment shown is Figure 5 The difference between the illustrated embodiments is that the optical waveguide 4 is implemented in the form of a first optical waveguide 41. The first optical waveguide 41 can be arranged on one side of the switching layer 52 where the first chip 21 and the second chip 22 are arranged, and is arranged independently of the switching layer 52.
[0123] In some embodiments, Fig.11 As shown, Fig.11 Another structural diagram of a chip packaging structure 10 provided in some embodiments of the present application. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optoelectronic component 31, a second optoelectronic component 32, and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first optoelectronic component 31 is electrically connected to the first chip 21, the second optoelectronic component 32 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optoelectronic component 31 and the second optoelectronic component 32.
[0124] In this embodiment, the substrate 5 may include a packaging substrate 51 and a transfer layer 52 stacked on the packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on a surface of the transfer layer 52 away from the packaging substrate 51 .
[0125] Exemplarily, the package substrate 51 may be connected to the transfer layer 52 via bumps.
[0126] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the transfer layer 52 in the substrate 5 via bumps or wire bonding ( Fig.11 In the figure, the first chip 21 and the second chip 22 are electrically connected to the transfer layer 52 in the substrate 5 through the bumps as an example for illustration).
[0127] For example, the transfer layer 52 may be a redistribution layer (RDL) 521 made by a redistribution process, or an interposer 522. The specific structures of the redistribution layer 521 and the interposer 522 in this embodiment are similar to those in the embodiment of the present invention. Figure 5 The embodiments shown are basically the same and will not be described in detail here.
[0128] In this embodiment, the optical waveguide 4 can be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 can be arranged on one side of the transfer layer 52 where the first chip 21 and the second chip 22 are arranged, and can be arranged independently of the transfer layer 52. For example, the first optical waveguide 41 can be suspended on one side of the transfer layer 52, and has no contact with the transfer layer 52.
[0129] In this embodiment, the electronic circuit and the photonic circuit in the first optoelectronic component 31 are monolithically integrated into a first optoelectronic chip 31 ′, and the electronic circuit and the photonic circuit in the second optoelectronic component 32 are monolithically integrated into a second optoelectronic chip 32 ′.
[0130] The first optoelectronic chip 31' is independently arranged with the first chip 21, and the second optoelectronic chip 32' is independently arranged with the second chip 22, and the first optoelectronic chip 31' and the second optoelectronic chip 32' are both arranged on the substrate 5. The first optoelectronic chip 31' is respectively connected to the first chip 21 and the first optical waveguide 41, and the second optoelectronic chip 32' is respectively connected to the second chip 22 and the first optical waveguide 41. Specifically, the first optical waveguide 41 connects the photonic circuit in the first optoelectronic chip 31' and the photonic circuit in the second optoelectronic chip 32', the first chip 21 is connected to the electronic circuit in the first optoelectronic chip 31', and the second chip 22 is connected to the electronic circuit in the second optoelectronic chip 32'. The first chip 21 and the first optoelectronic chip 31', and the second chip 22 and the second optoelectronic chip 32' can be electrically connected through the metal wiring in the transfer layer 52.
[0131] For example, the first optoelectronic chip 31' and the second optoelectronic chip 32' may be electrically connected to the transfer layer 52 by bumps or wire bonding ( Fig.11 In the figure, the first optoelectronic chip 31' and the second optoelectronic chip 32' are electrically connected to the transfer layer 52 in the substrate 5 through the bumps as an example for illustration).
[0132] Fig.11 The embodiment shown is Figure 5 The differences between the illustrated embodiments are:
[0133] The optical waveguide 4 is implemented in the form of a first optical waveguide 41. The first optical waveguide 41 is disposed on one side of the switching layer 52 where the first chip 21 and the second chip 22 are disposed, and is independently disposed from the switching layer 52.
[0134] The electronic circuit and the photonic circuit in the first optoelectronic component 31 can be monolithically integrated into a first optoelectronic chip 31', and the electronic circuit and the photonic circuit in the second optoelectronic component 32 can be monolithically integrated into a second optoelectronic chip 32'. The first optoelectronic chip 31' and the first chip 21 are independently arranged, and the second optoelectronic chip 32' and the second chip 22 are independently arranged. The first optoelectronic chip 31' and the second optoelectronic chip 32' are both arranged on the substrate 5. The first optoelectronic chip 31' is respectively connected to the first chip 21 and the first optical waveguide 41, and the second optoelectronic chip 32' is respectively connected to the second chip 22 and the first optical waveguide 41.
[0135] In some embodiments, Fig.12 As shown, Fig.12Another structural diagram of the chip packaging structure 10 provided in some embodiments of the present application. The chip packaging structure 10 includes: a substrate 5, a first chip 21, a second chip 22, a first optical chip 312, a first electrical chip 311, a second optical chip 322, a second electrical chip 321 and an optical waveguide 4. The first chip 21 and the second chip 22 are fixedly arranged on the substrate 5 at intervals, the first electrical chip 311 is electrically connected to the first chip 21, the second electrical chip 321 is electrically connected to the second chip 22, and the optical waveguide 4 is used to connect the first optical chip 312 and the second optical chip 322.
[0136] In this embodiment, the substrate 5 includes a packaging substrate 51 . The first chip 21 and the second chip 22 are disposed on one side surface of the packaging substrate 51 .
[0137] Exemplarily, the first chip 21 and the second chip 22 may be electrically connected to the substrate 5 via bumps or wire bonding. Specifically, the first chip 21 and the second chip 22 may be electrically connected to the package substrate 51 in the substrate 5 via bumps or wire bonding ( Fig.12 In the figure, the first chip 21 and the second chip 22 are electrically connected to the packaging substrate 51 in the substrate 5 through bumps as an example for illustration).
[0138] In this embodiment, the optical waveguide 4 can be implemented in the form of a first optical waveguide 41. The first optical waveguide 41 can be provided on one side of the package substrate 51 where the first chip 21 and the second chip 22 are provided, and can be provided independently of the package substrate 51. For example, the first optical waveguide 41 can be provided in the air on one side of the package substrate 51, and has no contact with the package substrate 51.
[0139] In this embodiment, the first optical chip 312 can be stacked on the first chip 21, and the second optical chip 322 can also be stacked on the second chip 22. The first optical chip 312 and the first chip 21 can be connected by wire bonding, and the second optical chip 322 and the second chip 22 can also be connected by wire bonding. Specifically, the first optical chip 312 is connected to the electronic circuit in the first chip 21, and the second optical chip 322 is connected to the electronic circuit in the second chip 22. Since the first optical chip 312 and the first chip 21 are stacked, and the second optical chip 322 and the second chip 22 are stacked, the interconnection path is short, which is conducive to improving signal transmission efficiency
[0140] Fig.12 The embodiment shown is Figure 5 The differences between the illustrated embodiments are:
[0141] The substrate 5 may not include the transfer layer 52 . The first chip 21 and the second chip 22 are disposed on one side surface of the package substrate 51 .
[0142] The optical waveguide 4 is implemented in the form of a first optical waveguide 41. The first optical waveguide 41 is disposed on one side of the package substrate 51 where the first chip 21 and the second chip 22 are disposed, and is independently disposed from the package substrate 51.
[0143] The first optical chip 312 is stacked on the first chip 21 , and the second optical chip 322 is also stacked on the second chip 22 .
[0144] Although combined with Figure 5 to Figure 12 Some embodiments of the present application are described, however, the above description is exemplary and not exhaustive, and therefore is not limited to the disclosed embodiments. Without departing from the scope of the above embodiments, many modifications and changes are obvious to those skilled in the art. For example, any combination of the arrangement of the substrate 5, the arrangement of the first chip 21, the second chip 22, the first optical chip 312, the arrangement between the first electrical chip 311, the second optical chip 322 and the second electrical chip 321, and the implementation form of the optical waveguide 41 are all within the scope of protection of the present application.
[0145] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.
Claims
1. A chip packaging structure, characterized in that: include: substrate; A first chip and a second chip are arranged on the substrate at intervals; A first optoelectronic component and a second optoelectronic component, wherein the first optoelectronic component and the second optoelectronic component both include a photonic circuit and an electronic circuit, the electronic circuit of the first optoelectronic component is connected to the first chip, and the electronic circuit of the second optoelectronic component is connected to the second chip; An optical waveguide is used to connect the photonic circuit of the first optoelectronic component and the photonic circuit of the second optoelectronic component.
2. The chip packaging structure according to claim 1, characterized in that: The optical waveguide is arranged on the surface of the substrate.
3. The chip packaging structure according to claim 2, characterized in that: The substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, and the first chip and the second chip are arranged on a side surface of the transfer layer away from the packaging substrate; The optical waveguide is arranged on a surface of the transfer layer which is away from the packaging substrate.
4. The chip packaging structure according to claim 1, characterized in that: The optical waveguide is arranged inside the substrate.
5. The chip packaging structure according to claim 4, characterized in that: The substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, and the first chip and the second chip are arranged on a side surface of the transfer layer away from the packaging substrate; The substrate further comprises a bridge substrate embedded in the transfer layer, and the optical waveguide is arranged in the bridge substrate.
6. The chip packaging structure according to claim 1, characterized in that: The optical waveguide is arranged on one side of the substrate where the first chip and the second chip are arranged, and is arranged independently of the substrate.
7. The chip packaging structure according to claim 6, characterized in that: The substrate comprises a packaging substrate and a transfer layer stacked on the packaging substrate, and the first chip and the second chip are arranged on a side surface of the transfer layer away from the packaging substrate; The optical waveguide is arranged on a side of the transfer layer away from the packaging substrate, and is arranged independently of the transfer layer.
8. The chip packaging structure according to claim 6, characterized in that: The substrate comprises a packaging substrate, and the first chip and the second chip are arranged on a surface of the packaging substrate; The optical waveguide is arranged on one side of the packaging substrate and is independently arranged from the packaging substrate.
9. The chip packaging structure according to claim 1, characterized in that: The photonic circuit and the electronic circuit of the first optoelectronic component are integrated and configured as a first optoelectronic chip, and the photonic circuit and the electronic circuit of the second optoelectronic component are integrated and configured as a second optoelectronic chip; The first optoelectronic chip is integrated with the first chip, and the second optoelectronic chip is integrated with the second chip.
10. The chip packaging structure according to claim 1, characterized in that: The photonic circuit and the electronic circuit of the first optoelectronic component are integrated and configured as a first optoelectronic chip, and the photonic circuit and the electronic circuit of the second optoelectronic component are integrated and configured as a second optoelectronic chip; The first optoelectronic chip is independently arranged from the first chip, the second optoelectronic chip is independently arranged from the second chip, and both the first optoelectronic chip and the second optoelectronic chip are arranged on the substrate.
11. The chip packaging structure according to claim 1, characterized in that: The photonic circuit of the first optoelectronic component is configured as a first optical chip, and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip; The first electrical chip is integrated with the first chip, and the first optical chip is disposed on the substrate; the second electrical chip is integrated with the second chip, and the second optical chip is disposed on the substrate.
12. The chip packaging structure according to claim 11, characterized in that: The substrate includes a first wire and a second wire, the first wire is used to connect the first chip and the first optical chip, and the second wire is used to connect the second chip and the second optical chip.
13. The chip packaging structure according to claim 1, characterized in that: The photonic circuit of the first optoelectronic component is configured as a first optical chip, and the electronic circuit of the first optoelectronic component is configured as a first electrical chip; the photonic circuit of the second optoelectronic component is configured as a second optical chip, and the electronic circuit of the second optoelectronic component is configured as a second electrical chip; The first electrical chip is integrated with the first chip, and the first optical chip is stacked on the first chip; the second electrical chip is integrated with the second chip, and the second optical chip is stacked on the second chip.
14. The chip packaging structure according to any one of claims 1 to 13, characterized in that: The first chip is a controller chip, and the second chip is a memory chip; The memory chip includes a plurality of stacked memory array bare chips and peripheral circuit bare chips.
15. A storage system, characterized in that: include: The chip packaging structure according to any one of claims 1 to 14; A packaging layer is provided to cover the first chip and the second chip.
16. An electronic device, characterized in that: include: A processor, and a storage system as claimed in claim 15, wherein the processor is coupled to the storage system; or, It comprises: a printed circuit board, and a chip packaging structure as claimed in any one of claims 1 to 14, wherein the chip packaging structure is arranged on the printed circuit board and is electrically connected to the printed circuit board.