Chain type SVG control system and configuration method thereof

Abstract

The invention relates to a chained SVG control system and a configuration method thereof, and belongs to the technical field of power electronics. The method is used for configuring a chained SVG control system of which a controller adopts a heterogeneous dual-core processor architecture based on an FPGA (Field Programmable Gate Array), and comprises the following steps: a control algorithm in the chained SVG control system is realized by an FPGA core, and a control logic in the chained SVG control system is realized by another core; the control algorithm comprises a virtual synchronous control function, commutation chain voltage sharing, control instruction generation and harmonic suppression; the control logic comprises chain type SVG control system start-stop control, unlocking and locking sequence control logic, chain type SVG control system state conversion and main and standby system switching. The control system comprises the controller, the controller adopts a heterogeneous dual-core processor architecture based on the FPGA, and the controller is configured by adopting the method. According to the method, on the premise that control hardware configuration is not changed, the execution time of a control algorithm is greatly shortened, and the cost is low while the control capability of the controller is improved.

Description

Technical Field

[0001] The invention belongs to the technical field of power electronics, and in particular relates to a chain-type SVG control system and a configuration method thereof. Background Art

[0002] In recent years, with the rapid development of power electronics technology, a large number of power electronic equipment have been connected to the power system, including wind power / photovoltaic inverters, charging piles, CNC machine tools, etc., which have also brought harmonic pollution, power fluctuations and flicker to the power system. In the past, the power system responded by adding synchronous phase regulators, passive / active filters, reactive power compensation devices and other measures. New energy power stations have long been abandoned.

[0003] Electrochemical energy storage technology and harmonic suppression technology have also developed rapidly in recent years, providing new ideas for solving the above problems. As an advanced power electronic device, the chain SVG has a fast response speed and can quickly emit or absorb the reactive power required by the system to realize the reactive dynamic compensation function; the chain SVG control system with energy storage topology adopts virtual synchronous machine control. Because the primary equipment contains energy storage equipment, it can provide inertial support in the event of a power grid failure, provide active power for the system, and have frequency modulation function; the chain SVG control system can effectively suppress system harmonics by detecting the system harmonics at the grid connection point and adopting a harmonic suppression strategy; the reactive power support function of SVG is one of its basic functions.

[0004] In the prior art, chain-type SVG usually adopts dual-core processors when realizing its reactive dynamic compensation function, such as chips integrating ARM processors and FPGA programmable logic devices, processors integrating DSP and FPGA, etc. Two cores of these dual-core processors jointly undertake various control functions of chain-type SVG, such as the Chinese invention patent with authorization announcement number CN107342593B discloses the use of DSP+FPGA heterogeneous multi-processor parallel control computing architecture, in which DSP is responsible for the outer loop control of the chain-type SVG control system, and FPGA is responsible for the inner loop control of the chain-type SVG control system, thereby maximizing the system performance. For example, Section 5.3 of the reference "Research on SVG Chain Energy Storage Converter and Its Control System" (Master's thesis of Mao Zhongkun, Nanchang Institute of Technology) discloses the use of ARM+FPGA dual-core architecture to set the main control board of the SVG control system, in which the ARM core is responsible for the realization of converter functions, the realization of control algorithms, event processing and communication functions, and the FPGA core is responsible for parallel processing, real-time processing, communication and logic protection management functions.

[0005] However, with the continuous enhancement of SVG control functions, new challenges have been put on the computing power of the controller. The amount of computation of the harmonic suppression algorithm is large and is positively correlated with the number of harmonics suppressed. Together with other control functions, the amount of computation of the system control algorithm can be increased several times at most. However, the configuration mode of the existing chain SVG controller has insufficient control capability, resulting in poor system dynamic response, poor current waveform control capability, and large harmonic distortion rate. It cannot give full play to the performance characteristics of low current harmonic distortion rate and high dynamic response of the multi-level chain SVG, which is not conducive to the regulation and control of reactive power. Replacing a higher-end controller not only significantly increases the cost, but also fails to effectively reduce the control system link delay, and the controller margin does not meet the design requirements. Summary of the invention

[0006] The object of the present invention is to provide a chain-type SVG control system and a configuration method thereof, so as to solve the problem of high cost in improving the control capability of the controller of the existing chain-type SVG control system.

[0007] The present invention provides a chain SVG control system configuration method for solving the above technical problems, which is used to configure a chain SVG control system whose controller adopts a heterogeneous dual-core processor architecture based on FPGA. The method is as follows: the control algorithm in the chain SVG control system is implemented by the FPGA core, and the control logic in the chain SVG control system is implemented by another core; the control algorithm includes virtual synchronization control function, commutation chain voltage balancing, control instruction generation and harmonic suppression; the control logic includes start and stop control of the chain SVG control system, unlocking sequential control logic, chain SVG control system state change and main and standby system switching.

[0008] Furthermore, the code for implementing the control algorithm in the FPGA and the code for implementing the control logic in another core are automatically generated by the code generation function of the pre-built chain SVG control system simulation model.

[0009] Furthermore, the chain SVG control system simulation model includes a primary equipment unit, an auxiliary monitoring / test unit and a secondary control unit. The data interaction between the units is realized through tags or data input / output functions. The primary equipment unit is used to simulate the primary equipment in the power grid; the auxiliary monitoring / test unit is used to realize simulation waveform viewing, harmonic generation and fault simulation, and the secondary control unit is used to realize analog quantity sampling, open-in and open-out control, control algorithm and control logic of the chain SVG control system.

[0010] Furthermore, the chain SVG control system simulation model is jointly modeled by Simulink simulation software and Xilinx software. After building the control algorithm model using the Xilinx Blockset model library, the control algorithm is compiled using the System Generator in the Xilinx software to achieve automatic generation of VHDL code, and the VHDL code is loaded into the FPGA.

[0011] Furthermore, the chain SVG control system simulation model is built using Simulink simulation software, and the control logic is compiled using Embedded Coder in the Simulink simulation software to achieve automatic generation of embedded C code, and the C code is loaded into another core.

[0012] Furthermore, the control algorithm is compiled using System Generator to generate a VHDL language code instance, and the code execution timing is directly checked through the instance to verify whether the FPGA timing operation is normal.

[0013] Furthermore, when the control algorithm of the chain SVG control system also includes at least one of a virtual synchronization control function, a virtual impedance function, a droop control function and a fault ride-through function, the virtual synchronization control function, the virtual impedance function, the droop control function and the fault ride-through function are all implemented by FPGA.

[0014] Furthermore, when the chain SVG control system is provided with a backup control system, another core implements the primary and backup system switching control logic.

[0015] The beneficial effects of the method of the present invention are as follows: utilizing the parallel computing characteristics of the FPGA in the processor of the existing chain SVG control system, the present invention proposes to redefine the control function of the heterogeneous dual-core processor based on the FPGA, the FPGA is used to implement the control algorithm with a large amount of calculation, and another different type of core is used to implement the control logic function with strong flexibility, and the computing power of the two cores in the processor is reasonably allocated to ensure that each control function of the chain SVG system can be accurately implemented, so that the performance characteristics of the low current harmonic distortion rate and high dynamic response of the chain SVG multi-level can be fully utilized. Without changing the control hardware configuration, the present invention greatly reduces the execution time of the control algorithm, can effectively reduce the control system link delay, improve the control accuracy, reduce the probability of system resonance, and improve the control capability of the controller at a low cost.

[0016] The chain SVG control system provided by the present invention to solve the above technical problems includes a controller, wherein the controller adopts a heterogeneous dual-core processor architecture based on FPGA, and the two core processors realize data interaction through a data interface. The controller of the system is configured using the chain SVG control system configuration method described above.

[0017] Furthermore, the controller is an ARM+FPGA dual-core processor.

[0018] The beneficial effects of the system of the present invention are: utilizing the parallel computing characteristics of the FPGA in the processor of the existing chain SVG control system, the present invention proposes to redefine the control function of the heterogeneous dual-core processor based on the FPGA, the FPGA is used to implement the control algorithm with a large amount of calculation, and another different type of core is used to implement the control logic function with strong flexibility, and the computing power of the two cores in the processor is reasonably allocated to ensure that each control function of the chain SVG system can be accurately implemented, so that the performance characteristics of the low current harmonic distortion rate and high dynamic response of the chain SVG multi-level can be fully utilized. Without changing the control hardware configuration, the present invention greatly reduces the execution time of the control algorithm, can effectively reduce the control system link delay, improve the control accuracy, reduce the probability of system resonance, and improve the control capability of the controller at a low cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 is a configuration block diagram of a chained SVG control system according to an embodiment of the present invention;

[0020] Figure 2 is a control algorithm block diagram of an embodiment of the present invention;

[0021] Figure 3 is a schematic diagram of a simulation model built using an HDL Coder library according to an embodiment of the present invention;

[0022] Figure 4 It is a detailed display diagram of a model constructed by calling a module of the HDL Coder model library according to an embodiment of the present invention;

[0023] Figure 5 is a software schematic diagram of generation according to an embodiment of the present invention;

[0024] Figure 6 It is a schematic diagram of the FPGA code area of ​​the multifunctional code generation model established by using System Generator according to an embodiment of the present invention;

[0025] Figure 7 1 is a schematic diagram of a main loop area of ​​a multifunctional code generation model established by using System Generator according to an embodiment of the present invention;

[0026] Figure 8 It is a schematic diagram of the ARM code area of ​​the multifunctional code generation model established by using System Generator according to an embodiment of the present invention;

[0027] Fig. 9 It is a detailed display diagram of the FPGA code area of ​​an embodiment of the present invention;

[0028] Fig.10 It is a schematic diagram of an IP core file for generating FPGA code according to an embodiment of the present invention;

[0029] Fig.11 It is a schematic diagram of the fault judgment function model of the ARM in an embodiment of the present invention;

[0030] Fig.12 It is a timing diagram of the phase-locked function implemented by the FGPA of an embodiment of the present invention. DETAILED DESCRIPTION

[0031] The specific implementation of the present invention will be further described below in conjunction with the accompanying drawings.

[0032] The basic idea of ​​the present invention is: for a chain SVG control system whose controller adopts a heterogeneous dual-core processor architecture based on FPGA, the parallel computing characteristics of FPGA are utilized, and according to the amount of calculation of the control algorithm and control logic in the chain SVG control system, the principle is to ensure that the subsequent maintenance and modification are simple and easy and the execution time of the core software is high-speed and controllable; the control function of each core of the heterogeneous dual-core processor based on FPGA is redefined, and the execution time of the control algorithm is greatly reduced without changing the control hardware configuration, which can effectively reduce the link delay of the control system, improve the control accuracy, and reduce the probability of system resonance, thereby improving the control capability of the controller at a low cost.

[0033] Embodiment of the chained SVG control system configuration method of the present invention

[0034] Based on the above basic idea, the configuration method of the chain SVG control system of the present invention is as follows: the control algorithm in the chain SVG control system is implemented by the FPGA core, and the control logic in the chain SVG control system is implemented by another core; the control algorithm includes virtual synchronization control function, commutation chain voltage balancing, control instruction generation and harmonic suppression; the control logic includes chain SVG control system start and stop control, unlocking sequential control logic, chain SVG control system state change and main and standby system switching.

[0035] Some chained SVG control systems also have at least one of a virtual synchronization control function, a virtual impedance function, a droop control function, and a fault ride-through function. For these chained SVG control systems, the virtual synchronization control function, the virtual impedance function, the droop control function, and / or the fault ride-through function are all implemented by FPGA. Some chained SVG control systems also have a redundant standby control system, and the active / standby switching control logic of the system is implemented by another core.

[0036] As a preferred implementation, the control algorithm of the chain SVG control system of this embodiment includes virtual synchronous control function, virtual impedance function, commutation chain voltage balancing, instruction generation function and important support functions for the power grid, including droop control function, harmonic suppression function and fault ride-through function; the control logic mainly includes the start and stop control of the chain SVG control system, unlocking and other sequential control logic, control system operation state transformation and main-standby system switching. The above control algorithm is implemented by FPGA, and the control logic is implemented by another core. The specific implementation principles of the virtual synchronous control function and the harmonic suppression function are as follows: Figure 2 shown.

[0037] When performing the above-mentioned system controller settings, in order to reduce the software implementation and software function testing links and improve the research and development efficiency, this embodiment integrates the implementation of the software code with the system research. The code for the FPGA to implement the control algorithm and the code for another core processor to implement the control logic can be automatically generated through the code generation function of the pre-built chain SVG control system simulation model.

[0038] As a preferred implementation, the chain SVG control system simulation model of this embodiment includes a primary equipment unit, an auxiliary monitoring / test unit and a secondary control unit. Data interaction between the units is realized through tags or data input / output functions. The primary equipment unit is used to simulate the primary equipment in the power grid; the auxiliary monitoring / test unit is used to realize simulation waveform viewing, harmonic generation and fault simulation, and the secondary control unit is used to realize analog quantity sampling, open-in and open-out control, control algorithm and control logic of the chain SVG control system.

[0039] Among them, Figure 1 As shown, the primary equipment includes power grid, circuit breaker, transformer, commutation chain unit, etc.; the secondary control unit includes analog sampling module, input and output control module, control algorithm module and control logic module; the auxiliary monitoring / test unit includes simulation waveform viewing module, harmonic generation module and fault simulation module, etc.

[0040] The purpose of building a chain SVG control system simulation model is to conduct system characteristic research and verify the correctness of the control algorithm and control logic on the one hand; on the other hand, it can realize the automatic generation of software code. Since the primary equipment and auxiliary monitoring / test unit do not need to generate software code, these two parts and the secondary control unit are independent of each other. As the actual engineering now has higher and higher requirements for the control function of SVG, the control algorithm is becoming more and more complex, the amount of calculation is several times larger than that of previous SVG projects, and the execution time of the control algorithm in the processor has also increased exponentially. Without changing the control hardware configuration, the functions of each core of the FPGA-based heterogeneous dual-core processor are redefined, the control algorithm module is implemented by FPGA, and the control logic module is implemented by another core, which ultimately achieves the effect of reducing the control link delay. According to the different code generation types, the control algorithm and control logic are also divided into two independent modules, and the communication between the two is realized through the data input / output function of the simulation model.

[0041] As a preferred implementation, the chain SVG control system simulation model is built using the Simulink software module in the MATLAB simulation software, and the codes generated by the simulation model include two types of VHDL language and C language codes. The VHDL code can be directly loaded into the FPGA, and the C language code is loaded into another core.

[0042] Most modules in the Simulink simulation model can automatically generate C code, including common mathematical functions, logical operations, state diagrams, various discrete controllers, etc. After the control logic module is built, it can be compiled through Embedded Coder to realize the automatic generation of embedded C code and load the C code into another core.

[0043] There are two main methods of generating VHDL code: one is general VHDL code generation, and the other is hardware-specific VHDL code generation.

[0044] For the general VHDL code generation method, the HDL Coder library in the Simulink model library is used to build the control algorithm model, set the complete input / output ports, and then the HDL Coder tool can be used to generate the control algorithm VHDL code, which can be loaded into any FPGA project. Figure 3 To build the control algorithm model, Figure 4 Model details for modules that call the HDL Coder model library; Figure 5 The generated software contains multiple vhd format files.

[0045] The FPGA software generated by the general VHDL code generation method cannot quickly and effectively calculate the software execution time, which is very inconvenient for the timing design of the FPGA; if the branch module built inside the model is called in a new model, the code generated by the new model and the code generated by the current model will be compiled together, which will cause the reused module to work abnormally, which is not convenient for modular management and generates a large number of files. To this end, this embodiment proposes a VHDL code generation method for a dedicated hardware series.

[0046] For the VHDL code generation method of the dedicated hardware series, the Simulink model can be jointly modeled with Xilinx, and the simulation model can be built using the Xilinx Blockset model library, which is compatible with most Xilinx series FPGAs. After building the control algorithm using the Xilinx Blockset model library, the control algorithm is compiled through System Generator to achieve automatic generation of VHDL code.

[0047] The FPGA code model built using the FPGA-specific library module can facilitate the design and calculation of code timing, and directly generate the IP core (internal operations are invisible), making it easy for the program to call multiple times.

[0048] The following takes a heterogeneous dual-core processor based on ARM+FPGA as an example to further illustrate the process of generating code using a dedicated hardware series VHDL code generation method.

[0049] When building a simulation model through System Generator, you can use either FPGA-specific library modules such as Xilinx Blockset or Simulink general library modules. ARM code needs to be modeled using general modules, and control logic such as state machines and fault protection judgments should be designed according to actual needs; ARM and FPGA realize data interaction through data interfaces. Figure 6-Figure 8 The various parts of the multi-function code generation model established by System Generator include FPGA code area, ARM code area and main loop area; Fig. 9 This is a detailed display of the FPGA code area. -1 and z -3 Can quickly calculate the execution time of the code; Fig.10 Generate IP core files for FPGA code, easy to use; Fig.11 This is the fault judgment function of ARM.

[0050] As a preferred implementation, after the code is automatically generated, if the runtime setting is wrong, it will also lead to errors in the running results, and it is necessary to verify whether the code execution timing is normal. The Simulink simulation model has a VHDL code instance function, which can effectively verify whether the FPGA timing operation is normal. You can set easily identifiable input variables for the input port and generate a running instance through the System Generator. Fig.12 The timing diagram of the phase-lock function is shown. The phase-lock control period is set to 50us. Fig.12 As shown, the phase-locked angle is updated every 50us and the control timing is as expected.

[0051] Chain SVG control system embodiment of the present invention

[0052] The chained SVG control system of the present invention includes a controller, which adopts a heterogeneous dual-core processor architecture based on FPGA. The two core processors realize data interaction through a data interface. It is characterized in that the controller of the system adopts the chained SVG control system configuration method mentioned in the above control method embodiment for configuration. The specific configuration method is shown in the above embodiment and will not be described in detail here.

[0053] The heterogeneous dual-core processor based on FPGA is usually an ARM+FPGA dual-core processor, or a DSP+FPGA dual-core processor. The configuration method of the present invention is applied to the ARM+FPGA dual-core processor, and the system performance improvement effect brought about is particularly obvious.

[0054] Without changing the control hardware configuration, the present invention makes full use of the parallel computing characteristics of FPGA, greatly reduces the execution time of the control algorithm, can effectively reduce the control system link delay, improve control accuracy, and reduce the probability of system resonance; at the same time, it can simplify the software development process and improve development efficiency.

Claims

1. A chain SVG control system configuration method, characterized in that: The method is used to configure a chain SVG control system whose controller adopts a heterogeneous dual-core processor architecture based on FPGA. The method is as follows: the control algorithm in the chain SVG control system is implemented by the FPGA core, and the control logic in the chain SVG control system is implemented by another core; the control algorithm includes a virtual synchronization control function, commutation chain voltage balancing, control instruction generation and harmonic suppression; the control logic includes start and stop control of the chain SVG control system, unlocking sequential control logic, chain SVG control system state change and main and standby system switching.

2. The chained SVG control system configuration method according to claim 1, characterized in that: The code for implementing the control algorithm in the FPGA and the code for implementing the control logic in another core are automatically generated through the code generation function of the pre-built chain SVG control system simulation model.

3. The chained SVG control system configuration method according to claim 2, characterized in that: The chain SVG control system simulation model includes a primary equipment unit, an auxiliary monitoring / test unit and a secondary control unit. The data interaction between the units is realized through tags or data input / output functions. The primary equipment unit is used to simulate the primary equipment in the power grid; the auxiliary monitoring / test unit is used to realize simulation waveform viewing, harmonic generation and fault simulation, and the secondary control unit is used to realize analog quantity sampling, open-in and open-out control, control algorithm and control logic of the chain SVG control system.

4. The chain SVG control system configuration method according to claim 2, characterized in that: The chain SVG control system simulation model is jointly modeled by Simulink simulation software and Xilinx software. After building a control algorithm model using the Xilinx Blockset model library, the control algorithm is compiled using the System Generator in the Xilinx software to achieve automatic generation of VHDL code, and the VHDL code is loaded into the FPGA.

5. The chain SVG control system configuration method according to claim 2, characterized in that: The chain SVG control system simulation model is built by using Simulink simulation software. The control logic is compiled by using Embedded Coder in the Simulink simulation software to realize automatic generation of embedded C code, and the C code is loaded into another core.

6. The chained SVG control system configuration method according to claim 2, characterized in that: Use SystemGenerator to compile the control algorithm and generate a VHDL language code instance. Then, use the instance to directly view the code execution timing and verify whether the FPGA timing is running normally.

7. The chained SVG control system configuration method according to claim 1, characterized in that: When the control algorithm of the chain SVG control system also includes at least one of a virtual synchronization control function, a virtual impedance function, a droop control function and a fault ride-through function, the virtual synchronization control function, the virtual impedance function, the droop control function and the fault ride-through function are all implemented by FPGA.

8. The chained SVG control system configuration method according to claim 1, characterized in that: When the chain SVG control system is provided with a backup control system, the main and backup system switching control logic is implemented by another core.

9. A chain SVG control system, the control system includes a controller, the controller adopts a heterogeneous dual-core processor architecture based on FPGA, and the two core processors realize data interaction through a data interface, characterized in that: The controller of the system is configured using the chain SVG control system configuration method described in any one of claims 1 to 8.

10. The chain SVG control system according to claim 9, characterized in that: The controller is a dual-core processor of ARM+FPGA.

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