Progressive isolation grounding device for series-parallel communication control of multiple groups of power supplies

Abstract

The invention discloses a progressive isolation grounding device for series-parallel communication control of multiple groups of power supplies, which comprises a power supply host and a plurality of power supply slaves connected with the host, and control signals are transmitted between upper and lower levels of the power supply slaves in an electrical isolation manner. A control signal sent by the host can be automatically converted into voltage step by step and is sequentially transmitted to the plurality of slaves. The host is provided with a host isolating circuit and a host output port, and one input side of the host isolating circuit uses a group of host power supply voltage; and the intermediate slave is provided with an intermediate input port, an intermediate isolation circuit and an intermediate output port, and the intermediate slave, the host output port and the output side of the host isolation circuit respectively use a group of intermediate power supply voltages. Therefore, the plurality of slave machines of the host do not have the problem of insufficient driving capability of the control signals, and the control signals are not interfered by common-ground noise and noise between alternating-current power supplies.

Description

Technical Field

[0001] The present invention relates to the technical field of serial-parallel communication control of multiple power supply groups, and in particular to a deferred isolation grounding device for serial-parallel communication control of multiple power supply groups. Background Art

[0002] An AC power system is often composed of multiple AC power units connected in series and parallel, and the control signals of the multiple AC power units are often connected to each other in a master-slave structure of a serial flow to reduce the complexity of the connection between the control signals of the multiple AC power units and improve their reliability. Figure 3 The control signal stream of the general master-slave architecture of multiple AC power supply units is shown, wherein an AC power supply unit is set as a host 80 (master), which has a host processor 81 for outputting a host output control signal d8 and outputting the host output control signal d8 through a host output port 83; an AC power supply unit is set as a first slave 90 (slave#1), which has a first processor 91 for reading the host output control signal d8 of the host 80 input through a first input port 92, and outputting a first output control signal d8 through a first output port 93 accordingly. d9; an AC power source unit is set as an nth slave n0 (slave#n), which has an nth processor n1 for reading an n-1th output control signal dn-1 outputted by a previous AC power source unit of the nth slave n0 inputted by an nth input port n2. Here, the connection between a second slave and an n-1th slave and between them (not shown) is similar to the first slave; thus, the host output control signal d8 sent by the host 80 (master) can be sequentially streamed from the first slave 90 (slave#1) to the nth slave n0 (slave#n). Figure 3 As shown, the host 80 and the first slave 90 (slave#1) to the nth slave n0 (slave#n) all use the same power supply and ground (such as Figure 3 The inverted ).but Figure 3 The control signal stream of the multiple AC power supply stand-alone master-slave architecture shown has the following problems: the voltage difference between the reference ground voltage of the signal and the reference ground voltage of the master becomes larger as it approaches the end of the master-slave architecture, and the strength of the control signal itself is also attenuated due to the limitation of the driving capability of the master, and the noise of each AC power supply stand-alone will also affect each other in high-power or high-frequency output.

[0003] It can be seen that the control signal stream of the common multiple AC power single machine master-slave architecture has the following disadvantages:

[0004] 1. The greater the required output power, the more AC power supply units are needed; the more you need to consider the problem of insufficient back-end signal driving capability.

[0005] 2. The more systems there are, the more likely the signal received by each AC power unit will be interfered by common ground noise and environmental factors such as system grounding.

[0006] 3. The higher the output power and frequency of the AC power supply, the more noise interference generated by the AC power supply itself will affect each other.

[0007] Therefore how to overcome the above-mentioned shortcomings, there is an urgent need. Summary of the invention

[0008] In order to solve the above problems, the object of the present invention is to provide a deferred isolation grounding device for controlling multiple groups of power supplies in series and parallel communication, which comprises:

[0009] A host having:

[0010] a host isolation circuit having an input side and an output side, the input side of the host isolation circuit using a set of host power supply voltages; and

[0011] a host output port, the host output port being connected to the output side of the host isolation circuit;

[0012] An intermediate slave having:

[0013] an intermediate input port connected to the host output port;

[0014] An intermediate isolation circuit has an input side and an output side, wherein the input side of the intermediate isolation circuit uses a set of intermediate power supply voltages;

[0015] The set of intermediate power supply voltages is transmitted to the host output port and the output side of the host isolation circuit via the intermediate input port, so that the output side of the host isolation circuit uses the set of intermediate power supply voltages.

[0016] Preferably, a processor of the host outputs a host control signal based on the group of host power supply voltages to the input side of the host isolation circuit, and the host isolation circuit converts the voltage of the received host control signal into a host secondary control signal based on the group of intermediate power supply voltages. After the host secondary control signal is output by the output side of the host isolation circuit, it is transmitted to the intermediate slave via the host output port and the intermediate input port.

[0017] Preferably, an intermediate processor and an intermediate buffer circuit of the intermediate slave output an intermediate control signal based on the group of intermediate power supply voltages to the input side of the intermediate isolation circuit according to the received secondary control signal of the host. The intermediate isolation circuit converts the received intermediate control signal into an intermediate secondary control signal based on a group of power supply voltages provided by the next-level intermediate slave. After the intermediate secondary control signal is output by the output side of the intermediate isolation circuit, it is transmitted to the next-level intermediate slave via the intermediate output port.

[0018] The present invention discloses a deferred isolation grounding device for serial-parallel communication control of multiple power supply groups, wherein the host and multiple slaves connected to the host transmit control signals in an electrically isolated manner between the upper and lower levels, and the control signal sent by the host can be automatically converted into voltage step by step and transmitted to the multiple slaves in sequence, so that the multiple slaves of the host will not have the problem of insufficient control signal driving ability, and the control signal will not be disturbed by environmental factors such as common ground noise and system grounding, and the control signal will not be disturbed by noise between AC power supplies. In this way, the purpose of the present invention can be achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 : Circuit structure schematic diagram of the present invention.

[0020] Figure 2A to Figure 2C : A schematic diagram of circuit connections of an embodiment of the present invention.

[0021] Figure 3 : Schematic diagram of the control signal streaming device connection of a general multiple power supply single machine master-slave architecture.

[0022]

Explanation of symbols

[0023] 10: Host

[0024] 11: Host processor

[0025] 12: Host buffer circuit

[0026] 14: Host isolation circuit

[0027] 15: Host input port

[0028] 16: Host output port

[0029] 107: Host transmission cable

[0030] 10A: Host control signal

[0031] 10B: Host secondary control signal

[0032] 20: First slave

[0033] 21: First processor

[0034] 22: First buffer circuit

[0035] 24: First isolation circuit

[0036] 25: First input port

[0037] 26: First output port

[0038] 207: First Transmission Cable

[0039] 20A: First control signal

[0040] 20B: First secondary control signal

[0041] 20C: First intermediate signal

[0042] N0: tail end slave

[0043] N1: Tail-end processor

[0044] N2: Tail end buffer circuit

[0045] N4: Tail end isolation circuit

[0046] N5: Tail input port

[0047] N6: Tail output port

[0048] N-10B: The secondary control signal output by the previous slave at the end of the slave

[0049] N0C: tail end intermediate signal

[0050] 80: Host

[0051] 81:Host processor

[0052] 82: Host input port

[0053] 83: Host output port

[0054] d8: Host output control signal

[0055] 90: First slave

[0056] 91: First processor

[0057] 92: First input port

[0058] 93: First output port

[0059] d9: first output control signal

[0060] n0: the nth slave

[0061] n1: nth processor

[0062] n2: nth input port

[0063] n3: nth output port

[0064] dn-1: n-1th output control signal

[0065] VDD_M: Host power supply

[0066] GND_M: Host ground

[0067] VDD_2: First power supply

[0068] GND_2: First ground

[0069] VDD_3: Second power supply

[0070] GND_3: Second ground

[0071] VDD_N: Tail power supply

[0072] GND_N: tail ground DETAILED DESCRIPTION

[0073] Please see Figure 1The circuit structure of the deferred isolation grounding device for controlling serial-parallel communication of multiple power supplies of the present invention is shown, which comprises: a host 10, which is a power supply system, and has a host processor 11 that outputs a host control signal 10A, a host isolation circuit 14, and the host isolation circuit 14 has an A side and a B side. The A side of the host isolation circuit 14 is connected to the host processor 11 to receive the host control signal 10A. At the same time, the host isolation circuit 14 outputs a host secondary control signal 10B from the B side of the host isolation circuit 14 according to the received host control signal 10A. The host 10 also has a host output port 16, and the host output port 16 has a plurality of metal pins for connection. The host output port 16 is connected to the B side of the host isolation circuit 14. The host secondary control signal 10B is output from the host output port 16 to the host output port 16. B is output via the host output port 16; wherein the host processor 11 and the A side of the host isolation circuit 14 both use a host power supply voltage VDD_M and a host ground voltage GND_M, while the B side of the host isolation circuit 14 and the host output port 16 use a first power supply voltage VDD_2 and a first ground voltage GND_2; wherein the A side of the host isolation circuit 14 receives the host control signal 10A based on the potential of the host power supply voltage VDD_M and the host ground voltage GND_M, and converts its voltage into the host secondary control signal 10B based on the potential of the first power supply voltage VDD_2 and the first ground voltage GND_2, so that the B side of the host isolation circuit 14 and the host output port 16 are electrically isolated from the rest of the host 10. The host isolation circuit 14 may be an electrical isolation circuit using capacitance, magnetic flux, or optical means, but the present invention is not limited thereto; the host processor 11 may be a microcontroller (MCU) or a CPU, but the present invention is not limited thereto; the host control signal 10A and the host secondary control signal 10B are both composed of a plurality of digital signals of the same number, but the present invention is not limited thereto; the combination of the host power supply voltage VDD_M and the host ground voltage GND_M may be referred to as the group of host power supply voltages, the combination of the first power supply voltage VDD_2 and the first ground voltage GND_2 may be referred to as the group of first power supply voltages, and so on.

[0074] Figure 1There is also a first slave 20, which is a power supply system, having a first input port 25, the first input port 25 having a plurality of metal pins for connection, the first input port 25 is connected to the host output port 16 of the host 10 via a host transmission cable 107, the first input port 25 receives the host secondary control signal 10B from the host output port 16; the first slave 20 also has a first buffer circuit 22, the first buffer circuit 22 is connected to the first input port 25, the first buffer circuit 22 receives the host secondary control signal 10B from the first input port 25, and outputs a first intermediate signal 20C from an output end of the first buffer circuit 22 accordingly; the first buffer The output end of the circuit 22, a first processor 21 of the first slave 20, and the A side of a first isolation circuit 24 of the first slave 20 are connected. The A side of the first isolation circuit 24 receives a first control signal 20A (which will be further explained below) from the first processor 21 and the first buffer circuit 22. At the same time, the B side of the first isolation circuit 24 is connected to a first output port 26. The first output port 26 has a plurality of metal pins for connection. The B side of the first isolation circuit 24 outputs a first secondary control signal 20B according to the first control signal 20A, and outputs it to an input port of a second slave of the next level (not shown) via the first output port 26 and a first transmission cable 207. The first processor 21, the first buffer circuit 22, the A side of the first isolation circuit 24, and the first input port 25 all use a first power supply voltage VDD_2 and a first ground voltage GND_2, while the B side of the first isolation circuit 24 and the first output port 26 use a second power supply voltage VDD_3 and a second ground voltage GND_3; the A side of the first isolation circuit 24 receives the first control signal 20A based on the potential of the first power supply voltage VDD_2 and the first ground voltage GND_2, and converts its voltage into the first secondary control signal 20B based on the potential of the second power supply voltage VDD_3 and the second ground voltage GND_3, so that the B side of the first isolation circuit 24 and the first output port 26 are electrically isolated from the rest of the first slave 20.

[0075] Figure 1There is also a tail end slave N0, which is a power supply system, having a tail end input port N5, the tail end input port N5 has a plurality of metal pins for connection, the tail end input port N5 is connected to an output port of the previous level slave via the previous level transmission cable N-107 (not shown), the tail end input port N5 receives a secondary control signal N-10B outputted from the previous level slave from the output port of the previous level slave; the tail end slave N0 also has a tail end buffer circuit N2, The tail end buffer circuit N2 is connected to the tail end input port N5, and the tail end buffer circuit N2 receives the secondary control signal N-10B output by the previous stage slave from the tail end input port N5, and accordingly outputs a tail end intermediate signal N0C from an output end of the tail end buffer circuit N2 to a tail end processor N1 of the tail end slave N0; wherein the tail end processor N1, the tail end buffer circuit N2, and the tail end input port N5 all use a tail end power supply voltage VDD_N and a tail end ground voltage GND_N. Since the tail end slave N0 is the last stage of the multiple power supply series-parallel connection of the present invention, its output part is omitted here. It is worth mentioning that, Figure 1 The circuit of the first level slave from the second slave 20 to the tail slave N0 is omitted, because the circuit of the first level slave from the second slave to the tail slave N0 and the connection mode between the second slave and the upper and lower slaves are similar to the circuit of the first slave 20 and the connection mode between the first slave 20 and its upper and lower hosts or slaves, so it is not repeated. Among them, the isolation circuit, processor, control signal and the secondary control signal of the above slave are similar to those of the host 10, but the present invention is not limited to this.

[0076] Please see Figure 2A to Figure 2C The embodiment of the deferred isolation grounding circuit of the present invention with multiple power supply series-parallel communication control is shown. In this embodiment, Figure 2A Regarding the host 10, the host buffer circuit 12 has 4 input pins 1A-4A, 4 output pins 1Y-4Y, and 1 enable pin EN. The enable pin EN is connected to the output pin EN2 of the host processor 11. At this time, the output pin EN2 of the host processor 11 outputs a digital voltage representing "1" to turn off the output of the host buffer circuit 12 ( Figure 2A The symbol X in the figure represents turning off the output. Figure 2AAs shown, the output pins D1~D3 and EN_B of the host processor 11 are connected to the A side of the host isolation circuit 14, and the host processor 11 outputs a host control signal 10A to the A side of the host isolation circuit 14 via the pins D1~D3 and EN_B. After the host isolation circuit 14 receives the host control signal 10A, a corresponding host secondary control signal 10B is outputted from the B side of the host isolation circuit 14, and the host secondary control signal 10B is then outputted from the host output port 16.

[0077] In this embodiment, Figure 2B Regarding the first slave 20, EN2 of the first processor 21 outputs a digital voltage representing "0" to enable the output of the first buffer circuit 22. At this time, the host secondary control signal 10B output by the host 10 is input to the first buffer circuit 22 of the first slave 20 via the first input port 25. The first buffer circuit 22 outputs a first intermediate signal 20C to the input pins D1 to D3 and EN1 of the first processor 21 according to the host secondary control signal 10B. At the same time, the first buffer circuit 22 also outputs the first intermediate signal The disable signals D1-D3 in the first intermediate signal 20C are output to the first isolation circuit 24, wherein the disable signals D1-D3 in the first intermediate signal 20C and an enable signal outputted from the output pin EN_B of the first processor 21 to the first isolation circuit 24 together form a first control signal 20A. After receiving the first control signal 20A, the first isolation circuit 24 outputs a corresponding first secondary control signal 20B from the B side of the first isolation circuit 24, and the first secondary control signal 20B is then outputted from the first output port 26. It is worth mentioning that the first buffer circuit 22 has the function of a conduction switch, so when the first buffer circuit 22 is turned on, the first intermediate signal 20C is similar to the host secondary control signal 10B; and the enable signal outputted by the output pin EN_B of the first processor 21 is the same as the enable signal in the first intermediate signal 20C received by the input pin EN1 of the first processor 21.

[0078] In this embodiment, Figure 2CThis is about the tail end slave N0, which is the last stage of the multiple power supply series-parallel connection in this embodiment. At this time, a previous stage secondary control signal N-10B output by the slave of the previous stage of the tail end slave N0 (i.e., the N-2 slave) is input to the tail end buffer circuit N2 through the tail end input port N5. The tail end buffer circuit N2 outputs a tail end intermediate signal N0C to the input pins D1~D3 and EN1 of the tail end processor N1 according to the secondary control signal N-10B of the previous stage slave. Since the tail end slave is the last stage of the multiple power supply series-parallel connection in this embodiment, its output part is omitted here. It is worth mentioning that the first slave 20 is between the host 10 and the tail end slave N0, so it can also be called the intermediate slave. The next stage slave of the first slave 20 can be called the second slave or the next stage slave of the intermediate slave, and the rest can be deduced by analogy.

[0079] As described above, the host and the slave disclosed in the present invention transmit control signals in an electrically isolated manner, and the control signal sent by the host 10 can be automatically converted step by step and transmitted to the first slave 20 to the tail slave N0 in sequence, so that no matter how many AC power units there are, there will be no problem of insufficient control signal driving ability, and the control signal will not be interfered by environmental factors such as common ground noise and system grounding, and the control signal will not be interfered by noise between AC power sources. In this way, the purpose of the present invention can be achieved.

Claims

1. A deferred isolation grounding device controlled by serial and parallel communication of multiple power supply groups, characterized in that: Include: A host having: a host isolation circuit having an input side and an output side, the input side of the host isolation circuit using a set of host power supply voltages; and a host output port, the host output port being connected to the output side of the host isolation circuit; An intermediate slave having: an intermediate input port, the intermediate input port being connected to the host output port; an intermediate isolation circuit having an input side and an output side, wherein the input side of the intermediate isolation circuit uses a set of intermediate power supply voltages; in The set of intermediate power supply voltages is transmitted to the host output port and the output side of the host isolation circuit via the intermediate input port, so that the output side of the host isolation circuit uses the set of intermediate power supply voltages.

2. The device according to claim 1, characterized in that A processor of the host outputs a host control signal based on the group of host power supply voltages to the input side of the host isolation circuit. The host isolation circuit converts the received host control signal into a host secondary control signal based on the group of intermediate power supply voltages. After the host secondary control signal is output by the output side of the host isolation circuit, it is transmitted to the intermediate slave via the host output port and the intermediate input port.

3. The device according to claim 2, characterized in that An intermediate processor and an intermediate buffer circuit of the intermediate slave output an intermediate control signal based on the group of intermediate power supply voltages to the input side of the intermediate isolation circuit according to the received host secondary control signal. The intermediate isolation circuit converts the received intermediate control signal into an intermediate secondary control signal based on a group of power supply voltages provided by the next-level intermediate slave. After the intermediate secondary control signal is output by the output side of the intermediate isolation circuit, it is transmitted to the next-level intermediate slave via the intermediate output port.

4. The device according to claim 3, characterized in that The intermediate processor controls whether the intermediate buffer circuit outputs the received host secondary control signal.

5. The device according to claim 4, characterized in that When the intermediate buffer circuit outputs the received host secondary control signal to the intermediate processor and the intermediate isolation circuit, the intermediate processor transmits an enable signal in the received host secondary control signal to the intermediate isolation circuit.

6. The device according to claim 4, characterized in that When the intermediate buffer circuit outputs the received host secondary control signal to the intermediate processor and the intermediate isolation circuit, the intermediate buffer circuit transmits a disable signal in the received host secondary control signal to the intermediate isolation circuit.

7. The device according to claim 2, characterized in that An intermediate processor and an intermediate buffer circuit of the intermediate slave output an intermediate control signal based on the group of intermediate power supply voltages to the input side of the intermediate isolation circuit according to the received host secondary control signal. The intermediate isolation circuit converts the intermediate control signal into an intermediate secondary control signal based on a group of power supply voltages provided by a tail-end slave. After the intermediate secondary control signal is output by the output side of the intermediate isolation circuit, it is transmitted to the tail-end slave via the intermediate output port.

8. The device according to claim 7, characterized in that The intermediate processor controls whether the intermediate buffer circuit outputs the received host secondary control signal.

9. The device according to claim 1, characterized in that The intermediate input port is connected to the host output port via a cable.

10. The device according to claim 3, characterized in that The intermediate output port is connected to the next-stage intermediate slave via a cable.

11. The device according to claim 7, characterized in that The intermediate output port is connected to the tail end slave via a cable.

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