Working mode switching method of power switching circuit and power switching circuit

Abstract

The invention provides a working mode switching method of a power switching circuit and the power switching circuit, and the method comprises the steps: enabling a low-power-consumption low-dropout linear regulator when the power switching circuit is switched from a normal mode to a low-power-consumption mode, the high-performance low-dropout linear regulator is connected with the low-power-consumption low-dropout linear regulator, so that the voltage output by the low-power-consumption low-dropout linear regulator is higher than the voltage output by the high-performance low-dropout linear regulator, and the low-power-consumption low-dropout linear regulator supplies When the power switching circuit is switched from the low-power-consumption mode to the normal mode, the high-performance low-dropout linear regulator is enabled, so that the voltage output by the high-performance low-dropout linear regulator is higher than that output by the low-power-consumption low-dropout linear regulator. Therefore, the high-performance low-dropout linear voltage regulator supplies power to the load. According to some embodiments, it is ensured that the load is always in a power supply state when the working modes are switched.

Description

Technical Field

[0001] The present application relates to the technical field of power management circuits, and in particular to a method for switching working modes of a power switching circuit and a power switching circuit. Background Art

[0002] Currently, many chips have multiple operating modes, and different operating modes have different requirements for low-dropout regulators (LDO).

[0003] For example, in normal mode, the LDO driving capability is required to be large, but the power consumption of the LDO itself is not required to be high; on the contrary, in low power mode, the driving capability of the LDO is not required to be high, but the power consumption of the LDO itself is required to be high. Therefore, in order to meet this requirement of the chip, many chips will use two LDOs with different power consumption to power a certain load, so as to achieve a compromise between the chip performance and power consumption of the system. However, in practice, during the process of switching the working mode of the two LDO outputs, if the switching scheme is not designed properly, it will cause an unwanted instantaneous power failure on the power supply of the powered load, causing system failure.

[0004] The present invention proposes a simple and easily implementable solution to solve the problem of instantaneous power failure on the powered load power supply that may be caused when two LDOs are switched, and has strong usability. Summary of the invention

[0005] The present application aims to propose a working mode switching method and a power switching circuit of a power switching circuit, so as to solve the problem of instantaneous power failure on the power supply of the powered load that may be caused when two LDOs perform working mode switching.

[0006] According to one aspect of the present application, a method for switching an operating mode of a power switching circuit is proposed, wherein the power switching circuit includes a high-performance low-dropout linear regulator, a low-power low-dropout linear regulator and a load, wherein a high-performance output end of the high-performance low-dropout linear regulator and a low-power output end of the low-power low-dropout linear regulator are electrically connected to the load, respectively, and the operating mode of the power switching circuit includes a normal mode and a low-power mode. The method includes: when the power switching circuit is switched from the normal mode to the low-power mode, enabling the low-power low-dropout linear regulator so that the voltage output by the low-power low-dropout linear regulator is higher than the voltage output by the high-performance low-dropout linear regulator, thereby the load is powered by the low-power low-dropout linear regulator; when the power switching circuit is switched from the low-power mode to the normal mode, enabling the high-performance low-dropout linear regulator so that the voltage output by the high-performance low-dropout linear regulator is higher than the voltage output by the low-power low-dropout linear regulator, thereby the load is powered by the high-performance low-dropout linear regulator.

[0007] According to some embodiments, when the power switching circuit switches from the normal mode to the low power mode, before enabling the low power low dropout linear regulator, the method includes: adjusting the load so that the power consumption of the load is within the tolerable power consumption range of the low power low dropout linear regulator.

[0008] According to some embodiments, when the power switching circuit operates in the low power consumption mode, the high performance low voltage dropout linear regulator is turned off.

[0009] According to some embodiments, when the power switching circuit operates in the normal mode, the load is adjusted so that the load operates in the normal mode.

[0010] According to some embodiments, the low-power low-voltage dropout linear regulator includes a low-power enable input and a low-power adjustment input. When the power switching circuit switches from the normal mode to the low-power mode, the low-power low-voltage dropout linear regulator is enabled, including: enabling the low-power enable input and the low-power adjustment input so that the voltage output by the low-power low-voltage dropout linear regulator is higher than the voltage output by the high-performance low-voltage dropout linear regulator.

[0011] According to some embodiments, the high-performance low-voltage dropout linear regulator includes a high-performance enable input terminal and a high-performance adjustment input terminal. When the power switching circuit switches from the low-power mode to the normal mode, the high-performance low-voltage dropout linear regulator is enabled, including: enabling the high-performance enable input terminal and the high-performance adjustment input terminal so that the voltage output by the high-performance low-voltage dropout linear regulator is higher than the voltage output by the low-power low-voltage dropout linear regulator.

[0012] According to some embodiments, the low power adjustment input terminal is pulled low at a time later than the high performance enable input terminal is pulled low.

[0013] According to some embodiments, the high performance adjustment input terminal is pulled low at a time later than the low power consumption enable input terminal is pulled low.

[0014] According to some embodiments, when the low power enable input terminal is in a low level state, the state of the low power adjustment input terminal includes a high level state or a low level state.

[0015] According to some embodiments, when the high-performance enable input terminal is in a high-level state, the state of the high-performance adjustment input terminal includes a high-level state or a low-level state.

[0016] According to one aspect of the present application, a power switching circuit is proposed, wherein the power switching circuit includes a high-performance low-dropout linear regulator, a low-power low-dropout linear regulator, and a load, wherein the high-performance output end of the high-performance low-dropout linear regulator and the low-power output end of the low-power low-dropout linear regulator are electrically connected to the load, respectively, and the working mode of the power switching circuit includes a normal mode and a low-power mode. When the power switching circuit works in the normal mode, the low-power low-dropout linear regulator is enabled so that the voltage output by the low-power low-dropout linear regulator is higher than The voltage output by the high-performance low-voltage dropout linear regulator is used to power the load, and the power switching circuit is switched from the normal mode to the low-power mode; when the power switching circuit operates in the low-power mode, the high-performance low-voltage dropout linear regulator is enabled so that the voltage output by the high-performance low-voltage dropout linear regulator is higher than the voltage output by the low-power low-voltage dropout linear regulator, so that the load is powered by the high-performance low-voltage dropout linear regulator, and the power switching circuit is switched from the low-power mode to the normal mode.

[0017] According to some embodiments, before the power switching circuit switches from the normal mode to the low power mode, the load is adjusted so that the power consumption of the load is within the tolerable power consumption range of the low power low dropout linear regulator.

[0018] According to some embodiments, when the power switching circuit operates in the low power consumption mode, the high-performance low voltage drop linear regulator is turned off; and / or when the power switching circuit operates in the normal mode, the load is adjusted so that the load operates in the normal mode.

[0019] According to some embodiments, the low-power low-dropout linear regulator includes a low-power enable input and a low-power adjustment input. When the power switching circuit switches from the normal mode to the low-power mode, the low-power enable input and the low-power adjustment input are enabled so that the voltage output by the low-power low-dropout linear regulator is higher than the voltage output by the high-performance low-dropout linear regulator; and / or the high-performance low-dropout linear regulator includes a high-performance enable input and a high-performance adjustment input. When the power switching circuit switches from the low-power mode to the normal mode, the high-performance enable input and the high-performance adjustment input are enabled so that the voltage output by the high-performance low-dropout linear regulator is higher than the voltage output by the low-power low-dropout linear regulator.

[0020] According to some embodiments, the low power adjustment input is pulled low later than the high performance enable input; and / or the high performance adjustment input is pulled low later than the low power enable input.

[0021] According to an embodiment of the present application, when the working mode is switched, it is ensured that the low-voltage difference linear regulator to be switched can be fully established before the switched low-voltage difference linear regulator is turned off, and the switched low-voltage difference linear regulator is passively turned off and then actively disconnected from the load, thereby ensuring that the load is always in a power supply state when the working mode is switched.

[0022] It should be understood that the foregoing general description and the following detailed description are exemplary only and are not restrictive of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for describing the embodiments. By describing the exemplary embodiments in detail with reference to the drawings, the above and other objectives, features and advantages of the present application will become more apparent.

[0024] Figure 1a A schematic diagram of a LDO output switching solution circuit in the prior art is shown.

[0025] Figure 1b The corresponding LDO output switching scheme principle schematic diagram is shown.

[0026] Figure 2aA circuit diagram of another LDO output switching solution in the prior art is shown.

[0027] Figure 2b The corresponding LDO output switching scheme timing diagram is shown.

[0028] Figure 3 A block diagram of a power switching circuit device according to an exemplary embodiment of the present application is shown.

[0029] Figure 4 A block diagram of another power switching circuit device according to an exemplary embodiment of the present application is shown.

[0030] Figure 5 A schematic diagram of a power switching circuit according to an exemplary embodiment of the present application is shown.

[0031] Figure 6 A schematic diagram of a working mode switching process of a power switching circuit according to an exemplary embodiment of the present application is shown.

[0032] Figure 7 A timing diagram of a working mode switching process of a power switching circuit according to an exemplary embodiment of the present application is shown. DETAILED DESCRIPTION

[0033] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this application will be comprehensive and complete and will fully convey the concepts of the example embodiments to those skilled in the art. In the figures, the same figures show the same or similar parts, and thus their repeated description will be omitted.

[0034] The user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with the relevant laws, regulations and standards of relevant countries and regions, and provide corresponding operation entrances for users to choose to authorize or refuse.

[0035] The described features, structures or characteristics may be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present disclosure. However, those skilled in the art will appreciate that the technical solutions of the present disclosure may be practiced without one or more of these specific details, or other modes, components, materials, devices or operations may be adopted. In these cases, known structures, methods, devices, implementations, materials or operations will not be shown or described in detail.

[0036] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0037] The terms "first", "second", etc. in the specification and claims of this application and the above-mentioned drawings are used to distinguish different objects, rather than to describe a specific order. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions. For example, a process, method, system, product or device that includes a series of steps or units is not limited to the listed steps or units, but optionally includes steps or units that are not listed, or optionally includes other steps or units inherent to these processes, methods, products or devices.

[0038] Figure 1a A schematic diagram of a LDO output switching solution circuit in the prior art is shown. Figure 1b The corresponding LDO output switching scheme principle schematic diagram is shown.

[0039] like Figure 1a and Figure 1b As shown, Figure 1b The output of the low-power LPLDO and the main LDO shown in the figure are connected to an output capacitor CL at the same time. The low-power LPLDO (Low Power Low-dropout Regulator, LDO)) is a normally open circuit. In order to avoid voltage fluctuations when the low-power LPLDO switches with the main LDO, the output voltage VOUT of the low-power LPLDO should be designed to be lower than the output voltage of the main LDO, and a tail current source is designed at its output stage to ensure that the entire low-power LPLDO is also in working state in the normal working mode, so as to avoid startup delay or startup overshoot when the low-power LPLDO switches with the main LDO.

[0040] Figure 1a and Figure 1b The problem with the switching scheme shown is that there is a period when the low-power LPLDO and the main LDO work at the same time during the process of entering the low-power mode. Since the output voltage of the main LDO is higher than the output voltage of the low-power LDO, the low-power LDO is inevitably forced to shut down. At the moment when the main LDO is turned off, the low-power LPLDO begins to really establish. Since the establishment of the low-power LPLDO takes time, at this time Figure 1bThe voltage at VDD will inevitably drop under the action of the load until the low-power LDO starts to work and pulls VDD up. Since the drop amplitude is unpredictable, it may cause a greater hidden danger in the system. The only solution is to make the load capacitor CL large enough so that it can provide enough current to the load before the low-power LPLDO starts to work, so as not to cause VDD to drop too much.

[0041] Figure 2a Another LDO output switching solution circuit diagram of the prior art is shown. Figure 2b The corresponding LDO output switching scheme timing diagram is shown.

[0042] like Figure 2a and Figure 2b As described, when the system shown is in normal mode, the switch S1 is disconnected, the low-power LDO circuit 200 is disconnected from the power supply of the MCU (Microcontroller Unit) circuit, the MCU is powered by the high-performance LDO circuit 100, the switch S2 is closed, the resistor R5 provides the load current for the low-power LDO circuit 200, and the output voltage of the low-power LDO circuit 200 is selected to be its highest voltage, that is, the same output voltage as the high-performance LDO circuit 100. When entering the low power mode, first the switch S1 is closed, and the low power LDO circuit 200 is connected to the power supply of the MCU circuit. At this time, the high performance LDO circuit 100 and the low power LDO circuit 200 work together to ensure that the power supply of the MCU circuit will not be powered off, and then the high performance LDO circuit 100 is turned off, and the low power LDO circuit 200 takes over the power supply of the MCU; when exiting the low power mode and entering the normal mode, the high performance LDO circuit 100 is first turned on. After the high performance LDO circuit 100 is started, the power supply of the MCU is taken over by the high performance LDO circuit 100, the switch S1 is disconnected, and the switch S2 is closed at the same time, the resistor R5 acts as the load of the low power LDO circuit, and the adjustable resistor R3 is also reset to the maximum value so that the output target value of the low power LDO circuit is the same as that of the high performance LDO circuit, and the system completes the switch from the low power mode to the normal mode.

[0043] Figure 2a and Figure 2bThe problem with the switching scheme shown is that the original design intention of the scheme is to make the output target value of the low-power LDO circuit the same as that of the high-performance LDO circuit by adjusting the adjustable resistor R3 in the normal mode, so as to ensure that the high-performance LDO circuit 100 and the low-power LDO circuit 200 work together in the initial stage of entering the low-power mode to ensure that the power supply of the MCU circuit will not be lost, and then shut down the high-performance LDO circuit 100. However, in practice, it is a very difficult problem to ensure that the output voltages of two independent LDOs are exactly the same, especially to ensure that the two output voltages are equal under different process corners, power supply voltages and temperatures.

[0044] For example, if the output voltage of the low-power LDO circuit 200 is lower than the output voltage of the high-performance LDO circuit 100, when the two LDO circuits are used to power the MCU, the low-power LDO circuit must be forced to be turned off; when the high-performance LDO circuit is turned off, the low-power LDO circuit also needs to be re-established, facing the same problem. Figure 1a and Figure 1b Same problem with the scheme shown.

[0045] In order to prevent the risk of the powered load power falling when the two LDO outputs are switched, according to an embodiment of the present application, when the working mode is switched, it is ensured that the LDO to be switched can be fully established before the switched LDO is turned off, and the switched LDO is passively turned off and then actively disconnected from the load.

[0046] For example, when the system switches from normal mode to low power mode, first ensure that the low power LDO is in normal working state, the output voltage of the low power LDO is higher than the output voltage of the high performance LDO, and the high performance LDO is passively turned off. After that, the high performance LDO can be turned off.

[0047] For another example, when the system switches from low power mode to normal mode, first ensure that the high-performance LDO is in normal working state, the output voltage of the high-performance LDO is higher than the output voltage of the low-power LDO, and the low-power LDO is passively turned off. After that, the high-performance LDO can be turned off.

[0048] According to the embodiments of the present application, the use of a large load capacitor CL can be avoided, thereby making the circuit structure of the present application simpler, more reliable, and significantly cost-effective, and having significant practical value.

[0049] The specific embodiments of the present application are described in detail below in conjunction with the accompanying drawings.

[0050] Figure 3 A block diagram of a power switching circuit device according to an exemplary embodiment of the present application is shown. Figure 3The power switching circuit shown includes a high-performance low-dropout linear regulator 101 , a low-power low-dropout linear regulator 103 , and a load 105 .

[0051] According to an embodiment of the present application, the high-performance output end of the high-performance low-voltage difference linear regulator and the low-power output end of the low-power low-voltage difference linear regulator are electrically connected to the load respectively, and the working mode of the power switching circuit includes a normal mode and a low-power mode.

[0052] When the system is running in normal mode, when the high-performance low-voltage dropout linear regulator is used to power the load, when the power switching circuit needs to switch from normal mode to low-power mode, the low-power low-voltage dropout linear regulator is enabled so that the voltage output by the low-power low-voltage dropout linear regulator is higher than the voltage output by the high-performance low-voltage dropout linear regulator, so that the low-power low-voltage dropout linear regulator is used to power the load, and the power switching circuit is switched from normal mode to low-power mode.

[0053] In a specific embodiment, when the voltage output by the low-power low-dropout linear regulator is higher than the voltage output by the high-performance low-dropout linear regulator, the high-performance low-dropout linear regulator will be passively turned off. In practice, when the low-power low-dropout linear regulator is in a normal working state, the high-performance low-dropout linear regulator is actively turned off to reduce system power consumption.

[0054] It should be noted here that when the power switching circuit switches from the normal mode to the low power mode, before enabling the low power low voltage drop linear regulator, it is necessary to adjust the load so that the power consumption of the load is within the tolerable power consumption range of the low power low voltage drop linear regulator.

[0055] When the system is running in a low-power working mode, when the low-performance low-dropout linear regulator is powering the load, when the power switching circuit needs to switch from the low-power mode to the normal mode, the high-performance low-dropout linear regulator is enabled so that the voltage output by the high-performance low-dropout linear regulator is higher than the voltage output by the low-power low-dropout linear regulator, so that the high-performance low-dropout linear regulator is powering the load, and the power switching circuit is switched from the low-power mode to the normal mode.

[0056] In a specific embodiment, when the voltage output by the high-performance low-dropout linear regulator is higher than the voltage output by the low-power low-dropout linear regulator, the low-power low-dropout linear regulator will be passively turned off. In practice, when the high-performance low-dropout linear regulator is in normal working state, the low-power low-dropout linear regulator will be actively turned off to reduce system power consumption.

[0057] When the power switching circuit operates in the normal mode, the load can be adjusted so that the load operates in the normal mode.

[0058] According to some embodiments of the present application, a low-power low-voltage dropout linear regulator includes a low-power enable input and a low-power adjustment input. When the power switching circuit switches from a normal mode to a low-power mode, the low-power enable input and the low-power adjustment input are enabled so that the voltage output by the low-power low-voltage dropout linear regulator is higher than the voltage output by the high-performance low-voltage dropout linear regulator, thereby switching the power switching circuit from a normal mode to a low-power mode.

[0059] According to other embodiments of the present application, the high-performance low-voltage dropout linear regulator includes a high-performance enable input terminal and a high-performance adjustment input terminal. When the power switching circuit switches from a low-power mode to a normal mode, the high-performance enable input terminal and the high-performance adjustment input terminal are enabled so that the voltage output by the high-performance low-voltage dropout linear regulator is higher than the voltage output by the low-power low-voltage dropout linear regulator, thereby switching the power switching circuit from a low-power mode to a normal mode.

[0060] In a specific embodiment, the time when the low power adjustment input terminal is pulled low is later than the time when the high performance enable input terminal is pulled low.

[0061] In some other embodiments, the high performance adjustment input terminal is pulled low later than the low power enable input terminal is pulled low.

[0062] according to Figure 3 In the embodiment shown, when the working mode is switched, it is ensured that the low-voltage difference linear regulator to be switched can be fully established before the switched low-voltage difference linear regulator is turned off, and the switched low-voltage difference linear regulator is passively turned off and then actively disconnected from the load, thereby ensuring that the load is always in a power supply state when the working mode is switched.

[0063] According to the embodiments of the present application, the use of a large load capacitor CL can be avoided, thereby making the circuit structure of the present application simpler, more reliable, and significantly cost-effective, and having significant practical value.

[0064] Figure 4 FIG. 4 shows another block diagram of a power switching circuit device according to an exemplary embodiment of the present application. Figure 4 The power switching circuit shown includes a high-performance low-voltage dropout linear regulator, a low-power low-voltage dropout linear regulator and a load, wherein the high-performance output end of the high-performance low-voltage dropout linear regulator and the low-power output end of the low-power low-voltage dropout linear regulator are electrically connected to the load respectively, and the working modes of the power switching circuit include a normal mode and a low-power mode.

[0065] like Figure 4As shown, the low power low dropout linear regulator includes a low power enable input terminal LDOLP_EN and a low power adjustment input terminal LDOLP_SET. Among them, the low power enable input terminal LDOLP_EN is effective at high level. When the low power adjustment input terminal LDOLP_SET is at a low level, the output voltage of the low power adjustment input terminal is higher.

[0066] When the power switching circuit switches from normal mode to low power mode, the low power low dropout linear regulator is enabled, that is, the low power enable input terminal LDOLP_EN and the low power adjustment input terminal LDOLP_SET are enabled, so that the voltage output by the low power low dropout linear regulator is higher than the voltage output by the high performance low dropout linear regulator.

[0067] like Figure 4 As shown, the high-performance low voltage drop linear regulator includes a high-performance enable input terminal LDO_EN and a high-performance adjustment input terminal LDO_SET. Among them, the high-performance enable input terminal LDO_EN is effective. When the high-performance adjustment input terminal LDO_SET is at a low level, the output voltage of the high-performance low power adjustment input terminal is higher.

[0068] When the power switching circuit switches from low power mode to normal mode, the high performance low voltage dropout linear regulator is enabled, that is, the high performance enable input terminal and the high performance adjustment input terminal are enabled, so that the voltage output by the high performance low voltage dropout linear regulator is higher than the voltage output by the low power low voltage dropout linear regulator.

[0069] When switching the working mode, in order to ensure that the low-voltage dropout linear regulator to be switched to can be fully established before the switched low-voltage dropout linear regulator is turned off, the time when the low-power adjustment input terminal is pulled low needs to be later than the time when the high-performance enable input terminal is pulled low, and the time when the high-performance adjustment input terminal is pulled low is later than the time when the low-power enable input terminal is pulled low.

[0070] According to an embodiment of the present application, when the power switching circuit switches from a normal mode to a low power mode, in order to make the output voltage of the low power low voltage dropout linear regulator higher than the output voltage of the high performance low voltage dropout linear regulator, when the low power adjustment input terminal LDOLP_SET is at a high level, the output voltage of the low power low voltage dropout linear regulator is ΔV1 higher than the nominal voltage of the output of the high performance low voltage dropout linear regulator when the high performance adjustment input terminal LDO_SET is at a low level, wherein ΔV1 is greater than zero.

[0071] According to other embodiments, when the power switching circuit switches from a low power mode to a normal mode, in order to make the output voltage of the high-performance low-dropout linear regulator higher than the output voltage of the low-power low-dropout linear regulator, when the high-performance adjustment input terminal LDO_SET is at a high level, the output voltage of the high-performance low-dropout linear regulator is ΔV2 higher than the nominal output voltage of the low-power low-dropout linear regulator when the low-power adjustment input terminal LDO_SET is at a low level, wherein ΔV2 is greater than zero.

[0072] In a specific embodiment, the signals of the enable input terminal and the adjustment input terminal of the low-power low-dropout linear regulator and the high-performance low-dropout linear regulator are both from the external digital logic circuit.

[0073] Figure 5 A schematic diagram of a power switching circuit according to an exemplary embodiment of the present application is shown. Figure 5 As shown, Figure 5 The power switching circuit shown includes a high-performance low-dropout linear regulator (or high-performance LDO), a low-power low-dropout linear regulator (or low-performance LDO) and a load, the high-performance output end of the high-performance low-dropout linear regulator and the low-power output end of the low-power low-dropout linear regulator are electrically connected to the load respectively, and the working modes of the power switching circuit include a normal mode and a low-power mode.

[0074] like Figure 5 As shown in the figure, LDO_EN is the enable input terminal of the high-performance LDO, and resistors R1 and R2 form the feedback network of the high-performance LDO. The ratio of resistors R1 and R2 determines the output voltage of the high-performance LDO. Resistor R1 is the high-performance adjustment input terminal of the high-performance LDO. By adjusting resistor R1, the output voltage of the high-performance LDO can be changed.

[0075] LDOLP_EN is the enable input terminal of the low power LDO. Resistors R3 and R4 form the feedback network of the low power LDO. The ratio of resistors R3 and R4 determines the output voltage of the low power LDO. Resistor R3 is the high performance adjustment input terminal of the low power LDO. By adjusting resistor R3, the output voltage of the low power LDO can be changed.

[0076] according to Figure 5 The illustrated embodiment can avoid the use of a large load capacitor CL, thereby making the circuit structure of the present application more concise, more reliable, and more cost-effective, thus having significant practical value.

[0077] Figure 6 FIG. 1 shows a schematic diagram of a working mode switching process of a power switching circuit according to an exemplary embodiment of the present application. Figure 6As shown, when the system (or the power switching circuit) operates in the normal mode, the high-performance LDO (or the high-performance low-dropout linear regulator) supplies power to the load.

[0078] When the power switching circuit switches from the normal mode to the low power mode, unnecessary loads are turned off so that the load power consumption is within the power consumption range that the low power LDO (or low power low dropout linear regulator) can bear.

[0079] After that, the low power LDO is turned on (or enabled) to supply power to the load. The high performance LDO will be passively turned off and the system will enter low power mode.

[0080] When the power switching circuit switches from low power mode to normal mode, the high performance LDO is turned on (enabled), and the load is powered by the high performance LDO. At this time, the necessary loads can be turned on to make the system run in normal mode, and the low power LDO is passively turned off.

[0081] This cycle repeats itself, and the power switching circuit switches the working mode.

[0082] Figure 7 A timing diagram of the working mode switching process of a power switching circuit according to an exemplary embodiment of the present application is shown below. Figure 4 and Figure 7 , a working mode switching process of a power switching circuit according to an exemplary embodiment of the present application is specifically described.

[0083] like Figure 4 and Figure 7 As shown, from T0 to T1, the system is in normal mode, LDO_EN = "1", LDO_SET = "0", LDOLP_EN = "0", LDOLP_SET = "0" or "1". The load is powered by the high-performance LDO, and the low-power LDO is turned off. At this time, the system runs in normal mode, and the load power consumption is large.

[0084] Since LDO_EN=“0”, the low power LDO is turned off, and LDOLP_SET being “0” or “1” will not affect the output voltage of the low power LDO. Therefore, LDOLP_SET can be either “0” or “1”.

[0085] If the system plans to enter low power mode, then between T0 and T1, first turn off unnecessary loads to make the power consumption on the load within the tolerable range of the low power LDO, and then make LDOLP_EN = "1" and LDOLP_SET = "1" at T1 to enable the low power LDO. As the low power LDO is established, when the output voltage of the low power LDO is higher than the output voltage of the high performance LDO, the high performance LDO is passively turned off and the load is powered by the low power LDO.

[0086] After the low-power LDO is established, at time T2, LDO_EN = "0" and LDOLP_SET = "0", and the high-performance LDO is actively turned off. The low-power LDO output returns to a relatively low voltage to continue to supply power to the load. In this way, the entire system completes the switch from normal mode to low-power mode.

[0087] At time T3, LDO_EN = "1" and LDO_SET = "1" are set to enable the high-performance LDO. As the high-performance LDO is established, when the voltage output by the high-performance LDO is higher than the output voltage of the low-power LDO, the low-power LDO is passively turned off, and the load is powered by the high-performance LDO. At this time, the necessary loads are turned on to return the system to normal mode.

[0088] At time T4, LDOLP_EN = "0" and LDO_SET = "0", the low-power LDO is actively turned off, and the high-performance LDO output returns to a relatively low voltage to continue to supply power to the load. In this way, the entire system completes the switch from low-power mode to normal mode.

[0089] It should be noted that during the entire working mode switching process, as long as LDO_EN = "0", LDO_SET can be set to "1" at any time; similarly, as long as LDOLP_EN = "0", LDOLP_SET can be set to "1" at any time; the process of LDO_SET and LDOLP_SET being set to "1" does not need to be strictly operated according to the above timing diagram.

[0090] When switching the working mode, in order to ensure that the low-dropout linear regulator to be switched to can be fully established before the switched low-dropout linear regulator is turned off, the time when LDOLP_SET is pulled low is not earlier than the time when LDO_EN is pulled low, and the time when LDO_SET is pulled low is not earlier than the time when LDOLP_EN is pulled low.

[0091] According to some embodiments, when the low power enable input terminal is in a low level state, the state of the low power adjustment input terminal includes a high level state or a low level state.

[0092] For example, if the static power consumption of the low power LDO is not a concern in normal operation mode, the low power LDO can be set to be normally on or off.

[0093] The embodiments of the present application are described in detail above. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and its core idea of ​​the present application. At the same time, changes or deformations made by those skilled in the art based on the ideas of the present application, the specific implementation methods and the scope of application of the present application, all belong to the scope of protection of the present application. In summary, the content of this specification should not be construed as a limitation on the present application.

Claims

1. A method for switching working modes of a power switching circuit, characterized in that: The power switching circuit includes a high-performance low-dropout linear regulator, a low-power low-dropout linear regulator, and a load, wherein the high-performance output end of the high-performance low-dropout linear regulator and the low-power output end of the low-power low-dropout linear regulator are electrically connected to the load respectively, and the working mode of the power switching circuit includes a normal mode and a low-power mode. The method includes: When the power switching circuit switches from the normal mode to the low power mode, the low power low voltage dropout linear regulator is enabled, so that the voltage output by the low power low voltage dropout linear regulator is higher than the voltage output by the high performance low voltage dropout linear regulator, so that the low power low voltage dropout linear regulator supplies power to the load; When the power switching circuit switches from the low power consumption mode to the normal mode, the high performance low voltage dropout linear regulator is enabled so that the voltage output by the high performance low voltage dropout linear regulator is higher than the voltage output by the low power consumption low voltage dropout linear regulator, thereby the high performance low voltage dropout linear regulator is used to power the load.

2. The working mode switching method according to claim 1, characterized in that: When the power switching circuit switches from the normal mode to the low power mode, before enabling the low power low dropout linear regulator, the method includes: The load is adjusted so that the power consumption of the load is within a tolerable power consumption range of the low-power low-dropout linear regulator.

3. The working mode switching method according to claim 1, characterized in that: When the power switching circuit operates in the low power consumption mode, turning off the high performance low voltage drop linear regulator; and / or When the power switching circuit operates in the normal mode, the low power consumption low voltage drop linear regulator is turned off.

4. The working mode switching method according to claim 1, characterized in that: The low power consumption low voltage drop linear regulator comprises a low power consumption enable input terminal and a low power consumption adjustment input terminal. When the power switching circuit switches from the normal mode to the low power mode, the low power low voltage drop linear regulator is enabled, including: enabling the low power enable input terminal and the low power adjustment input terminal so that the voltage output by the low power low dropout linear regulator is higher than the voltage output by the high performance low dropout linear regulator; and / or The high-performance low-dropout linear regulator includes a high-performance enable input terminal and a high-performance adjustment input terminal. When the power switching circuit switches from the low power consumption mode to the normal mode, the high performance low voltage drop linear regulator is enabled, including: The high-performance enable input terminal and the high-performance adjustment input terminal are enabled so that the voltage output by the high-performance low-dropout linear regulator is higher than the voltage output by the low-power low-dropout linear regulator.

5. The working mode switching method according to claim 4, characterized in that: The time when the low power consumption adjustment input terminal is pulled low is later than the time when the high performance enable input terminal is pulled low; and / or The time when the high-performance adjustment input terminal is pulled low is later than the time when the low-power enable input terminal is pulled low.

6. The working mode switching method according to claim 4, characterized in that: When the low power consumption enabling input terminal is in a low level state, the state of the low power consumption adjusting input terminal includes a high level state or a low level state.

7. A power switching circuit, characterized in that: The power switching circuit includes a high-performance low-dropout linear regulator, a low-power low-dropout linear regulator and a load, wherein the high-performance output end of the high-performance low-dropout linear regulator and the low-power output end of the low-power low-dropout linear regulator are electrically connected to the load respectively, and the working mode of the power switching circuit includes a normal mode and a low-power mode. When the power switching circuit operates in the normal mode, the low-power low-voltage dropout linear regulator is enabled, so that the voltage output by the low-power low-voltage dropout linear regulator is higher than the voltage output by the high-performance low-voltage dropout linear regulator, so that the load is powered by the low-power low-voltage dropout linear regulator, and the power switching circuit is switched from the normal mode to the low-power mode; When the power switching circuit operates in low power consumption mode, the high-performance low voltage dropout linear regulator is enabled so that the voltage output by the high-performance low voltage dropout linear regulator is higher than the voltage output by the low power consumption low voltage dropout linear regulator, so that the load is powered by the high-performance low voltage dropout linear regulator, and the power switching circuit is switched from the low power consumption mode to the normal mode.

8. The power switching circuit according to claim 7, characterized in that: Before the power switching circuit switches from the normal mode to the low power mode, the load is adjusted so that the power consumption of the load is within the tolerable power consumption range of the low power low dropout linear regulator.

9. The power switching circuit according to claim 7, characterized in that: When the power switching circuit operates in the low power consumption mode, turning off the high performance low voltage drop linear regulator; and / or When the power switching circuit operates in the normal mode, the low power consumption low voltage drop linear regulator is turned off.

10. The power switching circuit according to claim 7, characterized in that: The low power consumption low voltage drop linear regulator comprises a low power consumption enable input terminal and a low power consumption adjustment input terminal. When the power switching circuit switches from the normal mode to the low power mode, the low power enable input terminal and the low power adjustment input terminal are enabled so that the voltage output by the low power low dropout linear regulator is higher than the voltage output by the high performance low dropout linear regulator; and / or The high-performance low-voltage dropout linear regulator includes a high-performance enable input terminal and a high-performance adjustment input terminal. When the power switching circuit switches from the low-power mode to the normal mode, the high-performance enable input terminal and the high-performance adjustment input terminal are enabled so that the voltage output by the high-performance low-voltage dropout linear regulator is higher than the voltage output by the low-power low-voltage dropout linear regulator.

11. The power switching circuit according to claim 10, characterized in that: The time when the low power consumption adjustment input terminal is pulled low is later than the time when the high performance enable input terminal is pulled low; and / or The time when the high-performance adjustment input terminal is pulled low is later than the time when the low-power enable input terminal is pulled low.

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