A Regulatable Wide-Adaptation MOSFET Turn-Off Gate Driving Circuit and Driving Method

Abstract

A controllable wide - adaptation MOSFET turn - off gate drive circuit and drive method, which relates to the field of power electronics. The drive circuit matches the parasitic parameters of the power MOSFET to be controlled through parameter configuration to improve applicability; during the turn - off process of the power MOSFET to be controlled, the circuit controls the gate voltage to rapidly decrease when it is higher than the Miller plateau stage, remain at the Miller plateau voltage during the Miller plateau, linearly decrease from the Miller plateau to the threshold voltage stage, and rapidly decrease below the threshold voltage. By continuously and finely controlling the gate voltage, the regulation of the drain - source side voltage - current trajectory is realized, solving the problems that the existing turn - off drive circuit is difficult to finely regulate the gate voltage during the turn - off process of the power MOSFET device, unable to separately and finely regulate the drain - source side voltage - current trajectory of the power MOSFET, difficult to simultaneously meet the goals of low voltage overshoot and low turn - off loss during the turn - off process, and difficult to achieve the full - limit application of the power MOSFET device, resulting in difficulty in meeting the high - power - density requirements of power electronic devices.

Description

Technical Field

[0001] The present invention relates to the field of power electronics, and particularly to an adjustable wide-adaptation MOSFET turn-off gate drive circuit and a drive method. Background Art

[0002] During the turn-off process of a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor), it is necessary to convert the turn-off digital signal into a turn-off analog signal suitable for the power device through gate drive and apply it between the gate and source (hereinafter referred to as "gate-source") of the power MOSFET to complete the turn-off action. During the turn-off process of the power MOSFET, there is a contradiction between the voltage overshoot caused by the rising drain-source (hereinafter referred to as "drain-source") voltage and the turn-off loss. It is necessary to adjust the gate signal trajectory to change the drain-source side voltage and current trajectory so that the power MOSFET can be applied to the limit and meet the requirements of power electronic devices.

[0003] Currently, most existing drive circuits use a two-level turn-off method in cooperation with a gate resistor to adjust the voltage and current trajectory of the power MOSFET device during the turn-off process. It is impossible to finely and continuously regulate the gate voltage during the turn-off process, and it is impossible to separately regulate the drain-source side voltage and current trajectory of the power MOSFET. It is difficult to simultaneously meet the goals of low voltage overshoot and low turn-off loss during the turn-off process, and it is difficult to meet the high power density requirements of power electronic devices. Summary of the Invention

[0004] The present invention is to solve the problem that the existing turn-off drive circuit cannot finely and continuously regulate the gate voltage during the turn-off process of the power MOSFET device, resulting in the inability to separately regulate the drain-source side voltage and current trajectory of the power MOSFET, making it difficult to simultaneously meet the goals of low voltage overshoot and low turn-off loss during the turn-off process, making it difficult to apply the power MOSFET to the limit, and making it difficult to meet the high power density requirements of power electronic devices. A kind of adjustable wide-adaptation MOSFET turn-off gate drive circuit and a drive method are provided.

[0005] The technical solution adopted by the present invention is:

[0006] An adjustable wide-adaptation MOSFET turn-off gate drive circuit, which is applicable to power electronic devices using power MOSFET transistors. The power electronic devices include a power converter and an inverter. The drive circuit drives the power MOSFET (09) to be controlled through the port Vgate. The drive circuit includes:

[0007] Current mirror module (01), parameter configuration module (02), maintenance module (03), conduction module (04), control module (05), first discharge module (06), second discharge module (07), external gate resistor (08), nodes net1 to net6, power supply VDD, first turn-off enable signal (Vctrl1), second turn-off enable (Vctrl2), third turn-off enable signal (Vctrl3), fourth turn-off enable signal (Vctrl4), fifth turn-off enable (Vctrl5), sixth turn-off enable (Vctrl6), ground (GND);

[0008] The current mirror module (01) includes a first PMOS transistor (MP1), a second PMOS transistor (MP2), a third PMOS transistor (MP3), and a fourth PMOS transistor (MP4); the drain and gate of the third PMOS transistor (MP3) and the gate of the fourth PMOS transistor (MP4) are all connected to node net1, the source of the third PMOS transistor (MP3) is connected to the drain of the first PMOS transistor (MP1), the drain of the fourth PMOS transistor (MP4) is connected to node net2, the source of the fourth PMOS transistor (MP4) is connected to the gate of the first PMOS transistor (MP1), the gate of the second PMOS transistor (MP2), and the drain of the second PMOS transistor (MP2), and the sources of the first PMOS transistor (MP1) and the second PMOS transistor (MP2) are both connected to the power supply VDD;

[0009] The parameter configuration module (02) includes a first NMOS transistor (MN1), a first resistor (R1), a second resistor (R2), and a first capacitor (C1); the gate of the first NMOS transistor (MN1) is connected to the first turn-off enable signal (Vctrl1), the drain of the first NMOS transistor (MN1) is connected to node net1, and the source is connected to the second resistor (R2) and the first capacitor (C1) through the first resistor (R1), and one end of the second resistor (R2) and the first capacitor (C1) is connected to the source of the first NMOS transistor (MN1) through the first resistor (R1), and the other end is connected to the ground (GND);

[0010] The maintenance module (03) includes a second NMOS transistor (MN2), a third NMOS transistor (MN3), a fourth NMOS transistor (MN4), a first diode (D1), and a third resistor (R3); the anode of the first diode (D1) is connected to node net2, the cathode is connected to node net3, node net3 is connected to the drain of the second NMOS transistor (MN2) and the gate of the third NMOS transistor (MN3), the source of the second NMOS transistor (MN2) is connected to ground (GND), its gate and the source of the third NMOS transistor (MN3) are connected to node net4, the drain of the third NMOS transistor (MN3) is connected to the power supply VDD, the source of the fourth NMOS transistor (MN4) is connected to node net4, the gate is connected to the second turn-off enable (Vctrl2), and the drain is connected to the gate of the eleventh NSMO transistor (MN11) in the second current discharging module (07); node net4 is connected to ground (GND) through the third resistor (R3);

[0011] The conduction module (04) includes a fifth NMOS transistor (MN5), a second diode (D2), a fourth resistor (R4), and a fifth resistor (R5). Among them, the drain of the fifth NMOS transistor (MN5) is connected to the power supply VDD, the gate is connected to node net2, and the source is connected to node net5. The anode of the second diode (D2) is connected to node net2, and the cathode is connected to node net5. Node net5 is connected to node net6 through the fourth resistor (R4), and node net6 is connected to ground (GND) through the fifth resistor (R5);

[0012] The control module (05) includes a sixth NMOS transistor (MN6), a seventh NMOS transistor (MN7), and a sixth resistor (R6). The drain of the sixth NMOS transistor (MN6) is connected to the control power supply VCC, the gate is connected to the third turn-off enable signal (Vctrl3), and the source of the sixth NMOS transistor (MN6) is connected to node net6. The drain of the seventh NMOS transistor (MN7) is connected to node net6 through the sixth resistor (R6), the gate is connected to the fourth turn-off enable signal (Vctrl4), and the source is connected to ground (GND);

[0013] The first current discharging module (06) includes an eighth NMOS transistor (MN8) and a ninth NMOS transistor (MN9). The drain of the eighth NMOS transistor (MN8) is connected to the gate of the power MOSFET to be controlled (09) through port Vgate, its gate is connected to the fifth turn-off enable (Vctrl5), and its source is connected to the drain of the ninth NMOS transistor (MN9). The drain of the ninth NMOS transistor (MN9) is connected to the source of the eighth NMOS transistor (MN8), its gate is connected to the sixth turn-off enable (Vctrl6), and its source is connected to ground (GND);

[0014] The second discharge module (07) includes a tenth NMOS transistor (MN10) and an eleventh NMOS transistor (MN11). The drain of the tenth NMOS transistor (MN10) is connected to the gate of the power MOSFET (09) to be controlled through port Vgate, its gate is connected to node net6, and its source is connected to the drain of the eleventh NMOS transistor (MN11). The drain of the eleventh NMOS transistor (MN11) is connected to the source of the tenth NMOS transistor (MN10), its gate is connected to the drain of the fourth NMOS transistor (MN4) in the maintaining module (03), and its source is connected to the ground (GND).

[0015] The external gate resistor (08) is connected between port Vgate and the gate of the power MOSFET (09) to be controlled.

[0016] Further, the current mirror module (01) is connected to the parameter configuration module (02) at node net1, and is connected to the maintaining module (03) and the conduction module (04) at node net2;

[0017] The parameter configuration module (02) is connected to the current mirror module (01) at node net1, and its input is the first turn-off enable signal (Vctrl1);

[0018] The maintaining module (03) is connected to the current mirror module (01) at node net2, its input is the second turn-off enable signal (Vctrl2), and it is connected to the gate of the eleventh NMOS transistor (MN11) in the second discharge module (07) through the fourth NMOS (MN4);

[0019] The conduction module (04) is connected to the current mirror module (01) at node net2, and is connected to the control module (05) at node net6;

[0020] The control module (05) is connected to the conduction module (04) at node net6, its input terminals are the third turn-off enable signal (Vctrl3) and the fourth turn-off enable signal (Vctrl4), and it is connected to the gate of the tenth NMOS transistor (MN10) in the second discharge module (07);

[0021] The input of the first discharge module (06) is the fifth turn-off enable signal (Vctrl5) and the sixth turn-off enable signal (Vctrl6), and it is connected to the second discharge module (07) at port Vgate;

[0022] The second discharge module (07) is connected to the drain of the fourth NMOS transistor (MN4) in the maintaining module (03).

[0023] Further, the current mirror module (01) is configured to copy the current i1 in the path connected to the parameter configuration module (02) to the line connected to the maintenance module (03) during the pre-turn-off stage, form the current i2, and boost the voltage at the node net2 during the turn-off process of the power MOSFET to be controlled (09), so that the fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel during the pre-turn-off stage, and further enables the conduction module (04) to operate.

[0024] The parameter configuration module (O2) is configured to generate the current i1 in the line where the first NMOS transistor (MN1) is located during the pre-turn-off stage of the power MOSFET to be controlled (09) according to the first turn-off enable signal (Vctrl1).

[0025] The maintenance module (O3) is configured to, according to the current i2 copied by the current mirror module (01) during the pre-turn-off stage, first boost the voltage at the node net3, then boost the voltage at the node net4 during the pre-turn-off stage of the power MOSFET to be controlled (09). Subsequently, the voltage at the node net4 is transmitted to the gate of the eleventh NMOS transistor (MN11) in the second current discharge module (07) through the channel of the fourth NMOS transistor (MN4) by the second turn-off enable signal (Vctrl2), so that the eleventh NMOS transistor (MN11) establishes a channel.

[0026] The conduction module (04) is configured to enable the fifth NMOS transistor (MN5) to establish a channel under the influence of the voltage at the node net2 during the pre-turn-off stage of the power MOSFET to be controlled (09). At the same time, the voltage at the node net2 is transmitted to the node net5 through the second diode (D2), and the voltage at the node net5 is pulled down to the node net6 through the voltage division of the fourth resistor (R4) and the fifth resistor (R5), and is transmitted to the gate of the tenth NMOS transistor (MN10) in the second current discharge module (07), so that the tenth NMOS transistor (MN10) establishes a channel.

[0027] The control module (05) is configured to be controlled by the third turn-off enable signal (Vctrl3) and the fourth turn-off enable signal (Vctrl4) during the turn-off stage of the power MOSFET to be controlled (09), and change the voltages at the node net6 and the gate of the tenth NMOS transistor (MN10) in the second current discharge module (07).

[0028] The first current discharge module (06) is configured to be controlled by the fifth turn-off enable signal (Vctrl5) and the sixth turn-off enable signal (Vctrl6) during the turn-off process of the power MOSFET to be controlled (09), so that the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) establish channels, thereby discharging current through the port Vgate.

[0029] The second current discharge module (07) is used to obtain a channel establishment voltage for the eleventh NMOS transistor (MN11) from node net4 through the fourth NMOS transistor (MN4) during the pre-turn-off stage of the power MOSFET (09) to be controlled. During the turn-off stage of the power MOSFET (09) to be controlled, the channel opening degree of the tenth NMOS transistor (MN10) is controlled by node net6, changing the current-carrying capacity of the tenth NMOS transistor (MN10) and the eleventh NMOS transistor (MN11) in the second current discharge module (07), so that the second current discharge module (07) discharges current from port Vgate.

[0030] A driving method based on an adjustable wide-adaptation MOSFET turn-off gate driving circuit, the method comprising:

[0031] A method for, during the pre-turn-off stage, proportionally copying the current i1 in the path connected to the parameter configuration module (02) to the line connected to the maintenance module (03) to form a current i2, and raising the voltage at node net2 during the turn-off process of the power MOSFET (09) to be controlled, so that the fifth NMOS transistor (MN5) in the conduction module (04) establishes a channel during the pre-turn-off stage, thereby enabling the conduction module (04) to operate;

[0032] A method for generating a current i1 in the line where the first NMOS transistor (MN1) is located during the pre-turn-off stage of the power MOSFET (09) to be controlled according to the first turn-off enable signal (Vctrl1);

[0033] A method for, according to the current i2 copied by the current mirror module (01) during the pre-turn-off stage, first raising the voltage at node net3, then raising the voltage at node net4 during the pre-turn-off stage of the power MOSFET (09) to be controlled. Subsequently, the voltage at node net4 is transmitted to the gate of the eleventh NMOS transistor (MN11) in the second current discharge module (07) through the channel of the fourth NMOS transistor (MN4) by the second turn-off enable signal (Vctrl2), enabling the eleventh NMOS transistor (MN11) to establish a channel;

[0034] A method for, during the pre-turn-off stage of the power MOSFET (09) to be controlled, enabling the fifth NMOS transistor (MN5) to establish a channel under the influence of the voltage at node net2. At the same time, the voltage at node net2 is transmitted to node net5 through the second diode (D2), and the voltage at node net5 is pulled down to node net6 through voltage division by the fourth resistor (R4) and the fifth resistor (R5) and transmitted to the gate of the tenth NMOS transistor (MN10) in the second current discharge module (07), enabling the tenth NMOS transistor (MN10) to establish a channel;

[0035] A method for controlling the gate voltage of the tenth NMOS transistor (MN10) in node net6 and the second current discharge module (07) during the turn-off stage of the power MOSFET (09) to be controlled, which is controlled by the third turn-off enable signal (Vctrl3) and the fourth turn-off enable signal (Vctrl4);

[0036] A method for enabling the eighth NMOS transistor (MN8) and the ninth NMOS transistor (MN9) to establish channels during the turn-off process of the power MOSFET (09) to be controlled, which is controlled by the fifth turn-off enable signal (Vctrl5) and the sixth turn-off enable signal (Vctrl6), thereby discharging current through port Vgate;

[0037] A method for the eleventh NMOS transistor (MN11) to obtain a channel establishment voltage from node net4 through the fourth NMOS transistor (MN4) during the pre-turn-off stage of the power MOSFET (09) to be controlled, and for the node net6 to control the channel opening degree of the tenth NMOS transistor (MN10) during the turn-off stage of the power MOSFET (09) to be controlled, so as to change the current-carrying capabilities of the tenth NMOS transistor (MN10) and the eleventh NMOS transistor (MN11) in the second current discharge module (07), enabling the second current discharge module (07) to discharge current from port Vgate.

[0038] Furthermore, the first resistor (R1), the second resistor (R2), and the first capacitor (C1) in the parameter configuration module (02) are configured according to the parasitic parameters of the power MOSFET (09) to be controlled. The voltage waveforms of node net2 and node net6 in the current mirror module (01) are specifically represented as follows:

[0039] During the turn-off process of the power MOSFET (09) to be controlled, when the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller plateau (Vmiller), the voltage of node net2 appears as a voltage peak;

[0040] During the turn-off process of the power MOSFET (09) to be controlled, the voltage of node net6 is synchronous with the voltage of node net2. When the gate voltage of the power MOSFET (09) to be controlled is higher than the Miller plateau (Vmiller), the voltage of node net6 appears as a voltage peak.

[0041] Further, the voltage waveform of node net6 is specifically represented as follows: During the turn-off process of the power MOSFET to be controlled (09), when the gate voltage of the power MOSFET to be controlled (09) drops to the threshold voltage (Vth), the third turn-off enable signal (Vctrl3) and the fourth turn-off enable signal (Vctrl4) in the control module (05) synchronously control the sixth NMOS transistor (MN6) and the seventh NMOS transistor (MN7) to turn on, pulling up the voltage of node net6. At this time, the voltage of node net6 is pulled up and remains unchanged.

[0042] Further, the voltage waveform at the output terminal (Vgate) during the turn-off process of the power MOSFET to be controlled (09) is specifically represented as follows:

[0043] First stage: When the gate voltage of the power MOSFET to be controlled (09) is higher than the Miller plateau (Vmiller) voltage, the gate voltage rapidly drops to the Miller plateau (Vmiller) voltage;

[0044] Second stage: When the gate voltage of the power MOSFET to be controlled (09) is at the Miller plateau (Vmiller) voltage, the gate voltage remains at the Miller plateau (Vmiller) voltage;

[0045] Third stage: When the gate voltage of the power MOSFET to be controlled (09) is lower than the Miller plateau (Vmiller) voltage but higher than the threshold voltage (Vth), the gate voltage slowly decreases linearly;

[0046] Fourth stage: When the gate voltage of the power MOSFET to be controlled (09) is lower than the threshold voltage (Vth), the gate voltage rapidly drops to zero.

[0047] Further, during the turn-off process of the power MOSFET to be controlled (09), the gate voltage waveform of the power MOSFET to be controlled (09) is affected by the resistance and capacitance values of the first resistor (R1), the second resistor (R2), and the first capacitor (C1) in the parameter configuration module (02). The specific representation is as follows:

[0048] When the resistance and capacitance values of the second resistor (R2) and the first capacitor (C1) remain unchanged, the larger the resistance value of the first resistor (R1), the slower the gate voltage of the power MOSFET to be controlled (09) drops during the stage higher than the Miller plateau (Vmiller), that is, the smaller the absolute value of the slope of the gate voltage drop in this stage, and the longer the gate voltage stays at the Miller plateau (Vmiller) voltage;

[0049] When the resistance and capacitance values of the first resistor (R1) and the first capacitor (C1) remain unchanged, the larger the resistance value of the second resistor (R2), the shorter the time for the gate voltage of the power MOSFET to be controlled (09) to be lower than the Miller plateau (Vmiller) voltage. As a result, the turn-off time of the power MOSFET to be controlled (09) is shorter.

[0050] When the resistance values of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the slower the decline of the gate voltage of the power MOSFET to be controlled (09) during the stage higher than the Miller plateau (Vmiller), that is, the smaller the absolute value of the slope of the gate voltage decline during this stage.

[0051] Furthermore, during the turn-off process of the power MOSFET to be controlled (09), the waveforms of the drain-source current and drain-source voltage of the power MOSFET to be controlled (09) are specifically represented as follows:

[0052] When the resistance and capacitance values of the second resistor (R2) and the first capacitor (C1) remain unchanged, the larger the resistance value of the first resistor (R1), the slope of the drain-source voltage of the power MOSFET to be controlled (09) remains unchanged, and the absolute value of the slope of the drain-source current of the power MOSFET to be controlled (09) is larger;

[0053] When the resistance and capacitance values of the first resistor (R1) and the first capacitor (C1) remain unchanged, the larger the resistance value of the second resistor (R2), the smaller the slope of the drain-source voltage of the power MOSFET to be controlled (09), and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled (09);

[0054] When the resistance values of the first capacitor (R1) and the second resistor (R2) remain unchanged, the smaller the capacitance value of the first capacitor (C1), the smaller the slope of the drain-source voltage of the power MOSFET to be controlled (09), and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled (09).

[0055] Furthermore, during the turn-off process of the power MOSFET to be controlled (09), the drive circuit does not need to introduce the drain-source side information of the power MOSFET to be controlled (09), and only uses the change characteristics of the transconductance capacitance of the power MOSFET to be controlled (09) to regulate the gate voltage of the power MOSFET to be controlled (09), and finally completes the regulation of the drain-source voltage and current trajectories of the power MOSFET to be controlled (09); the drive circuit separately regulates the slopes of the drain-source voltage and drain-source current of the power MOSFET to be controlled (09) through the resistance and capacitance parameters in the parameter configuration module.

[0056] Beneficial effects: From the perspective of the power MOSFET turn-off mechanism, the present invention proposes a controllable wide-adaptation MOSFET turn-off gate drive circuit and a drive method, which continuously and finely regulate the gate voltage during the turn-off process of the power MOSFET, and realize the individual and fine regulation of the drain-source voltage and current trajectories during the turn-off process, so as to achieve the purpose of the power MOSFET having low voltage overshoot and low turn-off loss during the turn-off process, and realize the full-limited application of the power MOSFET. At the same time, the controllable wide-adaptation MOSFET turn-off gate drive circuit and drive method proposed by the present invention can adjust and configure parameters according to the parasitic parameters of the power MOSFET to adapt to power MOSFETs with different parasitic parameters and improve the applicability. In addition, the controllable wide-adaptation MOSFET turn-off gate drive circuit and drive method proposed by the present invention can realize the individual regulation of the drain-source voltage and drain-source current trajectories only by controlling the gate of the power MOSFET, without introducing high-voltage information on the drain-source side, reducing the insulation requirements and increasing the power density.

[0057] Compared with the prior art, the present invention has the following advantages:

[0058] 1. During the turn-off process of the power MOSFET to be controlled, by continuously and finely controlling the gate voltage of the power MOSFET to be controlled, the individual and fine regulation of the drain-source voltage and current trajectories of the power MOSFET to be controlled is realized, so that the power MOSFET has the characteristics of low voltage overshoot and low turn-off loss during the turn-off process, and the full-limited application of the power MOSFET is realized;

[0059] 2. By matching the parasitic parameters of the power MOSFET to be controlled through the parameter configuration module, the applicability of the circuit is improved;

[0060] 3. Avoid the introduction of high-voltage information on the drain-source side of the power MOSFET to be controlled, reduce the insulation requirements and increase the power density.

[0061] The present invention solves the problems that the existing drive circuit cannot continuously and finely regulate the gate voltage during the turn-off process of the power MOSFET device, cannot individually and finely regulate the drain-source voltage and current trajectories of the power MOSFET, it is difficult to simultaneously meet the goals of low voltage overshoot and low turn-off loss during the turn-off process, it is difficult to realize the full-limited application of the power MOSFET, and it is difficult to meet the high power density requirements of power electronic devices. Description of the Drawings

[0062] Figure 1 It is a topological schematic diagram of a controllable wide-adaptation MOSFET turn-off gate drive circuit;

[0063] Figure 2 It is a circuit schematic diagram of a controllable wide-adaptation MOSFET turn-off gate drive circuit;

[0064] Figure 3 For a controllable wide - adaptive MOSFET turn - off gate - driving circuit, waveforms of node net2, node net6, and the gate voltage of the power MOSFET to be controlled;

[0065] Figure 4 For a controllable wide - adaptive MOSFET turn - off gate - driving circuit, waveforms of the current of the first current - discharging module and the gate voltage of the power MOSFET to be controlled;

[0066] Figure 5 For the waveform of the gate voltage during the turn - off process of the power MOSFET to be controlled;

[0067] Figure 6 For the waveform of the gate voltage during the turn - off process of the power MOSFET to be controlled under the condition of the change of the first resistor in the parameter configuration module;

[0068] Figure 7 Schematic diagram of the waveform of the gate voltage during the turn - off process of the power MOSFET to be controlled under the condition of the change of the second resistor in the parameter configuration module;

[0069] Figure 8 For the waveform of the gate voltage during the turn - off process of the power MOSFET to be controlled under the condition of the change of the first capacitor in the parameter configuration module;

[0070] Figure 9 Waveforms of the drain - source voltage and drain - source current during the turn - off process of the power MOSFET to be controlled under the condition of the change of the first resistor in the parameter configuration module;

[0071] Figure 10 Waveforms of the drain - source voltage and drain - source current during the turn - off process of the power MOSFET to be controlled under the condition of the change of the second resistor in the parameter configuration module;

[0072] Figure 11 Waveforms of the drain - source voltage and drain - source current during the turn - off process of the power MOSFET to be controlled under the condition of the change of the first capacitor in the parameter configuration module. Detailed implementation manners

[0073] The technical solutions of the present invention will be further described below in conjunction with the accompanying drawings, but are not limited thereto. Any modification or equivalent replacement of the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention shall be covered by the protection scope of the present invention.

[0074] The present invention provides a controllable wide - adaptive MOSFET turn - off gate - driving circuit, as Figure 1As shown, it is applicable to a power electronic device using a power MOSFET. The power electronic device includes an electric energy converter and an inverter. The adjustable wide-adaptation MOSFET turn-off gate drive circuit includes a current mirror module, a parameter configuration module, a maintenance module, a conduction module, a control module, a first discharge module, a second discharge module, an external power MOSFET to be controlled, and an external gate resistor. Figure 2 As shown, where:

[0075] The current mirror module includes a first PMOS transistor MP1, a second PMOS transistor MP2, a third PMOS transistor MP3, and a fourth PMOS transistor MP4. Among them, the sources of the first PMOS transistor and the second PMOS transistor are connected to the power supply VDD. The gates of the first PMOS transistor and the second PMOS transistor are connected. The gates of the third PMOS transistor and the fourth PMOS transistor are connected. The drain of the second PMOS transistor, the source of the fourth PMOS transistor, and the gate of the second PMOS transistor are connected. The source of the first PMOS transistor and the drain of the third PMOS transistor are connected. The gate and the drain of the third PMOS transistor are connected to the node net1, and the drain of the fourth PMOS transistor is connected to the node net2.

[0076] The parameter configuration module includes a first NMOS transistor MN1, a first resistor R1, a second resistor R2, and a first capacitor C1. Among them, the gate of the first NMOS transistor is connected to the first turn-off enable signal Vctrl1. The drain of the first NMOS transistor is connected to the node net1. The source is connected to the second resistor and the first capacitor through the first resistor. One end of the second resistor and the first capacitor is connected to the source of the first NMOS transistor through the first resistor, and the other end is connected to the ground GND.

[0077] The maintenance module includes a second NMOS transistor MN2, a third NMOS transistor MN3, a fourth NMOS transistor MN4, a first diode D1, and a third resistor R3. Among them, the anode of the first diode is connected to the node net2, and the cathode is connected to the node net3. The node net3 is connected to the drain of the second NMOS transistor and the gate of the third NMOS transistor. The source of the second NMOS transistor is connected to the ground GND. Its gate and the source of the third NMOS transistor are connected to the node net4. The drain of the third NMOS transistor is connected to the power supply VDD. The source of the fourth NMOS transistor is connected to the node net4. The gate is connected to the second turn-off enable Vctrl2, and the drain is connected to the gate of the eleventh NSMO transistor MN11 in the second discharge module. The node net4 is connected to the ground through the third resistor.

[0078] The conduction module includes a fifth NMOS transistor MN5, a second diode D2, a fourth resistor R4, and a fifth resistor R5. Among them, the drain of the fifth NMOS transistor is connected to the power supply VDD, the gate is connected to the node net2, and the source is connected to the node net5. The anode of the second diode is connected to the node net2, and the cathode is connected to the node net5. The node net5 is connected to the node net6 through the fourth resistor, and the node net6 is connected to the ground through the fifth resistor;

[0079] The control module includes a sixth NMOS transistor MN6, a seventh NMOS transistor MN7, and a sixth resistor R6. Among them, the drain of the sixth NMOS transistor is connected to the control power supply VCC, the gate is connected to the third turn-off enable signal Vctrl3, and the source is connected to the node net6. The drain of the seventh NMOS transistor is connected to the node net6 through the sixth resistor, the gate is connected to the fourth turn-off enable signal Vctrl4, and the source is connected to the ground;

[0080] The first discharge module includes an eighth NMOS transistor MN8 and a ninth NMOS transistor MN9. Among them, the drain of the eighth NMOS transistor is connected to the gate of the power MOSFET to be controlled through an external gate resistor via the port Vgate, the gate is connected to the fifth turn-off enable signal Vctrl5, and the source is connected to the drain of the ninth NMOS transistor. The drain of the ninth NMOS transistor is connected to the source of the eighth NMOS transistor, the gate is connected to the sixth turn-off enable signal Vctrl6, and the source is connected to the ground GND;

[0081] The second discharge module includes a tenth NMOS transistor MN10 and an eleventh NMOS transistor MN11. Among them, the drain of the tenth NMOS transistor is connected to the gate of the power MOSFET to be controlled through an external gate resistor via the port Vgate, the gate is connected to the node net6, and the source is connected to the drain of the eleventh NMOS transistor. The drain of the eleventh NMOS transistor is connected to the source of the tenth NMOS transistor, the gate is connected to the drain of the fourth NMOS transistor in the maintenance module, and the source is connected to the ground GND;

[0082] The above-mentioned current mirror module is respectively connected to the parameter configuration module, the position module, and the conduction module at nodes net1 and net2; the input of the parameter configuration module is the first turn-off enable signal Vctrl1; the input of the maintenance module is the second turn-off enable signal Vctrl2; the maintenance module is connected to the current mirror module at node net2 and to the second current discharge module at the drain of the fourth NMOS transistor MN4; the conduction module is connected to the current mirror module at node net2 and to the control module and the first current discharge module at node net6; the input of the control module is the third turn-off enable signal Vctrl3 and the fourth turn-off enable signal Vctrl4, and it is connected to the conduction module and the second current discharge module at node net6; the input of the first current discharge module is the fifth turn-off enable signal Vctrl5 and the sixth turn-off enable signal Vctrl6, and it is connected to the second current discharge module at the output port Vgate; the second current discharge module is connected to the conduction module and the first current discharge module at node net6, to the maintenance module at the drain of the fourth NMOS transistor, and to the first current discharge module at the output terminal Vgate.

[0083] During the turn-off process of the power MOSFET to be controlled, the functions of the above-mentioned modules are specifically manifested as follows:

[0084] The current mirror module is used to copy the path current formed by it and the parameter configuration module to the path formed with the maintenance module. When the first turn-off enable signal Vctrl1 in the parameter configuration module is set high, the potentials of nodes net1 and net2 in the current mirror module are pulled high.

[0085] The parameter configuration module is used to control the current-carrying capacity of the branch where the first NMOS transistor is located according to the first turn-off enable signal Vctrl1 during the turn-off process of the power MOSFET to be controlled; in the pre-turn-off stage, the first turn-off enable signal Vctrl1 is set high, and the first NMOS transistor establishes a channel. At this time, the potential of node net1 in the current mirror module is pulled up, synchronously affecting the potential of node net2. At this time, the voltage waveform of node net2 is: during the turn-off process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the Miller plateau Vmiller stage, the voltage of node net2 presents a voltage peak.

[0086] The conduction module is used to conduct the voltage of node net2 in the node current mirror module to node net5, and use the fourth resistor and the fifth resistor to divide the voltage to pull down the potential of node net5, and the lowered potential is output from node net6 to the gate of the tenth NMOS tube in the second leakage module. Among them, the voltage waveform of node net6 is: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the Miller platform Vmiller stage, the voltage of node net6 presents a voltage peak, following the voltage waveform of node net2 in the current mirror module, such as Figure 3 shown.

[0087] The control module is used to control the sixth NMOS tube and the seventh NMOS tube to establish a channel according to the third shutdown enable signal Vctrl3 and the fourth shutdown enable signal Vctrl4. The control module is internally connected to the conduction module at the node net6, and the potential of the node net6 is changed according to the input third shutdown enable signal and the fourth shutdown enable signal. The voltage waveform of the node net6 connected to it is: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled drops to the threshold voltage Vth, the third shutdown enable and the fourth shutdown enable are set high at the same time. At this time, the sixth NMOS tube and the seventh NMOS tube establish a channel, so that the potential of the node net6 is pulled up again and remains unchanged, and the tenth NMOS tube in the second leakage module is driven to establish a channel so that it obtains the flow capacity, such as Figure 3 shown.

[0088] The maintenance module is used for, during the shutdown process of the power MOSFET to be controlled, when the potential of the node net2 in the current mirror module is pulled high, the potential of the node net3 is also pulled high, so that the third NMOS tube establishes a channel, and then the potential of the node net4 is pulled high by using the third NMOS tube and the third resistor R3 path, so that the second NMOS tube establishes a channel. Thus, during the shutdown process of the power MOSFET to be controlled, the maintenance module always has a voltage value at the node net4, and transmits the voltage of the node net4 to the gate of the eleventh NMOS tube in the second leakage module according to the second shutdown enable signal, so that the eleventh NMOS tube always maintains the channel establishment state during the shutdown process of the power MOSFET to be controlled.

[0089] The first current discharge module is used to control the eighth NMOS transistor and the ninth NMOS transistor to establish a channel according to the fifth turn-off enable signal Vctrl5 and the sixth turn-off enable signal Vctrl6, so that the lines where the eighth NMOS transistor and the ninth NMOS transistor are located obtain the current-carrying ability; the first current discharge module is connected to the second current discharge module at the output terminal Vgate, and this module discharges current from the output terminal Vgate. Specifically, during the turn-off process of the power MOSFET to be controlled, at the beginning of the turn-off process, the gate voltage of the power MOSFET to be controlled has not dropped yet, and the fifth turn-off enable signal and the sixth turn-off enable signal are both set high. At this time, the first current discharge module obtains the current-carrying ability and discharges current from the gate of the power MOSFET to be controlled through the output terminal Vgate; after the turn-off process ends, the gate voltage of the power MOSFET to be controlled will be zero, and the fifth turn-off enable signal and the sixth turn-off enable signal are both set low. At this time, the first current discharge module loses the current-carrying ability and stops discharging current through the output terminal Vgate.

[0090] As Figure 5 shown, during the turn-off process of the power MOSFET to be controlled, the waveform of its gate voltage is specifically shown as:

[0091] The first stage: when the gate voltage of the power MOSFET to be controlled is higher than the Miller plateau Vmiller voltage, the gate voltage rapidly drops to the Miller plateau voltage;

[0092] The second stage: when the gate voltage of the power MOSFET to be controlled is at the Miller plateau Vmiller voltage, the gate voltage remains at the Miller plateau voltage;

[0093] The third stage: when the gate voltage of the power MOSFET to be controlled is lower than the Miller plateau Vmiller voltage but higher than the threshold voltage Vth, the gate voltage slowly drops linearly;

[0094] The fourth stage: when the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage Vth, the gate voltage rapidly drops to zero.

[0095] Furthermore, the values of the first resistor, the second resistor, and the first capacitor inside the parameter configuration module can be configured according to the parasitic parameters of the power MOSFET to be controlled; during the turn-off process of the power MOSFET to be controlled, the internal resistance and capacitance values of the parameter configuration module have an impact on the gate voltage of the power MOSFET to be controlled. Specifically,

[0096] When the resistance and capacitance values of the second resistor R2 and the first capacitor C1 remain unchanged, the larger the resistance value of the first resistor R1, the slower the gate voltage of the power MOSFET to be controlled drops in the stage higher than the Miller plateau Vmiller, that is, the smaller the absolute value of the slope of the gate voltage drop in this stage, and the longer the gate voltage stays at the Miller plateau Vmiller voltage. AsFigure 6 as shown;

[0097] When the resistance and capacitance values of the first resistor R1 and the first capacitor C1 remain unchanged, the larger the resistance value of the second resistor R2, the shorter the time for the gate voltage of the power MOSFET to be controlled to be lower than the Miller plateau (Vmiller) voltage. As a result, the turn-off time of the power MOSFET to be controlled is shorter, as Figure 7 shown;

[0098] When the resistance values of the first capacitor R1 and the second resistor R2 remain unchanged, the smaller the capacitance value of the first capacitor C1, the slower the drop of the gate voltage of the power MOSFET to be controlled during the stage higher than the Miller plateau (Vmiller), that is, the smaller the absolute value of the slope of the gate voltage drop during this stage, as Figure 8 shown.

[0099] During the turn-off process of the power MOSFET to be controlled by the adjustable wide-adaptation MOSFET turn-off gate drive circuit, the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled are affected by the internal parameter values of the parameter configuration module. Specifically, it is manifested as:

[0100] When the resistance and capacitance values of the second resistor R2 and the first capacitor C1 remain unchanged, the larger the resistance value of the first resistor R1, the slope of the drain-source voltage of the power MOSFET to be controlled remains unchanged, and the absolute value of the slope of the drain-source current of the power MOSFET to be controlled is larger, as Figure 9 shown;

[0101] When the resistance and capacitance values of the first resistor R1 and the first capacitor C1 remain unchanged, the larger the resistance value of the second resistor R2, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled, and the absolute value of the slope of the drain-source current of the power MOSFET to be controlled is smaller, as Figure 10 shown;

[0102] When the resistance values of the first capacitor R1 and the second resistor R2 remain unchanged, the smaller the capacitance value of the first capacitor C1, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled, and the absolute value of the slope of the drain-source current of the power MOSFET to be controlled is smaller, as Figure 11 shown.

[0103] In the present invention, it is stated that "during the turn-off process of the power MOSFET (09) to be controlled, the drive circuit does not need to introduce the drain-source side information of the power MOSFET (09)". The power MOSFET is divided into a gate, a drain, and a source. Among them, the gate-source side bears the control voltage, and the drain-source side bears the power voltage, that is, the gate-source side is at low voltage and the drain-source side is at high voltage. The circuits are all connected to the gate, that is, the regulation is carried out on the low-voltage side;

[0104] The present invention provides a MOSFET turn-off gate drive circuit with adjustable wide adaptability, which is mainly applied to the turn-off drive of power MOSFET devices in power electronic devices. The circuit is designed without introducing the drain-source side information of the power MOSFET to be controlled. Only by utilizing the variation characteristics of the transconductance capacitance of the power MOSFET during the turn-off process, through continuous and fine regulation of the gate voltage of the power MOSFET to be controlled, separate fine regulation of the drain-source side voltage and current trajectories is achieved, and optimization is carried out between the turn-off loss and voltage overshoot, so as to achieve the goals of low voltage overshoot and low turn-off loss of the power MOSFET during the turn-off process, and realize the full limit application of the power MOSFET. At the same time, since the drain-source side information of the power MOSFET to be controlled is not introduced, the insulation requirements and circuit complexity are reduced, the power density is increased, and the high power density requirements of power electronic devices are met.

[0105] The present invention is illustrated by several specific embodiments. Those skilled in the art should understand that various transformations and equivalent substitutions can be made to the present invention without departing from the scope of the present invention. In addition, various modifications can be made to the present invention for specific situations or circumstances without departing from the scope of the present invention. Therefore, the present invention is not limited to the specific embodiments disclosed, but should include all embodiments falling within the scope of the claims of the present invention.

Claims

1. A controllable wide-adaptability MOSFET turn-off gate drive circuit, driving the controlled power MOSFET through the port Vgate, characterized in that: The driving circuit includes a current mirror module, a parameter configuration module, a maintenance module, a conduction module, a control module, a first leakage module, a second leakage module, an external gate resistor and nodes net1 to net6, wherein the gates of NMOSMN1, NMOS MN4, NMOS MN6, NMOS MN7, NMOS MN8 and NMOS MN9 in the driving circuit are respectively connected to the first to sixth shutdown enable signals; The current mirror module includes PMOS MP1, PMOS MP2, PMOS MP3 and PMOS MP4; the drain and gate of MP3 and the gate of MP4 are connected to the node net1, the source of MP3 is connected to the drain of MP1, the drain of MP4 is connected to the node net2, the source of MP4 is connected to the gate of MP1, the gate of MP2 and the drain of MP2, and the sources of MP1 and MP2 are connected to the power supply VDD; The parameter configuration module includes NMOS MN1, resistor R1, resistor R2 and capacitor C1; the drain of MN1 is connected to node net1, the source is connected to R2 and one end of C1 through R1, and the other end of R2 and C1 is connected to ground; The maintenance module includes NMOS MN2, NMOS MN3, NMOS MN4, diode D1 and resistor R3; the anode of D1 is connected to node net2, the cathode is connected to node net3, the drain of MN2 and the gate of MN3, the source of MN2 is grounded, the gate and the source of MN3, the source of MN4, and one end of R3 are connected to node net4, the drain of MN3 is connected to power supply VDD, the drain of MN4 is connected to the gate of NMOS MN11, and the other end of R3 is grounded; The conduction module includes NMOS MN5, diode D2, resistor R4 and resistor R5, the drain of MN5 is connected to the power supply VDD, the node net2 is connected to the gate of MN5 and the anode of D2, the node net5 is connected to the source of MN5, the cathode of D2 and one end of R4, the node net6 is connected to the other end of R4 and is grounded through R5; The control module includes NMOS MN6, NMOS MN7 and resistor R6, the drain of MN6 is connected to the control power supply VCC, the source is connected to the node net6, the drain of MN7 is connected to the node net6 through R6, and the source is grounded; The first leakage module includes NMOS MN8 and NMOS MN9, and the second leakage module includes NMOS MN10 and NMOS MN11, the drains of MN8 and MN10 are connected to the port Vgate, the sources of MN8 and MN10 are connected to the drains of MN9 and MN11 respectively, and the sources of MN9 and MN11 are grounded; The external gate resistor is connected between the terminal Vgate and the gate of the power MOSFET to be controlled.

2. The adjustable wide adaptability MOSFET turn-off gate drive circuit according to claim 1, characterized in that: The current mirror module is connected to the parameter configuration module at a node net1, and is connected to the maintenance module and the conduction module at a node net2; The input of the parameter configuration module is a first shutdown enable signal; The input of the maintenance module is the second shutdown enable signal, and is connected to the gate of NMOSMN11 in the second leakage module through NMOS MN4; The conduction module and the control module are connected to the node net6; The input end of the control module is the third shutdown enable signal and the fourth shutdown enable signal, which are connected to the gate of the NMOS MN10 in the second leakage module; The first leakage module is inputted with the fifth shutdown enable signal and the sixth shutdown enable signal, and is connected to the second leakage module at the port Vgate; The second leakage module is connected to the drain of the NMOS MN4 in the sustaining module.

3. The adjustable wide adaptability MOSFET turn-off gate drive circuit according to claim 2, characterized in that: The current mirror module is used to convert the current of the path connected to the parameter configuration module into i 1 is copied to the line connected to the maintenance module to form a current i 2. In the process of turning off the power MOSFET to be controlled, the voltage at the node net2 is pulled up, so that the NMOS MN5 in the conduction module establishes a channel in the pre-turnoff stage, thereby making the conduction module work; The parameter configuration module is used to generate a current in the circuit where the NMOS MN1 is located in the pre-turnoff stage of the power MOSFET to be controlled according to the first turn-off enable signal. i 1; The maintaining module is used to generate a current mirror module according to the current copied in the pre-shutdown stage. i 2. In the pre-turnoff stage of the power MOSFET to be controlled, the voltage of the node net3 is firstly pulled up, and then the voltage of the node net4 is pulled up. Subsequently, the voltage of the node net4 is transmitted to the gate of the NMOS MN11 in the second leakage module through the channel of the NMOS MN4 by the second turnoff enable signal, so that the NMOS MN11 establishes a channel; The conduction module is used to establish a channel for the NMOS MN5 under the influence of the node net2 voltage in the pre-turnoff stage of the power MOSFET to be controlled, and at the same time, transmit the node net2 voltage to the node net5 through the diode D2, and pull the node net5 voltage down to the node net6 through the resistor R4 and the resistor R5 voltage division, and transmit it to the gate of the NMOS MN10 in the second leakage module, so that the NMOS MN10 establishes a channel; The control module is used to change the gate voltage of the node net6 and the NMOS MN10 in the second leakage module under the control of the third shutdown enable signal and the fourth shutdown enable signal during the shutdown phase of the power MOSFET to be controlled; The first current discharge module is used to, during the shutdown process of the power MOSFET to be controlled, be controlled by the fifth shutdown enable signal and the sixth shutdown enable signal to enable the NMOS MN8 and the NMOS MN9 to establish a channel, thereby discharging current through the port Vgate; The second leakage module is used for, in the pre-turnoff stage of the power MOSFET to be controlled, NMOS MN11 obtains the channel establishment voltage from the node net4 through NMOS MN4, and in the turn-off stage of the power MOSFET to be controlled, the node net6 controls the channel opening degree of NMOS MN10, changes the current carrying capacity of NMOS MN10 and NMOS MN11 in the second leakage module, and enables the second leakage module to discharge current from the port Vgate.

4. A driving method for a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 3, characterized in that: The method includes: Configure the current mirror module, which is used to convert the current of the path connected to the parameter configuration module in the pre-shutdown stage i 1 is copied to the line connected to the maintenance module to form a current i 2. A method of increasing the voltage at the node net2 during the shutdown process of the power MOSFET to be controlled, so that the NMOS MN5 in the conduction module establishes a channel in the pre-shutdown stage, thereby making the conduction module work; A parameter configuration module is configured, wherein the parameter configuration module is used to generate a current in the circuit where the NMOS MN1 is located in the pre-turnoff stage of the power MOSFET to be controlled according to the first turnoff enable signal. i Method 1; A maintenance module is configured, the maintenance module is used to copy the current mirror module in the pre-shutdown stage according to the current i 2. In the pre-turnoff stage of the power MOSFET to be controlled, the voltage of the node net3 is firstly increased, and the voltage of the node net4 is secondly increased. Subsequently, the voltage of the node net4 is transmitted to the gate of the NMOS MN11 in the second leakage module through the channel of the NMOS MN4 by a second turnoff enable signal, so that the NMOS MN11 establishes a channel; A conduction module is configured, and the conduction module is used to establish a channel for the NMOS MN5 under the influence of the node net2 voltage in the pre-turnoff stage of the power MOSFET to be controlled, and at the same time, the node net2 voltage is transmitted to the node net5 through the diode D2, and the node net5 voltage is pulled down to the node net6 through the resistor R4 and the resistor R5 voltage division, and transmitted to the gate of the NMOS MN10 in the second leakage module, so that the NMOS MN10 establishes a channel; A control module is configured, and the control module is used to change the gate voltage of the node net6 and the NMOS MN10 in the second leakage module under the control of the third shutdown enable signal and the fourth shutdown enable signal during the shutdown phase of the power MOSFET to be controlled; A first discharge module is configured, and the first discharge module is used for, during the shutdown process of the power MOSFET to be controlled, being controlled by the fifth shutdown enable signal and the sixth shutdown enable signal, so that the NMOS MN8 and the NMOS MN9 establish a channel, thereby discharging current through the port Vgate; A second leakage module is configured. The second leakage module is used for, in the pre-turnoff stage of the power MOSFET to be controlled, NMOS MN11 obtains the channel establishment voltage from the node net4 through NMOS MN4. In the turn-off stage of the power MOSFET to be controlled, the node net6 controls the degree of opening of the channel of NMOS MN10, and changes the current carrying capacity of NMOS MN10 and NMOS MN11 in the second leakage module, so that the second leakage module discharges current from the port Vgate.

5. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: The resistor R1, the resistor R2, and the capacitor C1 in the parameter configuration module are configured according to the parasitic parameters of the power MOSFET to be controlled to control the voltage waveforms of the nodes net2 and net6. The specific performance method is as follows: During the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled is higher than the Miller platform, a voltage peak appears at the node net2; During the shutdown process of the power MOSFET to be controlled, the voltage of the node net6 is synchronized with the voltage of the node net2. When the gate voltage of the power MOSFET to be controlled is higher than the Miller platform (Vmiller), a voltage peak appears at the node net6.

6. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: The voltage waveform of the node net6 is specifically expressed as follows: during the shutdown process of the power MOSFET to be controlled, when the gate voltage of the power MOSFET to be controlled drops to the threshold voltage, the third shutdown enable signal and the fourth shutdown enable signal in the control module synchronously control NMOS MN6 and NMOS MN7 to turn on, thereby pulling up the voltage of the node net6. At this time, the voltage of the node net6 is pulled up and remains unchanged.

7. The driving method of a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 4, characterized in that: The gate voltage waveform during the shutdown process of the power MOSFET to be controlled is specifically expressed as follows: Phase 1: When the gate voltage of the power MOSFET to be controlled is higher than the Miller platform voltage, the gate voltage drops rapidly to the Miller platform voltage; The second stage: when the gate voltage of the power MOSFET to be controlled is at the Miller platform voltage, the gate voltage is maintained at the Miller platform voltage; The third stage: when the gate voltage of the power MOSFET to be controlled is lower than the Miller platform voltage but higher than the threshold voltage, the gate voltage slowly decreases linearly; Stage 4: When the gate voltage of the power MOSFET to be controlled is lower than the threshold voltage, the gate voltage drops rapidly to zero.

8. The driving method of a controllable wide-adaptability MOSFET turn-off gate drive circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET to be controlled, the gate voltage waveform of the power MOSFET to be controlled is affected by the resistance and capacitance values ​​of the resistor R1, the resistor R2 and the capacitor C1 in the parameter configuration module. The specific expression method is: When the resistance and capacitance values ​​of the resistor R2 and the capacitor C1 remain unchanged, the larger the resistance value of the resistor R1, the slower the gate voltage of the power MOSFET to be controlled decreases in the stage above the Miller platform, and the longer the gate voltage is at the Miller platform voltage; When the resistance and capacitance values ​​of the resistor R1 and the capacitor C1 remain unchanged, the larger the resistance value of the resistor R2 is, the shorter the time that the gate voltage of the power MOSFET to be controlled is lower than the Miller platform voltage is, and thus the shorter the turn-off time of the power MOSFET to be controlled is; When the resistance values ​​of the resistor R1 and the resistor R2 remain unchanged, the smaller the capacitance value of the capacitor C1 is, the slower the gate voltage of the power MOSFET to be controlled decreases in the stage above the Miller platform.

9. The driving method of a controllable wide-adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET to be controlled, the drain-source current and drain-source voltage waveforms of the power MOSFET to be controlled are specifically expressed as follows: When the resistance and capacitance values ​​of the resistor R2 and the capacitor C1 remain unchanged, the larger the resistance value of the resistor R1, the same the slope of the drain-source voltage of the power MOSFET to be controlled, and the larger the absolute value of the slope of the drain-source current of the power MOSFET to be controlled; When the resistance and capacitance values ​​of the resistor R1 and the capacitor C1 remain unchanged, the larger the resistance value of the resistor R2, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled; When the resistance values ​​of the resistor R1 and the resistor R2 remain unchanged, the smaller the capacitance value of the capacitor C1 is, the smaller the slope of the drain-source voltage of the power MOSFET to be controlled is, and the smaller the absolute value of the slope of the drain-source current of the power MOSFET to be controlled is.

10. The driving method of the adjustable wide adaptability MOSFET turn-off gate driving circuit according to claim 4, characterized in that: During the shutdown process of the power MOSFET to be controlled, the driving circuit does not need to introduce the drain-source side information of the power MOSFET to be controlled, and only uses the change characteristics of the transconductance capacitance of the power MOSFET to be controlled to regulate the gate voltage of the power MOSFET to be controlled, and finally completes the regulation of the drain-source voltage and current trajectory of the power MOSFET to be controlled; The driving circuit independently regulates the drain-source voltage and the slope of the drain-source current of the power MOSFET to be controlled through the resistance and capacitance parameters in the parameter configuration module.

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